[edk2-devel] [edk2-platforms: PATCH 8/9] Marvell/Cn9132Db: Introduce board support
Marcin Wojtas
mw at semihalf.com
Wed Aug 7 23:30:29 UTC 2019
This patch introduces all necessary components required
for building EDK2 firmware for CN9132-DB setup A.
Signed-off-by: Marcin Wojtas <mw at semihalf.com>
---
Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc | 72 +++++++++++
Platform/Marvell/Cn913xDb/Cn9132DbA.dsc | 45 +++++++
Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf | 29 +++++
Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf | 22 ++++
Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h | 4 +
Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c | 135 ++++++++++++++++++++
Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 42 ++++++
Platform/Marvell/Cn913xDb/Cn9132DbA.fdf.inc | 13 ++
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts | 6 -
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi | 20 ++-
10 files changed, 376 insertions(+), 12 deletions(-)
create mode 100644 Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc
create mode 100644 Platform/Marvell/Cn913xDb/Cn9132DbA.dsc
create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf
create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c
create mode 100644 Platform/Marvell/Cn913xDb/Cn9132DbA.fdf.inc
diff --git a/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc b/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc
new file mode 100644
index 0000000..a0b90fa
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc
@@ -0,0 +1,72 @@
+## @file
+# Component description file for the CN9132 Development Board (variant A)
+#
+# Copyright (c) 2019 Marvell International Ltd.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFixedAtBuild.common]
+ # CP115 count
+ gMarvellTokenSpaceGuid.PcdMaxCpCount|3
+
+ # MPP
+ gMarvellTokenSpaceGuid.PcdMppChipCount|4
+
+ # CP115 #2 MPP
+ gMarvellTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE
+ gMarvellTokenSpaceGuid.PcdChip3MppBaseAddress|0xF6440000
+ gMarvellTokenSpaceGuid.PcdChip3MppPinCount|64
+ gMarvellTokenSpaceGuid.PcdChip3MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip3MppSel1|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip3MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0x9, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip3MppSel3|{ 0x0, 0x0, 0x8, 0x0, 0x8, 0x0, 0x0, 0x2, 0x2, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip3MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip3MppSel5|{ 0x0, 0x0, 0x0, 0x0, 0xA, 0xB, 0xE, 0xE, 0xE, 0xE }
+ gMarvellTokenSpaceGuid.PcdChip3MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+
+ # ComPhy
+ gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1, 0x1 }
+ # ComPhy1
+ # 0: PCIE0 5 Gbps
+ # 1: PCIE0 5 Gbps
+ # 2: SATA0 5 Gbps
+ # 3: USB3_HOST1 5 Gbps
+ # 4: SFI 10.31 Gbps
+ # 5: PCIE2 5 Gbps
+ gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_SATA0), $(CP_USB3_HOST1), $(CP_SFI), $(CP_PCIE2)}
+ gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
+
+ # UtmiPhy
+ gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
+
+ # MDIO
+ gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
+
+ # PHY
+ gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
+
+ # NET
+ gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_1000), $(PHY_SPEED_10000), $(PHY_SPEED_10000) }
+ gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_RGMII), $(PHY_SFI), $(PHY_SFI) }
+ gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1, 0xFF, 0xFF }
+ gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1, 0x2 }
+ gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1, 0x1 }
+
+ # NonDiscoverableDevices
+ gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1, 0x0, 0x1 }
diff --git a/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc b/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc
new file mode 100644
index 0000000..12052ba
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc
@@ -0,0 +1,45 @@
+## @file
+# Component description file for the CN9132 Development Board (variant A)
+#
+# Copyright (c) 2019 Marvell International Ltd.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = Cn9132DbA
+ PLATFORM_GUID = b9d2c816-296f-460f-a190-fe9afdd208c7
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x0001000B
+ OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)-$(ARCH)
+ SUPPORTED_ARCHITECTURES = AARCH64|ARM
+ BUILD_TARGETS = DEBUG|RELEASE|NOOPT
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
+ BOARD_DXE_FV_COMPONENTS = Platform/Marvell/Cn913xDb/Cn9132DbA.fdf.inc
+
+ #
+ # Network definition
+ #
+ DEFINE NETWORK_IP6_ENABLE = FALSE
+ DEFINE NETWORK_TLS_ENABLE = FALSE
+ DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE
+ DEFINE NETWORK_ISCSI_ENABLE = FALSE
+
+!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+!include Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
+!include Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc
+!include Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc
+
+[Components.common]
+ Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf
+
+[LibraryClasses.common]
+ ArmadaBoardDescLib|Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf
+ NonDiscoverableInitLib|Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf
new file mode 100644
index 0000000..27a0214
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf
@@ -0,0 +1,29 @@
+## @file
+#
+# Copyright (C) 2019, Marvell International Ltd. and its affiliates<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = Cn9132DbABoardDescLib
+ FILE_GUID = cf7a0f12-45fe-417b-9c34-053605973b68
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmadaBoardDescLib
+
+[Sources]
+ Cn9132DbABoardDescLib.c
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Marvell/Marvell.dec
+
+[LibraryClasses]
+ DebugLib
+ IoLib
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf
new file mode 100644
index 0000000..c9e3b04
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf
@@ -0,0 +1,22 @@
+## @file
+#
+# Device tree description of the Marvell CN9130-DB-A platform
+#
+# Copyright (c) 2019, Marvell International Ltd. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = Cn9132DbADeviceTree
+ FILE_GUID = 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDefaultDtbFileGuid
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ cn9132-db-A.dts
+
+[Packages]
+ MdePkg/MdePkg.dec
diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h
index 6618737..084bea0 100644
--- a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h
+++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h
@@ -17,5 +17,9 @@
#define CN9130_DB_SDMMC_VCCQ_PIN 15
#define CN9131_DB_VBUS0_PIN 3
#define CN9131_DB_VBUS0_LIMIT_PIN 2
+#define CN9132_DB_VBUS0_PIN 2
+#define CN9132_DB_VBUS0_LIMIT_PIN 0
+#define CN9132_DB_VBUS1_PIN 3
+#define CN9132_DB_VBUS1_LIMIT_PIN 1
#endif
diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c
new file mode 100644
index 0000000..d2846dd
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c
@@ -0,0 +1,135 @@
+/**
+*
+* Copyright (C) 2019, Marvell International Ltd. and its affiliates.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Uefi.h>
+
+#include <Library/ArmadaBoardDescLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/MvGpioLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+//
+// GPIO Expander
+//
+STATIC MV_GPIO_EXPANDER mGpioExpander = {
+ PCA9555_ID,
+ 0x21,
+ 0x0,
+};
+
+
+EFI_STATUS
+EFIAPI
+ArmadaBoardGpioExpanderGet (
+ IN OUT MV_GPIO_EXPANDER **GpioExpanders,
+ IN OUT UINTN *GpioExpanderCount
+ )
+{
+ *GpioExpanderCount = 1;
+ *GpioExpanders = &mGpioExpander;
+
+ return EFI_SUCCESS;
+}
+
+//
+// PCIE
+//
+STATIC
+MV_PCIE_CONTROLLER mPcieController[] = {
+ { /* PCIE0 @0xF2640000 */
+ .PcieDbiAddress = 0xF2600000,
+ .ConfigSpaceAddress = 0xD0000000,
+ .HaveResetGpio = FALSE,
+ .PcieResetGpio = { 0 },
+ .PcieBusMin = 0,
+ .PcieBusMax = 0xFE,
+ .PcieIoTranslation = 0xDFF00000,
+ .PcieIoWinBase = 0x0,
+ .PcieIoWinSize = 0x10000,
+ .PcieMmio32Translation = 0,
+ .PcieMmio32WinBase = 0xC0000000,
+ .PcieMmio32WinSize = 0x10000000,
+ .PcieMmio64Translation = 0,
+ .PcieMmio64WinBase = MAX_UINT64,
+ .PcieMmio64WinSize = 0,
+ }
+};
+
+/**
+ Return the number and description of PCIE controllers used on the platform.
+
+ @param[in out] **PcieControllers Array containing PCIE controllers'
+ description.
+ @param[in out] *PcieControllerCount Amount of used PCIE controllers.
+
+ @retval EFI_SUCCESS The data were obtained successfully.
+ @retval other Return error status.
+
+**/
+EFI_STATUS
+EFIAPI
+ArmadaBoardPcieControllerGet (
+ IN OUT MV_PCIE_CONTROLLER CONST **PcieControllers,
+ IN OUT UINTN *PcieControllerCount
+ )
+{
+ *PcieControllers = mPcieController;
+ *PcieControllerCount = ARRAY_SIZE (mPcieController);
+
+ return EFI_SUCCESS;
+}
+
+//
+// Order of devices in SdMmcDescTemplate has to be in par with ArmadaSoCDescLib
+//
+STATIC
+MV_BOARD_SDMMC_DESC mSdMmcDescTemplate[] = {
+ { /* eMMC 0xF06E0000 */
+ 0, /* SOC will be filled by MvBoardDescDxe */
+ 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */
+ FALSE, /* Xenon1v8Enabled */
+ TRUE, /* Xenon8BitBusEnabled */
+ FALSE, /* XenonSlowModeEnabled */
+ 0x40, /* XenonTuningStepDivisor */
+ EmbeddedSlot /* SlotType */
+ },
+ { /* SD/MMC 0xF2780000 */
+ 0, /* SOC will be filled by MvBoardDescDxe */
+ 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */
+ FALSE, /* Xenon1v8Enabled */
+ FALSE, /* Xenon8BitBusEnabled */
+ FALSE, /* XenonSlowModeEnabled */
+ 0x19, /* XenonTuningStepDivisor */
+ EmbeddedSlot /* SlotType */
+ },
+ { /* SD/MMC 0xF6780000 */
+ 0, /* SOC will be filled by MvBoardDescDxe */
+ 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */
+ FALSE, /* Xenon1v8Enabled */
+ FALSE, /* Xenon8BitBusEnabled */
+ FALSE, /* XenonSlowModeEnabled */
+ 0x19, /* XenonTuningStepDivisor */
+ EmbeddedSlot /* SlotType */
+ }
+};
+
+EFI_STATUS
+EFIAPI
+ArmadaBoardDescSdMmcGet (
+ OUT UINTN *SdMmcDevCount,
+ OUT MV_BOARD_SDMMC_DESC **SdMmcDesc
+ )
+{
+ *SdMmcDesc = mSdMmcDescTemplate;
+ *SdMmcDevCount = ARRAY_SIZE (mSdMmcDescTemplate);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c
index dded150..42dc54a 100644
--- a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c
+++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c
@@ -118,6 +118,45 @@ Cp1XhciInit (
MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER);
}
+STATIC CONST MV_GPIO_PIN mCp2XhciVbusPins[] = {
+ {
+ MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER,
+ MV_GPIO_CP2_CONTROLLER0,
+ CN9132_DB_VBUS0_PIN,
+ TRUE,
+ },
+ {
+ MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER,
+ MV_GPIO_CP2_CONTROLLER0,
+ CN9132_DB_VBUS0_LIMIT_PIN,
+ TRUE,
+ },
+ {
+ MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER,
+ MV_GPIO_CP2_CONTROLLER0,
+ CN9132_DB_VBUS1_PIN,
+ TRUE,
+ },
+ {
+ MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER,
+ MV_GPIO_CP2_CONTROLLER0,
+ CN9132_DB_VBUS1_LIMIT_PIN,
+ TRUE,
+ },
+};
+
+STATIC
+EFI_STATUS
+EFIAPI
+Cp2XhciInit (
+ IN NON_DISCOVERABLE_DEVICE *This
+ )
+{
+ return ConfigurePins (mCp2XhciVbusPins,
+ ARRAY_SIZE (mCp2XhciVbusPins),
+ MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER);
+}
+
STATIC CONST MV_GPIO_PIN mCp0SdMmcPins[] = {
{
MV_GPIO_DRIVER_TYPE_PCA95XX,
@@ -159,6 +198,9 @@ NonDiscoverableDeviceInitializerGet (
return Cp0XhciInit;
case 2:
return Cp1XhciInit;
+ case 3:
+ case 4:
+ return Cp2XhciInit;
}
}
diff --git a/Platform/Marvell/Cn913xDb/Cn9132DbA.fdf.inc b/Platform/Marvell/Cn913xDb/Cn9132DbA.fdf.inc
new file mode 100644
index 0000000..2a5bc38
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/Cn9132DbA.fdf.inc
@@ -0,0 +1,13 @@
+#
+# Copyright (C) 2019 Marvell International Ltd. and its affiliates
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+# Per-board additional content of the DXE phase firmware volume
+
+ INF Silicon/Marvell/Drivers/Gpio/MvPca95xxDxe/MvPca95xxDxe.inf
+ INF Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf
+
+ # DTB
+ INF RuleOverride = DTB Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts
index e9464f8..724d7dc 100644
--- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts
@@ -55,12 +55,6 @@
&cp2_sata0 {
status = "okay";
- /* SLM-1521-V2, CON4 */
- sata-port at 0 {
- status = "okay";
- /* Generic PHY, providing serdes lanes */
- phys = <&cp2_comphy2 0>;
- };
};
/* CON 2 on SLM-1683 - microSD */
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi
index 8613607..7dc6c6e 100644
--- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi
@@ -6,15 +6,23 @@
*/
#undef CP110_NUM
-#undef CP110_PCIE_MEM_SIZE
+#undef CP110_NAME
+#undef CP110_BASE
+#undef CP110_PCIE0_BASE
+#undef CP110_PCIE1_BASE
+#undef CP110_PCIE2_BASE
#undef CP110_PCIEx_CPU_MEM_BASE
-#undef CP110_PCIEx_BUS_MEM_BASE
+#undef CP110_PCIEx_MEM_BASE
/* CP110-1 Settings */
+#define CP110_NAME cp2
#define CP110_NUM 2
-#define CP110_PCIE_MEM_SIZE(iface) (0xf00000)
-#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe5000000 + (iface) * 0x1000000)
-#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
+#define CP110_BASE f6000000
+#define CP110_PCIE0_BASE f6600000
+#define CP110_PCIE1_BASE f6620000
+#define CP110_PCIE2_BASE f6640000
+#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe5000000 + (iface) * 0x1000000)
+#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
#include "armada-cp110.dtsi"
@@ -124,7 +132,7 @@
&cp2_syscon0 {
cp2_pinctrl: pinctrl {
- compatible = "marvell,cp115-standalone-pinctrl";
+ compatible = "marvell,armada-7k-pinctrl";
cp2_i2c0_pins: cp2-i2c-pins-0 {
marvell,pins = "mpp37", "mpp38";
--
2.7.4
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