[edk2-devel] [edk2-platforms][PATCH V1 06/37] CoffeelakeSiliconPkg/Pch: Add Library include headers
Nate DeSimone
nathaniel.l.desimone at intel.com
Sat Aug 17 00:51:34 UTC 2019
Reviewed-by: Nate DeSimone <nathaniel.l.desimone at intel.com>
-----Original Message-----
From: Kubacki, Michael A
Sent: Friday, August 16, 2019 5:16 PM
To: devel at edk2.groups.io
Cc: Chaganty, Rangasai V <rangasai.v.chaganty at intel.com>; Chiu, Chasel <chasel.chiu at intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone at intel.com>; Gao, Liming <liming.gao at intel.com>; Kinney, Michael D <michael.d.kinney at intel.com>; Sinha, Ankit <ankit.sinha at intel.com>
Subject: [edk2-platforms][PATCH V1 06/37] CoffeelakeSiliconPkg/Pch: Add Library include headers
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082
Adds the following header files:
* Pch/Include/library
Cc: Sai Chaganty <rangasai.v.chaganty at intel.com>
Cc: Chasel Chiu <chasel.chiu at intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone at intel.com>
Cc: Liming Gao <liming.gao at intel.com>
Cc: Michael D Kinney <michael.d.kinney at intel.com>
Cc: Ankit Sinha <ankit.sinha at intel.com>
Signed-off-by: Michael Kubacki <michael.a.kubacki at intel.com>
---
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/BiosLockLib.h | 27 +
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/CnviLib.h | 24 +
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/DxePchPolicyLib.h | 58 ++
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GbeMdiLib.h | 265 +++++++
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib.h | 788 ++++++++++++++++++++
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioNativeLib.h | 166 +++++
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/OcWdtLib.h | 33 +
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib.h | 371 +++++++++
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchEspiLib.h | 141 ++++
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchGbeLib.h | 36 +
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchHsioLib.h | 109 +++
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchInfoLib.h | 407 ++++++++++
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPcieRpLib.h | 105 +++
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPcrLib.h | 226 ++++++
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPmcLib.h | 45 ++
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPolicyLib.h | 114 +++
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchResetLib.h | 24 +
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSbiAccessLib.h | 116 +++
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSerialIoLib.h | 240 ++++++
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSerialIoUartLib.h | 111 +++
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSmmControlLib.h | 23 +
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchWdtCommonLib.h | 121 +++
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PmcLib.h | 207 +++++
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SataLib.h | 76 ++
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SecPchLib.h | 22 +
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SpiFlashCommonLib.h | 98 +++
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SpiLib.h | 23 +
27 files changed, 3976 insertions(+)
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/BiosLockLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/BiosLockLib.h
new file mode 100644
index 0000000000..ee77334ecb
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/BiosLockLib.h
@@ -0,0 +1,27 @@
+/** @file
+ Header file for BiosLockLib.
+
+ Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _BIOSLOCK_LIB_H_
+#define _BIOSLOCK_LIB_H_
+
+/**
+ Enable BIOS lock. This will set the LE (Lock Enable) and EISS (Enable In SMM.STS).
+ When this is set, attempts to write the WPD (Write Protect Disable) bit in PCH
+ will cause a SMI which will allow the BIOS to verify that the write is from a valid source.
+
+ Bios should always enable LockDownConfig.BiosLock policy to set Bios Lock bit in FRC.
+ If capsule udpate is enabled, it's expected to not do BiosLock by setting BiosLock policy disable
+ so it can udpate BIOS region.
+ After flash update, it should utilize this lib to do BiosLock for security.
+**/
+VOID
+BiosLockEnable (
+ VOID
+ );
+
+#endif // _BIOSLOCK_LIB_H_
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/CnviLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/CnviLib.h
new file mode 100644
index 0000000000..f406e0d929
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/CnviLib.h
@@ -0,0 +1,24 @@
+/** @file
+ Header file for CnviLib.
+
+ Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CNVI_LIB_H_
+#define _CNVI_LIB_H_
+
+/**
+ Check if CNVi is present.
+
+ @retval TRUE CNVi is enabled
+ @retval FALSE CNVi is disabled
+
+**/
+BOOLEAN
+CnviIsPresent (
+ VOID
+ );
+
+#endif // _CNVI_LIB_H_
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/DxePchPolicyLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/DxePchPolicyLib.h
new file mode 100644
index 0000000000..4d1ed91f7e
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/DxePchPolicyLib.h
@@ -0,0 +1,58 @@
+/** @file
+ Prototype of the DxePchPolicyLib library.
+
+ Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_PCH_POLICY_LIB_H_
+#define _DXE_PCH_POLICY_LIB_H_
+
+#include <Protocol/PchPolicy.h>
+
+/**
+ This function prints the DXE phase policy.
+
+ @param[in] PchPolicy - PCH DXE Policy protocol
+**/
+VOID
+PchPrintPolicyProtocol (
+ IN PCH_POLICY_PROTOCOL *PchPolicy
+ );
+
+/**
+ CreatePchDxeConfigBlocks generates the config blocksg of PCH DXE Policy.
+ It allocates and zero out buffer, and fills in the Intel default settings.
+
+ @param[out] PchPolicy The pointer to get PCH Policy Protocol instance
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+CreatePchDxeConfigBlocks(
+ IN OUT PCH_POLICY_PROTOCOL **PchPolicy
+ );
+
+/**
+ PchInstallPolicyProtocol installs PCH Policy.
+ While installed, RC assumes the Policy is ready and finalized. So please update and override
+ any setting before calling this function.
+
+ @param[in] ImageHandle Image handle of this driver.
+ @param[in] PchPolicy The pointer to PCH Policy Protocol instance
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+
+**/
+EFI_STATUS
+EFIAPI
+PchInstallPolicyProtocol (
+ IN EFI_HANDLE ImageHandle,
+ IN PCH_POLICY_PROTOCOL *PchPolicy
+ );
+
+#endif // _DXE_PCH_POLICY_LIB_H_
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GbeMdiLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GbeMdiLib.h
new file mode 100644
index 0000000000..a6ce032eba
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GbeMdiLib.h
@@ -0,0 +1,265 @@
+/** @file
+ Header file for GbeMdiLib.
+
+ Conventions:
+
+ - Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ - In general, PCH registers are denoted by "_PCH_" in register names
+ - Registers / bits that are different between PCH generations are denoted by
+ "_PCH_[generation_name]_" in register/bit names.
+ - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
+ Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
+ e.g., "_PCH_H_", "_PCH_LP_"
+ Registers / bits names without _H_ or _LP_ apply for both H and LP.
+ - Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ - Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without [generation_name] inserted.
+
+ Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _GBE_MDI_LIB_H_
+#define _GBE_MDI_LIB_H_
+
+//
+//
+// PHY GENERAL registers
+// Registers 0 to 15 are defined by the specification
+// Registers 16 to 31 are left available to the vendor
+//
+#define B_PHY_MDI_PHY_ADDRESS_01 BIT21
+#define B_PHY_MDI_PHY_ADDRESS_MASK (BIT25 | BIT24 | BIT23 | BIT22 | BIT21)
+#define MDI_REG_SHIFT(x) (x << 16)
+#define R_PHY_MDI_PHY_REG_DATA_READ_WRITE 0x00120000
+// LAN PHY MDI registers and bits
+//
+
+//
+// Page 769 Port Control Registers
+// 6020h (769 * 32)
+//
+#define PHY_MDI_PAGE_769_PORT_CONTROL_REGISTERS 769
+
+//
+// Port General Configuration PHY Address 01, Page 769, Register 17
+//
+#define R_PHY_MDI_PAGE_769_REGISETER_17_PGC 0x0011
+//
+// Page 769, Register 17, BIT 4
+// Enables host wake up
+//
+#define B_PHY_MDI_PAGE_769_REGISETER_17_PGC_HOST_WAKE_UP BIT4
+//
+// Page 769, Register 17, BIT 2
+// Globally enable the MAC power down feature while the
+// GbE supports WoL. When set to 1b,
+// pages 800 and 801 are enabled for
+// configuration and Host_WU_Active is not blocked for writes.
+//
+#define B_PHY_MDI_PAGE_769_REGISETER_17_PGC_MACPD_ENABLE BIT2
+
+//
+// Page 800 Wake Up Registers
+// 6400h (800 * 32)
+//
+#define PHY_MDI_PAGE_800_WAKE_UP_REGISTERS 800
+//
+// Wake Up Control - WUC PHY Address 01, Page 800, Register 1
+// 1h (Register 1)
+//
+#define R_PHY_MDI_PAGE_800_REGISETER_1_WUC 0x0001
+//
+// Wake Up Control - (WUC)
+// Page 800, Register 1, BIT 0
+// Advance Power Management Enable (APME)
+// If set to 1b, APM wake up is enabled.
+//
+#define B_PHY_MDI_PAGE_800_REGISETER_1_WUC_APME BIT0
+//
+// Receive Address Low - RAL PHY Address 01, Page 800, Register 16
+// 10h (Register 16)
+//
+#define R_PHY_MDI_PAGE_800_REGISETER_16_RAL0 0x0010
+//
+// Receive Address Low - RAL PHY Address 01, Page 800, Register 17
+// 11h (Register 17)
+//
+#define R_PHY_MDI_PAGE_800_REGISETER_17_RAL1 0x0011
+//
+// Receive Address High - RAH PHY Address 01, Page 800, Register 18
+// 12h (Register 18)
+//
+#define R_PHY_MDI_PAGE_800_REGISETER_18_RAH0 0x0012
+//
+// Receive Address High - RAH PHY Address 01, Page 800, Register 19
+// 13h (Register 19)
+//
+#define R_PHY_MDI_PAGE_800_REGISETER_19_RAH1 0x0013
+//
+// Setting AV (BIT15 RAH is divided on two registers)
+// RAH Register 19, Page 800, BIT 31
+//
+// Address valid (AV)
+// When this bit is set, the relevant RAL and RAH are valid
+//
+#define B_PHY_MDI_PAGE_800_REGISETER_19_RAH1_ADDRESS_VALID BIT15
+//
+// Page 803 Host WoL Packet
+// 6460h (803 * 32)
+//
+#define PHY_MDI_PAGE_803_HOST_WOL_PACKET 803
+//
+// Host WoL Packet Clear - HWPC PHY Address 01, Page 803, Register 66
+//
+#define R_PHY_MDI_PAGE_803_REGISETER_66_HWPC 0x0042
+
+
+/**
+ Change Extended Device Control Register BIT 11 to 1 which
+ forces the interface between the MAC and the Phy to be on SMBus.
+ Cleared on the assertion of PCI reset.
+
+ @param [in] GbeBar GbE MMIO space
+
+**/
+VOID
+GbeMdiForceMACtoSMB (
+ IN UINT32 GbeBar
+ );
+
+/**
+ Test for MDIO operation complete.
+
+ @param [in] GbeBar GbE MMIO space
+
+ @retval EFI_SUCCESS
+ @retval EFI_TIMEOUT
+**/
+EFI_STATUS
+GbeMdiWaitReady (
+ IN UINT32 GbeBar
+ );
+
+/**
+ Acquire MDIO software semaphore.
+
+ 1. Ensure that MBARA offset F00h [5] = 1b
+ 2. Poll MBARA offset F00h [5] up to 200ms
+
+ @param [in] GbeBar GbE MMIO space
+
+ @retval EFI_SUCCESS
+ @retval EFI_TIMEOUT
+**/
+EFI_STATUS
+GbeMdiAcquireMdio (
+ IN UINT32 GbeBar
+ );
+
+/**
+ Release MDIO software semaphore by clearing MBARA offset F00h [5]
+
+ @param [in] GbeBar GbE MMIO space
+**/
+VOID
+GbeMdiReleaseMdio (
+ IN UINT32 GbeBar
+ );
+
+/**
+ Sets page on MDI
+ Page setting is attempted twice.
+ If first attempt failes MAC and the Phy are force to be on SMBus
+
+ @param [in] GbeBar GbE MMIO space
+ @param [in] Data Value to write in lower 16bits.
+
+ @retval EFI_SUCCESS Page setting was successfull
+ @retval EFI_DEVICE_ERROR Returned if both attermps of setting page failed
+**/
+EFI_STATUS
+GbeMdiSetPage (
+ IN UINT32 GbeBar,
+ IN UINT32 Page
+ );
+
+/**
+ Sets Register in current page.
+
+ @param [in] GbeBar GbE MMIO space
+ @param [in] register Register number
+
+ @return EFI_STATUS
+**/
+EFI_STATUS
+GbeMdiSetRegister (
+ IN UINT32 GbeBar,
+ IN UINT32 Register
+ );
+
+
+/**
+ Perform MDI read.
+
+ @param [in] GbeBar GbE MMIO space
+ @param [in] PhyAddress Phy Address General - 02 or Specific - 01
+ @param [in] PhyRegister Phy Register
+ @param [out] ReadData Return Value
+
+ @retval EFI_SUCCESS Based on response from GbeMdiWaitReady
+ @retval EFI_TIMEOUT Based on response from GbeMdiWaitReady
+ @retval EFI_INVALID_PARAMETER If Phy Address or Register validaton failed
+**/
+EFI_STATUS
+GbeMdiRead (
+ IN UINT32 GbeBar,
+ IN UINT32 PhyAddress,
+ IN UINT32 PhyRegister,
+ OUT UINT16 *ReadData
+ );
+
+/**
+ Perform MDI write.
+
+ @param [in] GbeBar GbE MMIO space
+ @param [in] PhyAddress Phy Address General - 02 or Specific - 01
+ @param [in] PhyRegister Phy Register
+ @param [in] WriteData Value to write in lower 16bits.
+
+ @retval EFI_SUCCESS Based on response from GbeMdiWaitReady
+ @retval EFI_TIMEOUT Based on response from GbeMdiWaitReady
+ @retval EFI_INVALID_PARAMETER If Phy Address or Register validaton failed
+**/
+EFI_STATUS
+GbeMdiWrite (
+ IN UINT32 GbeBar,
+ IN UINT32 PhyAddress,
+ IN UINT32 PhyRegister,
+ IN UINT32 WriteData
+ );
+
+/**
+ Gets Phy Revision and Model Number
+ from PHY IDENTIFIER register 2 (offset 3)
+
+ @param [in] GbeBar GbE MMIO space
+ @param [out] LanPhyRevision Return Value
+
+ @return EFI_STATUS
+ @return EFI_INVALID_PARAMETER When GbeBar is incorrect
+**/
+EFI_STATUS
+GbeMdiGetLanPhyRevision (
+ IN UINT32 GbeBar,
+ OUT UINT16 *LanPhyRevision
+ );
+
+#endif // _GBE_MDI_LIB_H_
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib.h
new file mode 100644
index 0000000000..25def24fca
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib.h
@@ -0,0 +1,788 @@
+/** @file
+ Header file for GpioLib.
+ All function in this library is available for PEI, DXE, and SMM
+
+ Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _GPIO_LIB_H_
+#define _GPIO_LIB_H_
+
+#include <GpioConfig.h>
+
+#define GPIO_NAME_LENGTH_MAX 32
+
+typedef struct {
+ GPIO_PAD GpioPad;
+ GPIO_CONFIG GpioConfig;
+} GPIO_INIT_CONFIG;
+
+/**
+ This procedure will initialize multiple GPIO pins. Use GPIO_INIT_CONFIG structure.
+ Structure contains fields that can be used to configure each pad.
+ Pad not configured using GPIO_INIT_CONFIG will be left with hardware default values.
+ Separate fields could be set to hardware default if it does not matter, except
+ GpioPad and PadMode.
+ Function will work in most efficient way if pads which belong to the same group are
+ placed in adjacent records of the table.
+ Although function can enable pads for Native mode, such programming is done
+ by reference code when enabling related silicon feature.
+
+ @param[in] NumberofItem Number of GPIO pads to be updated
+ @param[in] GpioInitTableAddress GPIO initialization table
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioConfigurePads (
+ IN UINT32 NumberOfItems,
+ IN GPIO_INIT_CONFIG *GpioInitTableAddress
+ );
+
+//
+// Functions for setting/getting multiple GpioPad settings
+//
+
+/**
+ This procedure will read multiple GPIO settings
+
+ @param[in] GpioPad GPIO Pad
+ @param[out] GpioData GPIO data structure
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetPadConfig (
+ IN GPIO_PAD GpioPad,
+ OUT GPIO_CONFIG *GpioData
+ );
+
+/**
+ This procedure will configure multiple GPIO settings
+
+ @param[in] GpioPad GPIO Pad
+ @param[in] GpioData GPIO data structure
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioSetPadConfig (
+ IN GPIO_PAD GpioPad,
+ IN GPIO_CONFIG *GpioData
+ );
+
+//
+// Functions for setting/getting single GpioPad properties
+//
+
+/**
+ This procedure will set GPIO output level
+
+ @param[in] GpioPad GPIO pad
+ @param[in] Value Output value
+ 0: OutputLow, 1: OutputHigh
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioSetOutputValue (
+ IN GPIO_PAD GpioPad,
+ IN UINT32 Value
+ );
+
+/**
+ This procedure will get GPIO output level
+
+ @param[in] GpioPad GPIO pad
+ @param[out] OutputVal GPIO Output value
+ 0: OutputLow, 1: OutputHigh
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetOutputValue (
+ IN GPIO_PAD GpioPad,
+ OUT UINT32 *OutputVal
+ );
+
+/**
+ This procedure will get GPIO input level
+
+ @param[in] GpioPad GPIO pad
+ @param[out] InputVal GPIO Input value
+ 0: InputLow, 1: InputHigh
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetInputValue (
+ IN GPIO_PAD GpioPad,
+ OUT UINT32 *InputVal
+ );
+
+/**
+ This procedure will get GPIO IOxAPIC interrupt number
+
+ @param[in] GpioPad GPIO pad
+ @param[out] IrqNum IRQ number
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetPadIoApicIrqNumber (
+ IN GPIO_PAD GpioPad,
+ OUT UINT32 *IrqNum
+ );
+
+/**
+ This procedure will configure GPIO input inversion
+
+ @param[in] GpioPad GPIO pad
+ @param[in] Value Value for GPIO input inversion
+ 0: No input inversion, 1: Invert input
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioSetInputInversion (
+ IN GPIO_PAD GpioPad,
+ IN UINT32 Value
+ );
+
+/**
+ This procedure will get GPIO pad input inversion value
+
+ @param[in] GpioPad GPIO pad
+ @param[out] InvertState GPIO inversion state
+ 0: No input inversion, 1: Inverted input
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetInputInversion (
+ IN GPIO_PAD GpioPad,
+ OUT UINT32 *InvertState
+ );
+
+/**
+ This procedure will set GPIO interrupt settings
+
+ @param[in] GpioPad GPIO pad
+ @param[in] Value Value of Level/Edge
+ use GPIO_INT_CONFIG as argument
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioSetPadInterruptConfig (
+ IN GPIO_PAD GpioPad,
+ IN GPIO_INT_CONFIG Value
+ );
+
+/**
+ This procedure will set GPIO electrical settings
+
+ @param[in] GpioPad GPIO pad
+ @param[in] Value Value of termination
+ use GPIO_ELECTRICAL_CONFIG as argument
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioSetPadElectricalConfig (
+ IN GPIO_PAD GpioPad,
+ IN GPIO_ELECTRICAL_CONFIG Value
+ );
+
+/**
+ This procedure will set GPIO Reset settings
+
+ @param[in] GpioPad GPIO pad
+ @param[in] Value Value for Pad Reset Configuration
+ use GPIO_RESET_CONFIG as argument
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioSetPadResetConfig (
+ IN GPIO_PAD GpioPad,
+ IN GPIO_RESET_CONFIG Value
+ );
+
+/**
+ This procedure will get GPIO Reset settings
+
+ @param[in] GpioPad GPIO pad
+ @param[in] Value Value of Pad Reset Configuration
+ based on GPIO_RESET_CONFIG
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetPadResetConfig (
+ IN GPIO_PAD GpioPad,
+ IN GPIO_RESET_CONFIG *Value
+ );
+
+/**
+ This procedure will get GPIO Host Software Pad Ownership for certain group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum Host Ownership register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[out] HostSwRegVal Value of Host Software Pad Ownership register
+ Bit position - PadNumber
+ Bit value - 0: ACPI Mode, 1: GPIO Driver mode
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioGetHostSwOwnershipForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ OUT UINT32 *HostSwRegVal
+ );
+
+/**
+ This procedure will get GPIO Host Software Pad Ownership for certain group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum Host Ownership register number for current group
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] HostSwRegVal Value of Host Software Pad Ownership register
+ Bit position - PadNumber
+ Bit value - 0: ACPI Mode, 1: GPIO Driver mode
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioSetHostSwOwnershipForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 HostSwRegVal
+ );
+
+/**
+ This procedure will get Gpio Pad Host Software Ownership
+
+ @param[in] GpioPad GPIO pad
+ @param[out] PadHostSwOwn Value of Host Software Pad Owner
+ 0: ACPI Mode, 1: GPIO Driver mode
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetHostSwOwnershipForPad (
+ IN GPIO_PAD GpioPad,
+ OUT UINT32 *PadHostSwOwn
+ );
+
+/**
+ This procedure will set Gpio Pad Host Software Ownership
+
+ @param[in] GpioPad GPIO pad
+ @param[in] PadHostSwOwn Pad Host Software Owner
+ 0: ACPI Mode, 1: GPIO Driver mode
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioSetHostSwOwnershipForPad (
+ IN GPIO_PAD GpioPad,
+ IN UINT32 PadHostSwOwn
+ );
+
+///
+/// Possible values of Pad Ownership
+/// If Pad is not under Host ownership then GPIO registers
+/// are not accessible by host (e.g. BIOS) and reading them
+/// will return 0xFFs.
+///
+typedef enum {
+ GpioPadOwnHost = 0x0,
+ GpioPadOwnCsme = 0x1,
+ GpioPadOwnIsh = 0x2,
+} GPIO_PAD_OWN;
+
+/**
+ This procedure will get Gpio Pad Ownership
+
+ @param[in] GpioPad GPIO pad
+ @param[out] PadOwnVal Value of Pad Ownership
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetPadOwnership (
+ IN GPIO_PAD GpioPad,
+ OUT GPIO_PAD_OWN *PadOwnVal
+ );
+
+/**
+ This procedure will check state of Pad Config Lock for pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[out] PadCfgLockRegVal Value of PadCfgLock register
+ Bit position - PadNumber
+ Bit value - 0: NotLocked, 1: Locked
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioGetPadCfgLockForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ OUT UINT32 *PadCfgLockRegVal
+ );
+
+/**
+ This procedure will check state of Pad Config Lock for selected pad
+
+ @param[in] GpioPad GPIO pad
+ @param[out] PadCfgLock PadCfgLock for selected pad
+ 0: NotLocked, 1: Locked
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetPadCfgLock (
+ IN GPIO_PAD GpioPad,
+ OUT UINT32 *PadCfgLock
+ );
+
+/**
+ This procedure will check state of Pad Config Tx Lock for pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLockTx register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[out] PadCfgLockTxRegVal Value of PadCfgLockTx register
+ Bit position - PadNumber
+ Bit value - 0: NotLockedTx, 1: LockedTx
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioGetPadCfgLockTxForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ OUT UINT32 *PadCfgLockTxRegVal
+ );
+
+/**
+ This procedure will check state of Pad Config Tx Lock for selected pad
+
+ @param[in] GpioPad GPIO pad
+ @param[out] PadCfgLock PadCfgLockTx for selected pad
+ 0: NotLockedTx, 1: LockedTx
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetPadCfgLockTx (
+ IN GPIO_PAD GpioPad,
+ OUT UINT32 *PadCfgLockTx
+ );
+
+/**
+ This procedure will clear PadCfgLock for selected pads within one group.
+ Unlocking a pad will cause an SMI (if enabled)
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToUnlock Bitmask for pads which are going to be unlocked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotUnlock, 1: Unlock
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioUnlockPadCfgForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToUnlock
+ );
+
+/**
+ This procedure will clear PadCfgLock for selected pad.
+ Unlocking a pad will cause an SMI (if enabled)
+
+ @param[in] GpioPad GPIO pad
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioUnlockPadCfg (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will set PadCfgLock for selected pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToLock Bitmask for pads which are going to be locked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotLock, 1: Lock
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioLockPadCfgForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToLock
+ );
+
+/**
+ This procedure will set PadCfgLock for selected pad
+
+ @param[in] GpioPad GPIO pad
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioLockPadCfg (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will clear PadCfgLockTx for selected pads within one group.
+ Unlocking a pad will cause an SMI (if enabled)
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLockTx register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToUnlockTx Bitmask for pads which are going to be unlocked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotUnLockTx, 1: LockTx
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioUnlockPadCfgTxForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToUnlockTx
+ );
+
+/**
+ This procedure will clear PadCfgLockTx for selected pad.
+ Unlocking a pad will cause an SMI (if enabled)
+
+ @param[in] GpioPad GPIO pad
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioUnlockPadCfgTx (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will set PadCfgLockTx for selected pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToLockTx Bitmask for pads which are going to be locked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotLockTx, 1: LockTx
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioLockPadCfgTxForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToLockTx
+ );
+
+/**
+ This procedure will set PadCfgLockTx for selected pad
+
+ @param[in] GpioPad GPIO pad
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioLockPadCfgTx (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will get Group to GPE mapping.
+ It will assume that only first 32 pads can be mapped to GPE.
+ To handle cases where groups have more than 32 pads and higher part of group
+ can be mapped please refer to GpioGetGroupDwToGpeDwX()
+
+ @param[out] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0
+ @param[out] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1
+ @param[out] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioGetGroupToGpeDwX (
+ IN GPIO_GROUP *GroupToGpeDw0,
+ IN GPIO_GROUP *GroupToGpeDw1,
+ IN GPIO_GROUP *GroupToGpeDw2
+ );
+
+/**
+ This procedure will get Group to GPE mapping. If group has more than 32 bits
+ it is possible to map only single DW of pins (e.g. 0-31, 32-63) because
+ ACPI GPE_DWx register is 32 bits large.
+
+ @param[out] GroupToGpeDw0 GPIO group mapped to GPE_DW0
+ @param[out] GroupDwForGpeDw0 DW of pins mapped to GPE_DW0
+ @param[out] GroupToGpeDw1 GPIO group mapped to GPE_DW1
+ @param[out] GroupDwForGpeDw1 DW of pins mapped to GPE_DW1
+ @param[out] GroupToGpeDw2 GPIO group mapped to GPE_DW2
+ @param[out] GroupDwForGpeDw2 DW of pins mapped to GPE_DW2
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioGetGroupDwToGpeDwX (
+ OUT GPIO_GROUP *GroupToGpeDw0,
+ OUT UINT32 *GroupDwForGpeDw0,
+ OUT GPIO_GROUP *GroupToGpeDw1,
+ OUT UINT32 *GroupDwForGpeDw1,
+ OUT GPIO_GROUP *GroupToGpeDw2,
+ OUT UINT32 *GroupDwForGpeDw2
+ );
+
+/**
+ This procedure will set Group to GPE mapping.
+ It will assume that only first 32 pads can be mapped to GPE.
+ To handle cases where groups have more than 32 pads and higher part of group
+ can be mapped please refer to GpioSetGroupDwToGpeDwX()
+
+ @param[in] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0
+ @param[in] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1
+ @param[in] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioSetGroupToGpeDwX (
+ IN GPIO_GROUP GroupToGpeDw0,
+ IN GPIO_GROUP GroupToGpeDw1,
+ IN GPIO_GROUP GroupToGpeDw2
+ );
+
+/**
+ This procedure will set Group to GPE mapping. If group has more than 32 bits
+ it is possible to map only single DW of pins (e.g. 0-31, 32-63) because
+ ACPI GPE_DWx register is 32 bits large.
+
+ @param[in] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0
+ @param[in] GroupDwForGpeDw0 DW of pins to be mapped to GPE_DW0
+ @param[in] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1
+ @param[in] GroupDwForGpeDw1 DW of pins to be mapped to GPE_DW1
+ @param[in] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2
+ @param[in] GroupDwForGpeDw2 DW of pins to be mapped to GPE_DW2
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioSetGroupDwToGpeDwX (
+ IN GPIO_GROUP GroupToGpeDw0,
+ IN UINT32 GroupDwForGpeDw0,
+ IN GPIO_GROUP GroupToGpeDw1,
+ IN UINT32 GroupDwForGpeDw1,
+ IN GPIO_GROUP GroupToGpeDw2,
+ IN UINT32 GroupDwForGpeDw2
+ );
+
+/**
+ This procedure will get GPE number for provided GpioPad.
+ PCH allows to configure mapping between GPIO groups and related GPE (GpioSetGroupToGpeDwX())
+ what results in the fact that certain Pad can cause different General Purpose Event. Only three
+ GPIO groups can be mapped to cause unique GPE (1-tier), all others groups will be under one common
+ event (GPE_111 for 2-tier).
+
+ 1-tier:
+ Returned GpeNumber is in range <0,95>. GpioGetGpeNumber() can be used
+ to determine what _LXX ACPI method would be called on event on selected GPIO pad
+
+ 2-tier:
+ Returned GpeNumber is 0x6F (111). All GPIO pads which are not mapped to 1-tier GPE
+ will be under one master GPE_111 which is linked to _L6F ACPI method. If it is needed to determine
+ what Pad from 2-tier has caused the event, _L6F method should check GPI_GPE_STS and GPI_GPE_EN
+ registers for all GPIO groups not mapped to 1-tier GPE.
+
+ @param[in] GpioPad GPIO pad
+ @param[out] GpeNumber GPE number
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetGpeNumber (
+ IN GPIO_PAD GpioPad,
+ OUT UINT32 *GpeNumber
+ );
+
+/**
+ This procedure is used to clear SMI STS for a specified Pad
+
+ @param[in] GpioPad GPIO pad
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioClearGpiSmiSts (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure is used by Smi Dispatcher and will clear
+ all GPI SMI Status bits
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+GpioClearAllGpiSmiSts (
+ VOID
+ );
+
+/**
+ This procedure is used to disable all GPI SMI
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+GpioDisableAllGpiSmi (
+ VOID
+ );
+
+/**
+ This procedure is used to register GPI SMI dispatch function.
+
+ @param[in] GpioPad GPIO pad
+ @param[out] GpiNum GPI number
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetGpiSmiNum (
+ IN GPIO_PAD GpioPad,
+ OUT UINTN *GpiNum
+ );
+
+/**
+ This procedure is used to check GPIO inputs belongs to 2 tier or 1 tier architecture
+
+ @param[in] GpioPad GPIO pad
+
+ @retval Data 0 means 1-tier, 1 means 2-tier
+**/
+BOOLEAN
+GpioCheckFor2Tier (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure is used to clear GPE STS for a specified GpioPad
+
+ @param[in] GpioPad GPIO pad
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioClearGpiGpeSts (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure is used to read GPE STS for a specified Pad
+
+ @param[in] GpioPad GPIO pad
+ @param[out] Data GPE STS data
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetGpiGpeSts (
+ IN GPIO_PAD GpioPad,
+ OUT UINT32* Data
+ );
+
+/**
+ This procedure is used to lock all GPIO pads except the ones
+ which were requested during their configuration to be left unlocked.
+ This function must be called before BIOS_DONE - before POSTBOOT_SAI is enabled.
+ FSP - call this function from wrapper before transition to FSP-S
+ UEFI/EDK - call this function before EndOfPei event
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioLockPads (
+ VOID
+ );
+
+/**
+ Generates GPIO name from GpioPad
+
+ @param[in] GpioPad GpioPad
+ @param[out] GpioNameBuffer Caller allocated buffer for GPIO name of GPIO_NAME_LENGTH_MAX size
+ @param[in] GpioNameBufferSize Size of the buffer
+
+ @retval CHAR8* Pointer to the GPIO name
+**/
+CHAR8*
+GpioGetPadName (
+ IN GPIO_PAD GpioPad,
+ OUT CHAR8* GpioNameBuffer,
+ IN UINT32 GpioNameBufferSize
+ );
+
+#endif // _GPIO_LIB_H_
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioNativeLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioNativeLib.h
new file mode 100644
index 0000000000..9956c60dd5
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioNativeLib.h
@@ -0,0 +1,166 @@
+/** @file
+ Header file for GpioLib for native and Si specific usage.
+ All function in this library is available for PEI, DXE, and SMM,
+
+ Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _GPIO_NATIVE_LIB_H_
+#define _GPIO_NATIVE_LIB_H_
+
+#include <GpioConfig.h>
+
+/**
+ This procedure will get number of pads for certain GPIO group
+
+ @param[in] Group GPIO group number
+
+ @retval Value Pad number for group
+ If illegal group number then return 0
+**/
+UINT32
+GpioGetPadPerGroup (
+ IN GPIO_GROUP Group
+ );
+
+/**
+ This procedure will get number of groups
+
+ @param[in] none
+
+ @retval Value Group number
+**/
+UINT32
+GpioGetNumberOfGroups (
+ VOID
+ );
+/**
+ This procedure will get lowest group
+
+ @param[in] none
+
+ @retval Value Lowest Group
+**/
+GPIO_GROUP
+GpioGetLowestGroup (
+ VOID
+ );
+
+/**
+ This procedure will get highest group
+
+ @param[in] none
+
+ @retval Value Highest Group
+**/
+GPIO_GROUP
+GpioGetHighestGroup (
+ VOID
+ );
+
+/**
+ This procedure will get group
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Group
+**/
+GPIO_GROUP
+GpioGetGroupFromGpioPad (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will get group index (0 based) from GpioPad
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Group Index
+**/
+UINT32
+GpioGetGroupIndexFromGpioPad (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will get group index (0 based) from group
+
+ @param[in] GpioGroup Gpio Group
+
+ @retval Value Group Index
+**/
+UINT32
+GpioGetGroupIndexFromGroup (
+ IN GPIO_GROUP GpioGroup
+ );
+
+/**
+ This procedure will get group from group index (0 based)
+
+ @param[in] GroupIndex Group Index
+
+ @retval GpioGroup Gpio Group
+**/
+GPIO_GROUP
+GpioGetGroupFromGroupIndex (
+ IN UINT32 GroupIndex
+ );
+
+/**
+ This procedure will get pad number (0 based) from Gpio Pad
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Pad Number
+**/
+UINT32
+GpioGetPadNumberFromGpioPad (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will return GpioPad from Group and PadNumber
+
+ @param[in] Group GPIO group
+ @param[in] PadNumber GPIO PadNumber
+
+ @retval GpioPad GpioPad
+**/
+GPIO_PAD
+GpioGetGpioPadFromGroupAndPadNumber (
+ IN GPIO_GROUP Group,
+ IN UINT32 PadNumber
+ );
+
+/**
+ This procedure will return GpioPad from GroupIndex and PadNumber
+
+ @param[in] GroupIndex GPIO GroupIndex
+ @param[in] PadNumber GPIO PadNumber
+
+ @retval GpioPad GpioPad
+**/
+GPIO_PAD
+GpioGetGpioPadFromGroupIndexAndPadNumber (
+ IN UINT32 GroupIndex,
+ IN UINT32 PadNumber
+ );
+
+/**
+ This function checks if SATA GP pin is enabled
+
+ @param[in] SataCtrlIndex SATA Controller Index
+ @param[in] SataPort SATA port number
+
+ @retval TRUE SATA GPx is enabled (pad is in required native mode)
+ FALSE SATA GPx is not enabled
+**/
+BOOLEAN
+GpioIsSataGpEnabled (
+ IN UINT32 SataCtrlIndex,
+ IN UINTN SataPort
+ );
+
+#endif // _GPIO_NATIVE_LIB_H_
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/OcWdtLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/OcWdtLib.h
new file mode 100644
index 0000000000..6ef0d08774
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/OcWdtLib.h
@@ -0,0 +1,33 @@
+/** @file
+ Header file for OC WDT Library.
+
+ Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _OC_WDT_LIB_H_
+#define _OC_WDT_LIB_H_
+
+/**
+ Check for unexpected reset.
+ If there was an unexpected reset, enforces WDT expiration.
+ Stops watchdog.
+**/
+VOID
+OcWdtResetCheck (
+ VOID
+ );
+
+/**
+ This function install WDT PPI
+
+ @retval EFI_STATUS Results of the installation of the WDT PPI
+**/
+EFI_STATUS
+EFIAPI
+OcWdtInit (
+ VOID
+ );
+
+#endif
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib.h
new file mode 100644
index 0000000000..7b6c82d390
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib.h
@@ -0,0 +1,371 @@
+/** @file
+ Header file for PchCycleDecodingLib.
+
+ Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_CYCLE_DECODING_LIB_H_
+#define _PCH_CYCLE_DECODING_LIB_H_
+
+/**
+ Set PCH TCO base address.
+ This cycle decoding is allowed to set when DMIC.SRL is 0.
+ Programming steps:
+ 1. set Smbus PCI offset 54h [8] to enable TCO base address.
+ 2. program Smbus PCI offset 50h [15:5] to TCO base address.
+ 3. set Smbus PCI offset 54h [8] to enable TCO base address.
+ 4. program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] to [Smbus PCI offset 50h[15:5], 1].
+
+ @param[in] Address Address for TCO base address.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid base address passed.
+**/
+EFI_STATUS
+PchTcoBaseSet (
+ IN UINT16 Address
+ );
+
+/**
+ Get PCH TCO base address.
+
+ @param[out] Address Address of TCO base address.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid pointer passed.
+**/
+EFI_STATUS
+PchTcoBaseGet (
+ OUT UINT16 *Address
+ );
+
+///
+/// structure of LPC general IO range register
+/// It contains base address, address mask, and enable status.
+///
+typedef struct {
+ UINT32 BaseAddr :16;
+ UINT32 Length :15;
+ UINT32 Enable : 1;
+} PCH_LPC_GEN_IO_RANGE;
+
+#define PCH_LPC_GEN_IO_RANGE_MAX 4
+#define ESPI_CS1_GEN_IO_RANGE_MAX 1
+#define PCH_H_ESPI_GEN_IO_RANGE_MAX PCH_LPC_GEN_IO_RANGE_MAX // @deprecated. Keep it here for backward compatibility.
+
+///
+/// structure of LPC general IO range register list
+/// It lists all LPC general IO ran registers supported by PCH.
+///
+typedef struct {
+ PCH_LPC_GEN_IO_RANGE Range[PCH_LPC_GEN_IO_RANGE_MAX];
+} PCH_LPC_GEN_IO_RANGE_LIST;
+
+/**
+ Set PCH LPC/eSPI generic IO range.
+ For generic IO range, the base address must align to 4 and less than 0xFFFF, and the length must be power of 2
+ and less than or equal to 256. Moreover, the address must be length aligned.
+ This function basically checks the address and length, which should not overlap with all other generic ranges.
+ If no more generic range register available, it returns out of resource error.
+ This cycle decoding is also required on DMI side
+ Some IO ranges below 0x100 have fixed target. The target might be ITSS,RTC,LPC,PMC or terminated inside P2SB
+ but all predefined and can't be changed. IO range below 0x100 will be rejected in this function except below ranges:
+ 0x00-0x1F,
+ 0x44-0x4B,
+ 0x54-0x5F,
+ 0x68-0x6F,
+ 0x80-0x8F,
+ 0xC0-0xFF
+ Steps of programming generic IO range:
+ 1. Program LPC/eSPI PCI Offset 84h ~ 93h of Mask, Address, and Enable.
+ 2. Program LPC/eSPI Generic IO Range in DMI
+
+ @param[in] Address Address for generic IO range base address.
+ @param[in] Length Length of generic IO range.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid base address or length passed.
+ @retval EFI_OUT_OF_RESOURCES No more generic range available.
+ @retval EFI_UNSUPPORTED DMIC.SRL is set.
+**/
+EFI_STATUS
+PchLpcGenIoRangeSet (
+ IN UINT16 Address,
+ IN UINTN Length
+ );
+
+/**
+ Set PCH eSPI CS1# generic IO range decoding.
+ For generic IO range, the base address must align to 4 and less than 0xFFFF, and the length must be power of 2
+ and less than or equal to 256. Moreover, the address must be length aligned.
+ This function basically checks the address and length, which should not overlap with all other generic ranges.
+ If no more generic range register available, it returns out of resource error.
+ This cycle decoding is also required on DMI side
+ Some IO ranges below 0x100 have fixed target. The target might be ITSS,RTC,LPC,PMC or terminated inside P2SB
+ but all predefined and can't be changed. IO range below 0x100 will be rejected in this function except below ranges:
+ 0x00-0x1F,
+ 0x44-0x4B,
+ 0x54-0x5F,
+ 0x68-0x6F,
+ 0x80-0x8F,
+ 0xC0-0xFF
+ Steps of programming generic IO range:
+ 1. Program eSPI PCI Offset A4h (eSPI CS1#) of Mask, Address, and Enable.
+ 2. Program eSPI Generic IO Range in DMI
+
+ @param[in] Address Address for generic IO range decoding.
+ @param[in] Length Length of generic IO range.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid base address or length passed.
+ @retval EFI_OUT_OF_RESOURCES No more generic range available.
+ @retval EFI_UNSUPPORTED eSPI secondary slave not supported
+**/
+EFI_STATUS
+PchEspiCs1GenIoRangeSet (
+ IN UINT16 Address,
+ IN UINTN Length
+ );
+
+/**
+ Get PCH LPC/eSPI generic IO range list.
+ This function returns a list of base address, length, and enable for all LPC/eSPI generic IO range registers.
+
+ @param[out] LpcGenIoRangeList Return all LPC/eSPI generic IO range register status.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid base address passed.
+**/
+EFI_STATUS
+PchLpcGenIoRangeGet (
+ OUT PCH_LPC_GEN_IO_RANGE_LIST *LpcGenIoRangeList
+ );
+
+/**
+ Get PCH eSPI CS1# generic IO range list.
+ This function returns a list of base address, length, and enable for all eSPI CS1# generic IO range registers.
+
+ @param[out] GenIoRangeList eSPI generic IO range registers.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid base address passed.
+ @retval EFI_UNSUPPORTED eSPI secondary slave not supported
+**/
+EFI_STATUS
+PchEspiCs1GenIoRangeGet (
+ OUT PCH_LPC_GEN_IO_RANGE_LIST *GenIoRangeList
+ );
+
+/**
+ Set PCH LPC/eSPI memory range decoding.
+ This cycle decoding is required to be set on DMI side
+ Programming steps:
+ 1. Program LPC PCI Offset 98h [0] to [0] to disable memory decoding first before changing base address.
+ 2. Program LPC PCI Offset 98h [31:16, 0] to [Address, 1].
+ 3. Program LPC Memory Range in DMI
+
+ @param[in] Address Address for memory base address.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid base address or length passed.
+ @retval EFI_OUT_OF_RESOURCES No more generic range available.
+ @retval EFI_UNSUPPORTED DMIC.SRL is set.
+**/
+EFI_STATUS
+PchLpcMemRangeSet (
+ IN UINT32 Address
+ );
+
+/**
+ Set PCH eSPI CS1# memory range decoding.
+ This cycle decoding is required to be set on DMI side
+ Programming steps:
+ 1. Program eSPI PCI Offset A8h (eSPI CS1#) [0] to [0] to disable memory decoding first before changing base address.
+ 2. Program eSPI PCI Offset A8h (eSPI CS1#) [31:16, 0] to [Address, 1].
+ 3. Program eSPI Memory Range in DMI
+
+ @param[in] Address Address for memory for decoding.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid base address or length passed.
+ @retval EFI_UNSUPPORTED eSPI secondary slave not supported
+**/
+EFI_STATUS
+PchEspiCs1MemRangeSet (
+ IN UINT32 Address
+ );
+
+/**
+ @deprecated. Keep this for backward compatibility.
+ It's replaced by PchEspiCs1MemRangeSet.
+**/
+EFI_STATUS
+PchEspiMemRange2Set (
+ IN UINT32 Address
+ );
+
+/**
+ Get PCH LPC/eSPI memory range decoding address.
+
+ @param[out] Address Address of LPC/eSPI memory decoding base address.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid base address passed.
+**/
+EFI_STATUS
+PchLpcMemRangeGet (
+ OUT UINT32 *Address
+ );
+
+/**
+ Get PCH eSPI CS1# memory range decoding address.
+
+ @param[out] Address Address of eSPI CS1# memory decoding base address.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid base address passed.
+ @retval EFI_UNSUPPORTED eSPI secondary slave not supported
+**/
+EFI_STATUS
+PchEspiCs1MemRangeGet (
+ OUT UINT32 *Address
+ );
+
+/**
+ Set PCH BIOS range deocding.
+ This will check General Control and Status bit 10 (GCS.BBS) to identify SPI or LPC/eSPI and program BDE register accordingly.
+ Please check EDS for detail of BiosDecodeEnable bit definition.
+ bit 15: F8-FF Enable
+ bit 14: F0-F8 Enable
+ bit 13: E8-EF Enable
+ bit 12: E0-E8 Enable
+ bit 11: D8-DF Enable
+ bit 10: D0-D7 Enable
+ bit 9: C8-CF Enable
+ bit 8: C0-C7 Enable
+ bit 7: Legacy F Segment Enable
+ bit 6: Legacy E Segment Enable
+ bit 5: Reserved
+ bit 4: Reserved
+ bit 3: 70-7F Enable
+ bit 2: 60-6F Enable
+ bit 1: 50-5F Enable
+ bit 0: 40-4F Enable
+ This cycle decoding is allowed to set when DMIC.SRL is 0.
+ Programming steps:
+ 1. if GCS.BBS is 0 (SPI), program SPI PCI offset D8h to BiosDecodeEnable.
+ if GCS.BBS is 1 (LPC/eSPi), program LPC/eSPI PCI offset D8h to BiosDecodeEnable.
+ 2. program LPC/eSPI/SPI BIOS Decode Enable, PCR[DMI] + 2744h to the same value programmed in LPC/eSPI or SPI PCI Offset D8h.
+
+ @param[in] BiosDecodeEnable Bios decode enable setting.
+
+ @retval EFI_SUCCESS Successfully completed.
+**/
+EFI_STATUS
+PchBiosDecodeEnableSet (
+ IN UINT16 BiosDecodeEnable
+ );
+
+/**
+ Set PCH LPC IO decode ranges.
+ Program LPC I/O Decode Ranges, PCR[DMI] + 2770h[15:0] to the same value programmed in LPC offset 80h.
+ Please check EDS for detail of Lpc IO decode ranges bit definition.
+ Bit 12: FDD range
+ Bit 9:8: LPT range
+ Bit 6:4: ComB range
+ Bit 2:0: ComA range
+
+ @param[in] LpcIoDecodeRanges Lpc IO decode ranges bit settings.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_UNSUPPORTED DMIC.SRL is set.
+**/
+EFI_STATUS
+PchLpcIoDecodeRangesSet (
+ IN UINT16 LpcIoDecodeRanges
+ );
+
+/**
+ Set PCH LPC and eSPI CS0# IO enable decoding.
+ Setup I/O Enables in DMI to the same value program in LPC/eSPI PCI offset 82h.
+ Note: Bit[15:10] of the source decode register is Read-Only. The IO range indicated by the Enables field
+ in LPC/eSPI PCI offset 82h[13:10] is always forwarded by DMI to subtractive agent for handling.
+ Please check EDS for detail of LPC/eSPI IO decode ranges bit definition.
+
+ @param[in] LpcIoEnableDecoding LPC IO enable decoding bit settings.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_UNSUPPORTED DMIC.SRL is set.
+**/
+EFI_STATUS
+PchLpcIoEnableDecodingSet (
+ IN UINT16 LpcIoEnableDecoding
+ );
+
+/**
+ Set PCH eSPI CS1# IO enable decoding.
+ Setup I/O Enables in DMI to the same value program in eSPI PCI offset A0h (eSPI CS1#).
+ Note: Bit[15:10] of the source decode register is Read-Only. The IO range indicated by the Enables field
+ in eSPI PCI offset A0h[13:10] is always forwarded by DMI to subtractive agent for handling.
+ Please check EDS for detail of eSPI IO decode ranges bit definition.
+
+ @param[in] IoEnableDecoding eSPI IO enable decoding bit settings.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_UNSUPPORTED DMI configuration is locked
+**/
+EFI_STATUS
+PchEspiCs1IoEnableDecodingSet (
+ IN UINT16 IoEnableDecoding
+ );
+
+/**
+ Set PCH IO port 80h cycle decoding to PCIE root port.
+ System BIOS is likely to do this very soon after reset before PCI bus enumeration, it must ensure that
+ the IO Base Address field (PCIe:1Ch[7:4]) contains a value greater than the IO Limit field (PCIe:1Ch[15:12])
+ before setting the IOSE bit. Otherwise the bridge will positively decode IO range 000h - FFFh by its default
+ IO range values.
+ This cycle decoding is allowed to set when DMIC.SRL is 0.
+ Programming steps:
+ 1. Program "RPR Destination ID", PCR[DMI] + 274Ch[31:16] to the Dest ID of RP.
+ 2. Program "Reserved Page Route", PCR[DMI] + 274Ch[11] to '1'. Use byte write on GCS+1 and leave the BILD bit which is RWO.
+ 3. Program IOSE bit of PCIE:Reg04h[0] to '1' for PCH to send such IO cycles to PCIe bus for subtractive decoding.
+
+ @param[in] RpPhyNumber PCIE root port physical number.
+
+ @retval EFI_SUCCESS Successfully completed.
+**/
+EFI_STATUS
+PchIoPort80DecodeSet (
+ IN UINTN RpPhyNumber
+ );
+
+/**
+ Get IO APIC registers base address.
+
+ @param[out] IoApicBase Buffer of IO APIC register address
+
+ @retval EFI_SUCCESS Successfully completed.
+**/
+EFI_STATUS
+PchIoApicBaseGet (
+ OUT UINT32 *IoApicBase
+ );
+
+/**
+ Get HPET base address.
+ This function will be unavailable after P2SB is hidden by PSF.
+
+ @param[out] HpetBase Buffer of HPET base address
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+**/
+EFI_STATUS
+PchHpetBaseGet (
+ OUT UINT32 *HpetBase
+ );
+
+#endif // _PCH_CYCLE_DECODING_LIB_H_
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchEspiLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchEspiLib.h
new file mode 100644
index 0000000000..c1d3c50ead
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchEspiLib.h
@@ -0,0 +1,141 @@
+/** @file
+ Header file for PchEspiLib.
+ All function in this library is available for PEI, DXE, and SMM,
+
+ Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_ESPI_LIB_H_
+#define _PCH_ESPI_LIB_H_
+
+/**
+ Checks if there's second slave connected under CS#1
+
+ @retval TRUE There's second slave
+ @retval FALSE There's no second slave
+**/
+BOOLEAN
+IsEspiSecondSlaveSupported (
+ VOID
+ );
+
+/**
+ Checks in slave General Capabilities register if it supports channel with requested number
+
+ @param[in] SlaveId Id of slave to check
+ @param[in] ChannelNumber Number of channel of which to check
+
+ @retval TRUE Channel with requested number is supported by slave device
+ @retval FALSE Channel with requested number is not supported by slave device
+**/
+BOOLEAN
+IsEspiSlaveChannelSupported (
+ UINT8 SlaveId,
+ UINT8 ChannelNumber
+ );
+
+/**
+ Is eSPI enabled in strap.
+
+ @retval TRUE Espi is enabled in strap
+ @retval FALSE Espi is disabled in strap
+**/
+BOOLEAN
+IsEspiEnabled (
+ VOID
+ );
+
+/**
+ Get configuration from eSPI slave
+
+ @param[in] SlaveId eSPI slave ID
+ @param[in] SlaveAddress Slave Configuration Register Address
+ @param[out] OutData Configuration data read
+
+ @retval EFI_SUCCESS Operation succeed
+ @retval EFI_INVALID_PARAMETER Slave ID is not supported
+ @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 is used in PchLp
+ @retval EFI_INVALID_PARAMETER Slave configuration register address exceed maximum allowed
+ @retval EFI_INVALID_PARAMETER Slave configuration register address is not DWord aligned
+ @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of operation
+**/
+EFI_STATUS
+PchEspiSlaveGetConfig (
+ IN UINT32 SlaveId,
+ IN UINT32 SlaveAddress,
+ OUT UINT32 *OutData
+ );
+
+/**
+ Set eSPI slave configuration
+
+ Note: A Set_Configuration must always be followed by a Get_Configuration in order to ensure
+ that the internal state of the eSPI-MC is consistent with the Slave's register settings.
+
+ @param[in] SlaveId eSPI slave ID
+ @param[in] SlaveAddress Slave Configuration Register Address
+ @param[in] InData Configuration data to write
+
+ @retval EFI_SUCCESS Operation succeed
+ @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 is used in PchLp
+ @retval EFI_INVALID_PARAMETER Slave configuration register address exceed maximum allowed
+ @retval EFI_INVALID_PARAMETER Slave configuration register address is not DWord aligned
+ @retval EFI_ACCESS_DENIED eSPI Slave write to address range 0 to 0x7FF has been locked
+ @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of operation
+**/
+EFI_STATUS
+PchEspiSlaveSetConfig (
+ IN UINT32 SlaveId,
+ IN UINT32 SlaveAddress,
+ IN UINT32 InData
+ );
+
+/**
+ Get status from eSPI slave
+
+ @param[in] SlaveId eSPI slave ID
+ @param[out] OutData Configuration data read
+
+ @retval EFI_SUCCESS Operation succeed
+ @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 is used in PchLp
+ @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of operation
+**/
+EFI_STATUS
+PchEspiSlaveGetStatus (
+ IN UINT32 SlaveId,
+ OUT UINT16 *OutData
+ );
+
+/**
+ eSPI slave in-band reset
+
+ @param[in] SlaveId eSPI slave ID
+
+ @retval EFI_SUCCESS Operation succeed
+ @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 is used in PchLp
+ @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of operation
+**/
+EFI_STATUS
+PchEspiSlaveInBandReset (
+ IN UINT32 SlaveId
+ );
+
+/**
+ eSPI Slave channel reset helper function
+
+ @param[in] SlaveId eSPI slave ID
+ @param[in] ChannelNumber Number of channel to reset
+
+ @retval EFI_SUCCESS Operation succeeded
+ @retval EFI_UNSUPPORTED Slave doesn't support that channel or invalid number specified
+ @retval EFI_TIMEOUT Operation has timeouted
+**/
+EFI_STATUS
+PchEspiSlaveChannelReset (
+ IN UINT8 SlaveId,
+ IN UINT8 ChannelNumber
+ );
+
+#endif // _PEI_DXE_SMM_PCH_ESPI_LIB_H_
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchGbeLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchGbeLib.h
new file mode 100644
index 0000000000..2a4dc986f4
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchGbeLib.h
@@ -0,0 +1,36 @@
+/** @file
+ Header file for PchGbeLib.
+
+ Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_GBE_LIB_H_
+#define _PCH_GBE_LIB_H_
+
+/**
+ Check whether GbE region is valid
+ Check SPI region directly since GBE might be disabled in SW.
+
+ @retval TRUE Gbe Region is valid
+ @retval FALSE Gbe Region is invalid
+**/
+BOOLEAN
+PchIsGbeRegionValid (
+ VOID
+ );
+
+
+/**
+ Check whether LAN controller is enabled in the platform.
+
+ @retval TRUE GbE is enabled
+ @retval FALSE GbE is disabled
+**/
+BOOLEAN
+PchIsGbePresent (
+ VOID
+ );
+
+#endif // _PCH_GBE_LIB_H_
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchHsioLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchHsioLib.h
new file mode 100644
index 0000000000..4f93f44120
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchHsioLib.h
@@ -0,0 +1,109 @@
+/** @file
+ Header file for PchHsioLib.
+
+ Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_HSIO_LIB_H_
+#define _PCH_HSIO_LIB_H_
+
+/**
+ Represents HSIO lane
+**/
+typedef struct {
+ UINT8 Index; ///< Lane index
+ UINT8 Pid; ///< Sideband ID
+ UINT16 Base; ///< Sideband base address
+} HSIO_LANE;
+
+/**
+ The function returns the Port Id and lane owner for the specified lane
+
+ @param[in] PhyMode Phymode that needs to be checked
+ @param[out] Pid Common Lane End Point ID
+ @param[out] LaneOwner Lane Owner
+
+ @retval EFI_SUCCESS Read success
+ @retval EFI_INVALID_PARAMETER Invalid lane number
+**/
+EFI_STATUS
+EFIAPI
+PchGetLaneInfo (
+ IN UINT32 LaneNum,
+ OUT UINT8 *PortId,
+ OUT UINT8 *LaneOwner
+ );
+
+/**
+ Get HSIO lane representation needed to perform any operation on the lane.
+
+ @param[in] LaneIndex Number of the HSIO lane
+ @param[out] HsioLane HSIO lane representation
+**/
+VOID
+HsioGetLane (
+ IN UINT8 LaneIndex,
+ OUT HSIO_LANE *HsioLane
+ );
+
+/**
+ Determine the lane number of a specified port
+
+ @param[in] PcieLaneIndex PCIE Root Port Lane Index
+ @param[out] LaneNum Lane Number
+
+ @retval EFI_SUCCESS Lane number valid.
+ @retval EFI_UNSUPPORTED Incorrect input device port
+**/
+EFI_STATUS
+PchGetPcieLaneNum (
+ UINT32 PcieLaneIndex,
+ UINT8 *LaneNum
+ );
+
+/**
+ Determine the lane number of a specified port
+
+ @param[in] SataLaneIndex Sata Lane Index
+ @param[out] LaneNum Lane Number
+
+ @retval EFI_SUCCESS Lane number valid.
+ @retval EFI_UNSUPPORTED Incorrect input device port
+**/
+EFI_STATUS
+PchGetSataLaneNum (
+ UINT32 SataLaneIndex,
+ UINT8 *LaneNum
+ );
+
+/**
+ Determine the lane number of a specified port
+
+ @param[in] Usb3LaneIndex USB3 Lane Index
+ @param[out] LaneNum Lane Number
+
+ @retval EFI_SUCCESS Lane number valid.
+ @retval EFI_UNSUPPORTED Incorrect input device port
+**/
+EFI_STATUS
+PchGetUsb3LaneNum (
+ UINT32 Usb3LaneIndex,
+ UINT8 *LaneNum
+ );
+
+/**
+ Determine the lane number of a specified port
+
+ @param[out] LaneNum GBE Lane Number
+
+ @retval EFI_SUCCESS Lane number valid.
+ @retval EFI_UNSUPPORTED Incorrect input device port
+**/
+EFI_STATUS
+PchGetGbeLaneNum (
+ UINT8 *LaneNum
+ );
+
+#endif // _PCH_HSIO_LIB_H_
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchInfoLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchInfoLib.h
new file mode 100644
index 0000000000..94a8204fa5
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchInfoLib.h
@@ -0,0 +1,407 @@
+/** @file
+ Header file for PchInfoLib.
+
+ Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_INFO_LIB_H_
+#define _PCH_INFO_LIB_H_
+
+#include <PchHda.h>
+
+typedef UINT8 PCH_STEPPING;
+#define PCH_A0 0x00
+#define PCH_A1 0x01
+#define PCH_B0 0x10
+#define PCH_B1 0x11
+#define PCH_C0 0x20
+#define PCH_C1 0x21
+#define PCH_D0 0x30
+#define PCH_D1 0x31
+#define PCH_STEPPING_MAX 0xFF
+
+typedef UINT8 PCH_SERIES;
+#define PCH_H 1
+#define PCH_LP 2
+#define PCH_SERVER 0x80
+#define PCH_UNKNOWN_SERIES 0xFF
+
+typedef UINT8 PCH_GENERATION;
+#define CNL_PCH 3
+#define CDF_PCH 0x80
+#define PCH_UNKNOWN_GENERATION 0xFF
+
+typedef enum {
+ RstUnsupported = 0,
+ RstPremium,
+ RstOptane,
+ RstMaxMode
+} RST_MODE;
+
+/**
+ Return LPC Device Id
+
+ @retval PCH_LPC_DEVICE_ID PCH Lpc Device ID
+**/
+UINT16
+PchGetLpcDid (
+ VOID
+ );
+
+/**
+ Return Pch stepping type
+
+ @retval PCH_STEPPING Pch stepping type
+**/
+PCH_STEPPING
+PchStepping (
+ VOID
+ );
+
+/**
+ Determine if PCH is supported
+
+ @retval TRUE PCH is supported
+ @retval FALSE PCH is not supported
+**/
+BOOLEAN
+IsPchSupported (
+ VOID
+ );
+
+/**
+ Return Pch Series
+
+ @retval PCH_SERIES Pch Series
+**/
+PCH_SERIES
+PchSeries (
+ VOID
+ );
+
+/**
+ Check if this is PCH LP series
+
+ @retval TRUE It's PCH LP series
+ @retval FALSE It's not PCH LP series
+**/
+BOOLEAN
+IsPchLp (
+ VOID
+ );
+
+/**
+ Check if this is PCH H series
+
+ @retval TRUE It's PCH H series
+ @retval FALSE It's not PCH H series
+**/
+BOOLEAN
+IsPchH (
+ VOID
+ );
+
+/**
+ Check if this is Server PCH
+
+ @retval TRUE It's a Server PCH
+ @retval FALSE It's not a Server PCH
+**/
+BOOLEAN
+IsPchServer (
+ VOID
+ );
+
+/**
+ Return Pch Generation
+
+ @retval PCH_GENERATION Pch Generation
+**/
+PCH_GENERATION
+PchGeneration (
+ VOID
+ );
+
+/**
+ Check if this is CDF PCH generation
+
+ @retval TRUE It's CDF PCH
+ @retval FALSE It's not CDF PCH
+**/
+BOOLEAN
+IsCdfPch (
+ VOID
+ );
+
+/**
+ @retval TRUE It's CNL PCH
+ @retval FALSE It's not CNL PCH
+**/
+BOOLEAN
+IsCnlPch (
+ VOID
+ );
+
+/**
+ Check if this is Server SKU
+
+ @retval TRUE It's PCH Server SKU
+ @retval FALSE It's not PCH Server SKU
+**/
+BOOLEAN
+IsPchServerSku (
+ VOID
+ );
+
+/**
+ Get Pch Maximum Pcie Root Port Number
+
+ @retval PcieMaxRootPort Pch Maximum Pcie Root Port Number
+**/
+UINT8
+GetPchMaxPciePortNum (
+ VOID
+ );
+
+/**
+ Get Pch Maximum Pcie Controller Number
+
+ @retval Pch Maximum Pcie Controller Number
+**/
+UINT8
+GetPchMaxPcieControllerNum (
+ VOID
+ );
+
+/**
+ Get Pch Maximum Pcie Clock Number
+
+ @retval Pch Maximum Pcie Clock Number
+**/
+UINT8
+GetPchMaxPcieClockNum (
+ VOID
+ );
+
+/**
+ Get Pch Usb2 Maximum Physical Port Number
+
+ @retval Pch Usb2 Maximum Physical Port Number
+**/
+UINT8
+GetPchUsb2MaxPhysicalPortNum (
+ VOID
+ );
+
+/**
+ Get Pch Maximum Usb2 Port Number of XHCI Controller
+
+ @retval Pch Maximum Usb2 Port Number of XHCI Controller
+**/
+UINT8
+GetPchXhciMaxUsb2PortNum (
+ VOID
+ );
+
+/**
+ Get Pch Maximum Usb3 Port Number of XHCI Controller
+
+ @retval Pch Maximum Usb3 Port Number of XHCI Controller
+**/
+UINT8
+GetPchXhciMaxUsb3PortNum (
+ VOID
+ );
+
+/**
+ Get Pch Maximum Serial IO controllers number
+
+ @retval Pch Maximum Serial IO controllers number
+**/
+UINT8
+GetPchMaxSerialIoControllersNum (
+ VOID
+ );
+
+/**
+ Get Pch Maximum Serial IO I2C controllers number
+
+ @retval Pch Maximum Serial IO I2C controllers number
+**/
+UINT8
+GetPchMaxSerialIoI2cControllersNum (
+ VOID
+ );
+
+/**
+ Get Pch Maximum Serial IO SPI controllers number
+
+ @retval Pch Maximum Serial IO SPI controllers number
+**/
+UINT8
+GetPchMaxSerialIoSpiControllersNum (
+ VOID
+ );
+
+/**
+ Get Pch Maximum Serial IO UART controllers number
+
+ @retval Pch Maximum Serial IO UART controllers number
+**/
+UINT8
+GetPchMaxSerialIoUartControllersNum (
+ VOID
+ );
+
+#define PCH_STEPPING_STR_LENGTH_MAX 3
+
+/**
+ Get PCH stepping ASCII string.
+ Function determines major and minor stepping versions and writes them into a buffer.
+ The return string is zero terminated
+
+ @param [out] Buffer Output buffer of string
+ @param [in] BufferSize Buffer size.
+ Must not be less then PCH_STEPPING_STR_LENGTH_MAX
+
+ @retval EFI_SUCCESS String copied successfully
+ @retval EFI_INVALID_PARAMETER The stepping is not supported, or parameters are NULL
+ @retval EFI_BUFFER_TOO_SMALL Input buffer size is too small
+**/
+EFI_STATUS
+PchGetSteppingStr (
+ OUT CHAR8 *Buffer,
+ IN UINT32 BufferSize
+ );
+
+/**
+ Get PCH series ASCII string.
+ The return string is zero terminated.
+
+ @retval Static ASCII string of PCH Series
+**/
+CHAR8*
+PchGetSeriesStr (
+ );
+
+/**
+ Get PCH Sku ASCII string
+ The return string is zero terminated.
+
+ @retval Static ASCII string of PCH Sku
+**/
+CHAR8*
+PchGetSkuStr (
+ VOID
+ );
+
+/**
+ Check if this chipset supports eMMC controller
+
+ @retval BOOLEAN TRUE if supported, FALSE otherwise
+**/
+BOOLEAN
+IsPchEmmcSupported (
+ VOID
+ );
+
+/**
+ Check if this chipset supports SD controller
+
+ @retval BOOLEAN TRUE if supported, FALSE otherwise
+**/
+BOOLEAN
+IsPchSdCardSupported (
+ VOID
+ );
+
+/**
+ Check if this chipset supports UFS controller
+
+ @retval BOOLEAN TRUE if supported, FALSE otherwise
+**/
+BOOLEAN
+IsPchUfsSupported (
+ VOID
+ );
+
+/**
+ Gets the maximum number of UFS controller supported by this chipset.
+
+ @return Number of supported UFS controllers
+**/
+UINT8
+PchGetMaxUfsNum (
+ VOID
+ );
+
+/**
+ Get RST mode supported by the silicon
+
+ @retval RST_MODE RST mode supported by silicon
+**/
+RST_MODE
+PchGetSupportedRstMode (
+ VOID
+ );
+
+/**
+ Check whether integrated LAN controller is supported.
+
+ @retval TRUE GbE is supported in PCH
+ @retval FALSE GbE is not supported by PCH
+**/
+BOOLEAN
+PchIsGbeSupported (
+ VOID
+ );
+
+/**
+ Check if given Display Audio Link T-Mode is supported
+
+ @param[in] Tmode T-mode support to be checked
+
+ @retval TRUE T-mode supported
+ @retval FALSE T-mode not supported
+**/
+BOOLEAN
+IsAudioIDispTmodeSupported (
+ IN PCH_HDAUDIO_IDISP_TMODE Tmode
+ );
+
+/**
+ Check if link between PCH and CPU is an P-DMI
+
+ @retval TRUE P-DMI link
+ @retval FALSE Not an P-DMI link
+**/
+BOOLEAN
+IsPchWithPdmi (
+ VOID
+ );
+
+/**
+ Check if link between PCH and CPU is an OP-DMI
+
+ @retval TRUE OP-DMI link
+ @retval FALSE Not an OP-DMI link
+**/
+BOOLEAN
+IsPchWithOpdmi (
+ VOID
+ );
+
+/**
+ Check if link between PCH and CPU is an F-DMI
+
+ @retval TRUE F-DMI link
+ @retval FALSE Not an F-DMI link
+**/
+BOOLEAN
+IsPchWithFdmi (
+ VOID
+ );
+
+#endif // _PCH_INFO_LIB_H_
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPcieRpLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPcieRpLib.h
new file mode 100644
index 0000000000..7c26f6939e
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPcieRpLib.h
@@ -0,0 +1,105 @@
+/** @file
+ Header file for PchPcieRpLib.
+
+ Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_PCIERP_LIB_H_
+#define _PCH_PCIERP_LIB_H_
+
+#define RST_PCIE_STORAGE_CR_1 0
+#define RST_PCIE_STORAGE_CR_2 1
+#define RST_PCIE_STORAGE_CR_3 2
+#define RST_PCIE_STORAGE_CR_INVALID 99
+
+typedef struct {
+ UINT8 DevNum;
+ UINT8 Pid;
+ UINT8 RpNumBase;
+} PCH_PCIE_CONTROLLER_INFO;
+
+/**
+ Get Pch Pcie Root Port Device and Function Number by Root Port physical Number
+
+ @param[in] RpNumber Root port physical number. (0-based)
+ @param[out] RpDev Return corresponding root port device number.
+ @param[out] RpFun Return corresponding root port function number.
+
+ @retval EFI_SUCCESS
+**/
+EFI_STATUS
+EFIAPI
+GetPchPcieRpDevFun (
+ IN UINTN RpNumber,
+ OUT UINTN *RpDev,
+ OUT UINTN *RpFun
+ );
+
+/**
+ Get Root Port physical Number by Pch Pcie Root Port Device and Function Number
+
+ @param[in] RpDev Root port device number.
+ @param[in] RpFun Root port function number.
+ @param[out] RpNumber Return corresponding physical Root Port index (0-based)
+
+ @retval EFI_SUCCESS Physical root port is retrieved
+ @retval EFI_INVALID_PARAMETER RpDev and/or RpFun are invalid
+ @retval EFI_UNSUPPORTED Root port device and function is not assigned to any physical root port
+**/
+EFI_STATUS
+EFIAPI
+GetPchPcieRpNumber (
+ IN UINTN RpDev,
+ IN UINTN RpFun,
+ OUT UINTN *RpNumber
+ );
+
+/**
+ Gets pci segment base address of PCIe root port.
+
+ @param RpIndex Root Port Index (0 based)
+ @return PCIe port base address.
+**/
+UINT64
+PchPcieBase (
+ IN UINT32 RpIndex
+ );
+
+/**
+ Determines whether L0s is supported on current stepping.
+
+ @return TRUE if L0s is supported, FALSE otherwise
+**/
+BOOLEAN
+PchIsPcieL0sSupported (
+ VOID
+ );
+
+/**
+ Some early PCH steppings require Native ASPM to be disabled due to hardware issues:
+ - RxL0s exit causes recovery
+ - Disabling PCIe L0s capability disables L1
+ Use this function to determine affected steppings.
+
+ @return TRUE if Native ASPM is supported, FALSE otherwise
+**/
+BOOLEAN
+PchIsPcieNativeAspmSupported (
+ VOID
+ );
+
+/**
+ Check the RST PCIe Storage Cycle Router number according to the root port number and PCH type
+
+ @param[in] RootPortNum Root Port Number
+
+ @return The RST PCIe Storage Cycle Router Number
+**/
+UINT8
+RstGetCycleRouterNumber (
+ IN UINT32 RootPortNum
+ );
+
+#endif // _PCH_PCIERP_LIB_H_
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPcrLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPcrLib.h
new file mode 100644
index 0000000000..2d57087c6b
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPcrLib.h
@@ -0,0 +1,226 @@
+/** @file
+ Header file for PchPcrLib.
+
+ Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_PCR_LIB_H_
+#define _PCH_PCR_LIB_H_
+
+#include <PchReservedResources.h>
+
+///
+/// Definition for PCR base address (defined in PchReservedResources.h)
+///
+//#define PCH_PCR_BASE_ADDRESS 0xFD000000
+//#define PCH_PCR_MMIO_SIZE 0x01000000
+/**
+ Definition for PCR address
+ The PCR address is used to the PCR MMIO programming
+**/
+#define PCH_PCR_ADDRESS(Pid, Offset) (PCH_PCR_BASE_ADDRESS | ((UINT8)(Pid) << 16) | (UINT16)(Offset))
+
+/**
+ PCH PCR boot script accessing macro
+ Those macros are only available for DXE phase.
+**/
+#define PCH_PCR_BOOT_SCRIPT_WRITE(Width, Pid, Offset, Count, Buffer) \
+ S3BootScriptSaveMemWrite (Width, PCH_PCR_ADDRESS (Pid, Offset), Count, Buffer); \
+
+#define PCH_PCR_BOOT_SCRIPT_READ_WRITE(Width, Pid, Offset, DataOr, DataAnd) \
+ S3BootScriptSaveMemReadWrite (Width, PCH_PCR_ADDRESS (Pid, Offset), DataOr, DataAnd); \
+
+#define PCH_PCR_BOOT_SCRIPT_READ(Width, Pid, Offset, BitMask, BitValue) \
+ S3BootScriptSaveMemPoll (Width, PCH_PCR_ADDRESS (Pid, Offset), BitMask, BitValue, 1, 1);
+
+typedef UINT8 PCH_SBI_PID;
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT32 PCR register value.
+**/
+UINT32
+PchPcrRead32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset
+ );
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT16 PCR register value.
+**/
+UINT16
+PchPcrRead16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset
+ );
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT8 PCR register value
+**/
+UINT8
+PchPcrRead8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT32 Value written to register
+**/
+UINT32
+PchPcrWrite32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT32 InData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT16 Value written to register
+**/
+UINT16
+PchPcrWrite16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT16 InData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT8 Value written to register
+**/
+UINT8
+PchPcrWrite8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT8 InData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT32 Value written to register
+
+**/
+UINT32
+PchPcrAndThenOr32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Write PCR register and read back.
+ The read back ensures the PCR cycle is completed before next operation.
+ It programs PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT32 Value read back from the register
+**/
+UINT32
+PchPcrAndThenOr32WithReadback (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT16 Value written to register
+
+**/
+UINT16
+PchPcrAndThenOr16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT8 Value written to register
+
+**/
+UINT8
+PchPcrAndThenOr8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+#endif // _PCH_PCR_LIB_H_
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPmcLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPmcLib.h
new file mode 100644
index 0000000000..36a0adb56f
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPmcLib.h
@@ -0,0 +1,45 @@
+/** @file
+ Header file for PchPmcLib.
+
+ Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_PMC_LIB_H_
+#define _PCH_PMC_LIB_H_
+
+typedef enum {
+ WarmBoot = 1,
+ ColdBoot,
+ PwrFlr,
+ PwrFlrSys,
+ PwrFlrPch,
+ PchPmStatusMax
+} PCH_PM_STATUS;
+
+/**
+ Query PCH to determine the Pm Status
+
+ @param[in] PmStatus - The Pch Pm Status to be probed
+
+ @retval Status TRUE if Status querried is Valid or FALSE if otherwise
+**/
+BOOLEAN
+GetPchPmStatus (
+ PCH_PM_STATUS PmStatus
+ );
+
+/**
+ Funtion to check if Battery lost or CMOS cleared.
+
+ @reval TRUE Battery is always present.
+ @reval FALSE CMOS is cleared.
+**/
+BOOLEAN
+EFIAPI
+PchIsRtcBatteryGood (
+ VOID
+ );
+
+#endif // _PCH_PMC_LIB_H_
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPolicyLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPolicyLib.h
new file mode 100644
index 0000000000..acd7a16e48
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPolicyLib.h
@@ -0,0 +1,114 @@
+/** @file
+ Prototype of the PeiPchPolicy library.
+
+ Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_PCH_POLICY_LIB_H_
+#define _PEI_PCH_POLICY_LIB_H_
+
+#include <Ppi/SiPolicy.h>
+
+/**
+ Print whole PCH_PREMEM_POLICY_PPI and serial out.
+
+ @param[in] SiPreMemPolicyPpi The RC PREMEM Policy PPI instance
+**/
+VOID
+EFIAPI
+PchPreMemPrintPolicyPpi (
+ IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
+ );
+
+/**
+ Print whole SI_POLICY_PPI and serial out.
+
+ @param[in] SiPolicyPpi The RC Policy PPI instance
+**/
+VOID
+EFIAPI
+PchPrintPolicyPpi (
+ IN SI_POLICY_PPI *SiPolicyPpi
+ );
+
+/**
+ Get PCH PREMEM config block table total size.
+
+ @retval Size of PCH PREMEM config block table
+**/
+UINT16
+EFIAPI
+PchGetPreMemConfigBlockTotalSize (
+ VOID
+ );
+
+/**
+ Get PCH config block table total size.
+
+ @retval Size of PCH config block table
+**/
+UINT16
+EFIAPI
+PchGetConfigBlockTotalSize (
+ VOID
+ );
+
+/**
+ PchAddPreMemConfigBlocks add all PCH config blocks.
+
+ @param[in] ConfigBlockTableAddress The pointer to add PCH config blocks
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+PchAddPreMemConfigBlocks (
+ IN VOID *ConfigBlockTableAddress
+ );
+
+/**
+ PchAddConfigBlocks add all PCH config blocks.
+
+ @param[in] ConfigBlockTableAddress The pointer to add PCH config blocks
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+PchAddConfigBlocks (
+ IN VOID *ConfigBlockTableAddress
+ );
+
+/**
+ Get Sata Config Policy
+
+ @param[in] SiPolicy The RC Policy PPI instance
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval SataConfig Pointer to Sata Config Policy
+**/
+PCH_SATA_CONFIG *
+GetPchSataConfig (
+ IN SI_POLICY_PPI *SiPolicy,
+ IN UINT32 SataCtrlIndex
+ );
+
+/**
+ Get Hsio Sata Pre Mem Config Policy
+
+ @param[in] SiPolicy The RC Policy PPI instance
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval Pointer to Hsio Sata Pre Mem Config Policy
+**/
+PCH_HSIO_SATA_PREMEM_CONFIG *
+GetPchHsioSataPreMemConfig (
+ IN SI_PREMEM_POLICY_PPI *SiPreMemPolicy,
+ IN UINT32 SataCtrlIndex
+ );
+
+#endif // _PEI_PCH_POLICY_LIB_H_
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchResetLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchResetLib.h
new file mode 100644
index 0000000000..ca2da4cfc1
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchResetLib.h
@@ -0,0 +1,24 @@
+/** @file
+ Header file for PCH RESET Driver.
+
+ Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_RESET_LIB_H_
+#define _PCH_RESET_LIB_H_
+
+/**
+ Initialize PCH Reset APIs
+
+ @retval EFI_SUCCESS APIs are installed successfully
+ @retval EFI_OUT_OF_RESOURCES Can't allocate pool
+**/
+EFI_STATUS
+EFIAPI
+PchInitializeReset (
+ VOID
+ );
+
+#endif
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSbiAccessLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSbiAccessLib.h
new file mode 100644
index 0000000000..779aac2d2a
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSbiAccessLib.h
@@ -0,0 +1,116 @@
+/** @file
+ Header file for PchSbiAccessLib.
+
+ Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_SBI_ACCESS_LIB_H_
+#define _PCH_SBI_ACCESS_LIB_H_
+
+#include <Library/PchPcrLib.h>
+
+/**
+ PCH SBI opcode definitions
+**/
+typedef enum {
+ MemoryRead = 0x0,
+ MemoryWrite = 0x1,
+ PciConfigRead = 0x4,
+ PciConfigWrite = 0x5,
+ PrivateControlRead = 0x6,
+ PrivateControlWrite = 0x7,
+ GpioLockUnlock = 0x13
+} PCH_SBI_OPCODE;
+
+/**
+ PCH SBI response status definitions
+**/
+typedef enum {
+ SBI_SUCCESSFUL = 0,
+ SBI_UNSUCCESSFUL = 1,
+ SBI_POWERDOWN = 2,
+ SBI_MIXED = 3,
+ SBI_INVALID_RESPONSE
+} PCH_SBI_RESPONSE;
+
+/**
+ Execute PCH SBI message
+ Take care of that there is no lock protection when using SBI programming in both POST time and SMI.
+ It will clash with POST time SBI programming when SMI happen.
+ Programmer MUST do the save and restore opration while using the PchSbiExecution inside SMI
+ to prevent from racing condition.
+ This function will reveal P2SB and hide P2SB if it's originally hidden. If more than one SBI access
+ needed, it's better to unhide the P2SB before calling and hide it back after done.
+
+ When the return value is "EFI_SUCCESS", the "Response" do not need to be checked as it would have been
+ SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would provide additional information
+ when needed.
+
+ @param[in] Pid Port ID of the SBI message
+ @param[in] Offset Offset of the SBI message
+ @param[in] Opcode Opcode
+ @param[in] Posted Posted message
+ @param[in, out] Data32 Read/Write data
+ @param[out] Response Response
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_DEVICE_ERROR Transaction fail
+ @retval EFI_INVALID_PARAMETER Invalid parameter
+ @retval EFI_TIMEOUT Timeout while waiting for response
+**/
+EFI_STATUS
+EFIAPI
+PchSbiExecution (
+ IN PCH_SBI_PID Pid,
+ IN UINT64 Offset,
+ IN PCH_SBI_OPCODE Opcode,
+ IN BOOLEAN Posted,
+ IN OUT UINT32 *Data32,
+ OUT UINT8 *Response
+ );
+
+/**
+ Full function for executing PCH SBI message
+ Take care of that there is no lock protection when using SBI programming in both POST time and SMI.
+ It will clash with POST time SBI programming when SMI happen.
+ Programmer MUST do the save and restore opration while using the PchSbiExecution inside SMI
+ to prevent from racing condition.
+ This function will reveal P2SB and hide P2SB if it's originally hidden. If more than one SBI access
+ needed, it's better to unhide the P2SB before calling and hide it back after done.
+
+ When the return value is "EFI_SUCCESS", the "Response" do not need to be checked as it would have been
+ SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would provide additional information
+ when needed.
+
+ @param[in] Pid Port ID of the SBI message
+ @param[in] Offset Offset of the SBI message
+ @param[in] Opcode Opcode
+ @param[in] Posted Posted message
+ @param[in] Fbe First byte enable
+ @param[in] Bar Bar
+ @param[in] Fid Function ID
+ @param[in, out] Data32 Read/Write data
+ @param[out] Response Response
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_DEVICE_ERROR Transaction fail
+ @retval EFI_INVALID_PARAMETER Invalid parameter
+ @retval EFI_TIMEOUT Timeout while waiting for response
+**/
+EFI_STATUS
+EFIAPI
+PchSbiExecutionEx (
+ IN PCH_SBI_PID Pid,
+ IN UINT64 Offset,
+ IN PCH_SBI_OPCODE Opcode,
+ IN BOOLEAN Posted,
+ IN UINT16 Fbe,
+ IN UINT16 Bar,
+ IN UINT16 Fid,
+ IN OUT UINT32 *Data32,
+ OUT UINT8 *Response
+ );
+
+#endif // _PCH_SBI_ACCESS_LIB_H_
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSerialIoLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSerialIoLib.h
new file mode 100644
index 0000000000..4962c67a7c
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSerialIoLib.h
@@ -0,0 +1,240 @@
+/** @file
+ Header file for PCH Serial IO Lib implementation.
+
+ Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_SERIAL_IO_LIB_H_
+#define _PCH_SERIAL_IO_LIB_H_
+
+typedef enum {
+ PchSerialIoIndexI2C0,
+ PchSerialIoIndexI2C1,
+ PchSerialIoIndexI2C2,
+ PchSerialIoIndexI2C3,
+ PchSerialIoIndexI2C4,
+ PchSerialIoIndexI2C5,
+ PchSerialIoIndexSpi0,
+ PchSerialIoIndexSpi1,
+ PchSerialIoIndexSpi2,
+ PchSerialIoIndexUart0,
+ PchSerialIoIndexUart1,
+ PchSerialIoIndexUart2,
+ PchSerialIoIndexMax
+} PCH_SERIAL_IO_CONTROLLER;
+
+typedef enum {
+ PchSerialIoDisabled,
+ PchSerialIoPci,
+ PchSerialIoAcpi,
+ PchSerialIoHidden
+} PCH_SERIAL_IO_MODE;
+
+typedef enum {
+ SERIAL_IO_UNKNOWN = 0,
+ SERIAL_IO_I2C,
+ SERIAL_IO_SPI,
+ SERIAL_IO_UART
+} PCH_SERIAL_IO_CONTROLLER_TYPE;
+
+enum PCH_LP_SERIAL_IO_CS_POLARITY {
+ PchSerialIoCsActiveLow = 0,
+ PchSerialIoCsActiveHigh = 1
+};
+enum PCH_LP_SERIAL_IO_HW_FLOW_CTRL {
+ PchSerialIoHwFlowCtrlDisabled = 0,
+ PchSerialIoHwFlowControlEnabled = 1
+};
+
+#define SERIALIO_HID_LENGTH 8 // including null terminator
+#define SERIALIO_UID_LENGTH 1
+#define SERIALIO_CID_LENGTH 1
+#define SERIALIO_TOTAL_ID_LENGTH SERIALIO_HID_LENGTH+SERIALIO_UID_LENGTH+SERIALIO_CID_LENGTH
+
+/**
+ Returns index of the last i2c controller
+
+ @param[in] Number Number of SerialIo controller
+
+ @retval Index of I2C controller
+**/
+PCH_SERIAL_IO_CONTROLLER
+GetMaxI2cNumber (
+ VOID
+ );
+
+/**
+ Returns string with AcpiHID assigned to selected SerialIo controller
+
+ @param[in] Number Number of SerialIo controller
+
+ @retval pointer to 8-byte string
+**/
+CHAR8*
+GetSerialIoAcpiHid (
+ IN PCH_SERIAL_IO_CONTROLLER Number
+ );
+
+/**
+ Checks if given Serial IO Controller Function equals 0
+
+ @param[in] SerialIoNumber Serial IO device
+
+ @retval TRUE if SerialIO Function is equal to 0
+ FALSE if Function is higher then 0
+**/
+BOOLEAN
+IsSerialIoFunctionZero (
+ IN PCH_SERIAL_IO_CONTROLLER SerialIoNumber
+ );
+
+/**
+ Checks if Device with given PciDeviceId is one of SerialIo controllers
+ If yes, its number is returned through Number parameter, otherwise Number is not updated
+
+ @param[in] PciDevId Device ID
+ @param[out] Number Number of SerialIo controller
+
+ @retval TRUE Yes it is a SerialIo controller
+ @retval FALSE No it isn't a SerialIo controller
+**/
+BOOLEAN
+IsSerialIoPciDevId (
+ IN UINT16 PciDevId,
+ OUT PCH_SERIAL_IO_CONTROLLER *Number
+ );
+
+/**
+ Checks if Device with given AcpiHID string is one of SerialIo controllers
+ If yes, its number is returned through Number parameter, otherwise Number is not updated
+
+ @param[in] AcpiHid String
+ @param[out] Number Number of SerialIo controller
+
+ @retval TRUE yes it is a SerialIo controller
+ @retval FALSE no it isn't a SerialIo controller
+**/
+BOOLEAN
+IsSerialIoAcpiHid (
+ IN CHAR8 *AcpiHid,
+ OUT PCH_SERIAL_IO_CONTROLLER *Number
+ );
+
+/**
+ Configures Serial IO Controller
+
+ @param[in] Controller Serial IO controller number
+ @param[in] DeviceMode Device operation mode
+ @param[in] PsfDisable Disable device at PSF level
+
+ @retval None
+**/
+VOID
+ConfigureSerialIoController (
+ IN PCH_SERIAL_IO_CONTROLLER Controller,
+ IN PCH_SERIAL_IO_MODE DeviceMode,
+ IN BOOLEAN PsfDisable
+ );
+
+/**
+ Returns Serial IO Controller Type I2C, SPI or UART
+
+ @param[in] Number Number of SerialIo controller
+
+ @retval I2C, SPI or UART
+ @retval UNKNOWN - in case if undefined controller
+**/
+PCH_SERIAL_IO_CONTROLLER_TYPE
+GetSerialIoControllerType (
+ IN PCH_SERIAL_IO_CONTROLLER Controller
+ );
+
+/**
+ Finds PCI Device Number of SerialIo devices.
+ SerialIo devices' BDF is configurable
+
+ @param[in] SerialIoNumber Serial IO device
+
+ @retval SerialIo device number
+**/
+UINT8
+GetSerialIoDeviceNumber (
+ IN PCH_SERIAL_IO_CONTROLLER SerialIoNumber
+ );
+
+/**
+ Finds PCI Function Number of SerialIo devices.
+ SerialIo devices' BDF is configurable
+
+ @param[in] SerialIoNumber Serial IO device
+
+ @retval SerialIo funciton number
+**/
+UINT8
+GetSerialIoFunctionNumber (
+ IN PCH_SERIAL_IO_CONTROLLER SerialIoNumber
+ );
+
+/**
+ Finds BAR values of SerialIo devices.
+ SerialIo devices can be configured to not appear on PCI so traditional method of reading BAR might not work.
+
+ @param[in] SerialIoDevice Serial IO device
+ @param[in] BarNumber 0=BAR0, 1=BAR1
+
+ @retval SerialIo Bar value
+**/
+UINTN
+FindSerialIoBar (
+ IN PCH_SERIAL_IO_CONTROLLER SerialIoDevice,
+ IN UINT8 BarNumber
+ );
+
+/**
+ Checks if given device corresponds to any of LPSS Devices
+
+ @param[in] DeviceNumber device number
+ @param[in] FunctionNumber function number
+
+ @retval TRUE if SerialIO Device/Function Number is equal to any of LPSS devices
+ FALSE Device/Function is not in Serial IO scope
+**/
+BOOLEAN
+IsSerialIoDevice (
+ IN UINT8 DeviceNumber,
+ IN UINT8 FunctionNumber
+ );
+
+/**
+ Checks if given Serial IO Controller is enabled or not
+
+ @param[in] DeviceNumber device number
+ @param[in] FunctionNumber function number
+
+ @retval TRUE TRUE if given serial io device is enabled.
+ @retval FALSE FALSE if given serial io device is disabled.
+**/
+BOOLEAN
+IsSerialIoDeviceEnabled (
+ IN UINT8 DeviceNumber,
+ IN UINT8 FunctionNumber
+ );
+
+/**
+ Gets Pci Config control offset
+
+ @param[in] DeviceNumber device number
+ @param[in] FunctionNumber function number
+
+ @retval CfgCtrAddr Offset of Pci config control
+ 0 if Device and Function do not correspond to Serial IO
+**/
+UINT16
+GetSerialIoConfigControlOffset (
+ IN UINT8 DeviceNumber,
+ IN UINT8 FunctionNumber
+ );
+
+#endif // _PEI_DXE_SMM_PCH_SERIAL_IO_LIB_H_
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSerialIoUartLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSerialIoUartLib.h
new file mode 100644
index 0000000000..f97051e97c
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSerialIoUartLib.h
@@ -0,0 +1,111 @@
+/** @file
+ Header file for PCH Serial IO UART Lib implementation.
+
+ Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_SERIAL_IO_UART_LIB_H_
+#define _PCH_SERIAL_IO_UART_LIB_H_
+
+typedef enum {
+ AccessMode8bit,
+ AccessMode32bit
+} UART_ACCESS_MODE;
+
+/**
+ Returns UART's currently active access mode, 8 or 32 bit
+
+ @param[in] MmioBase Base address of UART MMIO space
+
+ @retval AccessMode8bit
+ @retval AccessMode32bit
+**/
+UART_ACCESS_MODE
+DetectAccessMode (
+ IN UINTN MmioBase
+ );
+
+/**
+ Initialize selected SerialIo UART.
+
+ @param[in] UartNumber Selects Serial IO UART device (0-2)
+ @param[in] FifoEnable When TRUE, enables 64-byte FIFOs.
+ @param[in] BaudRate Baud rate.
+ @param[in] LineControl Data length, parity, stop bits.
+ @param[in] HardwareFlowControl Automated hardware flow control. If TRUE, hardware automatically checks CTS when sending data, and sets RTS when receiving data.
+**/
+VOID
+EFIAPI
+PchSerialIoUartInit (
+ IN UINT8 UartNumber,
+ IN BOOLEAN FifoEnable,
+ IN UINT32 BaudRate,
+ IN UINT8 LineControl,
+ IN BOOLEAN HardwareFlowControl
+ );
+
+
+/**
+ Write data to serial device.
+
+ If the buffer is NULL, then return 0;
+ if NumberOfBytes is zero, then return 0.
+
+ @param[in] UartNumber Selects Serial IO UART device (0-2)
+ @param[in] Buffer Point of data buffer which need to be writed.
+ @param[in] NumberOfBytes Number of output bytes which are cached in Buffer.
+
+ @retval Actual number of bytes writed to serial device.
+**/
+UINTN
+EFIAPI
+PchSerialIoUartOut (
+ IN UINT8 UartNumber,
+ IN UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+);
+
+/*
+ Read data from serial device and save the datas in buffer.
+
+ If the buffer is NULL, then return 0;
+ if NumberOfBytes is zero, then return 0.
+
+ @param[in] UartNumber Selects Serial IO UART device (0-2)
+ @param[out] Buffer Point of data buffer which need to be writed.
+ @param[in] NumberOfBytes Number of output bytes which are cached in Buffer.
+ @param[in] WaitUntilBufferFull When TRUE, function waits until whole buffer is filled. When FALSE, function returns as soon as no new characters are available.
+
+ @retval Actual number of bytes raed from serial device.
+
+**/
+UINTN
+EFIAPI
+PchSerialIoUartIn (
+ IN UINT8 UartNumber,
+ OUT UINT8 *Buffer,
+ IN UINTN NumberOfBytes,
+ IN BOOLEAN WaitUntilBufferFull
+);
+
+/**
+ Polls a serial device to see if there is any data waiting to be read.
+ If there is data waiting to be read from the serial device, then TRUE is returned.
+ If there is no data waiting to be read from the serial device, then FALSE is returned.
+
+ @param[in] UartNumber Selects Serial IO UART device (0-2)
+
+ @retval TRUE Data is waiting to be read from the serial device.
+ @retval FALSE There is no data waiting to be read from the serial device.
+
+**/
+BOOLEAN
+EFIAPI
+PchSerialIoUartPoll (
+ IN UINT8 UartNumber
+ );
+
+
+#endif // _PEI_DXE_SMM_PCH_SERIAL_IO_UART_LIB_H_
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSmmControlLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSmmControlLib.h
new file mode 100644
index 0000000000..34b9867c34
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSmmControlLib.h
@@ -0,0 +1,23 @@
+/** @file
+ Header file for SMM Control PEI Library.
+
+ Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_SMM_CONTROL_LIB_H_
+#define _PCH_SMM_CONTROL_LIB_H_
+
+/**
+ This function install PEI SMM Control PPI
+
+ @retval EFI_STATUS Results of the installation of the SMM Control PPI
+**/
+EFI_STATUS
+EFIAPI
+PchSmmControlInit (
+ VOID
+ );
+
+#endif
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchWdtCommonLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchWdtCommonLib.h
new file mode 100644
index 0000000000..69b9c1cdb7
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchWdtCommonLib.h
@@ -0,0 +1,121 @@
+/** @file
+ Library that contains common parts of WdtPei and WdtDxe. Not a standalone module.
+
+ Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_WDT_COMMON_LIB_H_
+#define _PCH_WDT_COMMON_LIB_H_
+
+extern UINT8 mAllowExpectedReset;
+
+/**
+ Reads LPC bridge to get Watchdog Timer address
+
+
+ @retval UINT32 Watchdog's address
+**/
+UINT32
+WdtGetAddress (
+ VOID
+ );
+
+/**
+ Reloads WDT with new timeout value and starts it. Also sets Unexpected Reset bit, which
+ causes the next reset to be treated as watchdog expiration - unless AllowKnownReset()
+ function was called too.
+
+ @param[in] TimeoutValue Time in seconds before WDT times out. Supported range = 1 - 1024.
+
+ @retval EFI_SUCCESS if everything's OK
+ @retval EFI_INVALID_PARAMETER if TimeoutValue parameter is wrong
+**/
+EFI_STATUS
+EFIAPI
+WdtReloadAndStart (
+ IN UINT32 TimeoutValue
+ );
+
+/**
+ Disables WDT timer.
+
+
+**/
+VOID
+EFIAPI
+WdtDisable (
+ VOID
+ );
+
+/**
+ Returns WDT failure status.
+
+
+ @retval V_PCH_OC_WDT_CTL_STATUS_FAILURE If there was WDT expiration or unexpected reset
+ @retval V_PCH_OC_WDT_CTL_STATUS_OK Otherwise
+**/
+UINT8
+EFIAPI
+WdtCheckStatus (
+ VOID
+ );
+
+/**
+ Normally, each reboot performed while watchdog runs is considered a failure.
+ This function allows platform to perform expected reboots with WDT running,
+ without being interpreted as failures.
+ In DXE phase, it is enough to call this function any time before reset.
+ In PEI phase, between calling this function and performing reset, ReloadAndStart()
+ must not be called.
+
+
+**/
+VOID
+EFIAPI
+WdtAllowKnownReset (
+ VOID
+ );
+
+/**
+ Returns information if WDT coverage for the duration of BIOS execution
+ was requested by an OS application
+
+
+ @retval TRUE if WDT was requested
+ @retval FALSE if WDT was not requested
+**/
+UINT8
+EFIAPI
+IsWdtRequired (
+ VOID
+ );
+
+/**
+ Returns WDT enabled/disabled status.
+
+
+ @retval TRUE if WDT is enabled
+ @retval FALSE if WDT is disabled
+**/
+UINT8
+EFIAPI
+IsWdtEnabled (
+ VOID
+ );
+
+/**
+ Returns WDT locked status.
+
+
+ @retval TRUE if WDT is locked
+ @retval FALSE if WDT is unlocked
+**/
+UINT8
+EFIAPI
+IsWdtLocked (
+ VOID
+ );
+
+#endif
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PmcLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PmcLib.h
new file mode 100644
index 0000000000..f1a2600216
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PmcLib.h
@@ -0,0 +1,207 @@
+/** @file
+ Header file for PmcLib.
+
+ Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PMC_LIB_H_
+#define _PMC_LIB_H_
+
+#pragma pack(1)
+
+typedef enum {
+ PmcNotASleepState,
+ PmcInS0State,
+ PmcS1SleepState,
+ PmcS2SleepState,
+ PmcS3SleepState,
+ PmcS4SleepState,
+ PmcS5SleepState,
+ PmcUndefinedState,
+} PMC_SLEEP_STATE;
+
+typedef struct {
+ UINT32 Buf0;
+ UINT32 Buf1;
+ UINT32 Buf2;
+ UINT32 Buf3;
+} PMC_IPC_COMMAND_BUFFER;
+
+#pragma pack()
+
+/**
+ Get PCH ACPI base address.
+
+ @retval Address Address of PWRM base address.
+**/
+UINT16
+PmcGetAcpiBase (
+ VOID
+ );
+
+/**
+ Get PCH PWRM base address.
+
+ @retval Address Address of PWRM base address.
+**/
+UINT32
+PmcGetPwrmBase (
+ VOID
+ );
+
+/**
+ This function checks if RTC Power Failure occurred by
+ reading RTC_PWR_FLR bit
+
+ @retval RTC Power Failure state: TRUE - Battery is always present.
+ FALSE - CMOS is cleared.
+**/
+BOOLEAN
+PmcIsRtcBatteryGood (
+ VOID
+ );
+
+/**
+ This function checks if Power Failure occurred by
+ reading PWR_FLR bit
+
+ @retval Power Failure state
+**/
+BOOLEAN
+PmcIsPowerFailureDetected (
+ VOID
+ );
+
+/**
+ This function checks if RTC Power Failure occurred by
+ reading SUS_PWR_FLR bit
+
+ @retval SUS Power Failure state
+**/
+BOOLEAN
+PmcIsSusPowerFailureDetected (
+ VOID
+ );
+
+/**
+ This function clears Power Failure status (PWR_FLR)
+**/
+VOID
+PmcClearPowerFailureStatus (
+ VOID
+ );
+
+/**
+ This function clears Global Reset status (GBL_RST_STS)
+**/
+VOID
+PmcClearGlobalResetStatus (
+ VOID
+ );
+
+/**
+ This function clears Host Reset status (HOST_RST_STS)
+**/
+VOID
+PmcClearHostResetStatus (
+ VOID
+ );
+
+/**
+ This function clears SUS Power Failure status (SUS_PWR_FLR)
+**/
+VOID
+PmcClearSusPowerFailureStatus (
+ VOID
+ );
+
+/**
+ This function sets state to which platform will get after power is reapplied
+
+ @param[in] PowerStateAfterG3 0: S0 state (boot)
+ 1: S5/S4 State
+**/
+VOID
+PmcSetPlatformStateAfterPowerFailure (
+ IN UINT8 PowerStateAfterG3
+ );
+
+/**
+ This function enables Power Button SMI
+**/
+VOID
+PmcEnablePowerButtonSmi (
+ VOID
+ );
+
+/**
+ This function disables Power Button SMI
+**/
+VOID
+PmcDisablePowerButtonSmi (
+ VOID
+ );
+
+/**
+ This function reads PM Timer Count driven by 3.579545 MHz clock
+
+ @retval PM Timer Count
+**/
+UINT32
+PmcGetTimerCount (
+ VOID
+ );
+
+/**
+ Get Sleep Type that platform has waken from
+
+ @retval SleepType Sleep Type
+**/
+PMC_SLEEP_STATE
+PmcGetSleepTypeAfterWake (
+ VOID
+ );
+
+/**
+ Clear PMC Wake Status
+**/
+VOID
+PmcClearWakeStatus (
+ VOID
+ );
+
+/**
+ Check if platform boots after shutdown caused by power button override event
+
+ @retval TRUE Power Button Override occurred in last system boot
+ @retval FALSE Power Button Override didn't occur
+**/
+BOOLEAN
+PmcIsPowerButtonOverrideDetected (
+ VOID
+ );
+
+/**
+ This function checks if SMI Lock is set
+
+ @retval SMI Lock state
+**/
+BOOLEAN
+PmcIsSmiLockSet (
+ VOID
+ );
+
+/**
+ Check global SMI enable is set
+
+ @retval TRUE Global SMI enable is set
+ FALSE Global SMI enable is not set
+**/
+BOOLEAN
+PmcIsGblSmiEn (
+ VOID
+ );
+
+#endif // _PMC_LIB_H_
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SataLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SataLib.h
new file mode 100644
index 0000000000..047d543009
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SataLib.h
@@ -0,0 +1,76 @@
+/** @file
+ Header file for PchSataLib.
+
+ Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_SATA_LIB_H_
+#define _PCH_SATA_LIB_H_
+
+#define SATA_1_CONTROLLER_INDEX 0
+#define SATA_2_CONTROLLER_INDEX 1
+#define SATA_3_CONTROLLER_INDEX 2
+
+/**
+ Get Pch Maximum Sata Port Number
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval Pch Maximum Sata Port Number
+**/
+UINT8
+GetPchMaxSataPortNum (
+ IN UINT32 SataCtrlIndex
+ );
+
+/**
+ Gets Maximum Sata Controller Number
+
+ @param[in] None
+
+ @retval Maximum Sata Controller Number
+**/
+UINT8
+GetPchMaxSataControllerNum (
+ VOID
+ );
+
+/**
+ Gets SATA controller PCIe Device Number
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval SATA controller PCIe Device Number
+**/
+UINT8
+GetSataPcieDeviceNum (
+ IN UINT32 SataCtrlIndex
+ );
+
+/**
+ Gets SATA controller PCIe Function Number
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval SATA controller PCIe Function Number
+**/
+UINT8
+GetSataPcieFunctionNum (
+ IN UINT32 SataCtrlIndex
+ );
+
+/**
+ Gets SATA controller PCIe config space base address
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval SATA controller PCIe config space base address
+**/
+UINT64
+GetSataRegBase (
+ IN UINT32 SataCtrlIndex
+ );
+
+#endif // _PCH_SATA_LIB_H_
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SecPchLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SecPchLib.h
new file mode 100644
index 0000000000..53283597e7
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SecPchLib.h
@@ -0,0 +1,22 @@
+/** @file
+ Header file for SEC PCH Lib.
+ All function in this library is available for SEC
+
+ Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SEC_PCH_LIB_H_
+#define _SEC_PCH_LIB_H_
+
+/**
+ This function do the PCH cycle decoding initialization.
+**/
+VOID
+EFIAPI
+EarlyCycleDecoding (
+ VOID
+ );
+
+#endif // _SEC_PCH_LIB_H_
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SpiFlashCommonLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SpiFlashCommonLib.h
new file mode 100644
index 0000000000..53c11bb59a
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SpiFlashCommonLib.h
@@ -0,0 +1,98 @@
+/** @file
+ The header file includes the common header files, defines
+ internal structure and functions used by SpiFlashCommonLib.
+
+ Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __SPI_FLASH_COMMON_LIB_H__
+#define __SPI_FLASH_COMMON_LIB_H__
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#define SECTOR_SIZE_4KB 0x1000 // Common 4kBytes sector size
+/**
+ Enable block protection on the Serial Flash device.
+
+ @retval EFI_SUCCESS Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashLock (
+ VOID
+ );
+
+/**
+ Read NumBytes bytes of data from the address specified by
+ PAddress into Buffer.
+
+ @param[in] Address The starting physical address of the read.
+ @param[in,out] NumBytes On input, the number of bytes to read. On output, the number
+ of bytes actually read.
+ @param[out] Buffer The destination data buffer for the read.
+
+ @retval EFI_SUCCESS Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashRead (
+ IN UINTN Address,
+ IN OUT UINT32 *NumBytes,
+ OUT UINT8 *Buffer
+ );
+
+/**
+ Write NumBytes bytes of data from Buffer to the address specified by
+ PAddresss.
+
+ @param[in] Address The starting physical address of the write.
+ @param[in,out] NumBytes On input, the number of bytes to write. On output,
+ the actual number of bytes written.
+ @param[in] Buffer The source data buffer for the write.
+
+ @retval EFI_SUCCESS Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashWrite (
+ IN UINTN Address,
+ IN OUT UINT32 *NumBytes,
+ IN UINT8 *Buffer
+ );
+
+/**
+ Erase the block starting at Address.
+
+ @param[in] Address The starting physical address of the block to be erased.
+ This library assume that caller garantee that the PAddress
+ is at the starting address of this block.
+ @param[in] NumBytes On input, the number of bytes of the logical block to be erased.
+ On output, the actual number of bytes erased.
+
+ @retval EFI_SUCCESS. Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashBlockErase (
+ IN UINTN Address,
+ IN UINTN *NumBytes
+ );
+
+#endif
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SpiLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SpiLib.h
new file mode 100644
index 0000000000..e56f3139d7
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SpiLib.h
@@ -0,0 +1,23 @@
+/** @file
+ Header file for Spi Library.
+
+ Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SPI_LIB_H_
+#define _SPI_LIB_H_
+
+/**
+ This function Initial SPI services
+
+ @retval EFI_STATUS Results of the installation of the SPI services
+**/
+EFI_STATUS
+EFIAPI
+SpiServiceInit (
+ VOID
+ );
+
+#endif
--
2.16.2.windows.1
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