[edk2-devel] [edk2-platforms][PATCH V1 01/37] CoffeelakeSiliconPkg: Add package and Include headers
Chiu, Chasel
chasel.chiu at intel.com
Sat Aug 17 01:08:20 UTC 2019
Reviewed-by: Chasel Chiu <chasel.chiu at intel.com>
> -----Original Message-----
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:15 AM
> To: devel at edk2.groups.io
> Cc: Chaganty, Rangasai V <rangasai.v.chaganty at intel.com>; Chiu, Chasel
> <chasel.chiu at intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone at intel.com>; Gao, Liming <liming.gao at intel.com>;
> Kinney, Michael D <michael.d.kinney at intel.com>; Sinha, Ankit
> <ankit.sinha at intel.com>
> Subject: [edk2-platforms][PATCH V1 01/37] CoffeelakeSiliconPkg: Add package
> and Include headers
>
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082
>
> Create the CoffeelakeSiliconPkg to provide an initial package for
> silicon initialization code for Coffee Lake (CFL) and Whiskey Lake
> (WHL) generation products.
>
> * Major areas of functionality are categorized into CPU, Management
> Engine (ME), Platform Controller Hub (PCH), and System Agent
> subdirectories.
> * Common libraries and headers are kept at the root of the package.
>
> Cc: Sai Chaganty <rangasai.v.chaganty at intel.com>
> Cc: Chasel Chiu <chasel.chiu at intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone at intel.com>
> Cc: Liming Gao <liming.gao at intel.com>
> Cc: Michael D Kinney <michael.d.kinney at intel.com>
> Cc: Ankit Sinha <ankit.sinha at intel.com>
> Signed-off-by: Michael Kubacki <michael.a.kubacki at intel.com>
> ---
> Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec | 714
> ++++++++++++++++++++
> Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock.h | 53
> ++
> Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock/SiConfig.h |
> 89 +++
> Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock/UsbConfig.h |
> 291 ++++++++
> Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/AslUpdateLib.h |
> 157 +++++
> Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/ConfigBlockLib.h |
> 64 ++
> Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/MmPciLib.h | 28
> +
> Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h |
> 123 ++++
> Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiConfigBlockLib.h |
> 58 ++
> Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiPolicyLib.h | 110
> +++
> Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/StallPpiLib.h | 22
> +
> Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/UsbLib.h | 34
> +
> Silicon/Intel/CoffeelakeSiliconPkg/Include/PcieRegs.h | 319
> +++++++++
> Silicon/Intel/CoffeelakeSiliconPkg/Include/Ppi/SiPolicy.h | 29 +
> Silicon/Intel/CoffeelakeSiliconPkg/Include/Private/Library/PcieInitLib.h |
> 26 +
> Silicon/Intel/CoffeelakeSiliconPkg/Include/Private/Library/UsbInitLib.h |
> 71 ++
> Silicon/Intel/CoffeelakeSiliconPkg/Include/Protocol/SiPolicyProtocol.h |
> 60 ++
> Silicon/Intel/CoffeelakeSiliconPkg/Include/Register/RegsUsb.h | 55
> ++
> Silicon/Intel/CoffeelakeSiliconPkg/Include/SiConfigHob.h | 19 +
> Silicon/Intel/CoffeelakeSiliconPkg/Include/SiPolicyStruct.h | 65
> ++
> Silicon/Intel/CoffeelakeSiliconPkg/Include/TraceHubCommonConfig.h
> | 23 +
> 21 files changed, 2410 insertions(+)
>
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec
> b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec
> new file mode 100644
> index 0000000000..fa8c11e93d
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec
> @@ -0,0 +1,714 @@
> +## @file
> +# Component description file for the Silicon Reference Code.
> +#
> +# Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> +DEC_SPECIFICATION = 0x00010017
> +PACKAGE_NAME = SiPkg
> +PACKAGE_VERSION = 0.1
> +PACKAGE_GUID = F245E276-44A0-46b3-AEB5-9898BBCF008D
> +
> +[Includes]
> + Include
> + SampleCode/Include
> + SampleCode/MdeModulePkg/Include
> + SampleCode/IntelFrameworkPkg/Include
> + #
> + # SystemAgent
> + #
> + SystemAgent/Include
> + SystemAgent/MemoryInit/Include
> + SystemAgent/AcpiTables
> + #
> + # Cpu
> + #
> + Cpu/Include
> + #
> + # Me
> + #
> + Me/Include
> + #
> + # Pch
> + #
> + Pch/Include
> +
> +[Guids.common.Private]
> + #
> + # PCH
> + #
> + gPchDeviceTableHobGuid = { 0xb3e123d0, 0x7a1e, 0x4db4, { 0xaf, 0x66,
> 0xbe, 0xd4, 0x1e, 0x9c, 0x66, 0x38 }}
> + gPchConfigHobGuid = { 0x524ed3ca, 0xb250, 0x49f5, { 0x94, 0xd9,
> 0xa2, 0xba, 0xff, 0xc7, 0x0e, 0x14 }}
> + gGpioLibUnlockHobGuid = { 0xA7892E49, 0x0F9F, 0x4166, { 0xB8, 0xD6,
> 0x8A, 0x9B, 0xD9, 0x8B, 0x17, 0x38 }}
> + gSiScheduleResetHobGuid = { 0xEA0597FF, 0x8858, 0x41CA, { 0xBB, 0xC1,
> 0xFE, 0x18, 0xFC, 0xD2, 0x8E, 0x22 }}
> +
> +[Guids]
> +##
> +## MdeModulePkg
> +##
> +gEfiMemoryTypeInformationGuid = {0x4c19049f, 0x4137, 0x4dd3, {0x9c,
> 0x10, 0x8b, 0x97, 0xa8, 0x3f, 0xfd, 0xfa}}
> +gEfiCapsuleVendorGuid = {0x711c703f, 0xc285, 0x4b10, {0xa3, 0xb0, 0x36,
> 0xec, 0xbd, 0x3c, 0x8b, 0xe2}}
> +gEfiConsoleOutDeviceGuid = { 0xd3b36f2c, 0xd551, 0x11d4, { 0x9a, 0x46, 0x0,
> 0x90, 0x27, 0x3f, 0xc1, 0x4d}}
> +
> +##
> +## IntelFrameworkPkg
> +##
> +gEfiSmmPeiSmramMemoryReserveGuid = {0x6dadf1d1, 0xd4cc, 0x4910,
> {0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d}}
> +
> +##
> +## Common
> +##
> +## Include/ConfigBlock/SiConfig.h
> +gSiConfigGuid = {0x4ed6d282, 0x22f3, 0x4fe1, {0xa6, 0x61, 0x6, 0x1a, 0x97,
> 0x38, 0x59, 0xd8 }}
> +gSiPkgTokenSpaceGuid = {0x977c97c1, 0x47e1, 0x4b6b, {0x96, 0x69, 0x43,
> 0x66, 0x99, 0xcb, 0xe4, 0x5b}}
> +
> +## Include/SiConfigHob.h
> +gSiConfigHobGuid = {0xb3903068, 0x7482, 0x4424, {0xba, 0x4b, 0x40, 0x5f,
> 0x8f, 0xd7, 0x65, 0x4e}}
> +
> +##
> +## System Agent
> +##
> +gSaAcpiTableStorageGuid = {0x3c0ed5e2, 0x91ea, 0x4b94, { 0x82, 0xd, 0x9d,
> 0xaf, 0x9a, 0x3b, 0xb4, 0xa2}}
> +gSaDataHobGuid = {0xe07d0bda, 0xbf90, 0x46a9, { 0xb0, 0x0e, 0xb2, 0xc4,
> 0x4a, 0x0e, 0xd6, 0xd0}}
> +gSaConfigHobGuid = {0x762fa2e6, 0xea3b, 0x41c8, { 0x8c, 0x52, 0x63, 0x76,
> 0x6d, 0x70, 0x39, 0xe0}}
> +gSaPegHobGuid = {0x440ab2e5, 0xa3ea, 0x466f, { 0x84, 0x96, 0xdf, 0xb1,
> 0x3b, 0x75, 0x29, 0x95}}
> +gSgAcpiTableStorageGuid = {0x8de8964f, 0x2939, 0x4b49, { 0xa3, 0x48, 0xf6,
> 0xb2, 0xb2, 0xde, 0x4a, 0x42}}
> +gSaSsdtAcpiTableStorageGuid = {0xca89914d, 0x2317, 0x452e, { 0xb2, 0x45,
> 0x36, 0xc6, 0xfb, 0x77, 0xa9, 0xc6}}
> +gPegSsdtAcpiTableStorageGuid = {0xE05B8635, 0xE5C0, 0x4D88, { 0xB6,
> 0x29, 0x19, 0xD6, 0xA2, 0xC6, 0xE9, 0x2E}}
> +gSgAcpiTablePchStorageGuid = {0xe3164526, 0x690a, 0x4e0d, { 0xb0, 0x28,
> 0xae, 0xa1, 0x6f, 0xe2, 0xbc, 0xf3}}
> +gSaMiscPeiPreMemConfigGuid = {0x4a525577, 0x3469, 0x4f11, { 0x99, 0xcf,
> 0xfb, 0xcd, 0x5e, 0xf1, 0x84, 0xe4}}
> +gSaMiscPeiConfigGuid = {0x1def8e6, 0xe998, 0x4e27, { 0x89, 0x98, 0x9c,
> 0xfa, 0xb2, 0x92, 0xbc, 0x50}}
> +gSaPciePeiPreMemConfigGuid = { 0x81baf3c9, 0xf295, 0x4572, { 0x8b, 0x21,
> 0x79, 0x3f, 0xa3, 0x1b, 0xa5, 0xdb}}
> +gSaPciePeiConfigGuid = { 0xdaa929a9, 0x5ec9, 0x486a, { 0xb0, 0xf7, 0x82,
> 0x3a, 0x55, 0xc7, 0xb5, 0xb3}}
> +gGraphicsPeiPreMemConfigGuid = { 0x0319c56b, 0xc43a, 0x42f1, { 0x80,
> 0xbe, 0xca, 0x5b, 0xd1, 0xd5, 0xc9, 0x28}}
> +gGraphicsPeiConfigGuid = { 0x04249ac0, 0x0088, 0x439f, { 0xa7, 0x4e, 0xa7,
> 0x04, 0x2a, 0x06, 0x2f, 0x5d}}
> +gSwitchableGraphicsConfigGuid = { 0xc7956998, 0xc065, 0x46c4, { 0x8e,
> 0x2f, 0x58, 0x2b, 0x67, 0xeb, 0xbe, 0x2f}}
> +gCpuTraceHubConfigGuid = { 0xf2e17477, 0x93f3, 0x430d, { 0x9e, 0x08, 0x3c,
> 0xcc, 0x6e, 0x2f, 0x6c, 0x4b}}
> +gMemoryConfigGuid = { 0x26cf084c, 0xc9db, 0x41bb, { 0x92, 0xc6, 0xd1,
> 0x97, 0xb8, 0xa1, 0xe4, 0xbf}}
> +gMemoryConfigNoCrcGuid = { 0xc56c73d0, 0x1cdb, 0x4c0c, { 0xa9, 0x57,
> 0xea, 0x62, 0xa9, 0xe6, 0xf5, 0x0c}}
> +gIpuPreMemConfigGuid = { 0x830a222b, 0x3ff5, 0x432e, { 0x9d, 0xd5, 0x4e,
> 0xe3, 0xfc, 0xa2, 0xaa, 0xa2}}
> +gGnaConfigGuid = { 0x53e0ef18, 0xb8a8, 0x4795, { 0xa6, 0x6d, 0xe4, 0x77,
> 0x2c, 0xc3, 0xae, 0x82}}
> +gVtdConfigGuid = { 0x03e5cf63, 0xbebb, 0x4041, { 0xb7, 0xe7, 0xbf, 0x54,
> 0x61, 0x20, 0xf1, 0xc5}}
> +gGraphicsDxeConfigGuid = {0x34d93161, 0xf78e, 0x4915, {0xad, 0xc4, 0xdb,
> 0x67, 0x16, 0x42, 0x39, 0x24}}
> +gMiscDxeConfigGuid = {0x7ce5f5ef, 0x4ef1, 0x4f9f, {0x8e, 0x29, 0x5f, 0xf4,
> 0x5f, 0x2f, 0xd8, 0xaf}}
> +gPcieDxeConfigGuid = {0x1ed2d6f1, 0xa9d2, 0x476e, {0x8e, 0x74, 0xad,
> 0xd9, 0x5b, 0x5, 0x10, 0x82}}
> +gMemoryDxeConfigGuid = {0xa5c7dda8, 0x686b, 0x404f, {0x86, 0x40, 0xf8,
> 0x2, 0xd, 0x84, 0x4c, 0x94}}
> +gVbiosDxeConfigGuid = {0x8df0f30a, 0x8156, 0x4897, {0xa2, 0x18, 0x1f,
> 0xd3, 0x91, 0xbc, 0x46, 0x26}}
> +gSaOverclockingPreMemConfigGuid = { 0x09ecc29d, 0xdbbe, 0x49fb, { 0xa6,
> 0x49, 0x4b, 0xf6, 0x40, 0xe2, 0xeb, 0xd6}}
> +gFspReservedMemoryResourceHobTsegGuid = { 0xd038747c, 0xd00c,
> 0x4980, { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55}}
> +
> +## Include/Guid/AcpiS3Context.h
> +gEfiAcpiVariableGuid = {0xaf9ffd67, 0xec10, 0x488a, {0x9d, 0xfc, 0x6c, 0xbf,
> 0x5e, 0xe2, 0x2c, 0x2e}}
> +
> +## IntelFsp2Pkg/IntelFsp2Pkg.dec gSiMemoryS3DataGuid is the same as
> gFspNonVolatileStorageHobGuid
> +gSiMemoryS3DataGuid = { 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27,
> 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 } }
> +gSiMemoryInfoDataGuid = { 0x9b2071d4, 0xb054, 0x4e0c, { 0x8d, 0x09,
> 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 } }
> +gSiMemoryPlatformDataGuid = { 0x6210d62f, 0x418d, 0x4999, { 0xa2, 0x45,
> 0x22, 0x10, 0x0a, 0x5d, 0xea, 0x44 } }
> +
> +## Include/MrcRmtData.h
> +gEfiMemorySchemaGuid = { 0xCE3F6794, 0x4883, 0x492C, { 0x8D, 0xBA, 0x2F,
> 0xC0, 0x98, 0x44, 0x77, 0x10}}
> +gMrcSchemaListHobGuid = { 0x3047C2AC, 0x5E8E, 0x4C55, { 0xA1, 0xCB, 0xEA,
> 0xAD, 0x0A, 0x88, 0x86, 0x1B}}
> +
> +## Include/SsaCommonConfig.h
> +gSsaPostcodeHookGuid = {0xADF0A27B, 0x61A6, 0x4F18, {0x9E, 0xAC, 0x46,
> 0x87, 0xE7, 0x9E, 0x6F, 0xBB}}
> +gSsaBiosVariablesGuid = {0x43eeffe8, 0xa978, 0x41dc, {0x9d, 0xb6, 0x54, 0xc4,
> 0x27, 0xf2, 0x7e, 0x2a}}
> +gSsaBiosResultsGuid = {0x8f4e928, 0xf5f, 0x46d4, {0x84, 0x10, 0x47, 0x9f, 0xda,
> 0x27, 0x9d, 0xb6}}
> +gHobUsageDataGuid = {0xc764a821, 0xec41, 0x450d, { 0x9c, 0x99, 0x27, 0x20,
> 0xfc, 0x7c, 0xe1, 0xf6 }}
> +
> +##
> +## Cpu
> +##
> +gSmramCpuDataHeaderGuid = {0x5848fd2d, 0xd6af, 0x474b, {0x82, 0x75,
> 0x95, 0xdd, 0xe7, 0x0a, 0xe8, 0x23}}
> +gCpuAcpiTableStorageGuid = {0xc38fb0e2, 0x0c43, 0x49c9, {0xb5, 0x44,
> 0x9b, 0x17, 0xaa, 0x4d, 0xcb, 0xa3}}
> +gHtBistHobGuid = {0xbe644001, 0xe7d4, 0x48b1, {0xb0, 0x96, 0x8b, 0xa0,
> 0x47, 0xbc, 0x7a, 0xe7}}
> +gCpuInitDataHobGuid = {0x266e31cc, 0x13c5, 0x4807, {0xb9, 0xdc, 0x39,
> 0xa6, 0xba, 0x88, 0xff, 0x1a}}
> +gEpcBiosDataGuid = {0xc60aa7f6, 0xe8d6, 0x4956, {0x8b, 0xa1, 0xfe, 0x26,
> 0x29, 0x8f, 0x5e, 0x87}}
> +gCpuSecurityPreMemConfigGuid = {0xfd5c346, 0x8260, 0x4067, {0x94, 0x69,
> 0xcf, 0x91, 0x68, 0xa3, 0x42, 0x90}}
> +gCpuConfigLibPreMemConfigGuid = {0xfc1c0ec2, 0xc6b4, 0x4f05, {0xbb, 0x85,
> 0xc8, 0x0, 0x8d, 0x5b, 0x4a, 0xb7}}
> +gCpuSgxConfigGuid = {0xc30bc5ac, 0x828a, 0x45ae, {0x83, 0x1b, 0x8e, 0xb,
> 0x73, 0x9a, 0xb2, 0xf2}}
> +gCpuTestConfigGuid = {0xd4dba957, 0xd9c, 0x4af2, {0x9d, 0x40, 0x35, 0xa8,
> 0x44, 0xe4, 0x93, 0xad}}
> +gCpuConfigGuid = {0x48c3aac9, 0xd66c, 0x42e4, {0x9b, 0x1d, 0x39, 0x4, 0x5f,
> 0x46, 0x53, 0x41}}
> +gCpuOverclockingPreMemConfigGuid = {0x396223b6, 0x6088, 0x44e7, {0x99,
> 0xcb, 0xfa, 0x8b, 0x99, 0x3d, 0xed, 0x4c}}
> +gCpuPidTestConfigGuid = {0x2511095f, 0xd49e, 0x4537, {0xa6, 0x60, 0x88,
> 0x71, 0x31, 0xd1, 0x53, 0xda}}
> +gCpuPowerMgmtBasicConfigGuid = {0xa021e31d, 0x7c14, 0x47da, {0xb5, 0xec,
> 0xca, 0xbb, 0x4d, 0x76, 0xed, 0xc8}}
> +gCpuPowerMgmtCustomConfigGuid = {0x562fa1c8, 0x55ee, 0x4e2f, {0x91,
> 0xca, 0x8d, 0x84, 0x50, 0x3, 0x2f, 0xe}}
> +gCpuPowerMgmtTestConfigGuid = {0x5161ed3d, 0x90bf, 0x436f, {0xb8, 0x33,
> 0xd7, 0x17, 0x89, 0xb3, 0x48, 0xc1}}
> +
> +##
> +## Me
> +##
> +gMePeiPreMemConfigGuid = {0x67ed113b, 0xd4ab, 0x43f5, {0x9c, 0x3c,
> 0x35, 0x44, 0x15, 0xaa, 0x47, 0x5c}}
> +gMePeiConfigGuid = {0x9bad5628, 0x657b, 0x48e3, {0xb1, 0x11, 0xc3, 0xb9,
> 0xeb, 0xea, 0xee, 0x17}}
> +gMeEopDoneHobGuid = {0x247323af, 0xc8f1, 0x4b8c, {0x90, 0x87, 0xaa, 0x4b,
> 0xa7, 0xb7, 0x6d, 0x6a}}
> +gMePreMemPolicyHobGuid = {0xe6de74a5, 0x21b, 0x4f78, {0xa3, 0xcd, 0x34,
> 0xd6, 0x7e, 0xe4, 0x82, 0xbf}}
> +gMePolicyHobGuid = {0x0341cf17, 0xbc8f, 0x4a20, {0xac, 0x28, 0x6c, 0x3c,
> 0x32, 0x4c, 0xd4, 0x17}}
> +
> +##
> +## PCH
> +##
> +gEfiSmbusArpMapGuid = {0x707be83e, 0x0bf6, 0x40a5, {0xbe, 0x64, 0x34,
> 0xc0, 0x3a, 0xa0, 0xb8, 0xe2}}
> +gIrmtAcpiTableStorageGuid = {0x6684d675, 0xee06, 0x49b2, {0x87, 0x6f,
> 0x79, 0xc5, 0x8f, 0xdd, 0xa5, 0xb7}}
> +gPchGlobalResetGuid = { 0x9db31b4c, 0xf5ef, 0x48bb, { 0x94, 0x2b, 0x18,
> 0x1f, 0x7e, 0x3a, 0x3e, 0x40 }}
> +gI2c0MasterGuid = {0xa121a5db, 0xb0cb, 0x46ec, {0xa0, 0xcb, 0x27, 0xf8,
> 0xda, 0x72, 0xd4, 0x0e}}
> +gI2c1MasterGuid = {0x55e3d0f9, 0xc954, 0x422d, {0x9c, 0x4c, 0xcc, 0x46,
> 0x12, 0x7c, 0x5b, 0xa8}}
> +gI2c2MasterGuid = {0x9289aa40, 0xdf32, 0x474e, {0xb0, 0x3a, 0xc7, 0x7f,
> 0x76, 0xd3, 0x45, 0x21}}
> +gI2c3MasterGuid = {0xd8b2c17f, 0x4117, 0x4166, {0x90, 0x17, 0x01, 0x68,
> 0xb4, 0x81, 0xac, 0x18}}
> +gI2c4MasterGuid = {0x513d943d, 0x15d9, 0x4bd0, {0xb1, 0x41, 0x14, 0x50,
> 0x2b, 0xbf, 0xa9, 0xf2}}
> +gI2c5MasterGuid = {0x50df382a, 0xb6bf, 0x4435, {0xae, 0xe6, 0x21, 0xf4,
> 0x85, 0x7c, 0xa8, 0xb4}}
> +gChipsetInitHobGuid = {0x8c7ee32c, 0x0870, 0x4bfa, {0x84, 0x79, 0x5b, 0xa5,
> 0x67, 0xc4, 0xae, 0x5b}}
> +
> +gPchGeneralPreMemConfigGuid = {0xC65F62FA, 0x52B9, 0x4837, {0x86,
> 0xEB, 0x1A, 0xFB, 0xD4, 0xAD, 0xBB, 0x3E}}
> +gDciPreMemConfigGuid = {0xAB4AF366, 0x2250, 0x40C3, {0x92, 0xDB, 0x36,
> 0x61, 0xC6, 0x71, 0x3C, 0x5A}}
> +gWatchDogPreMemConfigGuid = {0xFBCE08CC, 0x60F2, 0x4BDF, {0xB7,
> 0x88, 0x09, 0xBB, 0x81, 0x65, 0x52, 0x2B}}
> +gTraceHubPreMemConfigGuid = {0xC26AC3F6, 0xDAD0, 0x4E91, {0xB6,
> 0xD6, 0xD8, 0x51, 0x6F, 0x8F, 0x9B, 0x7B}}
> +gPchTraceHubPreMemConfigGuid = {0x8456c11, 0xdb85, 0x4914, {0x8d,
> 0x1a, 0xe5, 0xac, 0x64, 0x37, 0xe8, 0x96}}
> +gPcieRpPreMemConfigGuid = {0x8377AB38, 0xF8B0, 0x476A, { 0x9C, 0xA1,
> 0x68, 0xEA, 0x78, 0x57, 0xD8, 0x2A}}
> +gHpetPreMemConfigGuid = {0x7C75C0F1, 0xA20F, 0x42EB, {0x83, 0xDE,
> 0xE8, 0x58, 0xAB, 0x81, 0xC5, 0xDC}}
> +gSmbusPreMemConfigGuid = {0x77A6E62C, 0x716B, 0x4386, {0x9E, 0x9C,
> 0x23, 0xA0, 0x2E, 0x13, 0x7B, 0x3A}}
> +gLpcPreMemConfigGuid = {0xA6E6032F, 0x1E58, 0x407E, {0x9A, 0xB8, 0xC6,
> 0x30, 0xC6, 0xC4, 0x11, 0x8E}}
> +gHsioPciePreMemConfigGuid = {0xE8FB0C12, 0x0DA1, 0x4A20, {0xB3, 0x36,
> 0xFB, 0x75, 0x93, 0x8C, 0xE0, 0x14}}
> +gHsioSataPreMemConfigGuid = {0x732260D0, 0xA5C1, 0x4119, {0xAA, 0x0C,
> 0x93, 0xDC, 0xAC, 0x67, 0x0A, 0x31}}
> +gHsioPreMemConfigGuid = {0xbc9e5787, 0x3ddb, 0x4916, {0x8c, 0xcc, 0x82,
> 0xb8, 0x9, 0x43, 0xe2, 0xf0}} #deprecated
> +
> +gPchGeneralConfigGuid = {0x6ED94C8C, 0x25F7, 0x4686, {0xB2, 0x46, 0xCA,
> 0x4D, 0xE2, 0x95, 0x4B, 0x5D}}
> +gPcieRpConfigGuid = {0x0A53B507, 0x988B, 0x475C, {0xBF, 0x76, 0x33, 0xDE,
> 0x10, 0x6D, 0x94, 0x84}}
> +gSataConfigGuid = {0xF5F87B4F, 0xCC3C, 0x408D, {0x89, 0xE3, 0x61, 0xC5,
> 0x9C, 0x54, 0x07, 0xC4}}
> +gIoApicConfigGuid = {0x2873D0F1, 0x00F6, 0x40AB, {0xAC, 0x36, 0x9A, 0x68,
> 0xBA, 0x87, 0x3E, 0x6C}}
> +gCio2ConfigGuid = {0xFBC4C192, 0x789D, 0x4038, {0x90, 0xE1, 0x5E, 0x6D,
> 0xFD, 0x52, 0xAF, 0x8A}}
> +gDmiConfigGuid = {0xB3A61210, 0x1CD3, 0x4797, {0x8E, 0xE6, 0xD3, 0x42,
> 0x9C, 0x4F, 0x17, 0xBD}}
> +gFlashProtectionConfigGuid = {0xD0F71512, 0x9E32, 0x4CC9, {0xA5, 0xA3,
> 0xAD, 0x67, 0x9A, 0x06, 0x67, 0xB8}}
> +gHdAudioPreMemConfigGuid = {0xD38F1E2B, 0x21B3, 0x43D1, {0x9F, 0xA8,
> 0xA5, 0xE1, 0x78, 0x73, 0x1E, 0x88}}
> +gHdAudioConfigGuid = {0x7EB3CE7E, 0x82E0, 0x4CD7, {0xBD, 0xE5, 0xB2,
> 0xBF, 0x4E, 0x91, 0xC3, 0x4C}}
> +gHdAudioDxeConfigGuid = {0x22EFC2DE, 0x66EB, 0x412D, {0x97, 0x17, 0xE7,
> 0x7A, 0xA1, 0x4E, 0x87, 0x76}}
> +gInterruptConfigGuid = {0x09A2B815, 0xBE29, 0x45EF, {0xBF, 0xBF, 0x58,
> 0xEA, 0xAC, 0x5E, 0x29, 0x78}}
> +gIshPreMemConfigGuid = {0x7C24E649, 0xC1F0, 0x4CF9, {0x87, 0x96, 0xE7,
> 0xA0, 0xEE, 0x34, 0x43, 0xF8}}
> +gIshConfigGuid = {0x433AE2AA, 0xC5A6, 0x46ED, {0x94, 0x19, 0x1E, 0x5D,
> 0xB8, 0x1C, 0x57, 0x40}}
> +gLanConfigGuid = {0x4B2DE99E, 0x7517, 0x4D04, {0x8C, 0x02, 0xF1, 0x1A,
> 0x59, 0x2B, 0x14, 0x2F}}
> +gLockDownConfigGuid = {0x8A838E0A, 0xA639, 0x46F0, {0xA9, 0xCE, 0x70,
> 0xC4, 0x85, 0xFB, 0xA8, 0x0D}}
> +gP2sbConfigGuid = {0x2474DCB8, 0x4BB4, 0x49DA, {0x87, 0x83, 0x7C, 0xD3,
> 0xD3, 0x85, 0xFF, 0x07}}
> +gPmConfigGuid = {0x93826157, 0xDC85, 0x4E34, {0xAE, 0xD9, 0x6E, 0xA1,
> 0x0D, 0xF9, 0xE3, 0xA7}}
> +gPort61ConfigGuid = {0x59913475, 0x1960, 0x4099, {0x80, 0xEC, 0xAF, 0xC7,
> 0xCF, 0x5F, 0x9F, 0xAC}}
> +gScsConfigGuid = {0xF4DE6D52, 0xB5C9, 0x48C0, {0xA0, 0x4A, 0x68, 0x54,
> 0x20, 0x94, 0x05, 0xD0}}
> +gSerialIoConfigGuid = {0x6CC06EBF, 0x0D34, 0x4340, {0xBC, 0x16, 0xDA,
> 0x09, 0xE5, 0x78, 0x3A, 0xDB}}
> +gSerialIrqConfigGuid = {0x251701E7, 0xE266, 0x4623, {0x99, 0x68, 0x73,
> 0x8C, 0xD2, 0x23, 0x10, 0x96}}
> +gSpiConfigGuid = {0x150360EF, 0x99BE, 0x4E43, {0x94, 0xBB, 0xBD, 0x40,
> 0x26, 0xCA, 0x34, 0x57}}
> +gEspiConfigGuid = {0x60FBF3B8, 0x96D4, 0x4187, {0x84, 0x9E, 0xAA, 0xF7,
> 0x5C, 0x4B, 0xE1, 0xE3}}
> +gThermalConfigGuid = {0x4416506D, 0x1197, 0x4722, {0xA5, 0xB4, 0x46,
> 0x11, 0xF9, 0x23, 0x9E, 0xAE}}
> +gUsbConfigGuid = {0xB2DA9CCD, 0x6A8C, 0x4BB6, {0xB3, 0xE6, 0xCD, 0xFB,
> 0xB7, 0x66, 0x8B, 0xDE}}
> +gPchPcieStorageDetectHobGuid = {0xC682F3F4, 0x2F46, 0x495E, {0x98, 0xAA,
> 0x43, 0x14, 0x4B, 0xA5, 0xA4, 0x85}}
> +gCnviConfigGuid = {0xE53EBEF7, 0x103D, 0x4A70, {0x9B, 0x6A, 0x73, 0xEE,
> 0x5F, 0x4C, 0x8D, 0xF5}}
> +gHsioConfigGuid = {0xE53EBEE7, 0x103D, 0x4A71, {0x9B, 0x6A, 0x74, 0xEE,
> 0x5F, 0x4C, 0x8D, 0xF5}}
> +gPchRstHobGuid = {0x4ECA680C, 0x660D, 0x48F8, {0xAA, 0xD8, 0x94, 0xD6,
> 0x56, 0x10, 0xF9, 0x86}}
> +gPchInfoHobGuid = {0x99FD5E18, 0xE262, 0x4E6A, {0x82, 0x66, 0x77, 0xD0,
> 0x36, 0x5F, 0xD6, 0x3E}}
> +gGpioDxeConfigGuid = {0x06985984, 0xAFA3, 0x429C, {0x80, 0xCD, 0x69,
> 0x43, 0xF3, 0x38, 0x31, 0x4D}}
> +
> +##
> +## SecurityPkg
> +##
> +## GUID used to "Tcg2PhysicalPresence" variable and
> "Tcg2PhysicalPresenceFlags" variable for TPM2 request and response.
> +# Include/Guid/Tcg2PhysicalPresenceData.h
> +gEfiTcg2PhysicalPresenceGuid = { 0xaeb9c5c1, 0x94f1, 0x4d02, { 0xbf,
> 0xd9, 0x46, 0x2, 0xdb, 0x2d, 0x3c, 0x54 }}
> +gTpmDeviceInstanceTpm20PttGuid = {0x72cd3a7b, 0xfea5, 0x4f5e,
> {0x91, 0x65, 0x4d, 0xd1, 0x21, 0x87, 0xbb, 0x13}}
> +gTpmDeviceInstanceTpm20PttPtpGuid = {0x93d66f66, 0x55da, 0x4f03,
> {0x9b, 0x5f, 0x32, 0xcf, 0x9e, 0x54, 0x3b, 0x3a}}
> +gEfiTrEEPhysicalPresenceGuid = {0xf24643c2, 0xc622, 0x494e, {0x8a,
> 0x0d, 0x46, 0x32, 0x57, 0x9c, 0x2d, 0x5b}}
> +gTcoWdtHobGuid = { 0x3e405418, 0x0d8c, 0x4f1a, { 0xb0,
> 0x55, 0xbe, 0xf9, 0x08, 0x41, 0x46, 0x8d }}
> +
> +##
> +## Pre-Memory Performance
> +##
> +gPerfPchPrePolicyGuid = {0x3112356F, 0xCC77, 0x4E82, {0x86, 0xD5, 0x3E,
> 0x25, 0xEE, 0x81, 0x92, 0xA4}}
> +gPerfSiValidateGuid = {0x681F96E6, 0xF9CF, 0x464D, {0x97, 0x9A, 0xB1,
> 0x11, 0x33, 0xDE, 0x37, 0xA9}}
> +gPerfPchValidateGuid = {0xD0FF37D6, 0xA569, 0x4058, {0xB3, 0xDA, 0x29,
> 0x0B, 0x38, 0xC5, 0x32, 0x25}}
> +gPerfAmtValidateGuid = {0x9E949422, 0x4A7A, 0x4E41, {0xB0, 0xAB, 0x3C,
> 0x0D, 0x88, 0x0A, 0x00, 0xFF}}
> +gPerfCpuValidateGuid = {0xB760CFCC, 0xDEEF, 0x4C7E, {0x99, 0x5B, 0xED,
> 0xFE, 0xF2, 0x23, 0xB2, 0x09}}
> +gPerfMeValidateGuid = {0x8CF7A498, 0x588D, 0x4D39, {0xBD, 0xAC, 0x51,
> 0x0C, 0x31, 0xAF, 0x45, 0xD0}}
> +gPerfSaValidateGuid = {0xA73B382B, 0x62D4, 0x4A19, {0xBB, 0xF9, 0x09,
> 0x3E, 0xC5, 0xA5, 0x93, 0x11}}
> +gPerfHeciPreMemGuid = {0xD815D922, 0x4994, 0x40B3, {0x97, 0xCC,
> 0x07, 0xF3, 0x7D, 0x42, 0xE7, 0x97}}
> +gPerfPchPreMemGuid = {0xBB73E2B1, 0xB9FD, 0x4A80, {0xB8, 0x1A,
> 0x52, 0x39, 0xE9, 0x4D, 0x06, 0x2E}}
> +gPerfCpuPreMemGuid = {0xAC5FCBC6, 0x084D, 0x445D, {0xB3, 0xF3,
> 0xCA, 0x16, 0xDE, 0xE9, 0xBB, 0x47}}
> +gPerfMePreMemGuid = {0x6051338E, 0x0FFA, 0x40F7, {0xAF, 0xEF, 0xAB,
> 0x86, 0x7A, 0x38, 0xCC, 0xF3}}
> +gPerfAmtPreMemGuid = {0xDB732D50, 0x9BB8, 0x489A, {0xA1, 0xD1,
> 0xDD, 0xD2, 0x16, 0x1D, 0x72, 0xB8}}
> +gPerfAmtPostMemGuid = {0x0329D610, 0x4269, 0xD28F, {0x61, 0xBF,
> 0xB9, 0xA2, 0xD9, 0xFA, 0x96, 0x93}}
> +gPerfSaPreMemGuid = {0x76F18BDA, 0x2195, 0x4FB6, {0x9A, 0x94, 0x0E,
> 0x0B, 0xAC, 0xDE, 0xEC, 0xAB}}
> +gPerfEvlGuid = {0x8221518B, 0xAC19, 0x4E32, {0xAB, 0x5F, 0x00,
> 0x47, 0x0A, 0x50, 0x69, 0x40}}
> +gPerfMemGuid = {0x2B57B316, 0x5CF7, 0x4847, {0xB0, 0x76, 0x6B,
> 0x5D, 0x23, 0xC3, 0xAA, 0x3E}}
> +
> +##
> +## Post-Memory Performance
> +##
> +gPerfPchPostMemGuid = {0x70B67A99, 0x5556, 0x4315, {0xB3, 0x05,
> 0xD5, 0xDC, 0x4A, 0x35, 0x63, 0x70}}
> +gPerfSaPostMemGuid = {0x9FF0CE92, 0x883F, 0x43DC, {0x8A, 0x07, 0xE0,
> 0xCB, 0x6D, 0x56, 0x7D, 0xE0}}
> +gPerfS3CpuInitPostMemGuid = {0x976262C2, 0xD202, 0x4D12, {0x82, 0xAD,
> 0xF4, 0xA9, 0x8F, 0x9B, 0x96, 0x01}}
> +gPerfSaSecLockPostMemGuid = {0x272AC110, 0x0B60, 0x4D07, {0xA5, 0x58,
> 0x6D, 0x73, 0xE2, 0x43, 0x85, 0x95}}
> +gPerfCpuStrapPostMemGuid = {0x8EF4372B, 0x68F0, 0x4957, {0xBC, 0x4D,
> 0x7E, 0x5C, 0xFE, 0xDA, 0xB6, 0x3E}}
> +gPerfMpPostMemGuid = {0xA59BAC5B, 0xC6A4, 0x4AEB, {0x84, 0x32,
> 0x7A, 0x8B, 0x6B, 0x68, 0x5F, 0x37}}
> +gPerfCpuPostMemGuid = {0xE2FE5ED3, 0x1417, 0x451A, {0x95, 0xC9,
> 0xD0, 0xB2, 0xB9, 0x7B, 0xE0, 0x54}}
> +gPerfSaResetPostMemGuid = {0xBE152BEE, 0xFD19, 0x4274, {0xA8, 0xBA,
> 0xFB, 0x31, 0x42, 0xB5, 0xB5, 0xC3}}
> +gPerfCpuPowerMgmtGuid = {0x9ED307D6, 0x4AEB, 0x44A9, {0x9B, 0x11,
> 0xD8, 0x21, 0x84, 0x9A, 0xCB, 0xF7}}
> +gPerfMePostMemGuid = {0x2CC8626D, 0x3387, 0x4817, {0xAB, 0xF6,
> 0x86, 0x9A, 0xF5, 0xF0, 0x51, 0xAA}}
> +gPerfHdaPostMemGuid = {0xB31883B7, 0x5A05, 0x4040, {0x40, 0x80,
> 0x66, 0x8D, 0x29, 0x13, 0xD7, 0x84}}
> +
> +[Protocols.common.Private]
> + #
> + # SA
> + #
> + gSaIotrapSmiProtocolGuid = { 0x1861e089, 0xcaa3, 0x473e, { 0x84,
> 0x32, 0xdc, 0x1f, 0x94, 0xc6, 0xc1, 0xa6 }}
> +
> + #
> + # CPU
> + #
> + gPchPcieIoTrapProtocolGuid = { 0xd66a1cf, 0x79ad, 0x494b, { 0x97,
> 0x8b, 0xb2, 0x59, 0x81, 0x68, 0x93, 0x34 }}
> +
> +[Protocols]
> +##
> +## IntelFrameworkPkg
> +##
> +gEfiLegacyBiosProtocolGuid = {0xdb9a1e3d, 0x45cb, 0x4abb, {0x85, 0x3b,
> 0xe5, 0x38, 0x7f, 0xdb, 0x2e, 0x2d}}
> +gEfiLegacyInterruptProtocolGuid = {0x31ce593d, 0x108a, 0x485d, {0xad,
> 0xb2, 0x78, 0xf2, 0x1f, 0x29, 0x66, 0xbe}}
> +gEfiDataHubProtocolGuid = {0xae80d021, 0x618e, 0x11d4, {0xbc, 0xd7,
> 0x00, 0x80, 0xc7, 0x3c, 0x88, 0x81}}
> +
> +##
> +## MdeModulePkg
> +##
> +gEfiSmmVariableProtocolGuid = {0xed32d533, 0x99e6, 0x4209, {0x9c, 0xc0,
> 0x2d, 0x72, 0xcd, 0xd9, 0x98, 0xa7}}
> +
> +##
> +## SystemAgent
> +##
> +gBdatAccessGuid = {0x9477482c, 0x8717, 0x4725, {0x98, 0x28,
> 0x7b, 0xd8, 0xc9, 0xa3, 0x75, 0x6a}}
> +gIgdOpRegionProtocolGuid = {0x9e67aecf, 0x4fbb, 0x4c84, {0x99, 0xa5,
> 0x10, 0x73, 0x40, 0x7, 0x6d, 0xb4}}
> +gMemInfoProtocolGuid = {0xd4d2f201, 0x50e8, 0x4d45, {0x8e, 0x5,
> 0xfd, 0x49, 0xa8, 0x2a, 0x15, 0x69}}
> +gSaPolicyProtocolGuid = {0xc6aa1f27, 0x5597, 0x4802, {0x9f, 0x63,
> 0xd6, 0x28, 0x36, 0x59, 0x86, 0x35}}
> +gSaNvsAreaProtocolGuid = {0x149a10a5, 0x9d06, 0x4c6b, {0xbe, 0x44,
> 0x08, 0x92, 0xce, 0x20, 0x61, 0xac}}
> +gGopPolicyProtocolGuid = {0xec2e931b, 0x3281, 0x48a5, {0x81, 0x07,
> 0xdf, 0x8a, 0x8b, 0xed, 0x3c, 0x5d}}
> +gGopComponentName2ProtocolGuid = {0x651b7ebd, 0xce13, 0x41d0,
> {0x82, 0xe5, 0xa0, 0x63, 0xab, 0xbe, 0x9b, 0xb6}}
> +gGopOverrideProtocolGuid = {0x4a89a16e, 0x67b8, 0x4429, {0x8c,
> 0x47, 0x43, 0x67, 0x90, 0xf2, 0xf2, 0x69}}
> +
> +##
> +## AcpiTables
> +##
> +gEfiGlobalNvsAreaProtocolGuid = {0x074e1e48, 0x8132, 0x47a1, {0x8c,
> 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc}}
> +
> +##
> +## Cpu
> +##
> +gCpuInfoProtocolGuid = {0xe223cf65, 0xf6ce, 0x4122, {0xb3, 0xaf, 0x4b,
> 0xd1, 0x8a, 0xff, 0x40, 0xa1}}
> +gCpuNvsAreaProtocolGuid = {0xb9cf3f43, 0xbe3e, 0x4e45, {0xa0, 0xbe,
> 0x1a, 0x4, 0x89, 0xdf, 0x1a, 0xc9}}
> +gDxeCpuPolicyProtocolGuid = {0x8282b977, 0x22f9, 0x4134, {0x99, 0x43,
> 0x7b, 0xcc, 0x5f, 0x40, 0x33, 0x52}}
> +
> +##
> +## Me
> +##
> +gDxeMePolicyGuid = {0xa0b5dc52, 0x4f34, 0x3990, {0xd4, 0x91,
> 0x10, 0x8b, 0xe8, 0xba, 0x75, 0x42}}
> +
> +##
> +## PCH
> +##
> +gPchSpiProtocolGuid = {0xc7d289, 0x1347, 0x4de0, {0xbf, 0x42, 0xe, 0x26,
> 0x9d, 0xe, 0xf3, 0x4a}}
> +gWdtProtocolGuid = {0xb42b8d12, 0x2acb, 0x499a, {0xa9, 0x20, 0xdd, 0x5b,
> 0xe6, 0xcf, 0x09, 0xb1}}
> +gPchSerialIoUartDebugInfoProtocolGuid = {0x2fd2b1bd, 0x0387, 0x4ec6,
> {0x94, 0x1f, 0xf1, 0x4b, 0x7f, 0x1c, 0x94, 0xb6}}
> +gEfiSmmSmbusProtocolGuid = {0x72e40094, 0x2ee1, 0x497a, {0x8f, 0x33,
> 0x4c, 0x93, 0x4a, 0x9e, 0x9c, 0x0c}}
> +gPchSmmSpiProtocolGuid = {0x56521f06, 0xa62, 0x4822, {0x99, 0x63, 0xdf,
> 0x1, 0x9d, 0x72, 0xc7, 0xe1}}
> +gPchSmmIoTrapControlGuid = {0x514d2afd, 0x2096, 0x4283, {0x9d, 0xa6,
> 0x70, 0x0c, 0xd2, 0x7d, 0xc7, 0xa5}}
> +gPchTcoSmiDispatchProtocolGuid = {0x9e71d609, 0x6d24, 0x47fd, {0xb5,
> 0x72, 0x61, 0x40, 0xf8, 0xd9, 0xc2, 0xa4}}
> +gPchPcieSmiDispatchProtocolGuid = {0x3e7d2b56, 0x3f47, 0x42aa, {0x8f,
> 0x6b, 0x22, 0xf5, 0x19, 0x81, 0x8d, 0xab}}
> +gPchAcpiSmiDispatchProtocolGuid = {0xd52bb262, 0xf022, 0x49ec, {0x86,
> 0xd2, 0x7a, 0x29, 0x3a, 0x7a, 0x05, 0x4b}}
> +gPchSmiDispatchProtocolGuid = {0xE6A81BBF, 0x873D, 0x47FD, {0xB6, 0xBE,
> 0x61, 0xB3, 0xE5, 0x72, 0x09, 0x93}}
> +gPchResetCallbackProtocolGuid = {0x3a3300ab, 0xc929, 0x487d, {0xab,
> 0x34, 0x15, 0x9b, 0xc1, 0x35, 0x62, 0xc0}}
> +gPchNvsAreaProtocolGuid = {0x2e058b2b, 0xedc1, 0x4431, {0x87, 0xd9,
> 0xc6, 0xc4, 0xea, 0x10, 0x2b, 0xe3}}
> +gPchEmmcTuningProtocolGuid = {0x10fe7e3b, 0xdbe5, 0x4cfa, {0x90, 0x25,
> 0x40, 0x02, 0xcf, 0xdd, 0xbb, 0x89}}
> +gPchEspiSmiDispatchProtocolGuid = {0xB3C14FF3, 0xBAE8, 0x456C, {0x86,
> 0x31, 0x27, 0xFE, 0x0C, 0xEB, 0x34, 0x0C}}
> +gPchSmmPeriodicTimerControlGuid = {0x6906E93B, 0x603B, 0x4A0F, {0x86,
> 0x92, 0x83, 0x20, 0x04, 0xAA, 0xF2, 0xDB}}
> +gIoTrapExDispatchProtocolGuid = {0x5B48E913, 0x707B, 0x4F9D, {0xAF,
> 0x2E, 0xEE, 0x03, 0x5B, 0xCE, 0x39, 0x5D}}
> +gPchPolicyProtocolGuid = {0x543d5c93, 0x6a28, 0x4513, {0x85, 0x9a, 0x82,
> 0xa7, 0xb9, 0x12, 0xcb, 0xbe}}
> +gPchSraProtocolGuid = {0x7AE12E27, 0x5087, 0x46C8, {0xBF, 0xF0, 0x83, 0x9C,
> 0x53, 0x7B, 0x25, 0xEB}}
> +
> +##
> +## Hsti
> +##
> +## HstiSiliconDxe Driver Entry Point
> +gHstiProtocolGuid = { 0x1b05de41, 0xc93b, 0x4bb4, { 0xad, 0x47, 0x2a, 0x78,
> 0xac, 0xf, 0xc9, 0xe4 }}
> +## Handler to gather and publish HSTI results on ReadyToBootEvent
> +gHstiPublishCompleteProtocolGuid = {0x0f500be6, 0xece4, 0x4ed8, { 0x90,
> 0x81, 0x9a, 0xa9, 0xa5, 0x23, 0xfb, 0x7b}}
> +gEfiAdapterInformationProtocolGuid = { 0xE5DD1403, 0xD622, 0xC24E, {0x84,
> 0x88, 0xC7, 0x1B, 0x17, 0xF5, 0xE8, 0x02 }}
> +
> +##
> +## Silicon Policy
> +##
> +## Include/Protocol/SiPolicyProtocol.h
> +gDxeSiPolicyProtocolGuid = { 0xeca27516, 0x306c, 0x4e28, { 0x8c, 0x94, 0x4e,
> 0x52, 0x10, 0x96, 0x69, 0x5e }}
> +
> +[Ppis.common.Private]
> +
> +[Ppis]
> +##
> +## MdeModulePkg
> +##
> +gPeiCapsulePpiGuid = {0x3acf33ee, 0xd892, 0x40f4, {0xa2, 0xfc, 0x38, 0x54,
> 0xd2, 0xe1, 0x32, 0x3d}}
> +gPeiSmmAccessPpiGuid = {0x268f33a9, 0xcccd, 0x48be, {0x88, 0x17, 0x86,
> 0x05, 0x3a, 0xc3, 0x2e, 0xd6}}
> +gPeiSmmControlPpiGuid = {0x61c68702, 0x4d7e, 0x4f43, {0x8d, 0xef, 0xa7,
> 0x43, 0x05, 0xce, 0x74, 0xc5}}
> +
> +##
> +## SecurityPkg
> +##
> +gPeiTpmInitializationDonePpiGuid = {0xa030d115, 0x54dd, 0x447b, { 0x90,
> 0x64, 0xf2, 0x6, 0x88, 0x3d, 0x7c, 0xcc}}
> +
> +##
> +## Common
> +##
> +## Include/Ppi/SiPolicy.h
> +gSiPolicyPpiGuid = {0xaebffa01, 0x7edc, 0x49ff, {0x8d, 0x88, 0xcb, 0x84,
> 0x8c, 0x5e, 0x86, 0x70}}
> +
> +## Include/Ppi/SiPolicy.h
> +gSiPreMemPolicyPpiGuid = {0xc133fe57, 0x17c7, 0x4b09, {0x8b, 0x3c, 0x97,
> 0xc1, 0x89, 0xd0, 0xab, 0x8d}}
> +
> +##
> +## SystemAgent
> +##
> +gSsaBiosCallBacksPpiGuid = {0x99b56126, 0xe16c, 0x4d9b, {0xbb, 0x71,
> 0xaa, 0x35, 0x46, 0x1a, 0x70, 0x2f}}
> +gSsaBiosServicesPpiGuid = {0x55750d10, 0x6d3d, 0x4bf5, {0x89, 0xd8, 0xe3,
> 0x5e, 0xf0, 0xb0, 0x90, 0xf4}}
> +gEnablePeiGraphicsPpiGuid = {0x8e3bb474, 0x545, 0x4902, {0x86, 0xb0,
> 0x6c, 0xb5, 0xe2, 0x64, 0xb4, 0xa5}}
> +
> +##
> +## Cpu
> +##
> +gPeiCachePpiGuid = {0x09be4bc2, 0x790e, 0x4dea, {0x8b, 0xdc, 0x38, 0x05,
> 0x16, 0x98, 0x39, 0x44}}
> +
> +##
> +## Me
> +##
> +gMeDidSentPpiGuid = {0x45dc3106, 0xef67, 0x4c71, {0xb0, 0xf0, 0x97, 0x15,
> 0x9c, 0x7d, 0xbb, 0x7c}}
> +
> +##
> +## PCH
> +##
> +gWdtPpiGuid = {0xf38d1338, 0xaf7a, 0x4fb6, {0x91, 0xdb, 0x1a, 0x9c, 0x21,
> 0x83, 0x57, 0x0d}}
> +gPchSpiPpiGuid = {0xdade7ce3, 0x6971, 0x4b75, {0x82, 0x5e, 0xe, 0xe0,
> 0xeb, 0x17, 0x72, 0x2d}}
> +gPeiSmbusPolicyPpiGuid = {0x63b6e435, 0x32bc, 0x49c6, {0x81, 0xbd, 0xb7,
> 0xa1, 0xa0, 0xfe, 0x1a, 0x6c}}
> +gPchResetCallbackPpiGuid = {0x17865dc0, 0x0b8b, 0x4da8, {0x8b, 0x42,
> 0x7c, 0x46, 0xb8, 0x5c, 0xca, 0x4d}}
> +
> +[LibraryClasses]
> +##
> +## Common
> +##
> +AslUpdateLib|Include/Library/AslUpdateLib.h
> +SiPolicyLib|Include/Library/SiPolicyLib.h
> +UsbLib|Include/Library/UsbLib.h
> +UsbInitLib|Include/Private/Library/UsbInitLib.h
> +
> +##
> +## CPU
> +##
> +CpuMailboxLib|Cpu/Include/Library/CpuMailboxLib.h
> +CpuPlatformLib|Cpu/Include/Library/CpuPlatformLib.h
> +CpuPolicyLib|Cpu/Include/Library/CpuPolicyLib.h
> +
> +##
> +## Me
> +##
> +PeiMePolicyLib|Me/Include/Library/PeiMePolicyLib.h
> +
> +##
> +## Pch
> +##
> +GpioLib|Pch/Include/Library/GpioLib.h
> +GpioLib|Pch/Include/Library/GpioNativeLib.h
> +PchCycleDecodingLib|Pch/Include/Library/PchCycleDecodingLib.h
> +PchEspiLib|Pch/Include/Library/PchEspiLib.h
> +PchGbeLib|Pch/Include/Library/PchGbeLib.h
> +GbeMdiLib|Pch/Include/Library/GbeMdiLib.h
> +PchInfoLib|Pch/Include/Library/PchInfoLib.h
> +PchP2sbLib|Pch/Include/Library/PchP2sbLib.h
> +PchPcieRpLib|Pch/Include/Library/PchPcieRpLib.h
> +PchPcrLib|Pch/Include/Library/PchPcrLib.h
> +PchPmcLib|Pch/Include/Library/PchPmcLib.h
> +PchPolicyLib|Pch/Include/Library/PchPolicyLib.h
> +PchSbiAccessLib|Pch/Include/Library/PchSbiAccessLib.h
> +PchSerialIoLib|Pch/Include/Library/PchSerialIoLib.h
> +PchSerialIoUartLib|Pch/Include/Library/PchSerialIoUartLib.h
> +SecPchLib|Pch/Include/Library/SecPchLib.h
> +PchTraceHubLib|Pch/Include/Private/Library/PchTraceHubLib.h
> +PchSmmControlLib|Pch/IncludePrivate/Library/PchSmmControlLib.h
> +PchWdtCommonLib|Pch/Include/Library/PchWdtCommonLib.h
> +OcWdtLib|Pch/Include/Library/OcWdtLib.h
> +PchResetLib|Pch/Include/Library/PchResetLib.h
> +DxePchPolicyLib|Pch/Include/Library/DxePchPolicyLib.h
> +GpioNameBufferLib|Pch/IncludePrivate/Library/GpioNameBufferLib.h
> +
> +##
> +## Sa
> +##
> +DxeSaPolicyLib|SystemAgent/Include/Library/DxeSaPolicyLib.h
> +PeiSaPolicyLib|SystemAgent/Include/Library/PeiSaPolicyLib.h
> +SaPlatformLib|SystemAgent/Include/Library/SaPlatformLib.h
> +
> +##
> +## Memory
> +##
> +
> +[PcdsFixedAtBuild]
> +## From MdeModulePkg.dec
> +## Progress Code for S3 Suspend end.
> +## PROGRESS_CODE_S3_SUSPEND_END = (EFI_SOFTWARE_SMM_DRIVER |
> (EFI_OEM_SPECIFIC | 0x00000001)) = 0x03078001
> +gSiPkgTokenSpaceGuid.PcdProgressCodeS3SuspendEnd|0x03078001|UINT3
> 2|0x30001033
> +
> +##
> +## PcdNemCodeCacheBase is usally the same as PEI FV Base address,
> +## FLASH_BASE+FLASH_REGION_FV_RECOVERY_OFFSET from
> PlatformPkg.fdf.
> +##
> +## Restriction:
> +## 1) PcdNemCodeCacheBase - (PcdTemporaryRamBase +
> PcdTemporaryRamSize) >= 4K
> +## 2) PcdTemporaryRamBase >= 4G - 64M
> +##
> +gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase|0xFFF80000|UINT32|0x200
> 00009
> +
> +##
> +## NemCodeCacheSize is usally the same as PEI FV Size,
> +## FLASH_REGION_FV_RECOVERY_SIZE from PlatformPkg.fdf.
> +##
> +## Restriction:
> +## 1) PcdNemTotalCacheSize = NemCodeCacheSize + PcdTemporaryRamSize
> +## <= Maximun CPU NEM total size (Code + Data)
> +## = LLC size - 0.5M
> +## 2) PcdTemporaryRamSize <= Maximum CPU NEM data size
> +## = MLC size
> +## NOTE: The size restriction may be changed in next generation processor.
> +## Please refer to Processor BWG for detail.
> +##
> +gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress|0xFF800000|UINT32|0x10
> 000001
> +gSiPkgTokenSpaceGuid.PcdBiosSize|0x00800000|UINT32|0x10000002
> +gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xfef00000|UINT32|0x0001
> 0028
> +gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x2000|UINT32|0x00010029
> +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|0xFFE60000|UINT32|0x3
> 0000004
> +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize|0x000A0000|UINT32|0x30
> 000005
> +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|0x00660000|UINT32|0x
> 30000006
> +
> +##
> +## PcdEfiGcdAllocateType is using for EFI_GCD_ALLOCATE_TYPE selection
> +## value of the struct
> +## 0x00 EfiGcdAllocateAnySearchBottomUp
> +## 0x01 EfiGcdAllocateMaxAddressSearchBottomUp
> +## 0x03 EfiGcdAllocateAnySearchTopDown
> +## 0x04 EfiGcdAllocateMaxAddressSearchTopDown
> +##
> +## below value should not using in this situation
> +## 0x05 EfiGcdMaxAllocateType : design for max value of struct
> +## 0x02 EfiGcdAllocateAddress : design for speccification address allocate
> +##
> +gSiPkgTokenSpaceGuid.PcdEfiGcdAllocateType|0x01|UINT8|0x40000000
> +
> +gSiPkgTokenSpaceGuid.PcdSmmbaseSwSmi|0x55|UINT8|0x0010005
> +gSiPkgTokenSpaceGuid.PcdHwpSmi|0x27|UINT8|0x40000001
> +gSiPkgTokenSpaceGuid.PcdItbmSmi|0x29|UINT8|0x40000002
> +
> +gSiPkgTokenSpaceGuid.PcdAbove4GBMmioBase|0x0000004000000000|UIN
> T64|0x40000003
> +gSiPkgTokenSpaceGuid.PcdAbove4GBMmioSize|0x0000004000000000|UINT
> 64|0x40000004
> +
> +[PcdsDynamic, PcdsPatchableInModule]
> +## From MdeModulePkg.dec
> +## Default OEM ID for ACPI table creation, its length must be 0x6 bytes to
> follow ACPI specification.
> +gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemId|"INTEL "|VOID*|0x30001034
> +## Default OEM Table ID for ACPI table creation, it is "EDK2 ".
> +gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20202020324B4445|U
> INT64|0x30001035
> +## Default OEM Revision for ACPI table creation.
> +gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00000002|UINT32|0
> x30001036
> +## Default Creator ID for ACPI table creation.
> +gSiPkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x20202020|UINT32|0x30
> 001037
> +## Default Creator Revision for ACPI table creation.
> +gSiPkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x01000013|UINT32
> |0x30001038
> +
> +[PcdsFixedAtBuild, PcdsPatchableInModule]
> +## Maximun number of performance log entries during PEI phase.
> +gSiPkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|40|UINT8|0x0001
> 002f
> +## This value is used to set the base address of MCH
> +gSiPkgTokenSpaceGuid.PcdMchBaseAddress|0xFED10000|UINT64|0x000100
> 30
> +## This value is used to set the base address of PCH devices
> +gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress|0x0000EFA0|UINT16|0x0001
> 0031
> +gSiPkgTokenSpaceGuid.PcdTcoBaseAddress|0x0400|UINT16|0x00010034
> +gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800|UINT16|0x00010035
> +
> +## 32KB window
> +gSiPkgTokenSpaceGuid.PcdMchMmioSize|0x8000|UINT32|0x50000000
> +
> +## Stack size in the temporary RAM.
> +## 0 means half of TemporaryRamSize.
> +gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0|UINT32|0x000100
> 36
> +##
> +## PcdFviSmbiosType determines the SMBIOS OEM type (0x80 to 0xFF)
> defined in SMBIOS,
> +## values 0-0x7F will be treated as disable FVI reporting.
> +## FVI structure uses it as SMBIOS OEM type to provide version information.
> +##
> +gSiPkgTokenSpaceGuid.PcdFviSmbiosType|0xDD|UINT8|0x00010037
> +gSiPkgTokenSpaceGuid.PcdSaPciPrint|FALSE|BOOLEAN|0x00010039
> +##
> +## SMBIOS defaults
> +##
> +gSiPkgTokenSpaceGuid.PcdSmbiosDefaultSocketDesignation|"U3E1"|VOID*|
> 0x0001003a
> +gSiPkgTokenSpaceGuid.PcdSmbiosDefaultSerialNumber|"To Be Filled By
> O.E.M."|VOID*|0x0001003b
> +gSiPkgTokenSpaceGuid.PcdSmbiosDefaultAssetTag|"To Be Filled By
> O.E.M."|VOID*|0x0001003c
> +gSiPkgTokenSpaceGuid.PcdSmbiosDefaultPartNumber|"To Be Filled By
> O.E.M."|VOID*|0x0001003d
> +
> +##
> +## Allocate 56 KB [0x2000..0xFFFF] of I/O space for Pci Devices
> +## If PcdPciReservedMemLimit =0 Pci Reserved default MMIO Limit is
> 0xE0000000 else use PcdPciReservedMemLimit .
> +##
> +gSiPkgTokenSpaceGuid.PcdPciReservedIobase |0x2000
> |UINT16|0x00010041
> +gSiPkgTokenSpaceGuid.PcdPciReservedIoLimit |0xFFFF
> |UINT16|0x00010042
> +gSiPkgTokenSpaceGuid.PcdPciReservedMemLimit |0x0000
> |UINT32|0x00010043
> +
> +##
> +## Default 8MB TSEG
> +##
> +gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000|UINT32|0x00010046
> +##
> +## gSiPkgTokenSpaceGuid.PcdFwStsSmbiosType determines the SMBIOS OEM
> type (0x80 to 0xFF) defined
> +## in SMBIOS, values 0-0x7F will be treated as disable FWSTS SMBIOS
> reporting.
> +## FWSTS structure uses it as SMBIOS OEM type to provide FWSTS
> information.
> +##
> +gSiPkgTokenSpaceGuid.PcdFwStsSmbiosType|0xDB|UINT8|0x00010047
> +
> +##
> +## Maximum Address the AP Wakeup Buffer can start.
> +##
> +gSiPkgTokenSpaceGuid.PcdCpuApWakeupBufferMaxAddr|0x58000|UINT32|
> 0x00010048
> +
> +##
> +## Silicon Reference Code versions
> +##
> +
> +##Major:To represent code generation
> +gSiPkgTokenSpaceGuid.PcdSiliconInitVersionMajor
> |0x07|UINT8|0x00010049
> +
> +##Revision:Weekly build number
> +gSiPkgTokenSpaceGuid.PcdSiliconInitVersionRevision|0x57|UINT8|0x000100
> 51
> +
> +##Build[7:4]:Daily build number.
> +##Build[3:0]:Patch build number.
> +gSiPkgTokenSpaceGuid.PcdSiliconInitVersionBuild
> |0x40|UINT8|0x00010052
> +
> +
> +##
> +## Temp MEM IO resource
> +##
> +gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMin |2 |UINT8
> |0x00010053
> +gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMax |10 |UINT8
> |0x00010054
> +gSiPkgTokenSpaceGuid.PcdSiliconInitTempMemBaseAddr
> |0xFE600000|UINT32|0x00010055
> +gSiPkgTokenSpaceGuid.PcdSiliconInitTempMemSize
> |0x00200000|UINT32|0x00010056
> +
> +##
> +## This PCD specifies the base address of the HPET timer.
> +## The acceptable values are 0xFED00000, 0xFED01000, 0xFED02000, and
> 0xFED03000
> +##
> +gSiPkgTokenSpaceGuid.PcdHpetBaseAddress
> |0xFED00000|UINT32|0x00010057
> +gSiPkgTokenSpaceGuid.PcdSiHpetBaseAddress
> |0xFED00000|UINT32|0x00010060
> +##
> +## This PCD specifies the base address of the IO APIC.
> +## The acceptable values are 0xFECxx000.
> +##
> +#gSiPkgTokenSpaceGuid.PcdIoApicBaseAddress
> |0xFEC00000|UINT32|0x00010058
> +##
> +## Regbar Base Address
> +##
> +gSiPkgTokenSpaceGuid.PcdRegBarBaseAddress|0xFC000000|UINT32|0x0001
> 0059
> +
> +## Null-terminated string of the Version of Physical Presence interface
> supported by platform.
> +# @Prompt Version of Physical Presence interface supported by platform.
> +gSiPkgTokenSpaceGuid.PcdTcgPhysicalPresenceInterfaceVer|"1.3"|VOID*|0x
> 00000008
> +
> +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
> +##
> +## SerialIo Uart Configuration
> +##
> +gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable |0 |UINT8
> |0x00100001 # 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
> +gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber |2 |UINT8
> |0x00100002
> +gSiPkgTokenSpaceGuid.PcdSerialIoUartInputClock
> |1843200|UINT32|0x00100003
> +gSiPkgTokenSpaceGuid.PcdSerialIoUart0PinMuxing |0 |UINT8
> |0x00100009 # 0: default pins, 1: pins muxed with CNV_BRI/RGI
> +##
> +## PCI Express MMIO region length
> +## Valid settings: 0x10000000/256MB, 0x8000000/128MB, 0x4000000/64MB
> +##
> +gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000|UINT32|0x
> 0010004
> +
> +## Indidates if SMM Save State saved in MSRs.
> +# if enabled, SMM Save State will use the MSRs instead of the
> memory.<BR><BR>
> +# TRUE - SMM Save State will use the MSRs.<BR>
> +# FALSE - SMM Save State will use the memory.<BR>
> +# @Prompt SMM Save State uses MSRs.
> +gSiPkgTokenSpaceGuid.PcdCpuSmmMsrSaveStateEnable|FALSE|BOOLEAN|0
> x20000001
> +[PcdsDynamic]
> +
> +## Indidates if SMM Delay feature is supported.<BR><BR>
> +# TRUE - SMM Delay feature is supported.<BR>
> +# FALSE - SMM Delay feature is not supported.<BR>
> +# @Prompt SMM Delay feature.
> +gSiPkgTokenSpaceGuid.PcdCpuSmmUseDelayIndication|TRUE|BOOLEAN|0x
> 0010009
> +
> +## Indidates if SMM Block feature is supported.<BR><BR>
> +# TRUE - SMM Block feature is supported.<BR>
> +# FALSE - SMM Block feature is not supported.<BR>
> +# @Prompt SMM Block feature.
> +gSiPkgTokenSpaceGuid.PcdCpuSmmUseBlockIndication|TRUE|BOOLEAN|0x
> 001000A
> +
> +## Indidates if SMM Enable/Disable feature is supported.<BR><BR>
> +# TRUE - SMM Enable/Disable feature is supported.<BR>
> +# FALSE - SMM Enable/Disable feature is not supported.<BR>
> +# @Prompt SMM Enable/Disable feature.
> +gSiPkgTokenSpaceGuid.PcdCpuSmmUseSmmEnableIndication|TRUE|BOOLE
> AN|0x001000B
> +
> +## Indidates if SMM PROT MODE feature is supported.<BR><BR>
> +# TRUE - SMM PROT MODE feature is supported.<BR>
> +# FALSE - SMM PROT MODE feature is not supported.<BR>
> +# @Prompt SMM PROT MODE feature.
> +gSiPkgTokenSpaceGuid.PcdCpuSmmProtectedModeEnable|TRUE|BOOLEAN
> |0x001000C
> +
> +## Indidates if SMM Code Access Check feature is supported.<BR><BR>
> +# TRUE - SMM Code Access Check feature is supported.<BR>
> +# FALSE - SMM Code Access Check feature is not supported.<BR>
> +# @Prompt SMM Code Access Check feature.
> +gSiPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable|TRUE|BOOLEA
> N|0x001000D
> +
> +[PcdsFeatureFlag]
> +##
> +## Those PCDs are used to control build process.
> +##
> +gSiPkgTokenSpaceGuid.PcdTraceHubEnable
> |FALSE|BOOLEAN|0xF0000001
> +gSiPkgTokenSpaceGuid.PcdSmmVariableEnable
> |FALSE|BOOLEAN|0xF0000002
> +gSiPkgTokenSpaceGuid.PcdAtaEnable
> |FALSE|BOOLEAN|0xF0000004
> +gSiPkgTokenSpaceGuid.PcdSiCsmEnable
> |FALSE|BOOLEAN|0xF0000005
> +gSiPkgTokenSpaceGuid.PcdUseHpetTimer |TRUE
> |BOOLEAN|0xF0000006
> +gSiPkgTokenSpaceGuid.PcdSgEnable |TRUE
> |BOOLEAN|0xF0000008
> +gSiPkgTokenSpaceGuid.PcdAcpiEnable |TRUE
> |BOOLEAN|0xF0000009
> +gSiPkgTokenSpaceGuid.PcdSourceDebugEnable
> |FALSE|BOOLEAN|0xF000000B
> +gSiPkgTokenSpaceGuid.PcdPpmEnable |TRUE
> |BOOLEAN|0xF000000C
> +gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable
> |FALSE|BOOLEAN|0xF000000F
> +gSiPkgTokenSpaceGuid.PcdPttEnable
> |FALSE|BOOLEAN|0xF0000011
> +gSiPkgTokenSpaceGuid.PcdJhiEnable
> |FALSE|BOOLEAN|0xF0000012
> +gSiPkgTokenSpaceGuid.PcdSmbiosEnable |TRUE
> |BOOLEAN|0xF0000014
> +gSiPkgTokenSpaceGuid.PcdS3Enable |TRUE
> |BOOLEAN|0xF0000015
> +gSiPkgTokenSpaceGuid.PcdOverclockEnable
> |FALSE|BOOLEAN|0xF0000016
> +gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable
> |FALSE|BOOLEAN|0xF0000017
> +gSiPkgTokenSpaceGuid.PcdIgdEnable |TRUE
> |BOOLEAN|0xF000001A
> +gSiPkgTokenSpaceGuid.PcdPegEnable |TRUE
> |BOOLEAN|0xF000001B
> +gSiPkgTokenSpaceGuid.PcdSaDmiEnable |TRUE
> |BOOLEAN|0xF000001C
> +gSiPkgTokenSpaceGuid.PcdIpuEnable |TRUE
> |BOOLEAN|0xF000001D
> +gSiPkgTokenSpaceGuid.PcdGnaEnable |TRUE
> |BOOLEAN|0xF000001E
> +gSiPkgTokenSpaceGuid.PcdSaOcEnable |TRUE
> |BOOLEAN|0xF000001F
> +gSiPkgTokenSpaceGuid.PcdVtdEnable |TRUE
> |BOOLEAN|0xF0000020
> +gSiPkgTokenSpaceGuid.PcdBdatEnable
> |FALSE|BOOLEAN|0xF0000023
> +gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable |TRUE
> |BOOLEAN|0xF0000024
> +gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable |TRUE
> |BOOLEAN|0xF0000025
> +gSiPkgTokenSpaceGuid.PcdCflCpuEnable
> |FALSE|BOOLEAN|0xF0000027
> +gSiPkgTokenSpaceGuid.PcdOcWdtEnable
> |FALSE|BOOLEAN|0xF0000029
> +gSiPkgTokenSpaceGuid.PcdMinTreeEnable
> |FALSE|BOOLEAN|0xF000002A # To separate modules used in mininal source
> tree and advanced features
> +gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable
> |FALSE|BOOLEAN|0xF0000033
> +gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable
> |FALSE|BOOLEAN|0xF0000034
> +
> +gSiPkgTokenSpaceGuid.PcdEdk2MasterEnable
> |FALSE|BOOLEAN|0xF0000035
> +gSiPkgTokenSpaceGuid.PcdPpamEnable |TRUE
> |BOOLEAN|0xF0000036
> +
> +#This PCD is used to enable WDT for debug purposes in OverClocking.
> +gSiPkgTokenSpaceGuid.PcdOcEnableWdtforDebug
> |FALSE|BOOLEAN|0xF0000037
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock.h
> new file mode 100644
> index 0000000000..d0e3d94418
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock.h
> @@ -0,0 +1,53 @@
> +/** @file
> + Header file for Config Block Lib implementation
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _CONFIG_BLOCK_H_
> +#define _CONFIG_BLOCK_H_
> +
> +#include <Uefi/UefiBaseType.h>
> +#include <Uefi/UefiMultiPhase.h>
> +#include <Pi/PiBootMode.h>
> +#include <Pi/PiHob.h>
> +
> +#pragma pack (push,1)
> +
> +///
> +/// Config Block Header
> +///
> +typedef struct _CONFIG_BLOCK_HEADER {
> + EFI_HOB_GUID_TYPE GuidHob; ///< Offset 0-23 GUID
> extension HOB header
> + UINT8 Revision; ///< Offset 24 Revision of this
> config block
> + UINT8 Attributes; ///< Offset 25 The main revision
> for config block
> + UINT8 Reserved[2]; ///< Offset 26-27 Reserved for
> future use
> +} CONFIG_BLOCK_HEADER;
> +
> +///
> +/// Config Block
> +///
> +typedef struct _CONFIG_BLOCK {
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Header
> of config block
> + //
> + // Config Block Data
> + //
> +} CONFIG_BLOCK;
> +
> +///
> +/// Config Block Table Header
> +///
> +typedef struct _CONFIG_BLOCK_TABLE_STRUCT {
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 GUID
> number for main entry of config block
> + UINT8 Rsvd0[2]; ///< Offset 28-29 Reserved for
> future use
> + UINT16 NumberOfBlocks; ///< Offset 30-31 Number of
> config blocks (N)
> + UINT32 AvailableSize; ///< Offset 32-35 Current config
> block table size
> +///
> +/// Individual Config Block Structures are added here in memory as part of
> AddConfigBlock()
> +///
> +} CONFIG_BLOCK_TABLE_HEADER;
> +#pragma pack (pop)
> +
> +#endif // _CONFIG_BLOCK_H_
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock/SiConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock/SiConfig.h
> new file mode 100644
> index 0000000000..27b5a9440e
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock/SiConfig.h
> @@ -0,0 +1,89 @@
> +/** @file
> + Si Config Block
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SI_CONFIG_H_
> +#define _SI_CONFIG_H_
> +
> +#define SI_CONFIG_REVISION 3
> +
> +extern EFI_GUID gSiConfigGuid;
> +
> +
> +#pragma pack (push,1)
> +
> +/**
> + The Silicon Policy allows the platform code to publish a set of configuration
> + information that the RC drivers will use to configure the silicon hardware.
> +
> + <b>Revision 1</b>:
> + - Initial version.
> + <b>Revision 2</b>:
> + - Added TraceHubMemBase
> + <b>Revision 3</b>
> + - Deprecated SkipPostBootSai
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header
> + //
> + // Platform specific common policies that used by several silicon
> components.
> + //
> + UINT32 CsmFlag : 1; ///< Offset 44 BIT0: CSM status flag.
> + /**
> + @deprecated since revision 3
> + **/
> + UINT32 SkipPostBootSai : 1;
> + UINT32 RsvdBits : 30; ///< Reserved
> + UINT32 *SsidTablePtr; // Offset 48
> + UINT16 NumberOfSsidTableEntry; // Offset 52
> + UINT16 Reserved; // Offset 54
> + /**
> + If Trace Hub is enabled and trace to memory is desired, Platform code or
> BootLoader needs to allocate trace hub memory
> + as reserved, and save allocated memory base to TraceHubMemBase to
> ensure Trace Hub memory is configured properly.
> + To get total trace hub memory size please refer to
> TraceHubCalculateTotalBufferSize ()
> +
> + Noted: If EDKII memory service is used to allocate memory, it will require
> double memory size to support size-aligned memory allocation,
> + so Platform code or FSP Wrapper code should ensure enough memory
> available for size-aligned TraceHub memory allocation.
> + **/
> + UINT32 TraceHubMemBase; // Offset 58
> +} SI_CONFIG;
> +
> +#pragma pack (pop)
> +
> +#define DEFAULT_SSVID 0x8086
> +#define DEFAULT_SSDID 0x7270
> +#define MAX_DEVICE_COUNT 70
> +
> +///
> +/// Subsystem Vendor ID / Subsystem ID
> +///
> +typedef struct {
> + UINT16 SubSystemVendorId;
> + UINT16 SubSystemId;
> +} SVID_SID_VALUE;
> +
> +//
> +// Below is to match PCI_SEGMENT_LIB_ADDRESS () which can directly send to
> PciSegmentRead/Write functions.
> +//
> +typedef struct {
> + union {
> + struct {
> + UINT64 Register:12;
> + UINT64 Function:3;
> + UINT64 Device:5;
> + UINT64 Bus:8;
> + UINT64 Reserved1:4;
> + UINT64 Segment:16;
> + UINT64 Reserved2:16;
> + } Bits;
> + UINT64 SegBusDevFuncRegister;
> + } Address;
> + SVID_SID_VALUE SvidSidValue;
> + UINT32 Reserved;
> +} SVID_SID_INIT_ENTRY;
> +
> +#endif // _SI_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock/UsbConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock/UsbConfig.h
> new file mode 100644
> index 0000000000..8b51e2d47a
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock/UsbConfig.h
> @@ -0,0 +1,291 @@
> +/** @file
> + Common USB policy shared between PCH and CPU
> + Contains general features settings for xHCI and xDCI
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _USB_CONFIG_H_
> +#define _USB_CONFIG_H_
> +
> +#define USB_CONFIG_REVISION 3
> +extern EFI_GUID gUsbConfigGuid;
> +
> +#define MAX_USB2_PORTS 16
> +#define MAX_USB3_PORTS 10
> +
> +#pragma pack (push,1)
> +
> +#define PCH_USB_OC_PINS_MAX 8 ///< Maximal possible number of USB
> Over Current pins
> +
> +///
> +/// Overcurrent pins, the values match the setting of EDS, please refer to EDS
> for more details
> +///
> +typedef enum {
> + UsbOverCurrentPin0 = 0,
> + UsbOverCurrentPin1,
> + UsbOverCurrentPin2,
> + UsbOverCurrentPin3,
> + UsbOverCurrentPin4,
> + UsbOverCurrentPin5,
> + UsbOverCurrentPin6,
> + UsbOverCurrentPin7,
> + UsbOverCurrentPinMax,
> + UsbOverCurrentPinSkip = 0xFF
> +} USB_OVERCURRENT_PIN;
> +
> +/**
> + This structure configures per USB2 AFE settings.
> + It allows to setup the port electrical parameters.
> +**/
> +typedef struct {
> +/** Per Port HS Preemphasis Bias (PERPORTPETXISET)
> + 000b - 0mV
> + 001b - 11.25mV
> + 010b - 16.9mV
> + 011b - 28.15mV
> + 100b - 28.15mV
> + 101b - 39.35mV
> + 110b - 45mV
> + 111b - 56.3mV
> +**/
> + UINT8 Petxiset;
> +/** Per Port HS Transmitter Bias (PERPORTTXISET)
> + 000b - 0mV
> + 001b - 11.25mV
> + 010b - 16.9mV
> + 011b - 28.15mV
> + 100b - 28.15mV
> + 101b - 39.35mV
> + 110b - 45mV
> + 111b - 56.3mV
> +**/
> + UINT8 Txiset;
> +/**
> + Per Port HS Transmitter Emphasis (IUSBTXEMPHASISEN)
> + 00b - Emphasis OFF
> + 01b - De-emphasis ON
> + 10b - Pre-emphasis ON
> + 11b - Pre-emphasis & De-emphasis ON
> +**/
> + UINT8 Predeemp;
> +/**
> + Per Port Half Bit Pre-emphasis (PERPORTTXPEHALF)
> + 1b - half-bit pre-emphasis
> + 0b - full-bit pre-emphasis
> +**/
> + UINT8 Pehalfbit;
> +} USB20_AFE;
> +
> +/**
> + This structure configures per USB2 port physical settings.
> + It allows to setup the port location and port length, and configures the port
> strength accordingly.
> +**/
> +typedef struct {
> + /**
> + These members describe the specific over current pin number of USB 2.0
> Port N.
> + It is SW's responsibility to ensure that a given port's bit map is set only for
> + one OC pin Description. USB2 and USB3 on the same combo Port must use
> the same
> + OC pin (see: USB_OVERCURRENT_PIN).
> + **/
> + UINT32 OverCurrentPin : 8;
> + UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>.
> + UINT32 RsvdBits0 : 23; ///< Reserved bits
> + /**
> + Changing this policy values from default ones may require disabling USB2
> PHY Sus Well Power Gating
> + through Usb2PhySusPgEnable on PCH-LP
> + **/
> + USB20_AFE Afe; ///< USB2 AFE settings
> +} USB20_PORT_CONFIG;
> +
> +/**
> + This structure describes whether the USB3 Port N is enabled by platform
> modules.
> +**/
> +typedef struct {
> + /**
> + These members describe the specific over current pin number of USB 3.x
> Port N.
> + It is SW's responsibility to ensure that a given port's bit map is set only for
> + one OC pin Description. USB2 and USB3 on the same combo Port must use
> the same
> + OC pin (see: USB_OVERCURRENT_PIN).
> + **/
> + UINT32 OverCurrentPin : 8;
> +
> + /**
> + USB 3.0 TX Output Downscale Amplitude Adjustment (orate01margin)
> + HSIO_TX_DWORD8[21:16]
> + <b>Default = 00h</b>
> + **/
> + UINT32 HsioTxDownscaleAmp : 8;
> + /**
> + USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
> (ow2tapgen2deemph3p5)
> + HSIO_TX_DWORD5[21:16]
> + <b>Default = 29h</b> (approximately -3.5dB De-Emphasis)
> + **/
> + UINT32 HsioTxDeEmph : 8;
> +
> + UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>.
> + UINT32 HsioTxDeEmphEnable : 1; ///< Enable the write to USB 3.0 TX
> Output -3.5dB De-Emphasis Adjustment, <b>0: Disable</b>; 1: Enable.
> + UINT32 HsioTxDownscaleAmpEnable : 1; ///< Enable the write to USB 3.0
> TX Output Downscale Amplitude Adjustment, <b>0: Disable</b>; 1: Enable.
> + UINT32 RsvdBits0 : 5; ///< Reserved bits
> +} USB30_PORT_CONFIG;
> +
> +/**
> + The XDCI_CONFIG block describes the configurations
> + of the xDCI Usb Device controller.
> +**/
> +typedef struct {
> + /**
> + This member describes whether or not the xDCI controller should be
> enabled.
> + 0: Disable; <b>1: Enable</b>.
> + **/
> + UINT32 Enable : 1;
> + UINT32 RsvdBits0 : 31; ///< Reserved bits
> +} XDCI_CONFIG;
> +
> +//
> +// Below defines are for proper UPD construction and values syncing between
> UPD and policy
> +//
> +#define B_XHCI_HSIO_CTRL_ADAPT_OFFSET_CFG_EN BIT0 ///< Enable
> the write to Signed Magnatude number added to the CTLE code bit
> +#define B_XHCI_HSIO_FILTER_SELECT_N_EN BIT1 ///< Enable the
> write to LFPS filter select for n
> +#define B_XHCI_HSIO_FILTER_SELECT_P_EN BIT2 ///< Enable the
> write to LFPS filter select for p
> +#define B_XHCI_HSIO_LFPS_CFG_PULLUP_DWN_RES_EN BIT3 ///< Enable
> the write to olfpscfgpullupdwnres
> +#define N_XHCI_UPD_HSIO_CTRL_ADAPT_OFFSET_CFG 3
> +#define N_XHCI_UPD_HSIO_LFPS_CFG_PULLUP_DWN_RES 0
> +#define N_XHCI_UPD_HSIO_FILTER_SELECT_P 0
> +#define N_XHCI_UPD_HSIO_FILTER_SELECT_N 4
> +
> +typedef struct {
> + /**
> + Signed Magnatude number added to the CTLE
> code.(ctle_adapt_offset_cfg_4_0)
> + HSIO_RX_DWORD25 [20:16]
> + Ex: -1 -- 1_0001. +1: 0_0001
> + <b>Default = 0h</b>
> + **/
> + UINT32 HsioCtrlAdaptOffsetCfg : 5;
> + /**
> + LFPS filter select for n (filter_sel_n_2_0)
> + HSIO_RX_DWORD51 [29:27]
> + 0h:1.6ns
> + 1h:2.4ns
> + 2h:3.2ns
> + 3h:4.0ns
> + 4h:4.8ns
> + 5h:5.6ns
> + 6h:6.4ns
> + <b>Default = 0h</b>
> + **/
> + UINT32 HsioFilterSelN : 3;
> + /**
> + LFPS filter select for p (filter_sel_p_2_0)
> + HSIO_RX_DWORD51 [26:24]
> + 0h:1.6ns
> + 1h:2.4ns
> + 2h:3.2ns
> + 3h:4.0ns
> + 4h:4.8ns
> + 5h:5.6ns
> + 6h:6.4ns
> + <b>Default = 0h</b>
> + **/
> + UINT32 HsioFilterSelP : 3;
> + /**
> + Controls the input offset (olfpscfgpullupdwnres_sus_usb_2_0)
> + HSIO_RX_DWORD51 [2:0]
> + 000 Prohibited
> + 001 45K
> + 010 Prohibited
> + 011 31K
> + 100 36K
> + 101 36K
> + 110 36K
> + 111 36K
> + <b>Default = 3h</b>
> + **/
> + UINT32 HsioOlfpsCfgPullUpDwnRes : 3;
> +
> + UINT32 HsioCtrlAdaptOffsetCfgEnable : 1; ///< Enable the write to
> Signed Magnatude number added to the CTLE code, <b>0: Disable</b>; 1:
> Enable.
> + UINT32 HsioFilterSelNEnable : 1; ///< Enable the write to LFPS
> filter select for n, <b>0: Disable</b>; 1: Enable.
> + UINT32 HsioFilterSelPEnable : 1; ///< Enable the write to LFPS
> filter select for p, <b>0: Disable</b>; 1: Enable.
> + UINT32 HsioOlfpsCfgPullUpDwnResEnable : 1; ///< Enable the write to
> olfpscfgpullupdwnres, <b>0: Disable</b>; 1: Enable.
> + UINT32 RsvdBits0 : 14; ///< Reserved bits
> +} USB30_HSIO_RX_CONFIG;
> +
> +
> +/**
> + This member describes the expected configuration of the USB controller,
> + Platform modules may need to refer Setup options, schematic, BIOS
> specification to update this field.
> + The Usb20OverCurrentPins and Usb30OverCurrentPins field must be
> updated by referring the schematic.
> +
> + <b>Revision 1</b>:
> + - Initial version.
> + <b>Revision 2</b>:
> + - Added Usb2PhySusPgEnable - for enabling/disabling USB2 PHY SUS Well
> Power Gating
> + <b>Revision 3</b>:
> + Added HSIO Rx tuning policy options structure USB30_HSIO_RX_CONFIG
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
> + /**
> + This policy setting controls state of Compliance Mode enabling.
> + Compliance Mode can be enabled for testing through this option but
> defualt setting is Disabled.
> + <b>0:Disable</b>, 1: Enable
> + **/
> + UINT32 EnableComplianceMode : 1;
> + /**
> + This policy option when set will make BIOS program Port Disable Override
> register during PEI phase.
> + When disabled BIOS will not program the PDO during PEI phase and leave
> PDO register unlocked for later programming.
> + If this is disabled, platform code MUST set it before booting into OS.
> + <b>1: Enable</b>, 0: Disable
> + **/
> + UINT32 PdoProgramming : 1;
> + /**
> + This option allows for control whether USB should program the
> Overcurrent Pins mapping into xHCI.
> + Disabling this feature will disable overcurrent detection functionality.
> + Overcurrent Pin mapping data is contained in respective port structures
> (i.e. USB30_PORT_CONFIG) in OverCurrentPin field.
> + By default this Overcurrent functionality should be enabled and disabled
> only for OBS debug usage.
> + <b>1: Will program USB OC pin mapping in respective xHCI controller
> registers</b>
> + 0: Will clear OC pin mapping allow for OBS usage of OC pins
> + **/
> + UINT32 OverCurrentEnable : 1;
> + /**
> + <b>(Test)</b>
> + If this policy option is enabled then BIOS will program OCCFDONE bit in
> xHCI meaning that OC mapping data will be
> + consumed by xHCI and OC mapping registers will be locked. OverCurrent
> mapping data is taken from respective port data
> + structure from OverCurrentPin field.
> + If EnableOverCurrent policy is enabled this also should be enabled,
> otherwise xHCI won't consume OC mapping data.
> + <b>1: Program OCCFDONE bit and make xHCI consume OverCurrent
> mapping data</b>
> + 0: Do not program OCCFDONE bit making it possible to use OBS debug on
> OC pins.
> + **/
> + UINT32 XhciOcLock : 1;
> + /**
> + <b>(Test)</b>
> + This policy option enables USB2 PHY SUS Well Power Gating functionality.
> + Please note this is ignored on PCH H
> + <b>0: disable USB2 PHY SUS Well Power Gating</b>
> + 1: enable USB2 PHY SUS Well Power Gating
> + **/
> + UINT32 Usb2PhySusPgEnable : 1;
> + UINT32 RsvdBits0 : 27; ///< Reserved bits
> + /**
> + These members describe whether the USB2 Port N of PCH is enabled by
> platform modules.
> + **/
> + USB20_PORT_CONFIG PortUsb20[MAX_USB2_PORTS];
> + /**
> + These members describe whether the USB3 Port N of PCH is enabled by
> platform modules.
> + **/
> + USB30_PORT_CONFIG PortUsb30[MAX_USB3_PORTS];
> + /**
> + This member describes whether or not the xDCI controller should be
> enabled.
> + **/
> + XDCI_CONFIG XdciConfig;
> + /**
> + This member describes policy options for RX signal tuning in ModPHY
> + **/
> + USB30_HSIO_RX_CONFIG PortUsb30HsioRx[MAX_USB3_PORTS];
> +} USB_CONFIG;
> +
> +#pragma pack (pop)
> +
> +#endif // _USB_CONFIG_H_
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/AslUpdateLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/AslUpdateLib.h
> new file mode 100644
> index 0000000000..39baa6c03a
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/AslUpdateLib.h
> @@ -0,0 +1,157 @@
> +/** @file
> + ASL dynamic update library definitions.
> + This library provides dymanic update to various ASL structures.
> + There may be different libraries for different environments (PEI, BS, RT,
> SMM).
> + Make sure you meet the requirements for the library (protocol
> dependencies, use
> + restrictions, etc).
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _ASL_UPDATE_LIB_H_
> +#define _ASL_UPDATE_LIB_H_
> +
> +//
> +// Include files
> +//
> +#include <IndustryStandard/Acpi.h>
> +#include <Protocol/AcpiTable.h>
> +#include <Protocol/AcpiSystemDescriptionTable.h>
> +
> +//
> +// AML parsing definitions
> +//
> +#define AML_RESRC_TEMP_END_TAG 0x0079
> +
> +//
> +// ASL PSS package structure layout
> +//
> +#pragma pack (1)
> +typedef struct {
> + UINT8 NameOp; // 12h ;First opcode is a NameOp.
> + UINT8 PackageLead; // 20h ;First opcode is a NameOp.
> + UINT8 NumEntries; // 06h ;First opcode is a NameOp.
> + UINT8 DwordPrefix1; // 0Ch
> + UINT32 CoreFrequency; // 00h
> + UINT8 DwordPrefix2; // 0Ch
> + UINT32 Power; // 00h
> + UINT8 DwordPrefix3; // 0Ch
> + UINT32 TransLatency; // 00h
> + UINT8 DwordPrefix4; // 0Ch
> + UINT32 BmLatency; // 00h
> + UINT8 DwordPrefix5; // 0Ch
> + UINT32 Control; // 00h
> + UINT8 DwordPrefix6; // 0Ch
> + UINT32 Status; // 00h
> +} PSS_PACKAGE_LAYOUT;
> +#pragma pack()
> +
> +/**
> + Initialize the ASL update library state.
> + This must be called prior to invoking other library functions.
> +
> +
> + @retval EFI_SUCCESS The function completed successfully.
> +**/
> +EFI_STATUS
> +InitializeAslUpdateLib (
> + VOID
> + );
> +
> +/**
> + This procedure will update immediate value assigned to a Name
> +
> + @param[in] AslSignature The signature of Operation Region that
> we want to update.
> + @param[in] Buffer source of data to be written over original
> aml
> + @param[in] Length length of data to be overwritten
> +
> + @retval EFI_SUCCESS The function completed successfully.
> +**/
> +EFI_STATUS
> +UpdateNameAslCode(
> + IN UINT32 AslSignature,
> + IN VOID *Buffer,
> + IN UINTN Length
> + );
> +
> +/**
> + This procedure will update the name of ASL Method
> +
> + @param[in] AslSignature - The signature of Operation Region that we
> want to update.
> + @param[in] Buffer - source of data to be written over original aml
> + @param[in] Length - length of data to be overwritten
> +
> + @retval EFI_SUCCESS - The function completed successfully.
> + @retval EFI_NOT_FOUND - Failed to locate AcpiTable.
> +**/
> +EFI_STATUS
> +UpdateMethodAslCode (
> + IN UINT32 AslSignature,
> + IN VOID *Buffer,
> + IN UINTN Length
> + );
> +
> +/**
> + This function uses the ACPI support protocol to locate an ACPI table using
> the .
> + It is really only useful for finding tables that only have a single instance,
> + e.g. FADT, FACS, MADT, etc. It is not good for locating SSDT, etc.
> + Matches are determined by finding the table with ACPI table that has
> + a matching signature and version.
> +
> + @param[in] Signature Pointer to an ASCII string containing the
> Signature to match
> + @param[in, out] Table Updated with a pointer to the table
> + @param[in, out] Handle AcpiSupport protocol table handle for
> the table found
> + @param[in, out] Version On input, the version of the table
> desired,
> + on output, the versions the table belongs to
> + @see AcpiSupport protocol for details
> +
> + @retval EFI_SUCCESS The function completed successfully.
> +**/
> +EFI_STATUS
> +LocateAcpiTableBySignature (
> + IN UINT32 Signature,
> + IN OUT EFI_ACPI_DESCRIPTION_HEADER **Table,
> + IN OUT UINTN *Handle
> + );
> +
> +/**
> + This function uses the ACPI support protocol to locate an ACPI SSDT table.
> + The table is located by searching for a matching OEM Table ID field.
> + Partial match searches are supported via the TableIdSize parameter.
> +
> + @param[in] TableId Pointer to an ASCII string containing the
> OEM Table ID from the ACPI table header
> + @param[in] TableIdSize Length of the TableId to match. Table ID
> are 8 bytes long, this function
> + will consider it a match if the first TableIdSize
> bytes match
> + @param[in, out] Table Updated with a pointer to the table
> + @param[in, out] Handle AcpiSupport protocol table handle for
> the table found
> + @param[in, out] Version See AcpiSupport protocol, GetAcpiTable
> function for use
> +
> + @retval EFI_SUCCESS The function completed successfully.
> +**/
> +EFI_STATUS
> +LocateAcpiTableByOemTableId (
> + IN UINT8 *TableId,
> + IN UINT8 TableIdSize,
> + IN OUT EFI_ACPI_DESCRIPTION_HEADER **Table,
> + IN OUT UINTN *Handle
> + );
> +
> +/**
> + This function calculates and updates an UINT8 checksum.
> +
> + @param[in] Buffer Pointer to buffer to checksum
> + @param[in] Size Number of bytes to checksum
> + @param[in] ChecksumOffset Offset to place the checksum result in
> +
> + @retval EFI_SUCCESS The function completed successfully.
> +**/
> +EFI_STATUS
> +AcpiChecksum (
> + IN VOID *Buffer,
> + IN UINTN Size,
> + IN UINTN ChecksumOffset
> + );
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/ConfigBlockLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/ConfigBlockLib.h
> new file mode 100644
> index 0000000000..9a3bf373a6
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/ConfigBlockLib.h
> @@ -0,0 +1,64 @@
> +/** @file
> + Header file for Config Block Lib implementation
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _CONFIG_BLOCK_LIB_H_
> +#define _CONFIG_BLOCK_LIB_H_
> +
> +/**
> + Create config block table
> +
> + @param[in] TotalSize - Max size to be allocated for the
> Config Block Table
> + @param[out] ConfigBlockTableAddress - On return, points to a
> pointer to the beginning of Config Block Table Address
> +
> + @retval EFI_INVALID_PARAMETER - Invalid Parameter
> + @retval EFI_OUT_OF_RESOURCES - Out of resources
> + @retval EFI_SUCCESS - Successfully created Config Block Table at
> ConfigBlockTableAddress
> +**/
> +EFI_STATUS
> +EFIAPI
> +CreateConfigBlockTable (
> + IN UINT16 TotalSize,
> + OUT VOID **ConfigBlockTableAddress
> + );
> +
> +/**
> + Add config block into config block table structure
> +
> + @param[in] ConfigBlockTableAddress - A pointer to the beginning of
> Config Block Table Address
> + @param[out] ConfigBlockAddress - On return, points to a pointer
> to the beginning of Config Block Address
> +
> + @retval EFI_OUT_OF_RESOURCES - Config Block Table is full and cannot add
> new Config Block or
> + Config Block Offset Table is full and cannot add new
> Config Block.
> + @retval EFI_SUCCESS - Successfully added Config Block
> +**/
> +EFI_STATUS
> +EFIAPI
> +AddConfigBlock (
> + IN VOID *ConfigBlockTableAddress,
> + OUT VOID **ConfigBlockAddress
> + );
> +
> +/**
> + Retrieve a specific Config Block data by GUID
> +
> + @param[in] ConfigBlockTableAddress - A pointer to the beginning
> of Config Block Table Address
> + @param[in] ConfigBlockGuid - A pointer to the GUID uses to
> search specific Config Block
> + @param[out] ConfigBlockAddress - On return, points to a
> pointer to the beginning of Config Block Address
> +
> + @retval EFI_NOT_FOUND - Could not find the Config Block
> + @retval EFI_SUCCESS - Config Block found and return
> +**/
> +EFI_STATUS
> +EFIAPI
> +GetConfigBlock (
> + IN VOID *ConfigBlockTableAddress,
> + IN EFI_GUID *ConfigBlockGuid,
> + OUT VOID **ConfigBlockAddress
> + );
> +
> +#endif // _CONFIG_BLOCK_LIB_H_
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/MmPciLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/MmPciLib.h
> new file mode 100644
> index 0000000000..858f8ac5e6
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/MmPciLib.h
> @@ -0,0 +1,28 @@
> +/** @file
> + Get Pci Express address library implementation.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _MM_PCI_LIB_H_
> +#define _MM_PCI_LIB_H_
> +
> +/**
> + This procedure will get PCIE address
> +
> + @param[in] Bus Pci Bus Number
> + @param[in] Device Pci Device Number
> + @param[in] Function Pci Function Number
> +
> + @retval PCIE address
> +**/
> +UINTN
> +MmPciBase (
> + IN UINT32 Bus,
> + IN UINT32 Device,
> + IN UINT32 Function
> +);
> +
> +#endif // _PEI_DXE_SMM_MM_PCI_LIB_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h
> new file mode 100644
> index 0000000000..c6eb70f6e2
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h
> @@ -0,0 +1,123 @@
> +/** @file
> + Header file for PEI SiPolicyUpdate Library.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PEI_SI_POLICY_UPDATE_LIB_H_
> +#define _PEI_SI_POLICY_UPDATE_LIB_H_
> +
> +#include <Ppi/SiPolicy.h>
> +
> +/**
> + This function performs Silicon PEI Policy initialization.
> +
> + @param[in, out] SiPolicy The Silicon Policy PPI instance
> +
> + @retval EFI_SUCCESS The function completed successfully
> +**/
> +EFI_STATUS
> +EFIAPI
> +UpdatePeiSiPolicy (
> + IN OUT SI_POLICY_PPI *SiPolicy
> + );
> +
> +/**
> + This function performs CPU PEI Policy initialization in Post-memory.
> +
> + @param[in, out] SiPolicyPpi The SI Policy PPI instance
> +
> + @retval EFI_SUCCESS The PPI is installed and initialized.
> + @retval EFI ERRORS The PPI is not successfully installed.
> + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to
> initialize the driver
> +**/
> +EFI_STATUS
> +EFIAPI
> +UpdatePeiCpuPolicy (
> + IN OUT SI_POLICY_PPI *SiPolicyPpi
> + );
> +
> +/**
> + This function performs SI PEI Policy initialization.
> +
> + @param[in, out] SiPolicyPpi The SA Policy PPI instance
> +
> + @retval EFI_SUCCESS The PPI is installed and initialized.
> +**/
> +EFI_STATUS
> +EFIAPI
> +UpdatePeiSaPolicy (
> + IN OUT SI_POLICY_PPI *SiPolicyPpi
> + );
> +
> +
> +/**
> +This function performs SA PEI Policy initialization for PreMem.
> +
> + at param[in, out] SiPreMemPolicyPpi The SI PreMem Policy PPI instance
> +
> + at retval EFI_SUCCESS Update complete.
> +**/
> +EFI_STATUS
> +EFIAPI
> +UpdatePeiSaPolicyPreMem (
> +IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
> +);
> +
> +/**
> + This function performs PCH PEI Policy initialization.
> +
> + @param[in, out] SiPolicy The SI Policy PPI instance
> +
> + @retval EFI_SUCCESS The PPI is installed and initialized.
> + @retval EFI ERRORS The PPI is not successfully installed.
> + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to
> initialize the driver
> +**/
> +EFI_STATUS
> +EFIAPI
> +UpdatePeiPchPolicy (
> + IN OUT SI_POLICY_PPI *SiPolicy
> + );
> +
> +/**
> + This function performs PCH PEI Policy initialization.
> +
> + @param[in, out] SiPreMemPolicy The SI PreMem Policy PPI instance
> +
> + @retval EFI_SUCCESS The PPI is installed and initialized.
> + @retval EFI ERRORS The PPI is not successfully installed.
> + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to
> initialize the driver
> +**/
> +EFI_STATUS
> +EFIAPI
> +UpdatePeiPchPolicyPreMem (
> + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicy
> + );
> +
> +/**
> + Update the ME Policy Library
> +
> + @param[in, out] SiPolicy The SI Policy PPI instance
> +
> + @retval EFI_SUCCESS Update complete.
> +**/
> +EFI_STATUS
> +UpdatePeiMePolicy (
> + IN OUT SI_POLICY_PPI *SiPolicy
> + );
> +
> +/**
> + Update the ME Policy Library
> +
> + @param[in, out] SiPreMemPolicy The SI PreMem Policy PPI instance
> +
> + @retval EFI_SUCCESS Update complete.
> +**/
> +EFI_STATUS
> +UpdatePeiMePolicyPreMem (
> + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicy
> + );
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiConfigBlockLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiConfigBlockLib.h
> new file mode 100644
> index 0000000000..fd8582b981
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiConfigBlockLib.h
> @@ -0,0 +1,58 @@
> +/** @file
> + Prototype of the SiConfigBlockLib library.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SI_CONFIG_BLOCK_LIB_H_
> +#define _SI_CONFIG_BLOCK_LIB_H_
> +
> +
> +typedef
> +VOID
> +(*LOAD_DEFAULT_FUNCTION) (
> + IN VOID *ConfigBlockPointer
> + );
> +
> +typedef struct {
> + EFI_GUID *Guid;
> + UINT16 Size;
> + UINT8 Revision;
> + LOAD_DEFAULT_FUNCTION LoadDefault;
> +} COMPONENT_BLOCK_ENTRY;
> +
> +/**
> + GetComponentConfigBlockTotalSize get config block table total size.
> +
> + @param[in] ComponentBlocks Component blocks array
> + @param[in] TotalBlockCount Number of blocks
> +
> + @retval Size of config block table
> +**/
> +UINT16
> +EFIAPI
> +GetComponentConfigBlockTotalSize (
> + IN COMPONENT_BLOCK_ENTRY *ComponentBlocks,
> + IN UINT16 TotalBlockCount
> + );
> +
> +/**
> + AddComponentConfigBlocks add all config blocks.
> +
> + @param[in] ConfigBlockTableAddress The pointer to add config blocks
> + @param[in] ComponentBlocks Config blocks array
> + @param[in] TotalBlockCount Number of blocks
> +
> + @retval EFI_SUCCESS The policy default is initialized.
> + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create
> buffer
> +**/
> +EFI_STATUS
> +EFIAPI
> +AddComponentConfigBlocks (
> + IN VOID *ConfigBlockTableAddress,
> + IN COMPONENT_BLOCK_ENTRY *ComponentBlocks,
> + IN UINT16 TotalBlockCount
> + );
> +#endif // _SI_CONFIG_BLOCK_LIB_H_
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiPolicyLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiPolicyLib.h
> new file mode 100644
> index 0000000000..5633e2892c
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiPolicyLib.h
> @@ -0,0 +1,110 @@
> +/** @file
> + Prototype of the SiPolicyLib library.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SI_POLICY_LIB_H_
> +#define _SI_POLICY_LIB_H_
> +
> +#include <Ppi/SiPolicy.h>
> +
> +/**
> + Print whole SI_PREMEM_POLICY_PPI and serial out.
> +
> + @param[in] SiPreMemPolicyPpi The RC PREMEM Policy PPI instance
> +**/
> +VOID
> +EFIAPI
> +SiPreMemPrintPolicyPpi (
> + IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
> + );
> +
> +/**
> + Print whole SI_POLICY_PPI and serial out.
> +
> + @param[in] SiPolicyPpi The RC Policy PPI instance
> +**/
> +VOID
> +EFIAPI
> +SiPrintPolicyPpi (
> + IN SI_POLICY_PPI *SiPolicyPpi
> + );
> +
> +/**
> + SiCreatePreMemConfigBlocks creates the config blocksg of Silicon Policy.
> + It allocates and zero out buffer, and fills in the Intel default settings.
> +
> + @param[out] SiPreMemPolicyPpi The pointer to get Silicon PREMEM
> Policy PPI instance
> +
> + @retval EFI_SUCCESS The policy default is initialized.
> + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
> +**/
> +EFI_STATUS
> +EFIAPI
> +SiCreatePreMemConfigBlocks (
> + OUT SI_PREMEM_POLICY_PPI **SiPreMemPolicyPpi
> + );
> +
> +/**
> + SiCreateConfigBlocks creates the config blocksg of Silicon Policy.
> + It allocates and zero out buffer, and fills in the Intel default settings.
> +
> + @param[out] SiPolicyPpi The pointer to get Silicon Policy PPI instance
> +
> + @retval EFI_SUCCESS The policy default is initialized.
> + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
> +**/
> +EFI_STATUS
> +EFIAPI
> +SiCreateConfigBlocks (
> + OUT SI_POLICY_PPI **SiPolicyPpi
> + );
> +
> +/**
> + SiPreMemInstallPolicyPpi installs SiPreMemPolicyPpi.
> + While installed, RC assumes the Policy is ready and finalized. So please
> update and override
> + any setting before calling this function.
> +
> + @param[in] SiPreMemPolicyPpi The pointer to Silicon PREMEM Policy PPI
> instance
> +
> + @retval EFI_SUCCESS The policy is installed.
> + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
> +**/
> +EFI_STATUS
> +EFIAPI
> +SiPreMemInstallPolicyPpi (
> + IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
> + );
> +
> +/**
> + SiInstallPolicyPpi installs SiPolicyPpi.
> + While installed, RC assumes the Policy is ready and finalized. So please
> update and override
> + any setting before calling this function.
> +
> + @param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance
> +
> + @retval EFI_SUCCESS The policy is installed.
> + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
> +**/
> +EFI_STATUS
> +EFIAPI
> +SiInstallPolicyPpi (
> + IN SI_POLICY_PPI *SiPolicyPpi
> + );
> +
> +/**
> + Print out all silicon policy information.
> +
> + @param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance
> +
> + @retval none
> +**/
> +VOID
> +DumpSiPolicy (
> + IN SI_POLICY_PPI *SiPolicyPpi
> + );
> +
> +#endif // _SI_PREMEM_POLICY_LIB_H_
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/StallPpiLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/StallPpiLib.h
> new file mode 100644
> index 0000000000..cab5342c54
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/StallPpiLib.h
> @@ -0,0 +1,22 @@
> +/** @file
> + Header file for a library to install StallPpi.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _STALL_PPI_LIB_H_
> +#define _STALL_PPI_LIB_H_
> +
> +/**
> + This function is to install StallPpi
> +
> + @retval EFI_SUCCESS if Ppi is installed successfully.
> +**/
> +EFI_STATUS
> +EFIAPI
> +InstallStallPpi(
> + VOID
> + );
> +#endif //_STALL_PPI_LIB_H_
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/UsbLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/UsbLib.h
> new file mode 100644
> index 0000000000..a7cd305c62
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/UsbLib.h
> @@ -0,0 +1,34 @@
> +/** @file
> + Header file of available functions in general USB Library
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _USB_LIB_H_
> +#define _USB_LIB_H_
> +
> +#include <Uefi/UefiBaseType.h>
> +
> +/*
> + Disables requested ports through Port Disable Override register
> programming
> +
> + @param[in] XhciMmioBase xHCI Memory BAR0 address
> + @param[in] Usb2DisabledPorts Disabled ports bitmask with a bit for
> each USB2 port
> + i.e. BIT0 is Port 0, BIT1 is Port 1 etc
> + @param[in] Usb3DisabledPorts Disabled ports bitmask with a bit for
> each USB3 port
> + i.e. BIT0 is Port 0, BIT1 is Port 1 etc
> +
> + @retval EFI_SUCCESS Programming ended successfully and no
> errors occured
> + EFI_ACCESS_DENIED Port Disable Override register was locked
> and write
> + didn't go through. Platform may require restart to
> unlock.
> +*/
> +EFI_STATUS
> +UsbDisablePorts (
> + IN UINTN XhciMmioBase,
> + IN UINT32 Usb2DisabledPorts,
> + IN UINT32 Usb3DisabledPorts
> + );
> +
> +#endif // _USB_LIB_H
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/PcieRegs.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Include/PcieRegs.h
> new file mode 100644
> index 0000000000..86bed53c6f
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/PcieRegs.h
> @@ -0,0 +1,319 @@
> +/** @file
> + Register names for PCIE standard register
> +
> + Conventions:
> +
> + - Prefixes:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register sizes
> + Definitions beginning with "N_" are the bit position
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCIE_REGS_H_
> +#define _PCIE_REGS_H_
> +
> +#include <IndustryStandard/Pci30.h>
> +
> +//
> +// PCI type 0 Header
> +//
> +#define R_PCI_PI_OFFSET 0x09
> +#define R_PCI_SCC_OFFSET 0x0A
> +#define R_PCI_BCC_OFFSET 0x0B
> +
> +//
> +// PCI type 1 Header
> +//
> +#define R_PCI_BRIDGE_BNUM 0x18 ///< Bus Number
> Register
> +#define B_PCI_BRIDGE_BNUM_SBBN 0x00FF0000 ///<
> Subordinate Bus Number
> +#define B_PCI_BRIDGE_BNUM_SCBN 0x0000FF00 ///<
> Secondary Bus Number
> +#define B_PCI_BRIDGE_BNUM_PBN 0x000000FF ///< Primary
> Bus Number
> +#define B_PCI_BRIDGE_BNUM_SBBN_SCBN
> (B_PCI_BRIDGE_BNUM_SBBN | B_PCI_BRIDGE_BNUM_SCBN)
> +
> +#define R_PCI_BRIDGE_IOBL 0x1C ///< I/O Base and Limit
> Register
> +
> +#define R_PCI_BRIDGE_MBL 0x20 ///< Memory Base and
> Limit Register
> +#define B_PCI_BRIDGE_MBL_ML 0xFFF00000 ///< Memory
> Limit
> +#define B_PCI_BRIDGE_MBL_MB 0x0000FFF0 ///< Memory
> Base
> +
> +#define R_PCI_BRIDGE_PMBL 0x24 ///< Prefetchable
> Memory Base and Limit Register
> +#define B_PCI_BRIDGE_PMBL_PML 0xFFF00000 ///<
> Prefetchable Memory Limit
> +#define B_PCI_BRIDGE_PMBL_I64L 0x000F0000 ///< 64-bit
> Indicator
> +#define B_PCI_BRIDGE_PMBL_PMB 0x0000FFF0 ///<
> Prefetchable Memory Base
> +#define B_PCI_BRIDGE_PMBL_I64B 0x0000000F ///< 64-bit
> Indicator
> +
> +#define R_PCI_BRIDGE_PMBU32 0x28 ///< Prefetchable
> Memory Base Upper 32-Bit Register
> +#define B_PCI_BRIDGE_PMBU32 0xFFFFFFFF
> +
> +#define R_PCI_BRIDGE_PMLU32 0x2C ///< Prefetchable
> Memory Limit Upper 32-Bit Register
> +#define B_PCI_BRIDGE_PMLU32 0xFFFFFFFF
> +
> +//
> +// PCIE capabilities register
> +//
> +#define R_PCIE_CAP_ID_OFFSET 0x00 ///< Capability ID
> +#define R_PCIE_CAP_NEXT_PRT_OFFSET 0x01 ///< Next Capability
> Capability ID Pointer
> +
> +//
> +// PCI Express Capability List Register (CAPID:10h)
> +//
> +#define R_PCIE_XCAP_OFFSET 0x02 ///< PCI Express
> Capabilities Register (Offset 02h)
> +#define S_PCIE_XCAP 2
> +#define B_PCIE_XCAP_SI BIT8 ///< Slot Implemented
> +#define B_PCIE_XCAP_DT (BIT7 | BIT6 | BIT5 | BIT4) ///<
> Device/Port Type
> +#define N_PCIE_XCAP_DT 4
> +
> +#define R_PCIE_DCAP_OFFSET 0x04 ///< Device Capabilities
> Register (Offset 04h)
> +#define S_PCIE_DCAP 4
> +#define B_PCIE_DCAP_RBER BIT15 ///< Role-Based Error
> Reporting
> +#define B_PCIE_DCAP_E1AL (BIT11 | BIT10 | BIT9) ///<
> Endpoint L1 Acceptable Latency
> +#define N_PCIE_DCAP_E1AL 9
> +#define B_PCIE_DCAP_E0AL (BIT8 | BIT7 | BIT6) ///<
> Endpoint L0s Acceptable Latency
> +#define N_PCIE_DCAP_E0AL 6
> +#define B_PCIE_DCAP_MPS (BIT2 | BIT1 | BIT0) ///<
> Max_Payload_Size Supported
> +
> +#define R_PCIE_DCTL_OFFSET 0x08 ///< Device Control
> Register (Offset 08h)
> +#define B_PCIE_DCTL_MPS (BIT7 | BIT6 | BIT5) ///<
> Max_Payload_Size
> +#define N_PCIE_DCTL_MPS 5
> +#define B_PCIE_DCTL_URE BIT3 ///< Unsupported
> Request Reporting Enable
> +#define B_PCIE_DCTL_FEE BIT2 ///< Fatal Error Reporting
> Enable
> +#define B_PCIE_DCTL_NFE BIT1 ///< Non-Fatal Error
> Reporting Enable
> +#define B_PCIE_DCTL_CEE BIT0 ///< Correctable Error
> Reporting Enable
> +
> +#define R_PCIE_DSTS_OFFSET 0x0A ///< Device Status
> Register (Offset 0Ah)
> +#define B_PCIE_DSTS_TDP BIT5 ///< Transactions Pending
> +#define B_PCIE_DSTS_APD BIT4 ///< AUX Power Detected
> +#define B_PCIE_DSTS_URD BIT3 ///< Unsupported
> Request Detected
> +#define B_PCIE_DSTS_FED BIT2 ///< Fatal Error Detected
> +#define B_PCIE_DSTS_NFED BIT1 ///< Non-Fatal Error
> Detected
> +#define B_PCIE_DSTS_CED BIT0 ///< Correctable Error
> Detected
> +
> +#define R_PCIE_LCAP_OFFSET 0x0C ///< Link Capabilities
> Register (Offset 0Ch)
> +#define B_PCIE_LCAP_ASPMOC BIT22 ///< ASPM Optionality
> Compliance
> +#define B_PCIE_LCAP_CPM BIT18 ///< Clock Power
> Management
> +#define B_PCIE_LCAP_EL1 (BIT17 | BIT16 | BIT15) ///< L1
> Exit Latency
> +#define N_PCIE_LCAP_EL1 15
> +#define B_PCIE_LCAP_EL0 (BIT14 | BIT13 | BIT12) ///< L0s
> Exit Latency
> +#define N_PCIE_LCAP_EL0 12
> +#define B_PCIE_LCAP_APMS (BIT11 | BIT10) ///< Active
> State Power Management (ASPM) Support
> +#define B_PCIE_LCAP_APMS_L0S BIT10
> +#define B_PCIE_LCAP_APMS_L1 BIT11
> +#define N_PCIE_LCAP_APMS 10
> +#define B_PCIE_LCAP_MLW 0x000003F0 ///< Maximum
> Link Width
> +#define N_PCIE_LCAP_MLW 4
> +#define B_PCIE_LCAP_MLS (BIT3 | BIT2 | BIT1 | BIT0) ///<
> Max Link Speed
> +#define V_PCIE_LCAP_MLS_GEN3 3
> +
> +#define R_PCIE_LCTL_OFFSET 0x10 ///< Link Control
> Register (Offset 10h)
> +#define B_PCIE_LCTL_ECPM BIT8 ///< Enable Clock Power
> Management
> +#define B_PCIE_LCTL_ES BIT7 ///< Extended Synch
> +#define B_PCIE_LCTL_CCC BIT6 ///< Common Clock
> Configuration
> +#define B_PCIE_LCTL_RL BIT5 ///< Retrain Link
> +#define B_PCIE_LCTL_LD BIT4 ///< Link Disable
> +#define B_PCIE_LCTL_ASPM (BIT1 | BIT0) ///< Active State
> Power Management (ASPM) Control
> +#define V_PCIE_LCTL_ASPM_L0S 1
> +#define V_PCIE_LCTL_ASPM_L1 2
> +#define V_PCIE_LCTL_ASPM_L0S_L1 3
> +
> +#define R_PCIE_LSTS_OFFSET 0x12 ///< Link Status Register
> (Offset 12h)
> +#define B_PCIE_LSTS_LA BIT13 ///< Data Link Layer Link
> Active
> +#define B_PCIE_LSTS_SCC BIT12 ///< Slot Clock
> Configuration
> +#define B_PCIE_LSTS_LT BIT11 ///< Link Training
> +#define B_PCIE_LSTS_NLW 0x03F0 ///< Negotiated Link
> Width
> +#define N_PCIE_LSTS_NLW 4
> +#define V_PCIE_LSTS_NLW_1 0x0010
> +#define V_PCIE_LSTS_NLW_2 0x0020
> +#define V_PCIE_LSTS_NLW_4 0x0040
> +#define B_PCIE_LSTS_CLS 0x000F ///< Current Link Speed
> +#define V_PCIE_LSTS_CLS_GEN1 1
> +#define V_PCIE_LSTS_CLS_GEN2 2
> +#define V_PCIE_LSTS_CLS_GEN3 3
> +
> +#define R_PCIE_SLCAP_OFFSET 0x14 ///< Slot Capabilities
> Register (Offset 14h)
> +#define S_PCIE_SLCAP 4
> +#define B_PCIE_SLCAP_PSN 0xFFF80000 ///< Physical Slot
> Number
> +#define B_PCIE_SLCAP_SLS 0x00018000 ///< Slot Power
> Limit Scale
> +#define B_PCIE_SLCAP_SLV 0x00007F80 ///< Slot Power
> Limit Value
> +#define B_PCIE_SLCAP_HPC BIT6 ///< Hot-Plug Capable
> +#define B_PCIE_SLCAP_HPS BIT5 ///< Hot-Plug Surprise
> +
> +#define R_PCIE_SLCTL_OFFSET 0x18 ///< Slot Control
> Register (Offset 18h)
> +#define S_PCIE_SLCTL 2
> +#define B_PCIE_SLCTL_HPE BIT5 ///< Hot Plug Interrupt
> Enable
> +#define B_PCIE_SLCTL_PDE BIT3 ///< Presence Detect
> Changed Enable
> +
> +#define R_PCIE_SLSTS_OFFSET 0x1A ///< Slot Status Register
> (Offset 1Ah)
> +#define S_PCIE_SLSTS 2
> +#define B_PCIE_SLSTS_PDS BIT6 ///< Presence Detect State
> +#define B_PCIE_SLSTS_PDC BIT3 ///< Presence Detect
> Changed
> +
> +#define R_PCIE_RCTL_OFFSET 0x1C ///< Root Control
> Register (Offset 1Ch)
> +#define S_PCIE_RCTL 2
> +#define B_PCIE_RCTL_PIE BIT3 ///< PME Interrupt Enable
> +#define B_PCIE_RCTL_SFE BIT2 ///< System Error on Fatal
> Error Enable
> +#define B_PCIE_RCTL_SNE BIT1 ///< System Error on
> Non-Fatal Error Enable
> +#define B_PCIE_RCTL_SCE BIT0 ///< System Error on
> Correctable Error Enable
> +
> +#define R_PCIE_RSTS_OFFSET 0x20 ///< Root Status Register
> (Offset 20h)
> +#define S_PCIE_RSTS 4
> +
> +#define R_PCIE_DCAP2_OFFSET 0x24 ///< Device Capabilities
> 2 Register (Offset 24h)
> +#define B_PCIE_DCAP2_OBFFS (BIT19 | BIT18) ///< OBFF
> Supported
> +#define B_PCIE_DCAP2_LTRMS BIT11 ///< LTR Mechanism
> Supported
> +
> +#define R_PCIE_DCTL2_OFFSET 0x28 ///< Device Control 2
> Register (Offset 28h)
> +#define B_PCIE_DCTL2_OBFFEN (BIT14 | BIT13) ///< OBFF
> Enable
> +#define N_PCIE_DCTL2_OBFFEN 13
> +#define V_PCIE_DCTL2_OBFFEN_DIS 0 ///< Disabled
> +#define V_PCIE_DCTL2_OBFFEN_WAKE 3 ///< Enabled using
> WAKE# signaling
> +#define B_PCIE_DCTL2_LTREN BIT10 ///< LTR Mechanism
> Enable
> +#define B_PCIE_DCTL2_CTD BIT4 ///< Completion Timeout
> Disable
> +#define B_PCIE_DCTL2_CTV (BIT3 | BIT2 | BIT1 | BIT0) ///<
> Completion Timeout Value
> +#define V_PCIE_DCTL2_CTV_DEFAULT 0x0
> +#define V_PCIE_DCTL2_CTV_40MS_50MS 0x5
> +#define V_PCIE_DCTL2_CTV_160MS_170MS 0x6
> +#define V_PCIE_DCTL2_CTV_400MS_500MS 0x9
> +#define V_PCIE_DCTL2_CTV_1P6S_1P7S 0xA
> +
> +#define R_PCIE_LCTL2_OFFSET 0x30 ///< Link Control 2
> Register (Offset 30h)
> +#define B_PCIE_LCTL2_SD BIT6 ///< Selectable
> de-emphasis (0 = -6dB, 1 = -3.5dB)
> +#define B_PCIE_LCTL2_TLS (BIT3 | BIT2 | BIT1 | BIT0) ///<
> Target Link Speed
> +#define V_PCIE_LCTL2_TLS_GEN1 1
> +#define V_PCIE_LCTL2_TLS_GEN2 2
> +#define V_PCIE_LCTL2_TLS_GEN3 3
> +
> +#define R_PCIE_LSTS2_OFFSET 0x32 ///< Link Status 2
> Register (Offset 32h)
> +#define B_PCIE_LSTS2_LER BIT5 ///< Link Equalization
> Request
> +#define B_PCIE_LSTS2_EQP3S BIT4 ///< Equalization Phase 3
> Successful
> +#define B_PCIE_LSTS2_EQP2S BIT3 ///< Equalization Phase 2
> Successful
> +#define B_PCIE_LSTS2_EQP1S BIT2 ///< Equalization Phase 1
> Successful
> +#define B_PCIE_LSTS2_EC BIT1 ///< Equalization
> Complete
> +#define B_PCIE_LSTS2_CDL BIT0 ///< Current De-emphasis
> Level
> +
> +//
> +// PCI Power Management Capability (CAPID:01h)
> +//
> +#define R_PCIE_PMC_OFFSET 0x02 ///< Power
> Management Capabilities Register
> +#define S_PCIE_PMC 2
> +#define B_PCIE_PMC_PMES (BIT15 | BIT14 | BIT13 | BIT12
> | BIT11) ///< PME Support
> +#define B_PCIE_PMC_PMEC BIT3 ///< PME Clock
> +
> +#define R_PCIE_PMCS_OFFST 0x04 ///< Power
> Management Status/Control Register
> +#define S_PCIE_PMCS 4
> +#define B_PCIE_PMCS_BPCE BIT23 ///< Bus Power/Clock
> Control Enable
> +#define B_PCIE_PMCS_B23S BIT22 ///< B2/B3 Support
> +#define B_PCIE_PMCS_PMES BIT15 ///< PME_Status
> +#define B_PCIE_PMCS_PMEE BIT8 ///< PME Enable
> +#define B_PCIE_PMCS_NSR BIT3 ///< No Soft Reset
> +#define B_PCIE_PMCS_PS (BIT1 | BIT0) ///< Power State
> +#define V_PCIE_PMCS_PS_D0 0
> +#define V_PCIE_PMCS_PS_D3H 3
> +
> +//
> +// PCIE Extension Capability Register
> +//
> +#define B_PCIE_EXCAP_NCO 0xFFF00000 ///< Next
> Capability Offset
> +#define N_PCIE_EXCAP_NCO 20
> +#define V_PCIE_EXCAP_NCO_LISTEND 0
> +#define B_PCIE_EXCAP_CV 0x000F0000 ///< Capability
> Version
> +#define N_PCIE_EXCAP_CV 16
> +#define B_PCIE_EXCAP_CID 0x0000FFFF ///< Capability ID
> +
> +//
> +// Advanced Error Reporting Capability (CAPID:0001h)
> +//
> +#define V_PCIE_EX_AEC_CID 0x0001 ///< Capability ID
> +#define R_PCIE_EX_UEM_OFFSET 0x08 ///< Uncorrectable
> Error Mask Register
> +#define B_PCIE_EX_UEM_CT BIT14 ///< Completion
> Timeout Mask
> +#define B_PCIE_EX_UEM_UC BIT16 ///< Unexpected
> Completion
> +
> +//
> +// ACS Extended Capability (CAPID:000Dh)
> +//
> +#define V_PCIE_EX_ACS_CID 0x000D ///< Capability ID
> +#define R_PCIE_EX_ACSCAPR_OFFSET 0x04 ///< ACS Capability
> Register
> +//#define R_PCIE_EX_ACSCTLR_OFFSET 0x08 ///< ACS Control
> Register (NOTE: register size in PCIE spce is not match the PCH register size)
> +
> +
> +//
> +// Latency Tolerance Reporting Extended Capability Registers (CAPID:0018h)
> +//
> +#define R_PCH_PCIE_LTRECH_CID 0x0018
> +#define R_PCH_PCIE_LTRECH_MSLR_OFFSET 0x04
> +#define N_PCH_PCIE_LTRECH_MSLR_VALUE 0
> +#define N_PCH_PCIE_LTRECH_MSLR_SCALE 10
> +#define R_PCH_PCIE_LTRECH_MNSLR_OFFSET 0x06
> +#define N_PCH_PCIE_LTRECH_MNSLR_VALUE 0
> +#define N_PCH_PCIE_LTRECH_MNSLR_SCALE 10
> +//
> +// Secondary PCI Express Extended Capability Header (CAPID:0019h)
> +//
> +#define V_PCIE_EX_SPE_CID 0x0019 ///< Capability ID
> +#define R_PCIE_EX_LCTL3_OFFSET 0x04 ///< Link Control 3
> Register
> +#define B_PCIE_EX_LCTL3_PE BIT0 ///< Perform
> Equalization
> +#define R_PCIE_EX_LES_OFFSET 0x08 ///< Lane Error Status
> +#define R_PCIE_EX_L01EC_OFFSET 0x0C ///< Lane 0 and Lan 1
> Equalization Control Register (Offset 0Ch)
> +#define B_PCIE_EX_L01EC_UPL1TP 0x0F000000 ///< Upstream
> Port Lane 1 Transmitter Preset
> +#define N_PCIE_EX_L01EC_UPL1TP 24
> +#define B_PCIE_EX_L01EC_DPL1TP 0x000F0000 ///<
> Downstream Port Lane 1 Transmitter Preset
> +#define N_PCIE_EX_L01EC_DPL1TP 16
> +#define B_PCIE_EX_L01EC_UPL0TP 0x00000F00 ///< Upstream
> Port Transmitter Preset
> +#define N_PCIE_EX_L01EC_UPL0TP 8
> +#define B_PCIE_EX_L01EC_DPL0TP 0x0000000F ///<
> Downstream Port Transmitter Preset
> +#define N_PCIE_EX_L01EC_DPL0TP 0
> +
> +#define R_PCIE_EX_L23EC_OFFSET 0x10 ///< Lane 2 and Lane 3
> Equalization Control Register (Offset 10h)
> +#define B_PCIE_EX_L23EC_UPL3TP 0x0F000000 ///< Upstream
> Port Lane 3 Transmitter Preset
> +#define N_PCIE_EX_L23EC_UPL3TP 24
> +#define B_PCIE_EX_L23EC_DPL3TP 0x000F0000 ///<
> Downstream Port Lane 3 Transmitter Preset
> +#define N_PCIE_EX_L23EC_DPL3TP 16
> +#define B_PCIE_EX_L23EC_UPL2TP 0x00000F00 ///< Upstream
> Port Lane 2 Transmitter Preset
> +#define N_PCIE_EX_L23EC_UPL2TP 8
> +#define B_PCIE_EX_L23EC_DPL2TP 0x0000000F ///<
> Downstream Port Lane 2 Transmitter Preset
> +#define N_PCIE_EX_L23EC_DPL2TP 0
> +
> +
> +//
> +// L1 Sub-States Extended Capability Register (CAPID:001Eh)
> +//
> +#define V_PCIE_EX_L1S_CID 0x001E ///< Capability ID
> +#define R_PCIE_EX_L1SCAP_OFFSET 0x04 ///< L1 Sub-States
> Capabilities
> +#define B_PCIE_EX_L1SCAP_PTV 0x00F80000 //< Port
> Tpower_on value
> +#define N_PCIE_EX_L1SCAP_PTV 19
> +#define B_PCIE_EX_L1SCAP_PTPOS 0x00030000 //< Port
> Tpower_on scale
> +#define N_PCIE_EX_L1SCAP_PTPOS 16
> +#define B_PCIE_EX_L1SCAP_CMRT 0x0000FF00 //< Common
> Mode Restore time
> +#define N_PCIE_EX_L1SCAP_CMRT 8
> +#define V_PCIE_EX_L1SCAP_PTPOS_2us 0
> +#define V_PCIE_EX_L1SCAP_PTPOS_10us 1
> +#define V_PCIE_EX_L1SCAP_PTPOS_100us 2
> +#define B_PCIE_EX_L1SCAP_L1PSS BIT4 ///< L1 PM substates
> supported
> +#define B_PCIE_EX_L1SCAP_AL1SS BIT3 ///< ASPM L1.1
> supported
> +#define B_PCIE_EX_L1SCAP_AL12S BIT2 ///< ASPM L1.2
> supported
> +#define B_PCIE_EX_L1SCAP_PPL11S BIT1 ///< PCI-PM L1.1
> supported
> +#define B_PCIE_EX_L1SCAP_PPL12S BIT0 ///< PCI-PM L1.2
> supported
> +#define R_PCIE_EX_L1SCTL1_OFFSET 0x08 ///< L1 Sub-States
> Control 1
> +#define N_PCIE_EX_L1SCTL1_L12LTRTLSV 29
> +#define N_PCIE_EX_L1SCTL1_L12LTRTLV 16
> +#define R_PCIE_EX_L1SCTL2_OFFSET 0x0C ///< L1 Sub-States
> Control 2
> +#define N_PCIE_EX_L1SCTL2_POWT 3
> +
> +//
> +// Base Address Offset
> +//
> +#define R_BASE_ADDRESS_OFFSET_0 0x0010 ///< Base Address
> Register 0
> +#define R_BASE_ADDRESS_OFFSET_1 0x0014 ///< Base Address
> Register 1
> +#define R_BASE_ADDRESS_OFFSET_2 0x0018 ///< Base Address
> Register 2
> +#define R_BASE_ADDRESS_OFFSET_3 0x001C ///< Base Address
> Register 3
> +#define R_BASE_ADDRESS_OFFSET_4 0x0020 ///< Base Address
> Register 4
> +#define R_BASE_ADDRESS_OFFSET_5 0x0024 ///< Base Address
> Register 5
> +#define B_PCI_BAR_MEMORY_TYPE_MASK (BIT1 | BIT2)
> +#define B_PCI_BAR_MEMORY_TYPE_64 BIT2
> +
> +#endif
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Ppi/SiPolicy.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Ppi/SiPolicy.h
> new file mode 100644
> index 0000000000..ac270e24fb
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Ppi/SiPolicy.h
> @@ -0,0 +1,29 @@
> +/** @file
> + Silicon Policy PPI is used for specifying platform
> + related Intel silicon information and policy setting.
> + This PPI is consumed by the silicon PEI modules and carried
> + over to silicon DXE modules.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SI_POLICY_PPI_H_
> +#define _SI_POLICY_PPI_H_
> +
> +#include <SiPolicyStruct.h>
> +#include <PchAccess.h>
> +#include <PchPolicyCommon.h>
> +#include <PchPreMemPolicyCommon.h>
> +#include <SaPolicyCommon.h>
> +#include <CpuPolicyCommon.h>
> +
> +extern EFI_GUID gSiPreMemPolicyPpiGuid;
> +extern EFI_GUID gSiPolicyPpiGuid;
> +
> +typedef struct _SI_PREMEM_POLICY_STRUCT SI_PREMEM_POLICY_PPI;
> +typedef struct _SI_POLICY_STRUCT SI_POLICY_PPI;
> +
> +#endif // _SI_POLICY_PPI_H_
> +
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Private/Library/PcieInitLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Private/Library/PcieInitLib.h
> new file mode 100644
> index 0000000000..fe676f8519
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Private/Library/PcieInitLib.h
> @@ -0,0 +1,26 @@
> +/** @file
> + PCIe Initialization Library header file
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCIE_INIT_LIB_H_
> +#define _PCIE_INIT_LIB_H_
> +
> +#include <Uefi/UefiBaseType.h>
> +#include <Library/DebugLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/PostCodeLib.h>
> +#include <Library/HobLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/TimerLib.h>
> +#include <Library/PeiServicesLib.h>
> +#include <IndustryStandard/Pci30.h>
> +#include <Library/PciSegmentLib.h>
> +#include <Library/GpioLib.h>
> +#include <SaRegs.h>
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Private/Library/UsbInitLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Private/Library/UsbInitLib.h
> new file mode 100644
> index 0000000000..f05cf0fdea
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Private/Library/UsbInitLib.h
> @@ -0,0 +1,71 @@
> +/** @file
> + Header file for USB initialization library.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _USB_INIT_LIB_H_
> +#define _USB_INIT_LIB_H_
> +
> +#include <Ppi/SiPolicy.h>
> +
> +/**
> + Common entry point for PCH and CPU xDCI controller
> +
> + @param[in] UsbConfig The USB_CONFIG policy instance
> + @param[in] XdciPciMmBase xDCI PCI config space address
> +**/
> +VOID
> +XdciConfigure (
> + IN USB_CONFIG *UsbConfig,
> + IN UINT64 XhciPciMmBase
> + );
> +
> +/**
> + Common entry point for PCH and CPU xHCI controller
> +
> + @param[in] UsbConfig The USB_CONFIG policy instance
> + @param[in] XhciPciMmBase xHCI PCI config space address
> +**/
> +VOID
> +XhciConfigure (
> + IN USB_CONFIG *UsbConfig,
> + IN UINT64 XhciPciMmBase
> + );
> +
> +/**
> + Configure xHCI after initialization
> +
> + @param[in] UsbConfig The USB_CONFIG policy instance
> + @param[in] XhciPciMmBase XHCI PCI CFG Base Address
> +**/
> +VOID
> +XhciConfigureAfterInit (
> + IN USB_CONFIG *UsbConfig,
> + IN UINT64 XhciPciMmBase
> + );
> +
> +/**
> + Locks xHCI configuration by setting the proper lock bits in controller
> +
> + @param[in] UsbConfig The USB_CONFIG policy instance
> + @param[in] XhciPciBase xHCI PCI config space address
> +**/
> +VOID
> +XhciLockConfiguration (
> + IN USB_CONFIG *UsbConfig,
> + IN UINT64 XhciPciBase
> + );
> +
> +/**
> + Tune the USB 2.0 high-speed signals quality.
> +
> + @param[in] UsbConfig The USB_CONFIG policy instance
> +**/
> +VOID
> +Usb2AfeProgramming (
> + IN USB_CONFIG *UsbConfig
> + );
> +#endif // _USB_INIT_LIB_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Protocol/SiPolicyProtocol.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Protocol/SiPolicyProtocol.h
> new file mode 100644
> index 0000000000..671e94b3bc
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Protocol/SiPolicyProtocol.h
> @@ -0,0 +1,60 @@
> +/** @file
> + Protocol used for specifying platform related Silicon information and policy
> setting.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SI_POLICY_PROTOCOL_H_
> +#define _SI_POLICY_PROTOCOL_H_
> +
> +#include <IndustryStandard/Hsti.h>
> +
> +//
> +// DXE_SI_POLICY_PROTOCOL revisions
> +//
> +#define DXE_SI_POLICY_PROTOCOL_REVISION 2
> +
> +extern EFI_GUID gDxeSiPolicyProtocolGuid;
> +
> +#pragma pack (push,1)
> +
> +/**
> + The protocol allows the platform code to publish a set of configuration
> information that the
> + Silicon drivers will use to configure the processor in the DXE phase.
> + This Policy Protocol needs to be initialized for Silicon configuration.
> + @note The Protocol has to be published before processor DXE drivers are
> dispatched.
> +**/
> +typedef struct {
> + /**
> + This member specifies the revision of the Si Policy protocol. This field is used
> to indicate backward
> + compatible changes to the protocol. Any such changes to this protocol will
> result in an update in the revision number.
> +
> + <b>Revision 1</b>:
> + - Initial version
> + <b>Revision 2</b>:
> + - Added SmbiosOemTypeFirmwareVersionInfo to determines the SMBIOS
> OEM type
> + **/
> + UINT8 Revision;
> + /**
> + SmbiosOemTypeFirmwareVersionInfo determines the SMBIOS OEM type
> (0x80 to 0xFF) defined in SMBIOS,
> + values 0-0x7F will be treated as disable FVI reporting.
> + FVI structure uses it as SMBIOS OEM type to provide version information.
> + **/
> + UINT8 SmbiosOemTypeFirmwareVersionInfo;
> + UINT8 ReservedByte[6]; ///< Reserved bytes, align to
> multiple 8.
> + /**
> + This member describes a pointer to Hsti results from previous boot. In
> order to mitigate the large performance cost
> + of performing all of the platform security tests on each boot, we can save
> the results across boots and retrieve
> + and point this policy to them prior to the launch of HstiSiliconDxe. Logic
> should be implemented to not populate this
> + upon major platform changes (i.e changes to setup option or platform
> hw)to ensure that results accurately reflect the
> + configuration of the platform.
> + **/
> + ADAPTER_INFO_PLATFORM_SECURITY *Hsti; ///< This is a pointer to Hsti
> results from previous boot
> + UINTN HstiSize; ///< Size of results, if setting Hsti policy to
> point to previous results
> +} DXE_SI_POLICY_PROTOCOL;
> +
> +#pragma pack (pop)
> +
> +#endif
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Register/RegsUsb.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Register/RegsUsb.h
> new file mode 100644
> index 0000000000..58a185c8fd
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Register/RegsUsb.h
> @@ -0,0 +1,55 @@
> +/** @file
> + Register names for USB Host and device controller
> +
> + Conventions:
> +
> + - Register definition format:
> +
> Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpa
> ce_RegisterName
> + - Prefix:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register size
> + Definitions beginning with "N_" are the bit position
> + - [GenerationName]:
> + Three letter acronym of the generation is used .
> + Register name without GenerationName applies to all generations.
> + - [ComponentName]:
> + This field indicates the component name that the register belongs to (e.g.
> PCH, SA etc.)
> + Register name without ComponentName applies to all components.
> + Register that is specific to -H denoted by "_PCH_H_" in component name.
> + Register that is specific to -LP denoted by "_PCH_LP_" in component name.
> + - SubsystemName:
> + This field indicates the subsystem name of the component that the
> register belongs to
> + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
> + - RegisterSpace:
> + MEM - MMIO space register of subsystem.
> + IO - IO space register of subsystem.
> + PCR - Private configuration register of subsystem.
> + CFG - PCI configuration space register of subsystem.
> + - RegisterName:
> + Full register name.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _REGS_USB_H_
> +#define _REGS_USB_H_
> +
> +//
> +// USB3 (XHCI) related definitions
> +// @todo: Add CPU PCI defs for xHCI
> +//
> +#define PCI_BUS_NUMBER_PCH_XHCI 0
> +#define PCI_DEVICE_NUMBER_PCH_XHCI 20
> +#define PCI_FUNCTION_NUMBER_PCH_XHCI 0
> +
> +//
> +// xDCI (OTG) USB Device Controller
> +//
> +#define PCI_DEVICE_NUMBER_PCH_XDCI 20
> +#define PCI_FUNCTION_NUMBER_PCH_XDCI 1
> +#endif // _REGS_USB_H_
> +
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/SiConfigHob.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Include/SiConfigHob.h
> new file mode 100644
> index 0000000000..b5aeccbe5d
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/SiConfigHob.h
> @@ -0,0 +1,19 @@
> +/** @file
> + Silicon Config HOB is used for gathering platform
> + related Intel silicon information and config setting.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SI_CONFIG_HOB_H_
> +#define _SI_CONFIG_HOB_H_
> +
> +#include <SiPolicyStruct.h>
> +
> +extern EFI_GUID gSiConfigHobGuid;
> +
> +// Rename SI_CONFIG_HOB into SI_CONFIG_HOB_DATA for it does not follow
> HOB structure.
> +typedef CONST SI_CONFIG SI_CONFIG_HOB_DATA;
> +#endif
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/SiPolicyStruct.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Include/SiPolicyStruct.h
> new file mode 100644
> index 0000000000..da16aad257
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/SiPolicyStruct.h
> @@ -0,0 +1,65 @@
> +/** @file
> + Intel reference code configuration policies.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SI_POLICY_STRUCT_H_
> +#define _SI_POLICY_STRUCT_H_
> +
> +#include <ConfigBlock.h>
> +#include <ConfigBlock/SiConfig.h>
> +
> +/**
> + Silicon Policy revision number
> + Any change to this structure will result in an update in the revision number
> +
> + This member specifies the revision of the Silicon Policy. This field is used to
> indicate change
> + to the policy structure.
> +
> + <b>Revision 1</b>:
> + - Initial version.
> +**/
> +#define SI_POLICY_REVISION 1
> +
> +/**
> + Silicon pre-memory Policy revision number
> + Any change to this structure will result in an update in the revision number
> +
> + <b>Revision 1</b>:
> + - Initial version.
> +**/
> +#define SI_PREMEM_POLICY_REVISION 1
> +
> +
> +/**
> + SI Policy PPI in Pre-Mem\n
> + All SI config block change history will be listed here\n\n
> +
> + - <b>Revision 1</b>:
> + - Initial version.\n
> +**/
> +struct _SI_PREMEM_POLICY_STRUCT {
> + CONFIG_BLOCK_TABLE_HEADER TableHeader;
> +/*
> + Individual Config Block Structures are added here in memory as part of
> AddConfigBlock()
> +*/
> +};
> +
> +/**
> + SI Policy PPI\n
> + All SI config block change history will be listed here\n\n
> +
> + - <b>Revision 1</b>:
> + - Initial version.\n
> +**/
> +struct _SI_POLICY_STRUCT {
> + CONFIG_BLOCK_TABLE_HEADER TableHeader;
> +/*
> + Individual Config Block Structures are added here in memory as part of
> AddConfigBlock()
> +*/
> +};
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Include/TraceHubCommonConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Include/TraceHubCommonConfig.h
> new file mode 100644
> index 0000000000..7e056a25af
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/TraceHubCommonConfig.h
> @@ -0,0 +1,23 @@
> +/** @file
> + Common configurations for CPU and PCH trace hub
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _TRACE_HUB_COMMON_CONFIG_H_
> +#define _TRACE_HUB_COMMON_CONFIG_H_
> +
> +///
> +/// The TRACE_HUB_ENABLE_MODE describes the desired TraceHub mode of
> operation
> +///
> +typedef enum {
> + TraceHubModeDisabled = 0, ///< TraceHub Disabled
> + TraceHubModeTargetDebugger = 1, ///< TraceHub Target Debugger
> mode, debug on target device itself, config to PCI mode
> + TraceHubModeHostDebugger = 2, ///< TraceHub Host Debugger
> mode, debugged by host with cable attached, config to ACPI mode
> + TraceHubModeMax
> +} TRACE_HUB_ENABLE_MODE;
> +
> +
> +#endif
> --
> 2.16.2.windows.1
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