[edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 07/12] PciBusDxe: Record the PCI-Express Capability Structure
Javeed, Ashraf
ashraf.javeed at intel.com
Fri Nov 1 15:09:47 UTC 2019
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2194
The code changes are made to record the PCI device's PCI-Express
Capability Structure register set during early PCI enumeration phase.
This data shall be used during PCI feature enumeration phase.
Signed-off-by: Ashraf Javeed <ashraf.javeed at intel.com>
Cc: Jian J Wang <jian.j.wang at intel.com>
Cc: Hao A Wu <hao.a.wu at intel.com>
Cc: Ray Ni <ray.ni at intel.com>
---
MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 6 +++++-
MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 34 ++++++++++++++++++++++------------
MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 78 insertions(+), 13 deletions(-)
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
index 95a677b..dc29ef3 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
@@ -266,9 +266,13 @@ struct _PCI_IO_DEVICE {
BOOLEAN IsPciExp;
//
- // For SR-IOV
+ // For PCI Express Capability List Structure
//
UINT8 PciExpressCapabilityOffset;
+ PCI_CAPABILITY_PCIEXP PciExpStruct;
+ //
+ // For SR-IOV
+ //
UINT32 AriCapabilityOffset;
UINT32 SrIovCapabilityOffset;
UINT32 MrIovCapabilityOffset;
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
index c7eafff..2343702 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
@@ -230,7 +230,7 @@ PciSearchDevice (
PciIoDevice = NULL;
DEBUG ((
- EFI_D_INFO,
+ DEBUG_INFO,
"PciBus: Discovered %s @ [%02x|%02x|%02x]\n",
IS_PCI_BRIDGE (Pci) ? L"PPB" :
IS_CARDBUS_BRIDGE (Pci) ? L"P2C" :
@@ -397,7 +397,7 @@ DumpPpbPaddingResource (
if ((Type != PciBarTypeUnknown) && ((ResourceType == PciBarTypeUnknown) || (ResourceType == Type))) {
DEBUG ((
- EFI_D_INFO,
+ DEBUG_INFO,
" Padding: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx\n",
mBarTypeStr[Type], Descriptor->AddrRangeMax, Descriptor->AddrLen
));
@@ -424,7 +424,7 @@ DumpPciBars (
}
DEBUG ((
- EFI_D_INFO,
+ DEBUG_INFO,
" BAR[%d]: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx;\tOffset = 0x%02x\n",
Index, mBarTypeStr[MIN (PciIoDevice->PciBar[Index].BarType, PciBarTypeMaxType)],
PciIoDevice->PciBar[Index].Alignment, PciIoDevice->PciBar[Index].Length, PciIoDevice->PciBar[Index].Offset
@@ -437,13 +437,13 @@ DumpPciBars (
}
DEBUG ((
- EFI_D_INFO,
+ DEBUG_INFO,
" VFBAR[%d]: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx;\tOffset = 0x%02x\n",
Index, mBarTypeStr[MIN (PciIoDevice->VfPciBar[Index].BarType, PciBarTypeMaxType)],
PciIoDevice->VfPciBar[Index].Alignment, PciIoDevice->VfPciBar[Index].Length, PciIoDevice->VfPciBar[Index].Offset
));
}
- DEBUG ((EFI_D_INFO, "\n"));
+ DEBUG ((DEBUG_INFO, "\n"));
}
/**
@@ -1903,7 +1903,7 @@ PciParseBar (
// Fix the length to support some special 64 bit BAR
//
if (Value == 0) {
- DEBUG ((EFI_D_INFO, "[PciBus]BAR probing for upper 32bit of MEM64 BAR returns 0, change to 0xFFFFFFFF.\n"));
+ DEBUG ((DEBUG_INFO, "[PciBus]BAR probing for upper 32bit of MEM64 BAR returns 0, change to 0xFFFFFFFF.\n"));
Value = (UINT32) -1;
} else {
Value |= ((UINT32)(-1) << HighBitSet32 (Value));
@@ -2153,7 +2153,17 @@ CreatePciIoDevice (
NULL
);
if (!EFI_ERROR (Status)) {
- PciIoDevice->IsPciExp = TRUE;
+ PciIoDevice->IsPciExp = TRUE;
+ //
+ // read the PCI device's entire PCI Express Capability structure
+ //
+ PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint8,
+ PciIoDevice->PciExpressCapabilityOffset,
+ sizeof (PCI_CAPABILITY_PCIEXP) / sizeof (UINT8),
+ &PciIoDevice->PciExpStruct
+ );
}
if (PcdGetBool (PcdAriSupport)) {
@@ -2206,7 +2216,7 @@ CreatePciIoDevice (
&Data32
);
DEBUG ((
- EFI_D_INFO,
+ DEBUG_INFO,
" ARI: forwarding enabled for PPB[%02x:%02x:%02x]\n",
Bridge->BusNumber,
Bridge->DeviceNumber,
@@ -2215,7 +2225,7 @@ CreatePciIoDevice (
}
}
- DEBUG ((EFI_D_INFO, " ARI: CapOffset = 0x%x\n", PciIoDevice->AriCapabilityOffset));
+ DEBUG ((DEBUG_INFO, " ARI: CapOffset = 0x%x\n", PciIoDevice->AriCapabilityOffset));
}
}
@@ -2325,12 +2335,12 @@ CreatePciIoDevice (
PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - Bus + 1);
DEBUG ((
- EFI_D_INFO,
+ DEBUG_INFO,
" SR-IOV: SupportedPageSize = 0x%x; SystemPageSize = 0x%x; FirstVFOffset = 0x%x;\n",
SupportedPageSize, PciIoDevice->SystemPageSize >> 12, FirstVFOffset
));
DEBUG ((
- EFI_D_INFO,
+ DEBUG_INFO,
" InitialVFs = 0x%x; ReservedBusNum = 0x%x; CapOffset = 0x%x\n",
PciIoDevice->InitialVFs, PciIoDevice->ReservedBusNum, PciIoDevice->SrIovCapabilityOffset
));
@@ -2345,7 +2355,7 @@ CreatePciIoDevice (
NULL
);
if (!EFI_ERROR (Status)) {
- DEBUG ((EFI_D_INFO, " MR-IOV: CapOffset = 0x%x\n", PciIoDevice->MrIovCapabilityOffset));
+ DEBUG ((DEBUG_INFO, " MR-IOV: CapOffset = 0x%x\n", PciIoDevice->MrIovCapabilityOffset));
}
}
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c
index 9e6671d..df9e696 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c
@@ -467,6 +467,14 @@ GetPciFeaturesConfigurationTable (
return EFI_SUCCESS;
}
+ //
+ // The PCI features configuration table is not built for RCiEP, return NULL
+ //
+ if (PciDevice->PciExpStruct.Capability.Bits.DevicePortType == \
+ PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT) {
+ *PciFeaturesConfigTable = NULL;
+ return EFI_SUCCESS;
+ }
if (IsDevicePathEnd (PciDevice->DevicePath)){
//
@@ -575,6 +583,45 @@ IsPciRootPortEmpty (
}
+/**
+ helper routine to dump the PCIe Device Port Type
+**/
+VOID
+DumpDevicePortType (
+ IN UINT8 DevicePortType
+ )
+{
+ switch (DevicePortType){
+ case PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT:
+ DEBUG (( DEBUG_INFO, "PCIe endpoint found\n"));
+ break;
+ case PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT:
+ DEBUG (( DEBUG_INFO, "legacy PCI endpoint found\n"));
+ break;
+ case PCIE_DEVICE_PORT_TYPE_ROOT_PORT:
+ DEBUG (( DEBUG_INFO, "PCIe Root Port found\n"));
+ break;
+ case PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT:
+ DEBUG (( DEBUG_INFO, "PCI switch upstream port found\n"));
+ break;
+ case PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT:
+ DEBUG (( DEBUG_INFO, "PCI switch downstream port found\n"));
+ break;
+ case PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE:
+ DEBUG (( DEBUG_INFO, "PCIe-PCI bridge found\n"));
+ break;
+ case PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE:
+ DEBUG (( DEBUG_INFO, "PCI-PCIe bridge found\n"));
+ break;
+ case PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT:
+ DEBUG (( DEBUG_INFO, "RCiEP found\n"));
+ break;
+ case PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR:
+ DEBUG (( DEBUG_INFO, "RC Event Collector found\n"));
+ break;
+ }
+}
+
/**
Process each PCI device as per the pltaform and device-specific policy.
@@ -590,8 +637,12 @@ SetupDevicePciFeatures (
)
{
EFI_STATUS Status;
+ PCI_REG_PCIE_CAPABILITY PcieCap;
OTHER_PCI_FEATURES_CONFIGURATION_TABLE *OtherPciFeaturesConfigTable;
+ PcieCap.Uint16 = PciDevice->PciExpStruct.Capability.Uint16;
+ DumpDevicePortType ((UINT8)PcieCap.Bits.DevicePortType);
+
OtherPciFeaturesConfigTable = NULL;
Status = GetPciFeaturesConfigurationTable (PciDevice, &OtherPciFeaturesConfigTable);
if (EFI_ERROR( Status)) {
--
2.21.0.windows.1
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