[edk2-devel] [edk2-platforms][PATCH V1 05/19] PurleyOpenBoardPkg/BoardMtOlympus: Remove all files
Kubacki, Michael A
michael.a.kubacki at intel.com
Fri Nov 1 21:03:28 UTC 2019
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2322
The current set of maintainers do not plan to maintain this package
moving forward. Simply leaving the code as unmaintained is
undesirable for several reasons including presence of build issues,
functional issues, and lack of consistency with other Intel
platform/silicon code in design and usage.
It is suggested that these be removed for the next stable tag due
to lack of recent testing.
This change removes all files for BoardMtOlympus.
Cc: Nate DeSimone <nathaniel.l.desimone at intel.com>
Cc: Michael D Kinney <michael.d.kinney at intel.com>
Cc: Shifei A Lu <shifei.a.lu at intel.com>
Cc: Isaac W Oram <isaac.w.oram at intel.com>
Cc: Xiaohu Zhou <bowen.zhou at intel.com>
Signed-off-by: Michael Kubacki <michael.a.kubacki at intel.com>
---
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BasePlatformHookLib/BasePlatformHookLib.inf | 38 --
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf | 41 --
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf | 41 --
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPostMemLib.inf | 38 --
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPreMemLib.inf | 71 ---
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitLib.h | 17 -
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BasePlatformHookLib/BasePlatformHookLib.c | 294 ----------
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c | 35 --
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/DxeMtOlympusAcpiTableLib.c | 52 --
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c | 61 --
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmMtOlympusAcpiEnableLib.c | 36 --
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c | 119 ----
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/AllLanesEparam.c | 43 --
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/GpioTable.c | 296 ----------
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/IioBifur.c | 88 ---
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPostMemLib.c | 45 --
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPreMemLib.c | 111 ----
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusDetect.c | 27 -
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitPostMemLib.c | 85 ---
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitPreMemLib.c | 593 --------------------
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/UsbOC.c | 45 --
21 files changed, 2176 deletions(-)
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BasePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BasePlatformHookLib/BasePlatformHookLib.inf
deleted file mode 100644
index d86a8f6cd0..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BasePlatformHookLib/BasePlatformHookLib.inf
+++ /dev/null
@@ -1,38 +0,0 @@
-### @file
-#
-# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-###
-
-[Defines]
- INF_VERSION = 0x00010017
- BASE_NAME = BasePlatformHookLib
- FILE_GUID = E22ADCC6-ED90-4A90-9837-C8E7FF9E963D
- VERSION_STRING = 1.0
- MODULE_TYPE = BASE
- LIBRARY_CLASS = PlatformHookLib
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
-#
-
-[LibraryClasses]
- BaseLib
- IoLib
- PciLib
-
-[Packages]
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- PurleyOpenBoardPkg/PlatPkg.dec
- PurleySktPkg/SocketPkg.dec
- LewisburgPkg/PchRcPkg.dec
- PurleyRcPkg/RcPkg.dec
-
-[FixedPcd]
-
-[Sources]
- BasePlatformHookLib.c
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf
deleted file mode 100644
index d4f63fa7e1..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf
+++ /dev/null
@@ -1,41 +0,0 @@
-### @file
-#
-# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-###
-
-[Defines]
- INF_VERSION = 0x00010017
- BASE_NAME = DxeBoardAcpiTableLib
- FILE_GUID = 6562E0AE-90D8-4D41-8C97-81286B4BE7D2
- VERSION_STRING = 1.0
- MODULE_TYPE = BASE
- LIBRARY_CLASS = BoardAcpiTableLib
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
-#
-
-[LibraryClasses]
- BaseLib
- IoLib
- PciLib
-
-[Packages]
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- MinPlatformPkg/MinPlatformPkg.dec
- PurleyOpenBoardPkg/PlatPkg.dec
- LewisburgPkg/PchRcPkg.dec
-
-[Pcd]
- gOemSkuTokenSpaceGuid.PcdAcpiGnvsAddress
-
-[Sources]
- DxeMtOlympusAcpiTableLib.c
- DxeBoardAcpiTableLib.c
-
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
deleted file mode 100644
index 6b463a544b..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
+++ /dev/null
@@ -1,41 +0,0 @@
-### @file
-#
-# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-###
-
-[Defines]
- INF_VERSION = 0x00010017
- BASE_NAME = SmmBoardAcpiEnableLib
- FILE_GUID = 549E69AE-D3B3-485B-9C17-AF16E20A58AD
- VERSION_STRING = 1.0
- MODULE_TYPE = BASE
- LIBRARY_CLASS = BoardAcpiEnableLib
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
-#
-
-[LibraryClasses]
- BaseLib
- IoLib
- PciLib
- MmPciLib
- PchCycleDecodingLib
-
-[Packages]
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- MinPlatformPkg/MinPlatformPkg.dec
- PurleyOpenBoardPkg/PlatPkg.dec
- LewisburgPkg/PchRcPkg.dec
-
-[Sources]
- SmmMtOlympusAcpiEnableLib.c
- SmmSiliconAcpiEnableLib.c
- SmmBoardAcpiEnableLib.c
-
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPostMemLib.inf b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
deleted file mode 100644
index 1948a97925..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
+++ /dev/null
@@ -1,38 +0,0 @@
-### @file
-#
-# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-###
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = PeiBoardPostMemInitLib
- FILE_GUID = 30F407D6-6B92-412A-B2DA-8E73E2B386E6
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = BoardInitLib
-
-[LibraryClasses]
- BaseLib
- DebugLib
- BaseMemoryLib
- MemoryAllocationLib
- PcdLib
-
-[Packages]
- MinPlatformPkg/MinPlatformPkg.dec
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- PurleyRcPkg/RcPkg.dec
- PurleySktPkg/SocketPkg.dec
-
-[Sources]
- PeiMtOlympusInitPostMemLib.c
- PeiBoardInitPostMemLib.c
-
-[FixedPcd]
-
-[Pcd]
-
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
deleted file mode 100644
index f3f671c20a..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
+++ /dev/null
@@ -1,71 +0,0 @@
-### @file
-#
-# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-###
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = PeiBoardInitPreMemLib
- FILE_GUID = 73AA24AE-FB20-43F9-A3BA-448953A03A78
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = BoardInitLib
-
-[LibraryClasses]
- BaseLib
- DebugLib
- BaseMemoryLib
- MemoryAllocationLib
- PcdLib
- GpioLib
-
-[Packages]
- MinPlatformPkg/MinPlatformPkg.dec
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- PurleyRcPkg/RcPkg.dec
- PurleySktPkg/SocketPkg.dec
- LewisburgPkg/PchRcPkg.dec
- PurleyOpenBoardPkg/PlatPkg.dec
-
-[Sources]
- PeiMtOlympusDetect.c
- PeiMtOlympusInitPreMemLib.c
- PeiBoardInitPreMemLib.c
- GpioTable.c
- UsbOC.c
- IioBifur.c
- AllLanesEparam.c
-
-[Pcd]
- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
- gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount
- gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable
- gOemSkuTokenSpaceGuid.PcdMemTsegSize
- gOemSkuTokenSpaceGuid.PcdMemIedSize
-
- gOemSkuTokenSpaceGuid.PcdSetupData
- gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData
- gOemSkuTokenSpaceGuid.PcdSocketIioConfigData
- gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData
- gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData
- gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData
- gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData
- gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData
-
- gOemSkuTokenSpaceGuid.PcdUsb20OverCurrentMappings
- gOemSkuTokenSpaceGuid.PcdUsb30OverCurrentMappings
- gOemSkuTokenSpaceGuid.PcdIioBifurcationTable
- gOemSkuTokenSpaceGuid.PcdIioBifurcationTableEntries
- gOemSkuTokenSpaceGuid.PcdIioSlotTable
- gOemSkuTokenSpaceGuid.PcdIioSlotTableEntries
- gOemSkuTokenSpaceGuid.PcdAllLanesEparamTable
- gOemSkuTokenSpaceGuid.PcdAllLanesEparamTableSize
-
-[FixedPcd]
- gEfiPchTokenSpaceGuid.PcdPchAcpiIoPortBaseAddress
- gEfiPchTokenSpaceGuid.PcdTcoBaseAddress
-
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitLib.h b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitLib.h
deleted file mode 100644
index bada6aef36..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitLib.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef _PEI_MT_OLYMPUS_BOARD_INIT_LIB_H_
-#define _PEI_MT_OLYMPUS_BOARD_INIT_LIB_H_
-
-#include <Uefi.h>
-#include <Library/BaseLib.h>
-#include <Library/PcdLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/DebugLib.h>
-
-#endif
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BasePlatformHookLib/BasePlatformHookLib.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BasePlatformHookLib/BasePlatformHookLib.c
deleted file mode 100644
index 8051e33311..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BasePlatformHookLib/BasePlatformHookLib.c
+++ /dev/null
@@ -1,294 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <Base.h>
-#include <Library/IoLib.h>
-#include <Library/PcdLib.h>
-#include <Library/SerialPortLib.h>
-#include <Library/DebugLib.h>
-
-#define R_ICH_IOPORT_PCI_INDEX 0xCF8
-#define R_ICH_IOPORT_PCI_DATA 0xCFC
-#define R_ICH_LPC_IO_DEC 0x80
-
-#define PCI_DEVICE_NUMBER_ICH_LPC 31
-#define PCI_FUNCTION_NUMBER_ICH_LPC 0
-
-#define PCI_CF8_ADDR(Bus, Dev, Func, Off) \
- (((Off) & 0xFF) | (((Func) & 0x07) << 8) | (((Dev) & 0x1F) << 11) | (((Bus) & 0xFF) << 16) | (1 << 31))
-#define ICH_LPC_CF8_ADDR(Offset) PCI_CF8_ADDR(0, PCI_DEVICE_NUMBER_ICH_LPC, PCI_FUNCTION_NUMBER_ICH_LPC, Offset)
-
-#include "SioRegs.h"
-
-#include <Platform.h>
-#include <PchAccess.h>
-
-//
-// ---------------------------------------------
-// UART Register Offsets
-// ---------------------------------------------
-//
-#define BAUD_LOW_OFFSET 0x00
-#define BAUD_HIGH_OFFSET 0x01
-#define IER_OFFSET 0x01
-#define LCR_SHADOW_OFFSET 0x01
-#define FCR_SHADOW_OFFSET 0x02
-#define IR_CONTROL_OFFSET 0x02
-#define FCR_OFFSET 0x02
-#define EIR_OFFSET 0x02
-#define BSR_OFFSET 0x03
-#define LCR_OFFSET 0x03
-#define MCR_OFFSET 0x04
-#define LSR_OFFSET 0x05
-#define MSR_OFFSET 0x06
-
-//
-// ---------------------------------------------
-// UART Register Bit Defines
-// ---------------------------------------------
-//
-#define LSR_TXRDY 0x20
-#define LSR_RXDA 0x01
-#define DLAB 0x01
-
-#define UART_DATA 8
-#define UART_STOP 1
-#define UART_PARITY 0
-#define UART_BREAK_SET 0
-
-UINT16 gComBase = 0x3f8;
-UINTN gBps = 115200;
-UINT8 gData = 8;
-UINT8 gStop = 1;
-UINT8 gParity = 0;
-UINT8 gBreakSet = 0;
-
-
-/**
-
- Read AHB register.
-
- @param RegIndex: register index.
-
- @retval value of register.
-
-**/
-UINT32
-ReadAHBDword(
- UINT32 RegIndex
-){
- UINT8 bValue;
- UINT32 rdValue = 0;
-
- IoWrite8 (SIO_INDEX_PORT, REG_LOGICAL_DEVICE);
- IoWrite8 (0xED, 0);//short delay.
- IoWrite8 (SIO_DATA_PORT, SIO_SMI);
- IoWrite8 (0xED, 0);//short delay.
-
- IoWrite8 (SIO_INDEX_PORT, 0x30);
- IoWrite8 (0xED, 0);//short delay.
- IoWrite8 (SIO_DATA_PORT, 1);
- IoWrite8 (0xED, 0);//short delay.
-
- IoWrite8 (SIO_INDEX_PORT, 0xf8);
- bValue = IoRead8(SIO_DATA_PORT);
- bValue &= 0xfc;
- bValue |= 2; // 4 byte window.
- IoWrite8 (SIO_DATA_PORT, bValue);
- IoWrite8 (0xED, 0);//short delay.
-
- IoWrite8 (SIO_INDEX_PORT, 0xf0);
- IoWrite8 (0xED, 0);//short delay.
- IoWrite8 (SIO_DATA_PORT, (UINT8)((RegIndex >> 24)& 0xff));
-
- IoWrite8 (SIO_INDEX_PORT, 0xf1);
- IoWrite8 (0xED, 0);//short delay.
- IoWrite8 (SIO_DATA_PORT, (UINT8)((RegIndex >> 16)& 0xff));
-
- IoWrite8 (SIO_INDEX_PORT, 0xf2);
- IoWrite8 (0xED, 0);//short delay.
- IoWrite8 (SIO_DATA_PORT, (UINT8)((RegIndex >> 8) & 0xff));
-
- IoWrite8 (SIO_INDEX_PORT, 0xf3);
- IoWrite8 (0xED, 0);//short delay.
- IoWrite8 (SIO_DATA_PORT, (UINT8)((RegIndex )& 0xff));
-
- // trigger read
- IoWrite8 (SIO_INDEX_PORT, 0xfe);
- IoRead8 (SIO_DATA_PORT);
-
-
- IoWrite8 (SIO_INDEX_PORT, 0xf4);
- rdValue += IoRead8 (SIO_DATA_PORT);
- rdValue <<= 8;
-
- IoWrite8 (SIO_INDEX_PORT, 0xf5);
- rdValue += IoRead8 (SIO_DATA_PORT);
- rdValue <<= 8;
-
- IoWrite8 (SIO_INDEX_PORT, 0xf6);
- rdValue += IoRead8 (SIO_DATA_PORT);
- rdValue <<= 8;
-
- IoWrite8 (SIO_INDEX_PORT, 0xf7);
- rdValue += IoRead8 (SIO_DATA_PORT);
-
-
- return rdValue;
-
-}
-
-
-/**
-
- GC_TODO: add routine description
-
- @param Exist - GC_TODO: add arg description
-
- @retval RETURN_SUCCESS - GC_TODO: add retval description
-
-**/
-UINT32
-IsSioExist (
- VOID
-)
-{
- UINT32 SioExit;
- UINT32 DeviceID;
-
- SioExit = 0;
-
- IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK);
- IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK);
-
- IoWrite8 (SIO_INDEX_PORT, REG_LOGICAL_DEVICE);
- IoWrite8 (SIO_DATA_PORT, SIO_UART1);
-
- if(IoRead8(SIO_DATA_PORT) == SIO_UART1){
- DeviceID=0;
- SioExit |= EXIST;
- }
-
- IoWrite8 (SIO_INDEX_PORT, SIO_LOCK);
-
- return SioExit;
-}
-
-/**
-
- GC_TODO: add routine description
-
- @param None
-
- @retval None
-
-**/
-VOID
-InitializeSio (
- VOID
- )
-{
-
- UINT32 SioExist;
- UINT32 SioEnable;
- UINT32 Decode;
- UINT32 Enable;
-
- //
- // Enable LPC decode
- // Set COMA/COMB base
- //
-
- Decode = ((V_PCH_LPC_IOD_COMA_3F8 << N_PCH_LPC_IOD_COMA) | (V_PCH_LPC_IOD_COMB_2F8 << N_PCH_LPC_IOD_COMB));
- Enable = ( B_PCH_LPC_IOE_ME2 | B_PCH_LPC_IOE_SE | B_PCH_LPC_IOE_ME1 \
- | B_PCH_LPC_IOE_KE | B_PCH_LPC_IOE_CBE | B_PCH_LPC_IOE_CAE);
- IoWrite32 (R_ICH_IOPORT_PCI_INDEX, (UINT32) (ICH_LPC_CF8_ADDR (R_ICH_LPC_IO_DEC)));
-
- IoWrite32 (R_ICH_IOPORT_PCI_DATA, Decode | (Enable << 16));
-
- MmioWrite16 (PCH_PCR_ADDRESS(PID_DMI, R_PCH_PCR_DMI_LPCIOD), (UINT16)Decode);
- MmioWrite16 (PCH_PCR_ADDRESS(PID_DMI, R_PCH_PCR_DMI_LPCIOE), (UINT16)Enable);
- SioExist = IsSioExist ();
- SioEnable = SioExist;
-
- if (SioEnable == EXIST) {
- IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK);
- IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK);
-
- //
- //COM1
- //
- IoWrite8 (SIO_INDEX_PORT, REG_LOGICAL_DEVICE);
- IoWrite8 (SIO_DATA_PORT, SIO_UART1);
-
- //
- //active COM1
- //
- IoWrite8 (SIO_INDEX_PORT, ACTIVATE);
- IoWrite8 (SIO_DATA_PORT, 1);
-
- IoWrite8 (SIO_INDEX_PORT, SIO_LOCK);
-
- }
-}
-
-/**
- Performs platform specific initialization required for the CPU to access
- the hardware associated with a SerialPortLib instance. This function does
- not initialize the serial port hardware itself. Instead, it initializes
- hardware devices that are required for the CPU to access the serial port
- hardware. This function may be called more than once.
-
- @retval RETURN_SUCCESS The platform specific initialization succeeded.
- @retval RETURN_DEVICE_ERROR The platform specific initialization could not be completed.
-
-**/
-RETURN_STATUS
-EFIAPI
-PlatformHookSerialPortInitialize (
- VOID
- )
-{
- UINTN Divisor;
- UINT8 OutputData;
- UINT8 Data;
-
- InitializeSio();
- //
- // Some init is done by the platform status code initialization.
- //
- //
- // Map 5..8 to 0..3
- //
- Data = (UINT8) (gData - (UINT8) 5);
-
- //
- // Calculate divisor for baud generator
- //
- Divisor = 115200 / gBps;
-
- //
- // Set communications format
- //
- OutputData = (UINT8) ((DLAB << 7) | ((gBreakSet << 6) | ((gParity << 3) | ((gStop << 2) | Data))));
- IoWrite8 (gComBase + LCR_OFFSET, OutputData);
-
- //
- // Configure baud rate
- //
- IoWrite8 (gComBase + BAUD_HIGH_OFFSET, (UINT8) (Divisor >> 8));
- IoWrite8 (gComBase + BAUD_LOW_OFFSET, (UINT8) (Divisor & 0xff));
-
- //
- // Switch back to bank 0
- //
- OutputData = (UINT8) ((~DLAB << 7) | ((gBreakSet << 6) | ((gParity << 3) | ((gStop << 2) | Data))));
- IoWrite8 (gComBase + LCR_OFFSET, OutputData);
-
- return RETURN_SUCCESS;
-}
-
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c
deleted file mode 100644
index ff497540de..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <Base.h>
-#include <Uefi.h>
-#include <PiDxe.h>
-#include <Library/BaseLib.h>
-#include <Library/IoLib.h>
-#include <Library/BoardAcpiTableLib.h>
-#include <Library/PcdLib.h>
-#include <Library/DebugLib.h>
-
-EFI_STATUS
-EFIAPI
-MtOlympusBoardUpdateAcpiTable (
- IN OUT EFI_ACPI_COMMON_HEADER *Table,
- IN OUT EFI_ACPI_TABLE_VERSION *Version
- );
-
-EFI_STATUS
-EFIAPI
-BoardUpdateAcpiTable (
- IN OUT EFI_ACPI_COMMON_HEADER *Table,
- IN OUT EFI_ACPI_TABLE_VERSION *Version
- )
-{
- MtOlympusBoardUpdateAcpiTable (Table, Version);
-
- return EFI_SUCCESS;
-}
-
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/DxeMtOlympusAcpiTableLib.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/DxeMtOlympusAcpiTableLib.c
deleted file mode 100644
index 297de88047..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/DxeMtOlympusAcpiTableLib.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <Base.h>
-#include <Uefi.h>
-#include <PiDxe.h>
-#include <Library/BaseLib.h>
-#include <Library/IoLib.h>
-#include <Library/BoardAcpiTableLib.h>
-#include <Library/PcdLib.h>
-#include <Library/DebugLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Acpi/GlobalNvsAreaDef.h>
-
-GLOBAL_REMOVE_IF_UNREFERENCED BIOS_ACPI_PARAM *mGlobalNvsArea;
-
-VOID
-MtOlympusUpdateGlobalNvs (
- VOID
- )
-{
-
- //
- // Allocate and initialize the NVS area for SMM and ASL communication.
- //
- mGlobalNvsArea = (VOID *)(UINTN)PcdGet64 (PcdAcpiGnvsAddress);
-
- //
- // Update global NVS area for ASL and SMM init code to use
- //
-
-
-}
-
-EFI_STATUS
-EFIAPI
-MtOlympusBoardUpdateAcpiTable (
- IN OUT EFI_ACPI_COMMON_HEADER *Table,
- IN OUT EFI_ACPI_TABLE_VERSION *Version
- )
-{
- if (Table->Signature == EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) {
- MtOlympusUpdateGlobalNvs ();
- }
-
- return EFI_SUCCESS;
-}
-
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c
deleted file mode 100644
index b2a82560b8..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <Base.h>
-#include <Uefi.h>
-#include <PiDxe.h>
-#include <Library/BaseLib.h>
-#include <Library/IoLib.h>
-#include <Library/BoardAcpiEnableLib.h>
-#include <Library/PcdLib.h>
-#include <Library/DebugLib.h>
-
-EFI_STATUS
-EFIAPI
-MtOlympusBoardEnableAcpi (
- IN BOOLEAN EnableSci
- );
-
-EFI_STATUS
-EFIAPI
-MtOlympusBoardDisableAcpi (
- IN BOOLEAN DisableSci
- );
-
-EFI_STATUS
-EFIAPI
-SiliconEnableAcpi (
- IN BOOLEAN EnableSci
- );
-
-EFI_STATUS
-EFIAPI
-SiliconDisableAcpi (
- IN BOOLEAN DisableSci
- );
-
-EFI_STATUS
-EFIAPI
-BoardEnableAcpi (
- IN BOOLEAN EnableSci
- )
-{
- SiliconEnableAcpi (EnableSci);
- return MtOlympusBoardEnableAcpi (EnableSci);
-}
-
-EFI_STATUS
-EFIAPI
-BoardDisableAcpi (
- IN BOOLEAN DisableSci
- )
-{
- SiliconDisableAcpi (DisableSci);
- return MtOlympusBoardDisableAcpi (DisableSci);
-}
-
-
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmMtOlympusAcpiEnableLib.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmMtOlympusAcpiEnableLib.c
deleted file mode 100644
index b97b2992cb..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmMtOlympusAcpiEnableLib.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <Base.h>
-#include <Uefi.h>
-#include <PiDxe.h>
-#include <Library/BaseLib.h>
-#include <Library/IoLib.h>
-#include <Library/BoardAcpiTableLib.h>
-#include <Library/PcdLib.h>
-#include <Library/DebugLib.h>
-
-EFI_STATUS
-EFIAPI
-MtOlympusBoardEnableAcpi (
- IN BOOLEAN EnableSci
- )
-{
- // enable additional board register
- return EFI_SUCCESS;
-}
-
-EFI_STATUS
-EFIAPI
-MtOlympusBoardDisableAcpi (
- IN BOOLEAN DisableSci
- )
-{
- // enable additional board register
- return EFI_SUCCESS;
-}
-
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
deleted file mode 100644
index ff803aa5ce..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <Base.h>
-#include <Uefi.h>
-#include <PiDxe.h>
-#include <Library/BaseLib.h>
-#include <Library/IoLib.h>
-#include <Library/BoardAcpiEnableLib.h>
-#include <Library/PcdLib.h>
-#include <Library/DebugLib.h>
-#include <PchAccess.h>
-#include <Library/PchCycleDecodingLib.h>
-
-/**
- Clear Port 80h
-
- SMI handler to enable ACPI mode
-
- Dispatched on reads from APM port with value EFI_ACPI_ENABLE_SW_SMI
-
- Disables the SW SMI Timer.
- ACPI events are disabled and ACPI event status is cleared.
- SCI mode is then enabled.
-
- Clear SLP SMI status
- Enable SLP SMI
-
- Disable SW SMI Timer
-
- Clear all ACPI event status and disable all ACPI events
-
- Disable PM sources except power button
- Clear status bits
-
- Disable GPE0 sources
- Clear status bits
-
- Disable GPE1 sources
- Clear status bits
-
- Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
-
- Enable SCI
-**/
-EFI_STATUS
-EFIAPI
-SiliconEnableAcpi (
- IN BOOLEAN EnableSci
- )
-{
- UINT32 SmiEn;
- UINT16 Pm1En;
- UINT16 Pm1Cnt;
- UINT16 PchPmBase;
-
- //
- // Init Power Management I/O Base aka ACPI Base
- //
- PchAcpiBaseGet (&PchPmBase);
-
- SmiEn = IoRead32 (PchPmBase + R_PCH_SMI_EN);
-
- //
- // Disable SW SMI Timer and legacy USB
- //
- SmiEn &= ~(B_PCH_SMI_EN_SWSMI_TMR | B_PCH_SMI_EN_LEGACY_USB | B_PCH_SMI_EN_LEGACY_USB2);
-
- //
- // And enable SMI on write to B_PCH_ACPI_PM1_CNT_SLP_EN when SLP_TYP is written
- //
- SmiEn |= B_PCH_SMI_EN_ON_SLP_EN;
- IoWrite32 (PchPmBase + R_PCH_SMI_EN, SmiEn);
-
- //
- // Disable PM sources except power button
- //
- Pm1En = B_PCH_ACPI_PM1_EN_PWRBTN;
- IoWrite16 (PchPmBase + R_PCH_ACPI_PM1_EN, Pm1En);
-
- //
- // Enable SCI
- //
- Pm1Cnt = IoRead16 (PchPmBase + R_PCH_ACPI_PM1_CNT);
- Pm1Cnt |= B_PCH_ACPI_PM1_CNT_SCI_EN;
- IoWrite16 (PchPmBase + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
-
- return EFI_SUCCESS;
-}
-
-EFI_STATUS
-EFIAPI
-SiliconDisableAcpi (
- IN BOOLEAN DisableSci
- )
-{
- UINT16 Pm1Cnt;
- UINT16 PchPmBase;
-
- //
- // Init Power Management I/O Base aka ACPI Base
- //
- PchAcpiBaseGet (&PchPmBase);
-
- Pm1Cnt = IoRead16 (PchPmBase + R_PCH_ACPI_PM1_CNT);
-
- //
- // Disable SCI
- //
- Pm1Cnt &= ~B_PCH_ACPI_PM1_CNT_SCI_EN;
-
- IoWrite16 (PchPmBase + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
-
- return EFI_SUCCESS;
-}
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/AllLanesEparam.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/AllLanesEparam.c
deleted file mode 100644
index a245721277..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/AllLanesEparam.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef MINIBIOS_BUILD
-#include <PiPei.h>
-#include <Platform.h>
-#include <Library/HobLib.h>
-#include <Library/DebugLib.h>
-#endif
-
-#include <SysHost.h>
-
-#define SPEED_REC_96GT 0
-#define SPEED_REC_104GT 1
-#define ADAPTIVE_CTLE 0x3f
-
-#pragma pack(1)
-
-ALL_LANES_EPARAM_LINK_INFO KtiMtOlympusAllLanesEparamTable[] = {
- //
- // SocketID, Freq, Link, TXEQL, CTLEPEAK
- //
-
- //
- // Socket 0
- //
- {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK0), 0x2E39343F, ADAPTIVE_CTLE},
- {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK1), 0x2F39353F, ADAPTIVE_CTLE},
-
- //
- // Socket 1
- //
- {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK0), 0x2D37353F, ADAPTIVE_CTLE},
- {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK1), 0x2F3A343F, ADAPTIVE_CTLE}
-};
-
-#pragma pack()
-
-UINT32 KtiMtOlympusAllLanesEparamTableSize = sizeof(KtiMtOlympusAllLanesEparamTable);
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/GpioTable.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/GpioTable.c
deleted file mode 100644
index 21d83a0c02..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/GpioTable.c
+++ /dev/null
@@ -1,296 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <PiPei.h>
-#include <Library/DebugLib.h>
-
-#include <Library/GpioLib.h>
-#include <GpioPinsSklH.h>
-#include <Library/PcdLib.h>
-
-#include <Register/PchRegsPcr.h>
-#include <Library/PchPcrLib.h>
-#include <Register/PchRegsSpi.h>
-
-GPIO_INIT_CONFIG mGpioTableMicrosoftWcs[] =
-{
-// Group A
- {GPIO_SKL_H_GPP_A0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone }},//GPP_A_0_LPC_RCIN_N_ESPI_ALERT1_N
- { GPIO_SKL_H_GPP_A1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_1_LAD_0_ESPI_IO_0
- { GPIO_SKL_H_GPP_A2, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_2_LAD_1_ESPI_IO_1
- { GPIO_SKL_H_GPP_A3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_3_LAD_2_ESPI_IO_2
- { GPIO_SKL_H_GPP_A4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_4_LAD_3_ESPI_IO_3
- { GPIO_SKL_H_GPP_A5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_5_LPC_LFRAME_N_ESPI_CS0_N
- { GPIO_SKL_H_GPP_A6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_6_IRQ_LPC_SERIRQ_ESPI_CS1_N
- { GPIO_SKL_H_GPP_A7, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_7_IRQ_LPC_PIRQA_N_ESPI_ALERT0_N
- { GPIO_SKL_H_GPP_A8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_8_FM_LPC_CLKRUN_N
- { GPIO_SKL_H_GPP_A9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_9_CLK_24M_66M_LPC0_ESPI
- { GPIO_SKL_H_GPP_A10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_10_TP_PCH_GPP_A_10
- { GPIO_SKL_H_GPP_A11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_11_FM_LPC_PME_N
- { GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_A_12_IRQ_PCH_SCI_WHEA_N
- { GPIO_SKL_H_GPP_A13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_A_13_FM_EUP_LOT6_N MSFT_WCS_override: Reset Type
- { GPIO_SKL_H_GPP_A14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_14_ESPI_RESET_N
- { GPIO_SKL_H_GPP_A15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_15_SUSACK_N
- { GPIO_SKL_H_GPP_A16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_16_TP_PCH_GPP_A_16
- { GPIO_SKL_H_GPP_A17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_17_FM_KTI_SLOW_MODE_N
- { GPIO_SKL_H_GPP_A18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_A_18_FM_BIOS_ADV_FUNCTIONS
- //{GPIO_SKL_H_GPP_A19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetNormal,GpioTermNone}},//GPP_A_19_FM_ME_RCVR_N
- { GPIO_SKL_H_GPP_A20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_A_20_TP_PCH_GPP_A_20 MSFT_WCS_override: Reset Type
- { GPIO_SKL_H_GPP_A21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_21_TP_PCH_GPP_A_21
- { GPIO_SKL_H_GPP_A22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_22_TP_PCH_GPP_A_22
- { GPIO_SKL_H_GPP_A23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_23_TP_PCH_GPP_A_23
- // Group B
- { GPIO_SKL_H_GPP_B0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_0_CORE_VID_0
- { GPIO_SKL_H_GPP_B1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_1_CORE_VID_1
- { GPIO_SKL_H_GPP_B2, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_2_VRALERT_N
- { GPIO_SKL_H_GPP_B3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_3_FM_QAT_ENABLE_N
- { GPIO_SKL_H_GPP_B4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_4_TP_PCH_GPP_B_4
- { GPIO_SKL_H_GPP_B5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_5_PU_PCH_GPP_B_5
- { GPIO_SKL_H_GPP_B6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_B_6_PU_PCH_GPP_B_6
- { GPIO_SKL_H_GPP_B7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_B_7_PU_PCH_GPP_B_7
- { GPIO_SKL_H_GPP_B8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_8_PU_PCH_GPP_B_8
- { GPIO_SKL_H_GPP_B9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_9_PU_PCH_GPP_B_9
- { GPIO_SKL_H_GPP_B10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_10_PU_PCH_GPP_B_10
- { GPIO_SKL_H_GPP_B11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_11_FM_PMBUS_ALERT_B_EN
- { GPIO_SKL_H_GPP_B12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_12_TP_SLP_S0_N
- { GPIO_SKL_H_GPP_B13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_13_RST_PLTRST_N
- { GPIO_SKL_H_GPP_B14, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_B_14_FM_PCH_BIOS_RCVR_SPKR
- { GPIO_SKL_H_GPP_B15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_15_FM_CPU_ERR0_LVT3_N
- { GPIO_SKL_H_GPP_B16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_16_FM_CPU_ERR1_LVT3_N
- { GPIO_SKL_H_GPP_B17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_17_TP_PCH_GPP_B_17
- { GPIO_SKL_H_GPP_B18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_B_18_PU_NO_REBOOT MSFT_WCS_override: Reset Type
- { GPIO_SKL_H_GPP_B19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_19_TP_PCH_GPP_B_19
- { GPIO_SKL_H_GPP_B20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_B_20_FM_BIOS_POST_CMPLT_N
- { GPIO_SKL_H_GPP_B21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_21_TP_LINK_WIDTH_ID5
- { GPIO_SKL_H_GPP_B22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_22_FM_PCH_BOOT_BIOS_DEVICE
- { GPIO_SKL_H_GPP_B23, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_B_23_FM_PCH_BMC_THERMTRIP_EXI_STRAP_N
- // Group C
- { GPIO_SKL_H_GPP_C0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_C_0_SMB_HOST_STBY_LVC3_SCL
- { GPIO_SKL_H_GPP_C1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_C_1_SMB_HOST_STBY_LVC3_SDA
- { GPIO_SKL_H_GPP_C2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_C_2_PU_PCH_TLS_ENABLE_STRAP
- { GPIO_SKL_H_GPP_C3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_C_3_SMB_SMLINK0_STBY_LVC3_SCL
- { GPIO_SKL_H_GPP_C4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_C_4_SMB_SMLINK0_STBY_LVC3_SDA
- { GPIO_SKL_H_GPP_C5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_C_5_IRQ_SML0_ALERT_N MSFT_WCS_override: Reset Type
- { GPIO_SKL_H_GPP_C6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_C_6_SMB_PMBUS_SML1_STBY_LVC3_SCL
- { GPIO_SKL_H_GPP_C7, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_C_7_SMB_PMBUS_SML1_STBY_LVC3_SDA
- { GPIO_SKL_H_GPP_C8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_8_FM_PASSWORD_CLEAR_N
- { GPIO_SKL_H_GPP_C9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_9_FM_MFG_MODE
- { GPIO_SKL_H_GPP_C10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_10_FM_PCH_SATA_RAID_KEY
- { GPIO_SKL_H_GPP_C11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_11_TP_FP_AUD_DETECT_N
- { GPIO_SKL_H_GPP_C12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_C_12_FM_BOARD_REV_ID0
- { GPIO_SKL_H_GPP_C13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_C_13_FM_BOARD_REV_ID1
- { GPIO_SKL_H_GPP_C14, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioResetNormal, GpioTermNone } },//GPP_C_14_FM_BMC_PCH_SCI_LPC_N
- { GPIO_SKL_H_GPP_C15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_15_TP_LINK_WIDTH_ID0
- { GPIO_SKL_H_GPP_C16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_16_TP_LINK_WIDTH_ID1
- { GPIO_SKL_H_GPP_C17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_17_TP_LINK_WIDTH_ID2
- { GPIO_SKL_H_GPP_C18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_18_TP_LINK_WIDTH_ID3
- { GPIO_SKL_H_GPP_C19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_19_TP_LINK_WIDTH_ID4 , MSFT_WCS_override for AVA Slot3_PRSNT_N_2_4
- { GPIO_SKL_H_GPP_C20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_20_FM_THROTTLE_N
- { GPIO_SKL_H_GPP_C21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_21_RST_PCH_MIC_MUX_N
- { GPIO_SKL_H_GPP_C22, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone } },//GPP_C_22_IRQ_BMC_PCH_SMI_LPC_N
- { GPIO_SKL_H_GPP_C23, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone } },//GPP_C_23_FM_CPU_CATERR_DLY_LVT3_N
- // Group D
- { GPIO_SKL_H_GPP_D0, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntNmi, GpioResetNormal, GpioTermNone } },//GPP_D_0_IRQ_BMC_PCH_NMI
- { GPIO_SKL_H_GPP_D1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_1_FP_PWR_LED_N
- { GPIO_SKL_H_GPP_D2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_D_2_FM_TBT_FORCE_PWR
- { GPIO_SKL_H_GPP_D3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_D_3 [PVDDQ_KLM_PINALERT_N]
- { GPIO_SKL_H_GPP_D4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_D_4_FM_PLD_PCH_DATA
- { GPIO_SKL_H_GPP_D5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_5_TP_PCH_GPP_D_5
- { GPIO_SKL_H_GPP_D6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_6_TP_PCH_GPP_D_6
- { GPIO_SKL_H_GPP_D7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_7_TP_PCH_GPP_D_7
- { GPIO_SKL_H_GPP_D8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_8_TP_PCH_GPP_D_8
- { GPIO_SKL_H_GPP_D9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_9_TP_PCH_GPP_D_9
- { GPIO_SKL_H_GPP_D10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_10_FM_M2_SSD_DEVSLP , MSFT_WCS_override for AVA Slot3_PRSNT_N_2_6
- { GPIO_SKL_H_GPP_D11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_11_FM_LA_TRIGGER_N
- { GPIO_SKL_H_GPP_D12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_12_SGPIO_SSATA_DATA1
- { GPIO_SKL_H_GPP_D13, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_13_SMB_SMLINK5_STBY_LVC3_SCL
- { GPIO_SKL_H_GPP_D14, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_14_SMB_SMLINK5_STBY_LVC3_SDA
- { GPIO_SKL_H_GPP_D15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_15_SSATA_SDATAOUT0
- { GPIO_SKL_H_GPP_D16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_16_TP_PCH_GPP_D_16
- { GPIO_SKL_H_GPP_D17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_17_TP_PCH_GPP_D_17
- { GPIO_SKL_H_GPP_D18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_D_18_TP_PCH_GPP_D_18
- { GPIO_SKL_H_GPP_D19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_D_19_FM_PS_PWROK_DLY_SEL
- { GPIO_SKL_H_GPP_D20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_20_TP_PCH_GPP_D_20
- { GPIO_SKL_H_GPP_D21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_21_SPC_IE_LVC3_RX
- { GPIO_SKL_H_GPP_D22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_22_SPC_IE_LVC3_TX
- { GPIO_SKL_H_GPP_D23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_23_TP_PCH_GPP_D_23
- // Group E
- { GPIO_SKL_H_GPP_E0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_0_TP_PCH_GPP_E_0
- { GPIO_SKL_H_GPP_E1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_1_TP_PCH_GPP_E_1
- { GPIO_SKL_H_GPP_E2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_2_TP_PCH_GPP_E_2
- { GPIO_SKL_H_GPP_E3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_3_FM_ADR_TRIGGER_N
- { GPIO_SKL_H_GPP_E4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_4_TP_PCH_GPP_E_4
- { GPIO_SKL_H_GPP_E5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_5_TP_PCH_GPP_E_5
- { GPIO_SKL_H_GPP_E6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_6_TP_PCH_GPP_E_6
- { GPIO_SKL_H_GPP_E7, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutLow, GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone } },//GPP_E_7_FM_ADR_SMI_GPIO_N MSFT_WCS_override: INT config and reset type
- { GPIO_SKL_H_GPP_E8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_8_LED_PCH_SATA_HDD_N
- { GPIO_SKL_H_GPP_E9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_9_FM_OC0_USB_N
- { GPIO_SKL_H_GPP_E10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_10_FM_OC1_USB_N
- { GPIO_SKL_H_GPP_E11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_11_FM_OC2_USB_N
- { GPIO_SKL_H_GPP_E12, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_12_FM_OC3_USB_N
- // Group F
- { GPIO_SKL_H_GPP_F0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_0_TP_PCH_GPP_F_0
- { GPIO_SKL_H_GPP_F1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_1_TP_PCH_GPP_F_1
- { GPIO_SKL_H_GPP_F2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_2_TP_PCH_GPP_F_2
- { GPIO_SKL_H_GPP_F3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_3_TP_PCH_GPP_F_3
- { GPIO_SKL_H_GPP_F4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_4_TP_PCH_GPP_F_4
- { GPIO_SKL_H_GPP_F5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_F_5_IRQ_TPM_SPI_N
- { GPIO_SKL_H_GPP_F6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_F_6_JTAG_PCH_PLD_TCK
- { GPIO_SKL_H_GPP_F7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_F_7_JTAG_PCH_PLD_TDI
- { GPIO_SKL_H_GPP_F8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_F_8_JTAG_PCH_PLD_TMS
- { GPIO_SKL_H_GPP_F9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_F_9_JTAG_PCH_PLD_TDO
- { GPIO_SKL_H_GPP_F10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_10_SGPIO_SATA_CLOCK
- { GPIO_SKL_H_GPP_F11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_11_SGPIO_SATA_LOAD, MSFT_WCS_override for AVA Slot5_PRSNT_N_2_1
- { GPIO_SKL_H_GPP_F12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_12_SGPIO_SATA_DATA1, MSFT_WCS_override for AVA Slot4_PRSNT_N_2_1
- { GPIO_SKL_H_GPP_F13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_13_SGPIO_SATA_DATA0, MSFT_WCS_override for AVA Slot3_PRSNT_N_2_1
- { GPIO_SKL_H_GPP_F14, { GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_14_LED_PCH_SSATA_HDD_N
- { GPIO_SKL_H_GPP_F15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_15_FM_OC4_USB_N
- { GPIO_SKL_H_GPP_F16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_16_FM_OC5_USB_N
- { GPIO_SKL_H_GPP_F17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_17_FM_OC6_USB_N
- { GPIO_SKL_H_GPP_F18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_18_FM_OC7_USB_N
- { GPIO_SKL_H_GPP_F19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_19_SMB_GBE_STBY_LVC3_SCL
- { GPIO_SKL_H_GPP_F20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_20_SMB_GBE_STBY_LVC3_SDA
- { GPIO_SKL_H_GPP_F21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_21_TP_PCH_GPP_F_21
- { GPIO_SKL_H_GPP_F22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_22_SGPIO_SSATA_CLOCK
- { GPIO_SKL_H_GPP_F23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_23_SGPIO_SSATA_LOAD
- // Group G
- { GPIO_SKL_H_GPP_G0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_0_FAN_TACH_0_FAN_TACH0IE, MSFT_WCS_override for AVA Slot5_PRSNT_N_2_3
- { GPIO_SKL_H_GPP_G1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_1_FAN_TACH_1_FAN_TACH1IE, MSFT_WCS_override for AVA Slot5_PRSNT_N_2_4
- { GPIO_SKL_H_GPP_G2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_2_FAN_TACH_2_FAN_TACH2IE, MSFT_WCS_override for AVA Slot5_PRSNT_N_2_6
- { GPIO_SKL_H_GPP_G3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_3_FAN_TACH_3_FAN_TACH3IE
- { GPIO_SKL_H_GPP_G4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_4_FAN_TACH_4_FAN_TACH4IE
- { GPIO_SKL_H_GPP_G5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_5_FAN_TACH_5_FAN_TACH5IE
- { GPIO_SKL_H_GPP_G6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_6_FAN_TACH_6_FAN_TACH6IE
- { GPIO_SKL_H_GPP_G7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_7_FAN_TACH_7_FAN_TACH7IE
- { GPIO_SKL_H_GPP_G8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_G_8_FAN_PWM_0_FAN_PWM0IE MSFT_WCS_override: Reset Type
- { GPIO_SKL_H_GPP_G9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_9_FAN_PWM_1_FAN_PWM1IE
- { GPIO_SKL_H_GPP_G10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_G_10_FAN_PWM_2_FAN_PWM2IE MSFT_WCS_override: Reset Type
- { GPIO_SKL_H_GPP_G11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_G_11_FAN_PWM_3_FAN_PWM3IE MSFT_WCS_override: Reset Type
- { GPIO_SKL_H_GPP_G12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_G_12_FM_BOARD_SKU_ID0
- { GPIO_SKL_H_GPP_G13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_G_13_FM_BOARD_SKU_ID1
- { GPIO_SKL_H_GPP_G14, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_G_14_FM_BOARD_SKU_ID2
- { GPIO_SKL_H_GPP_G15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_G_15_FM_BOARD_SKU_ID3
- { GPIO_SKL_H_GPP_G16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_G_16_FM_BOARD_SKU_ID4
- { GPIO_SKL_H_GPP_G17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_17_ADR_COMPLETE
- { GPIO_SKL_H_GPP_G18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_18_FM_NMI_EVENT_N
- { GPIO_SKL_H_GPP_G19, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_19_FM_SMI_ACTIVE_N
- { GPIO_SKL_H_GPP_G20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_20_IRQ_SML1_PMBUS_ALERT_N
- { GPIO_SKL_H_GPP_G21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_21_FM_SATAEXPRESS_DEVSLP
- { GPIO_SKL_H_GPP_G22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_22_FM_BIOS_IMAGE_SWAP_N
- { GPIO_SKL_H_GPP_G23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_23_FM_SSATA_PCIE_SEL
- // Group H
- { GPIO_SKL_H_GPP_H0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_0_PU_PCH_GPP_H_0
- { GPIO_SKL_H_GPP_H1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_1_FM_SWAP_OVERRIDE_N
- { GPIO_SKL_H_GPP_H2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_2_FM_PCH_MGPIO_TEST0
- { GPIO_SKL_H_GPP_H3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_3_FM_PCH_MGPIO_TEST1
- { GPIO_SKL_H_GPP_H4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_4_FM_PCH_MGPIO_TEST4
- { GPIO_SKL_H_GPP_H5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_5_FM_CLKREQ_M2_SSD_N
- { GPIO_SKL_H_GPP_H6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_6_FM_OCULINK1_PCIE_SSD0_PRSNT_N
- { GPIO_SKL_H_GPP_H7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_7_FM_OCULINK1_PCIE_SSD1_PRSNT_N
- { GPIO_SKL_H_GPP_H8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_8_FM_CLKREQ_NIC1_N
- { GPIO_SKL_H_GPP_H9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_9_FM_PCH_MGPIO_TEST5
- { GPIO_SKL_H_GPP_H10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_10_SMB_SMLINK2_STBY_LVC3_SCL
- { GPIO_SKL_H_GPP_H11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_11_SMB_SMLINK2_STBY_LVC3_SDA
- { GPIO_SKL_H_GPP_H12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_12_FM_ESPI_FLASH_MODE
- { GPIO_SKL_H_GPP_H13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_13_SMB_SMLINK3_STBY_LVC3_SCL
- { GPIO_SKL_H_GPP_H14, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_14_SMB_SMLINK3_STBY_LVC3_SDA
- { GPIO_SKL_H_GPP_H15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_H_15_PU_ADR_TIMER_HOLD_OFF_N
- { GPIO_SKL_H_GPP_H16, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_16_SMB_SMLINK4_STBY_LVC3_SCL
- { GPIO_SKL_H_GPP_H17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_17_SMB_SMLINK4_STBY_LVC3_SDA
- { GPIO_SKL_H_GPP_H18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_H_18_FM_LT_KEY_DOWNGRADE_N
- { GPIO_SKL_H_GPP_H19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_H_19_TP_PCH_GPP_H_19
- { GPIO_SKL_H_GPP_H20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_H_20_FM_PCH_MGPIO_TEST2
- { GPIO_SKL_H_GPP_H21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_H_21_FM_PCH_MGPIO_TEST3 MSFT_WCS_override: Reset Type
- { GPIO_SKL_H_GPP_H22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_H_22_TP_PCH_GPP_H_22
- { GPIO_SKL_H_GPP_H23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_H_23_FM_SSATA_PCIE_M2_SEL , MSFT_WCS_override for AVA Slot4_PRSNT_N_2_3
- // Group I
- { GPIO_SKL_H_GPP_I0, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_0_GBE_TDO
- { GPIO_SKL_H_GPP_I1, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_1_GBE_TCK
- { GPIO_SKL_H_GPP_I2, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_2_GBE_TMS
- { GPIO_SKL_H_GPP_I3, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_3_GBE_TDI
- { GPIO_SKL_H_GPP_I4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_4_FP_LED_STATUS_GREEN_PCH_N
- { GPIO_SKL_H_GPP_I5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_5_FP_LED_STATUS_AMBER_PCH_N
- { GPIO_SKL_H_GPP_I6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_6_FP_ID_LED_PCH_N
- { GPIO_SKL_H_GPP_I7, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_7_JTAG_GBE_TRST_N
- { GPIO_SKL_H_GPP_I8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_8_FP_ID_BTN_PCH_N
- { GPIO_SKL_H_GPP_I9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_9_FM_MEM_THERM_EVENT_PCH_N
- { GPIO_SKL_H_GPP_I10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_10_TP_PCH_GPP_I_10
- // Group GPD
- { GPIO_SKL_H_GPD0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_0_FM_FIVRBREAK_N
- { GPIO_SKL_H_GPD1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_1_ACPRESENT
- { GPIO_SKL_H_GPD2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_2_LAN_WAKEB
- { GPIO_SKL_H_GPD3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_3_PWRBTNB
- { GPIO_SKL_H_GPD4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_4_SLP_S3B
- { GPIO_SKL_H_GPD5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_5_SLP_S4B
- { GPIO_SKL_H_GPD6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_6_SLP_AB
- { GPIO_SKL_H_GPD7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_7_TP_GPD_7
- { GPIO_SKL_H_GPD8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_8_CLK_33K_PCH_SUSCLK_PLD
- { GPIO_SKL_H_GPD9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_9_TP_SLP_WLAN
- { GPIO_SKL_H_GPD10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_10_SLP_S5B_N
- { GPIO_SKL_H_GPD11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_11_FM_PHY_DISABLE_N
- // Group J
- { GPIO_SKL_H_GPP_J0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_0_LED_GBE_0_ACTIVITY
- { GPIO_SKL_H_GPP_J1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_1_LED_GBE_0_SPEED
- { GPIO_SKL_H_GPP_J2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_2_LED_GBE_1_ACTIVITY
- { GPIO_SKL_H_GPP_J3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_3_LED_GBE_1_SPEED
- { GPIO_SKL_H_GPP_J4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_4_LED_GBE_2_ACTIVITY, MSFT_WCS_override for AVA Slot3_PRSNT_N_2_3
- { GPIO_SKL_H_GPP_J5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_5_LED_GBE_2_SPEED, MSFT_WCS_override for AVA Slot4_PRSNT_N_2_6
- { GPIO_SKL_H_GPP_J6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_J_6_LED_GBE_3_ACTIVITY MSFT_WCS_override: Reset Type
- { GPIO_SKL_H_GPP_J7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_J_7_LED_GBE_3_SPEED MSFT_WCS_override: Reset Type
- { GPIO_SKL_H_GPP_J8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_8_SMB_GBE0_LVC3_R_SCL
- { GPIO_SKL_H_GPP_J9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_9_SMB_GBE0_LVC3_R_SDA
- { GPIO_SKL_H_GPP_J10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_10_SMB_GBE1_LVC3_R_SCL
- { GPIO_SKL_H_GPP_J11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_11_SMB_GBE1_LVC3_R_SDA
- { GPIO_SKL_H_GPP_J12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_12_SMB_GBE2_LVC3_R_SCL
- { GPIO_SKL_H_GPP_J13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_13_SMB_GBE2_LVC3_R_SDA
- { GPIO_SKL_H_GPP_J14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_14_SMB_GBE3_LVC3_R_SCL
- { GPIO_SKL_H_GPP_J15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_15_SMB_GBE3_LVC3_R_SDA, MSFT_WCS_override for AVA Slot4_PRSNT_N_2_4
- { GPIO_SKL_H_GPP_J16, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_16_FM_T1_LVC3_MOD_ABS0
- { GPIO_SKL_H_GPP_J17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_17_LED_GBE_0_LOW_SPEED
- { GPIO_SKL_H_GPP_J18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_J_18_FM_L1_LVC3_MOD_ABS0 MSFT_WCS_override: Reset Type
- { GPIO_SKL_H_GPP_J19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_19_LED_GBE_1_LOW_SPEED
- { GPIO_SKL_H_GPP_J20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_20_FM_T2_LVC3_MOD_ABS0
- { GPIO_SKL_H_GPP_J21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_21_LED_GBE_2_LOW_SPEED
- { GPIO_SKL_H_GPP_J22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_22_FM_L2_LVC3_MOD_ABS0
- { GPIO_SKL_H_GPP_J23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_23_LED_GBE_3_LOW_SPEED
- // Group K
- { GPIO_SKL_H_GPP_K0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_0_CLK_50M_CKMNG_PCH
- { GPIO_SKL_H_GPP_K1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_1_RMII_PCH_BMC_RXD<0>
- { GPIO_SKL_H_GPP_K2, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_2_RMII_PCH_BMC_RXD<1>
- { GPIO_SKL_H_GPP_K3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_3_GBE_NCSI_CRS_DV_R
- { GPIO_SKL_H_GPP_K4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_4_RMII_BMC_PCH_TX_EN
- { GPIO_SKL_H_GPP_K5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_5_RMII_BMC_PCH_TXD<0>
- { GPIO_SKL_H_GPP_K6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_6_RMII_BMC_PCH_TXD<1>
- { GPIO_SKL_H_GPP_K7, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_7_RMII_PCH_BMC_RX_ER
- { GPIO_SKL_H_GPP_K8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_8_PD_RMII_PCH_ARB_IN
- { GPIO_SKL_H_GPP_K9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_9_PU_RMII_PCH_ARB_OUT
- { GPIO_SKL_H_GPP_K10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_10_RST_PCIE_PCH_PERST_N
- //{GPIO_SKL_H_GPP_K11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, GpioTermNone}},//GPP_K_11_PD_1P8_3P3_RCOMP
- // Group L
- //{GPIO_SKL_H_GPP_L0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis,GpioResetDeep, GpioTermNone}},//GPP_L_0
- //{GPIO_SKL_H_GPP_L1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis,GpioResetDeep, GpioTermNone}},//GPP_L_1
- { GPIO_SKL_H_GPP_L2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_2_VISA2CH0_D0
- { GPIO_SKL_H_GPP_L3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_3_VISA2CH0_D1
- { GPIO_SKL_H_GPP_L4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_4_VISA2CH0_D2
- { GPIO_SKL_H_GPP_L5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_5_VISA2CH0_D3
- { GPIO_SKL_H_GPP_L6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_6_VISA2CH0_D4
- { GPIO_SKL_H_GPP_L7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_7_VISA2CH0_D5
- { GPIO_SKL_H_GPP_L8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_8_VISA2CH0_D6
- { GPIO_SKL_H_GPP_L9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_9_VISA2CH0_D7
- { GPIO_SKL_H_GPP_L10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_10_VISA2CH0_CLK
- { GPIO_SKL_H_GPP_L11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_11_VISA2CH1_D0
- { GPIO_SKL_H_GPP_L12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_12_VISA2CH1_D1
- { GPIO_SKL_H_GPP_L13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_13_VISA2CH1_D2
- { GPIO_SKL_H_GPP_L14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_14_VISA2CH1_D3
- { GPIO_SKL_H_GPP_L15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_15_VISA2CH1_D4
- { GPIO_SKL_H_GPP_L16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_16_VISA2CH1_D5
- { GPIO_SKL_H_GPP_L17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_17_VISA2CH1_D6
- { GPIO_SKL_H_GPP_L18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_18_VISA2CH1_D7
- { GPIO_SKL_H_GPP_L19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_19_VISA2CH1_CLK
-};
-
-UINTN mGpioTableSizeMicrosoftWcs = sizeof(mGpioTableMicrosoftWcs);
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/IioBifur.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/IioBifur.c
deleted file mode 100644
index fa2a4d36ce..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/IioBifur.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <PiPei.h>
-#include <IioPlatformData.h>
-
-#include <Guid/HobList.h>
-#include <Protocol/IioUds.h>
-#include <Library/HobLib.h>
-#include <Library/GpioLib.h>
-#include <GpioPinsSklH.h>
-#include <Ppi/ReadOnlyVariable2.h>
-#include <IioBifurcationSlotTable.h>
-
-
-#define ENABLE 1
-#define DISABLE 0
-#define NO_SLT_IMP 0xFF
-#define SLT_IMP 1
-#define HIDE 1
-#define NOT_HIDE 0
-#define VPP_PORT_0 0
-#define VPP_PORT_1 1
-#define VPP_PORT_MAX 0xFF
-#define VPP_ADDR_MAX 0xFF
-#define PWR_VAL_MAX 0xFF
-#define PWR_SCL_MAX 0xFF
-
-
-IIO_BIFURCATION_ENTRY mIioBifurcationTable[] =
-{
- { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 }, //Slot3: skt0/Iou0 Port1A x16
- { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, //PCH uplink x16
- { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_x4x4x4x4 }, //Slot1: skt0/Iou2 Port3A/3B, Slot2: skt0/Iou Port3C/3D (x8 slots)
- { Iio_Socket0, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 }, //MCP x16
- { Iio_Socket0, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 }, //MCP x16
- { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxx8xxx8 }, //Slot4: skt1/IOU0 x16 Port1A/1B, 1C/1D for 2 x8 FPGAs
- { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxx8x4x4 }, //OCulink x8: skt1/Iou1 Port2C/2D, M.2 slots skt1/Iou1 Port1A, 2B (x4x4)
- { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 }, //Slot5: skt1/IOU2 x16
- { Iio_Socket1, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 }, //MCP
- { Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 }, //MCP
-};
-
-UINT8 mIioBifurcationTableEntries = sizeof(mIioBifurcationTable)/sizeof(IIO_BIFURCATION_ENTRY);
-
-IIO_SLOT_CONFIG_ENTRY mIioSlotTable[] = {
- // Port | Slot | Inter | Power Limit | Power Limit | Hot | Vpp | Vpp | PcieSSD | PcieSSD | PcieSSD | Hidden
- // Index | | lock | Scale | Value | Plug | Port | Addr | Cap | VppPort | VppAddr |
- { PORT_1A_INDEX, 3, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_0, VPP_ADDR_MAX, HIDE }, //S0Slt3
-// { PORT_1B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, ENABLE, VPP_PORT_1, 0x4C, HIDE },
-// { PORT_1C_INDEX, 1, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, ENABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE },
- { PORT_2A_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE },
- // Slot 2 supports HP: PCA9555 (CPU0) Addres 0x40, SCH (Rev 0.604) P 118 (MRL in J65)
- { PORT_3A_INDEX, 1, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, ENABLE, VPP_PORT_0, 0x40, ENABLE, VPP_PORT_0, 0x40, NOT_HIDE },
- { PORT_3B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_1, 0x40, HIDE },
- { PORT_3C_INDEX, 2, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_0, 0x42, HIDE },
- { PORT_3D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_1, 0x42, HIDE },
- { SOCKET_1_INDEX +
- PORT_0_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE },
- // Slot 4 supports HP: PCA9554 (CPU1) Address 0x40, SCH (Rev 0.604) P 121 (MRL in J287)
- { SOCKET_1_INDEX +
- PORT_1A_INDEX, 4, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE }, //x16
-// { SOCKET_1_INDEX +
-// PORT_1B_INDEX, NO_SLT_IMP, ENABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, ENABLE, VPP_PORT_1, 0x40, HIDE },
-// { SOCKET_1_INDEX +
-// PORT_1C_INDEX, NO_SLT_IMP, ENABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, ENABLE, VPP_PORT_0, 0x42, HIDE },
-// { SOCKET_1_INDEX +
-// PORT_1D_INDEX, NO_SLT_IMP, ENABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, ENABLE, VPP_PORT_1, 0x42, HIDE },
- { SOCKET_1_INDEX +
- PORT_2A_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_1, VPP_ADDR_MAX, ENABLE, VPP_PORT_0, 0x44, NOT_HIDE }, //x4
- { SOCKET_1_INDEX +
- PORT_2B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, ENABLE, VPP_PORT_1, 0x44, HIDE }, //x4
- { SOCKET_1_INDEX +
- PORT_2C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, ENABLE, VPP_PORT_0, 0x46, HIDE }, //x8
- { SOCKET_1_INDEX +
-// PORT_2D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, ENABLE, VPP_PORT_1, 0x46, HIDE },
-// { SOCKET_1_INDEX +
- PORT_3A_INDEX, 5, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, ENABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE }, //x16
-// { SOCKET_1_INDEX +
-// PORT_3C_INDEX, 7, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, ENABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE },
- // Note: On Neon City, Slot 3 is assigned to PCH's PCIE port
-};
-
-UINT8 mIioSlotTableEntries = sizeof(mIioSlotTable)/sizeof(IIO_SLOT_CONFIG_ENTRY);
\ No newline at end of file
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPostMemLib.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPostMemLib.c
deleted file mode 100644
index f04f1e7c40..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPostMemLib.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <PiPei.h>
-#include <Library/BaseLib.h>
-#include <Library/IoLib.h>
-#include <Library/BoardInitLib.h>
-#include <Library/PcdLib.h>
-#include <Library/DebugLib.h>
-
-EFI_STATUS
-EFIAPI
-MtOlympusBoardInitBeforeSiliconInit (
- VOID
- );
-
-EFI_STATUS
-EFIAPI
-MtOlympusBoardInitAfterSiliconInit (
- VOID
- );
-
-EFI_STATUS
-EFIAPI
-BoardInitBeforeSiliconInit (
- VOID
- )
-{
- MtOlympusBoardInitBeforeSiliconInit ();
- return EFI_SUCCESS;
-}
-
-EFI_STATUS
-EFIAPI
-BoardInitAfterSiliconInit (
- VOID
- )
-{
- MtOlympusBoardInitAfterSiliconInit ();
- return EFI_SUCCESS;
-}
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPreMemLib.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPreMemLib.c
deleted file mode 100644
index 511bc01339..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPreMemLib.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <PiPei.h>
-#include <Library/BaseLib.h>
-#include <Library/IoLib.h>
-#include <Library/BoardInitLib.h>
-#include <Library/PcdLib.h>
-#include <Library/DebugLib.h>
-
-EFI_STATUS
-EFIAPI
-MtOlympusBoardDetect (
- VOID
- );
-
-EFI_BOOT_MODE
-EFIAPI
-MtOlympusBoardBootModeDetect (
- VOID
- );
-
-EFI_STATUS
-EFIAPI
-MtOlympusBoardDebugInit (
- VOID
- );
-
-EFI_STATUS
-EFIAPI
-MtOlympusBoardInitBeforeMemoryInit (
- VOID
- );
-
-EFI_STATUS
-EFIAPI
-MtOlympusBoardInitAfterMemoryInit (
- VOID
- );
-
-EFI_STATUS
-EFIAPI
-BoardDetect (
- VOID
- )
-{
- MtOlympusBoardDetect ();
- return EFI_SUCCESS;
-}
-
-EFI_STATUS
-EFIAPI
-BoardDebugInit (
- VOID
- )
-{
- MtOlympusBoardDebugInit ();
- return EFI_SUCCESS;
-}
-
-EFI_BOOT_MODE
-EFIAPI
-BoardBootModeDetect (
- VOID
- )
-{
- return MtOlympusBoardBootModeDetect ();
-}
-
-EFI_STATUS
-EFIAPI
-BoardInitBeforeMemoryInit (
- VOID
- )
-{
- MtOlympusBoardInitBeforeMemoryInit ();
- return EFI_SUCCESS;
-}
-
-EFI_STATUS
-EFIAPI
-BoardInitAfterMemoryInit (
- VOID
- )
-{
- MtOlympusBoardInitAfterMemoryInit ();
- return EFI_SUCCESS;
-}
-
-EFI_STATUS
-EFIAPI
-BoardInitBeforeTempRamExit (
- VOID
- )
-{
- return EFI_SUCCESS;
-}
-
-EFI_STATUS
-EFIAPI
-BoardInitAfterTempRamExit (
- VOID
- )
-{
- return EFI_SUCCESS;
-}
-
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusDetect.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusDetect.c
deleted file mode 100644
index 11221828da..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusDetect.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <PiPei.h>
-#include <Library/DebugLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/IoLib.h>
-#include <Library/HobLib.h>
-#include <Library/PcdLib.h>
-#include <Library/PciLib.h>
-#include <Library/PcdLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/BoardInitLib.h>
-
-EFI_STATUS
-EFIAPI
-MtOlympusBoardDetect (
- VOID
- )
-{
- DEBUG ((EFI_D_INFO, "MtOlympusBoardDetect\n"));
- return EFI_SUCCESS;
-}
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitPostMemLib.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitPostMemLib.c
deleted file mode 100644
index 7bcbe6e4a4..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitPostMemLib.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <PiPei.h>
-#include <Library/DebugLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/IoLib.h>
-#include <Library/HobLib.h>
-#include <Library/PcdLib.h>
-#include <Library/PciLib.h>
-#include <Library/BoardInitLib.h>
-
-#include <Setup/IioUniversalData.h>
-
-#include "PeiMtOlympusInitLib.h"
-
-VOID
-GetIioUdsHob (
- IN IIO_UDS **UdsHobPtr
- )
-{
- EFI_GUID UniversalDataGuid = IIO_UNIVERSAL_DATA_GUID;
- EFI_HOB_GUID_TYPE *GuidHob;
-
- ASSERT(UdsHobPtr);
-
- *UdsHobPtr = NULL;
-
- GuidHob = GetFirstGuidHob (&UniversalDataGuid);
- if (GuidHob){
- *UdsHobPtr = GET_GUID_HOB_DATA (GuidHob);
- return;
- }
-
- ASSERT(FALSE);
-}
-
-EFI_STATUS
-EFIAPI
-MtOlympusBoardInitBeforeSiliconInit (
- VOID
- )
-{
- return EFI_SUCCESS;
-}
-
-EFI_STATUS
-EFIAPI
-MtOlympusBoardInitAfterSiliconInit (
- VOID
- )
-{
- IIO_UDS *IioUds;
-
- DEBUG((EFI_D_ERROR, "MtOlympusBoardInitAfterSiliconInit\n"));
-
- GetIioUdsHob(&IioUds);
-
- DEBUG ((EFI_D_ERROR, "Memory TOLM: %X\n", IioUds->PlatformData.MemTolm));
- DEBUG (
- (EFI_D_ERROR,
- "PCIE BASE: %lX Size : %X\n",
- IioUds->PlatformData.PciExpressBase,
- IioUds->PlatformData.PciExpressSize)
- );
- DEBUG (
- (EFI_D_ERROR,
- "PCI32 BASE: %X Limit: %X\n",
- IioUds->PlatformData.PlatGlobalMmiolBase,
- IioUds->PlatformData.PlatGlobalMmiolLimit)
- );
- DEBUG (
- (EFI_D_ERROR,
- "PCI64 BASE: %lX Limit: %lX\n",
- IioUds->PlatformData.PlatGlobalMmiohBase,
- IioUds->PlatformData.PlatGlobalMmiohLimit)
- );
- DEBUG ((EFI_D_ERROR, "UC START: %lX End : %lX\n", IioUds->PlatformData.PlatGlobalMmiohBase, (IioUds->PlatformData.PlatGlobalMmiohLimit + 1)));
-
- return EFI_SUCCESS;
-}
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitPreMemLib.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitPreMemLib.c
deleted file mode 100644
index 42858ed74b..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitPreMemLib.c
+++ /dev/null
@@ -1,593 +0,0 @@
-/** @file
-
-Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <Base.h>
-#include <PiPei.h>
-#include <Uefi.h>
-#include <Library/DebugLib.h>
-#include <Library/BaseLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/IoLib.h>
-#include <Library/HobLib.h>
-#include <Library/PcdLib.h>
-#include <Library/PciLib.h>
-#include <Library/BoardInitLib.h>
-#include <Library/PeiServicesLib.h>
-#include <Library/PeiServicesTablePointerLib.h>
-
-#include "PeiMtOlympusInitLib.h"
-
-#include <Ppi/BootInRecoveryMode.h>
-#include <Ppi/PchPolicy.h>
-#include <Ppi/ReadOnlyVariable2.h>
-#include <Ppi/FirmwareVolumeInfo.h>
-#include <Ppi/Reset.h>
-#include <Ppi/Smbus2.h>
-#include <Platform.h>
-#include <GpioPinsSklH.h>
-#include <Library/GpioLib.h>
-
-#include <Guid/SetupVariable.h>
-#include <Guid/PchRcVariable.h>
-#include <Guid/MemoryTypeInformation.h>
-
-#include <Library/MemoryAllocationLib.h>
-#include <Library/PeiServicesLib.h>
-#include <Library/DebugPrintErrorLevelLib.h>
-#include <Library/PrintLib.h>
-#include <SetupTable.h>
-#include <Library/PchCycleDecodingLib.h>
-
-#include <Platform.h>
-#include <Register/PchRegsPcr.h>
-#include <Register/PchRegsLpc.h>
-#include <Register/PchRegsSpi.h>
-#include <PchAccess.h>
-#include <Library/MmPciBaseLib.h>
-#include <IndustryStandard/Pci22.h>
-
-#include <Protocol/IioUds.h>
-
-#include <Ppi/MasterBootMode.h>
-#include <Ppi/EndOfPeiPhase.h>
-#include <Ppi/MemoryDiscovered.h>
-#include <Ppi/ReadOnlyVariable2.h>
-#include <Library/SiliconPolicyInitLib.h>
-#include <Library/SiliconPolicyUpdateLib.h>
-#include <Library/GpioLib.h>
-#include <Guid/GlobalVariable.h>
-#include <Library/TimerLib.h>
-#include <Register/PchRegsPmc.h>
-#include <Library/PchCycleDecodingLib.h>
-#include <Register/PchRegsLpc.h>
-#include <Guid/FirmwareFileSystem3.h>
-#include <Guid/SetupVariable.h>
-#include <Guid/PchRcVariable.h>
-#include <Guid/SocketVariable.h>
-#include <Library/PchPcrLib.h>
-#include <IioBifurcationSlotTable.h>
-#include <KtiHost.h>
-
-#include "SioRegs.h"
-
-#define LEGACY_8259_MASK_REGISTER_MASTER 0x21
-#define LEGACY_8259_MASK_REGISTER_SLAVE 0xA1
-
-extern GPIO_INIT_CONFIG mGpioTableMicrosoftWcs[];
-extern UINTN mGpioTableSizeMicrosoftWcs;
-
-extern PCH_USB_OVERCURRENT_PIN Usb20OverCurrentMappings[PCH_MAX_USB2_PORTS];
-extern PCH_USB_OVERCURRENT_PIN Usb30OverCurrentMappings[PCH_MAX_USB3_PORTS];
-
-extern IIO_BIFURCATION_ENTRY mIioBifurcationTable[];
-extern UINT8 mIioBifurcationTableEntries;
-extern IIO_SLOT_CONFIG_ENTRY mIioSlotTable[];
-extern UINT8 mIioSlotTableEntries;
-extern ALL_LANES_EPARAM_LINK_INFO KtiMtOlympusAllLanesEparamTable[];
-extern UINT32 KtiMtOlympusAllLanesEparamTableSize;
-
-/**
-
- Initialize the GPIO IO selection, GPIO USE selection, and GPIO signal inversion registers.
-
- @param PeiServices - PeiService point.
- @param CpuIo - CpuIo PPI to read/write IO ports.
-
- @retval EFI_SUCCESS - Init succeed.
-
-**/
-VOID
-LpcSioEarlyInit (
- VOID
- )
-{
- PchLpcGenIoRangeSet ((0x600 & 0xFF0), 0x10, LPC_ESPI_FIRST_SLAVE);
-
- IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK);
- IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK);
-
- //
- //mailbox
- //
- IoWrite8 (SIO_INDEX_PORT, REG_LOGICAL_DEVICE);
- IoWrite8 (SIO_DATA_PORT, SIO_MAILBOX);
-
- IoWrite8 (SIO_INDEX_PORT, BASE_ADDRESS_HIGH0);
- IoWrite8 (SIO_DATA_PORT, (UINT8)(0x600 >> 8));
-
- IoWrite8 (SIO_INDEX_PORT, BASE_ADDRESS_LOW0);
- IoWrite8 (SIO_DATA_PORT, (UINT8)(0x600 & 0xFF));
- //
- //active mailbox
- //
- IoWrite8 (SIO_INDEX_PORT, ACTIVATE);
- IoWrite8 (SIO_DATA_PORT, 1);
-
- IoWrite8 (SIO_INDEX_PORT, SIO_LOCK);
-}
-
-
-VOID
-EarlyPlatformPchInit (
- IN EFI_PEI_SERVICES **PeiServices,
- IN SYSTEM_CONFIGURATION *SystemConfiguration,
- IN PCH_RC_CONFIGURATION *PchRcConfiguration
- )
-{
- UINT16 Data16;
- UINT8 Data8;
- UINTN LpcBaseAddress;
- UINT8 TcoRebootHappened;
- UINTN PmcBaseAddress;
- UINTN SpiBaseAddress;
- UINTN P2sbBase;
-
- DEBUG((DEBUG_ERROR, "EarlyPlatformPchInit - Start\n"));
-
- LpcBaseAddress = MmPciBase (
- DEFAULT_PCI_BUS_NUMBER_PCH,
- PCI_DEVICE_NUMBER_PCH_LPC,
- PCI_FUNCTION_NUMBER_PCH_LPC
- );
- PmcBaseAddress = MmPciBase (
- DEFAULT_PCI_BUS_NUMBER_PCH,
- PCI_DEVICE_NUMBER_PCH_PMC,
- PCI_FUNCTION_NUMBER_PCH_PMC
- );
- SpiBaseAddress = MmPciBase (
- DEFAULT_PCI_BUS_NUMBER_PCH,
- PCI_DEVICE_NUMBER_PCH_SPI,
- PCI_FUNCTION_NUMBER_PCH_SPI
- );
-
- //
- // Program bar
- //
- P2sbBase = MmPciBase (
- DEFAULT_PCI_BUS_NUMBER_PCH,
- PCI_DEVICE_NUMBER_PCH_P2SB,
- PCI_FUNCTION_NUMBER_PCH_P2SB
- );
-
- MmioWrite32 (P2sbBase + R_PCH_P2SB_SBREG_BAR, PCH_PCR_BASE_ADDRESS);
- MmioOr8 (P2sbBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
-
- //
- // LPC I/O Configuration
- //
- PchLpcIoDecodeRangesSet (
- (V_PCH_LPC_IOD_LPT_378 << N_PCH_LPC_IOD_LPT) |
- (V_PCH_LPC_IOD_COMB_3E8 << N_PCH_LPC_IOD_COMB) |
- (V_PCH_LPC_IOD_COMA_3F8 << N_PCH_LPC_IOD_COMA)
- );
-
- PchLpcIoEnableDecodingSet (
- B_PCH_LPC_IOE_ME2 |
- B_PCH_LPC_IOE_SE |
- B_PCH_LPC_IOE_ME1 |
- B_PCH_LPC_IOE_KE |
- B_PCH_LPC_IOE_HGE |
- B_PCH_LPC_IOE_LGE |
- B_PCH_LPC_IOE_FDE |
- B_PCH_LPC_IOE_PPE |
- B_PCH_LPC_IOE_CBE |
- B_PCH_LPC_IOE_CAE,
- LPC_ESPI_FIRST_SLAVE
- );
-
- //
- // Enable the upper 128-byte bank of RTC RAM
- //
- PchPcrAndThenOr32 (PID_RTC, R_PCH_PCR_RTC_CONF, (UINT32)~0, B_PCH_PCR_RTC_CONF_UCMOS_EN);
-
- //
- // Disable the Watchdog timer expiration from causing a system reset
- //
- PchPcrAndThenOr32 (PID_ITSS, R_PCH_PCR_ITSS_GIC, (UINT32)~0, B_PCH_PCR_ITSS_GIC_AME);
-
- //
- // Halt the TCO timer
- //
- Data16 = IoRead16 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO1_CNT);
- Data16 |= B_PCH_TCO_CNT_TMR_HLT;
- IoWrite16 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO1_CNT, Data16);
-
- //
- // Read the Second TO status bit
- //
- Data8 = IoRead8 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO2_STS);
- DEBUG((EFI_D_ERROR, "pre read:%x\n", Data8));
-
- Data8 = IoRead8 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO2_STS);
- DEBUG((EFI_D_ERROR, "read:%x\n", Data8));
- if ((Data8 & B_PCH_TCO2_STS_SECOND_TO) == B_PCH_TCO2_STS_SECOND_TO) {
- TcoRebootHappened = 1;
- DEBUG ((EFI_D_ERROR, "EarlyPlatformPchInit - TCO Second TO status bit is set. This might be a TCO reboot\n"));
- } else {
- TcoRebootHappened = 0;
- }
-
- //
- // Clear the Second TO status bit
- //
- Data8 |= B_PCH_TCO2_STS_SECOND_TO;
- IoWrite8 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO2_STS, Data8);
-
- //
- // Disable SERR NMI and IOCHK# NMI in port 61
- //
- Data8 = IoRead8 (R_PCH_NMI_SC);
- Data8 |= (B_PCH_NMI_SC_PCI_SERR_EN | B_PCH_NMI_SC_IOCHK_NMI_EN);
- IoWrite8 (R_PCH_NMI_SC, Data8);
-
- PchPcrAndThenOr32 (PID_ITSS, R_PCH_PCR_ITSS_GIC, (UINT32)~B_PCH_PCR_ITSS_GIC_AME, 0);
-
- //
- // Clear EISS bit to allow for SPI use
- //
- MmioAnd8 (SpiBaseAddress + R_PCH_SPI_BC, (UINT8)~B_PCH_SPI_BC_EISS);
-
- DEBUG((DEBUG_ERROR, "EarlyPlatformPchInit - End\n"));
-}
-
-
-/**
-
- Initialize POC register by Variable.
-
- @param *SystemConfiguration - Pointer to SystemConfiguration variables.
-
- @retval EFI_SUCCESS - Success.
-
-**/
-EFI_STATUS
-UpdatePlatformInfo (
- IN SYSTEM_CONFIGURATION *SystemConfiguration,
- IN SOCKET_CONFIGURATION *SocketConfiguration
- )
-{
- SOCKET_PROCESSORCORE_CONFIGURATION *SocketProcessorCoreConfig;
- SOCKET_IIO_CONFIGURATION *SocketIioConfig;
- UINT32 PcIoApicEnable;
-#if MAX_SOCKET <= 4
- UINTN Index;
-#endif
-
- DEBUG((EFI_D_ERROR, "platform update platform info entry\n"));
-
- SocketProcessorCoreConfig = &SocketConfiguration->SocketProcessorCoreConfiguration;
- SocketIioConfig = &SocketConfiguration->IioConfig;
-
-#if MAX_SOCKET <= 4
- for (Index = 0; Index < 24; Index++) {
- if (SocketIioConfig->DevPresIoApicIio[Index]) {
- PcIoApicEnable |= (1 << Index);
- }
- }
-
-#else
- // Enable all 32 IOxAPIC
- PcIoApicEnable = 0xFFFFFFFF;
-#endif
- PcdSet32 (PcdPcIoApicEnable, PcIoApicEnable);
- //
- // Check to make sure TsegSize is in range, if not use default.
- //
- if (SocketProcessorCoreConfig->TsegSize > MAX_PROCESSOR_TSEG) {
- SocketProcessorCoreConfig->TsegSize = MAX_PROCESSOR_TSEG; // if out of range make default 64M
- }
- PcdSet32 (PcdMemTsegSize, (0x400000 << SocketProcessorCoreConfig->TsegSize));
- if (SocketProcessorCoreConfig->IedSize > 0) {
- PcdSet32 (PcdMemIedSize, (0x400000 << (SocketProcessorCoreConfig->IedSize - 1)));
- } else {
- PcdSet32 (PcdMemIedSize, 0);
- }
-
- //
- // Minimum SMM range in TSEG should be larger than 3M
- //
- ASSERT (PcdGet32 (PcdMemTsegSize) - PcdGet32 (PcdMemIedSize) >= 0x300000);
-
- return EFI_SUCCESS;
-}
-
-/**
- Clear any SMI status or wake status left from boot.
-
- @retval EFI_SUCCESS The function completed successfully.
-**/
-EFI_STATUS
-ClearPchSmiAndWake (
- VOID
- )
-{
- UINT16 ABase;
- UINT16 Pm1Sts;
-
-
- //
- // Clear any SMI or wake state from the boot
- //
- Pm1Sts |=
- (
- B_PCH_ACPI_PM1_STS_PWRBTN
- );
- PchAcpiBaseGet (&ABase);
- //
- // Write them back
- //
- IoWrite16 (ABase + R_PCH_ACPI_PM1_STS, Pm1Sts);
-
- //
- // Clear the GPE and PM enable
- //
- IoWrite16 (ABase + R_PCH_ACPI_PM1_EN, 0);
- IoWrite32 (ABase + R_PCH_ACPI_GPE0_EN_127_96, 0);
-
- return EFI_SUCCESS;
-}
-
-EFI_STATUS
-PlatformInitGpios (
- VOID
-)
-{
- EFI_STATUS Status;
- GPIO_INIT_CONFIG *GpioTable;
- UINTN TableSize;
-
- TableSize = mGpioTableSizeMicrosoftWcs;
- DEBUG ((DEBUG_ERROR, "UBA:Size of GpioTable 0x%X, blocks: 0x%X.\n", TableSize, (TableSize/sizeof (GPIO_INIT_CONFIG)) ));
-
- GpioTable = mGpioTableMicrosoftWcs;
- DEBUG ((DEBUG_ERROR, "UBA: ConfigureGpio() MtOlympus Start.\n"));
- Status = GpioConfigurePads (TableSize/sizeof (GPIO_INIT_CONFIG), GpioTable);
- DEBUG ((DEBUG_ERROR, "UBA: ConfigureGpio() MtOlympus End.\n"));
-
- return EFI_SUCCESS;
-}
-
-VOID
-SetUsbConfig (
- VOID
- )
-{
- PcdSet64 (PcdUsb20OverCurrentMappings, (UINT64)(UINTN)Usb20OverCurrentMappings);
- PcdSet64 (PcdUsb30OverCurrentMappings, (UINT64)(UINTN)Usb30OverCurrentMappings);
-}
-
-VOID
-IioPortBifurcationConfig (
- VOID
- )
-{
- PcdSet64 (PcdIioBifurcationTable, (UINT64)(UINTN)mIioBifurcationTable);
- PcdSet8 (PcdIioBifurcationTableEntries, mIioBifurcationTableEntries);
- PcdSet64 (PcdIioSlotTable, (UINT64)(UINTN)mIioSlotTable);
- PcdSet8 (PcdIioSlotTableEntries, mIioSlotTableEntries);
-}
-
-VOID
-AllLanesEparamTableConfig (
- VOID
- )
-{
- PcdSet64 (PcdAllLanesEparamTable, (UINT64)(UINTN)KtiMtOlympusAllLanesEparamTable);
- PcdSet32 (PcdAllLanesEparamTableSize, KtiMtOlympusAllLanesEparamTableSize);
-}
-
-EFI_STATUS
-PchLanConfig (
- IN SYSTEM_CONFIGURATION *SystemConfig
-)
-{
- GpioSetOutputValue (GPIO_SKL_H_GPP_I9, (UINT32)SystemConfig->LomDisableByGpio);
-
- return EFI_SUCCESS;
-}
-
-/**
- Write to mask registers of master and slave 8259 PICs.
-
-**/
-VOID
-STATIC
-Mask8259Interrupts (
- VOID
- )
-{
- IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, 0xFF);
- IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, 0xFF);
-}
-
-EFI_STATUS
-EFIAPI
-MtOlympusBoardInitBeforeMemoryInit (
- VOID
- )
-{
- EFI_STATUS Status;
- SETUP_DATA SetupData;
- SYSTEM_CONFIGURATION SystemConfiguration;
- PCH_RC_CONFIGURATION PchRcConfiguration;
- SOCKET_CONFIGURATION SocketConfiguration;
- UINT16 ABase;
- UINT16 Pm1Sts;
- UINT32 Pm1Cnt;
- CONST EFI_PEI_SERVICES ** PeiServices;
-
- PeiServices = GetPeiServicesTablePointer ();
-
- ZeroMem (&SetupData, sizeof(SETUP_DATA));
- CopyMem (&SetupData.SocketConfig.IioConfig, PcdGetPtr(PcdSocketIioConfigData), sizeof(SOCKET_IIO_CONFIGURATION));
- CopyMem (&SetupData.SocketConfig.CommonRcConfig, PcdGetPtr(PcdSocketCommonRcConfigData), sizeof(SOCKET_COMMONRC_CONFIGURATION));
- CopyMem (&SetupData.SocketConfig.CsiConfig, PcdGetPtr(PcdSocketMpLinkConfigData), sizeof(SOCKET_MP_LINK_CONFIGURATION));
- CopyMem (&SetupData.SocketConfig.MemoryConfig, PcdGetPtr(PcdSocketMemoryConfigData), sizeof(SOCKET_MEMORY_CONFIGURATION));
- CopyMem (&SetupData.SocketConfig.PowerManagementConfig, PcdGetPtr(PcdSocketPowerManagementConfigData), sizeof(SOCKET_POWERMANAGEMENT_CONFIGURATION));
- CopyMem (&SetupData.SocketConfig.SocketProcessorCoreConfiguration, PcdGetPtr(PcdSocketProcessorCoreConfigData), sizeof(SOCKET_PROCESSORCORE_CONFIGURATION));
- CopyMem (&SetupData.SystemConfig, PcdGetPtr(PcdSetupData), sizeof(SYSTEM_CONFIGURATION));
- CopyMem (&SetupData.PchRcConfig, PcdGetPtr(PcdPchRcConfigurationData), sizeof(PCH_RC_CONFIGURATION));
-
- CopyMem (&SocketConfiguration, &(SetupData.SocketConfig), sizeof (SOCKET_CONFIGURATION));
- CopyMem (&PchRcConfiguration, &(SetupData.PchRcConfig), sizeof (PCH_RC_CONFIGURATION));
- CopyMem (&SystemConfiguration, &(SetupData.SystemConfig), sizeof (SYSTEM_CONFIGURATION));
-
- ///
- /// Set LPC SIO
- ///
- MmioOr16(
- (MmPciBase(DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, PCI_FUNCTION_NUMBER_PCH_LPC) + R_PCH_LPC_IOE),
- B_PCH_LPC_IOE_SE
- );
-
- LpcSioEarlyInit ();
-
- Status = PlatformInitGpios ();
- ASSERT_EFI_ERROR (Status);
-
- SetUsbConfig ();
- IioPortBifurcationConfig ();
- AllLanesEparamTableConfig ();
-
- ///
- /// Do Early PCH init
- ///
- EarlyPlatformPchInit ((EFI_PEI_SERVICES**)PeiServices, &SystemConfiguration, &PchRcConfiguration);
-
- ///
- /// Clear PCH SMI and Wake
- /// Clear all pending SMI. On S3 clear power button enable so it will not generate an SMI.
- ///
- Status = ClearPchSmiAndWake();
- ASSERT_EFI_ERROR (Status);
- ///----------------------------------------------------------------------------------
- ///
- /// BIOS should check the WAK_STS bit in PM1_STS[15] (PCH register ABASE+00h) before memory
- /// initialization to determine if ME has reset the system while the host was in a sleep state.
- /// If WAK_STS is not set, BIOS should ensure a non-sleep exit path is taken by overwriting
- /// PM1_CNT[12:10] (PCH register ABASE+04h) to 111b to force an s5 exit.
- ///
- PchAcpiBaseGet (&ABase);
- Pm1Sts = IoRead16 (ABase + R_PCH_ACPI_PM1_STS);
- if ((Pm1Sts & B_PCH_ACPI_PM1_STS_WAK) == 0) {
- Pm1Cnt = IoRead32 (ABase + R_PCH_ACPI_PM1_CNT);
- Pm1Cnt |= V_PCH_ACPI_PM1_CNT_S5;
- IoWrite32 (ABase + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
- }
-
- UpdatePlatformInfo (&SystemConfiguration, &SocketConfiguration);
-
- //
- // Do platform specific on-board Zoar init
- //
- PchLanConfig (&SystemConfiguration);
-
- //
- // The 8259 PIC is still functional and not masked by default even if APIC is
- // enabled. So need to disable all 8259 interrupts.
- //
- Mask8259Interrupts ();
-
- return EFI_SUCCESS;
-}
-
-/**
-
- Turn off system if needed.
-
- @param PeiServices Pointer to PEI Services
- @param CpuIo Pointer to CPU I/O Protocol
-
- @retval None.
-
-**/
-VOID
-CheckPowerOffNow (
- VOID
- )
-{
-
- UINT16 Pm1Sts;
-
- //
- // Read and check the ACPI registers
- //
- Pm1Sts = IoRead16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI_PM1_STS);
- DEBUG ((EFI_D_ERROR, "CheckPowerOffNow()- Pm1Sts= 0x%04x\n", Pm1Sts ));
-
- if ((Pm1Sts & B_PCH_ACPI_PM1_STS_PWRBTN) == B_PCH_ACPI_PM1_STS_PWRBTN) {
- IoWrite16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI_PM1_STS, B_PCH_ACPI_PM1_STS_PWRBTN);
- IoWrite16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI_PM1_CNT, V_PCH_ACPI_PM1_CNT_S5);
- IoWrite16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI_PM1_CNT, V_PCH_ACPI_PM1_CNT_S5 + B_PCH_ACPI_PM1_CNT_SLP_EN);
- }
-}
-
-EFI_STATUS
-EFIAPI
-MtOlympusBoardInitAfterMemoryInit (
- VOID
- )
-{
- EFI_STATUS Status;
- EFI_BOOT_MODE BootMode;
- UINT16 Pm1Cnt;
-
- Status = PeiServicesGetBootMode (&BootMode);
- ASSERT_EFI_ERROR (Status);
-
- //
- // Check if user wants to turn off in PEI phase
- //
- if (BootMode != BOOT_ON_S3_RESUME) {
- CheckPowerOffNow ();
- } else {
- Pm1Cnt = IoRead16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI_PM1_CNT);
- Pm1Cnt &= ~B_PCH_ACPI_PM1_CNT_SLP_TYP;
- IoWrite16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
- }
-
- return EFI_SUCCESS;
-}
-
-EFI_STATUS
-EFIAPI
-MtOlympusBoardDebugInit (
- VOID
- )
-{
- return EFI_SUCCESS;
-}
-
-EFI_BOOT_MODE
-EFIAPI
-MtOlympusBoardBootModeDetect (
- VOID
- )
-{
- return BOOT_WITH_FULL_CONFIGURATION;
-}
-
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/UsbOC.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/UsbOC.c
deleted file mode 100644
index a9375b116e..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/UsbOC.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <PiPei.h>
-
-#include <Library/PcdLib.h>
-#include <PchLimits.h>
-#include <PchPolicyCommon.h>
-
-PCH_USB_OVERCURRENT_PIN Usb20OverCurrentMappings[PCH_MAX_USB2_PORTS] = {
- PchUsbOverCurrentPinSkip, //1 BMC,skip
- PchUsbOverCurrentPinSkip, //2 BMC,skip
- PchUsbOverCurrentPin0, //3 USB REAR PANEL, OC0
- PchUsbOverCurrentPin1, //4 USB REAR PANEL, OC1
- PchUsbOverCurrentPin1, //5 USB REAR PANEL, OC1
- PchUsbOverCurrentPinSkip, //6 Internal USB3.0, NC, skip(org OC2 in schematic)
- PchUsbOverCurrentPinSkip, //7 NC, skip
- PchUsbOverCurrentPin4, //8 Internal USB2.0, OC4
- PchUsbOverCurrentPinSkip, //9 NC, skip
- PchUsbOverCurrentPinSkip, //10 NC, skip
- PchUsbOverCurrentPin6, //11 USB FRONT PANEL, OC6
- PchUsbOverCurrentPin5, //12 USB STORAGE FRONT PANNEL, OC5
- PchUsbOverCurrentPin6, //13 USB FRONT PANEL, OC6
- PchUsbOverCurrentPin5, //14 USB STORAGE FRONT PANNEL, OC5
- PchUsbOverCurrentPinSkip,
- PchUsbOverCurrentPinSkip
- };
-
-PCH_USB_OVERCURRENT_PIN Usb30OverCurrentMappings[PCH_MAX_USB3_PORTS] = {
- PchUsbOverCurrentPin6, //1 USB FRONT PANEL, OC6
- PchUsbOverCurrentPin6, //2 USB FRONT PANEL, OC6
- PchUsbOverCurrentPin0, //3 USB REAR PANEL, OC0
- PchUsbOverCurrentPin1, //4 USB REAR PANEL, OC1
- PchUsbOverCurrentPin1, //5 USB REAR PANEL, OC1
- PchUsbOverCurrentPinSkip, //6 Internal USB3.0, NC, skip(org OC2 in schematic)
- PchUsbOverCurrentPinSkip,
- PchUsbOverCurrentPinSkip,
- PchUsbOverCurrentPinSkip,
- PchUsbOverCurrentPinSkip
- };
-
--
2.16.2.windows.1
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