[edk2-devel] [edk2] question about : DmaBufferAlignment in CPU Arch driver

[Tiger Liu(BJ-RD)]

Dear All:
I have a question about DmaBufferAlignment in CPU Arch driver.

Based on PI Spec:
......
This is typically the size of the largest data cache line in the platform.
This value can be determined by looking at the data cache line sizes of all the caches present in the platform, and returning the largest.
This is used by the root bridge I/O abstraction protocols to guarantee that no two DMA buffers ever share the same cache line.
The value in this field is a constant that must not be modified after the CPU Architectural Protocol is installed. All consumers must treat this as a read-only field.

But, I study Kabylake sample code, it uses UefiCpuPkg/CpuDxe/CpuDxe.inf,
And it declares  4 (DmaBufferAlignment).

For x86 cpu, the cache line size is usually 64 bytes.

Why not set 64 in CPU Arch protocol interface struct?

Thanks


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