[edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 02/14] Silicon/SiFive: Add library module of SiFive RISC-V cores

[Abner Chang]

> -----Original Message-----
> From: devel at edk2.groups.io [mailto:devel at edk2.groups.io] On Behalf Of
> Leif Lindholm
> Sent: Wednesday, October 2, 2019 5:15 AM
> To: devel at edk2.groups.io; Chen, Gilbert <gilbert.chen at hpe.com>
> Subject: Re: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 02/14]
> Silicon/SiFive: Add library module of SiFive RISC-V cores
> 
> On Thu, Sep 19, 2019 at 11:51:19AM +0800, Gilbert Chen wrote:
> > Initial version of SiFive RISC-V core libraries. Library of each core
> > creates processor core SMBIOS data hob for building SMBIOS  records in
> > DXE phase.
> 
> So yes, this implementation needs to change.
> These should all implement the same LibraryClass.
No. It shouldn't be the same library class (If you were saying the same LibraryClass). RISC-V SoC could be the combination of different RISC-V cores, or even the cores from different vendors. This depends on how SoC vendor combine those IPs.
Either U54 or E51 could be a standalone SoC, while U54MC is the combination of 4 x U54 core and one E51 core.

U5MC under Platform/SiFive could be 1-8 U5 core and optionally support E5 core.  This is the special case for U500 VC707 platform because the core number could be customized.

> Also, U54 appears to be a simple superset of U51.
U54 is a single core. 

> 
> What I would suggest is creating a
> Silicon/SiFive/Library/SiFiveCoreInfoLib, which calls into a
> SiFiveSoCCoreInfoLib in Silicon/SiFive/<SoC>/Library, providing the acual SoC-
> specific bits.

Platform system firmware integrator just pull in the necessary core libraries from Silicon/{vendor}  and invoke the function to create specific core bits.
I think this implementation is well and flexible which has no need to change.

> 
> /
>     Leif
> 
> > Signed-off-by: Gilbert Chen <gilbert.chen at hpe.com>
> > ---
> >  .../E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c    | 242
> +++++++++++++++++
> >  .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf        |  51 ++++
> >  .../U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c    | 294
> +++++++++++++++++++++
> >  .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf        |  51 ++++
> >  .../Library/PeiCoreInfoHobLib/CoreInfoHob.c        | 185 +++++++++++++
> >  .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf        |  50 ++++
> >  6 files changed, 873 insertions(+)
> >  create mode 100644
> > Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
> >  create mode 100644
> > Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
> >  create mode 100644
> > Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c
> >  create mode 100644
> > Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
> >  create mode 100644
> > Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c
> >  create mode 100644
> >
> Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCoreInfoHobL
> > ib.inf
> 
> 


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