[edk2-devel] [edk2-staging/RISC-V-V2 PATCH v1 19/22]: MdeModulePkg/DxeIplPeim:RISC-V platform DXEIPL.
Leif Lindholm
leif.lindholm at linaro.org
Thu Sep 5 16:50:05 UTC 2019
On Wed, Sep 04, 2019 at 06:43:14PM +0800, Abner Chang wrote:
> - Implement RISC-V DxeIpl.
> - Provide DxeIpl platform implementation-specifc library for RISC-V platform. Two libraries are provided in this commit,
> * Defualt library which simply switch stack and transfer
> control to DXE core.
> * Switch stack, privilege mode and then transfer control to
> DXE core through RISC-V opensbi.
No comments beyond SPDX/license and contribution agreement.
/
Leif
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Abner Chang <abner.chang at hpe.com>
> ---
> MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 13 +++-
> MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c | 76 ++++++++++++++++++++++
> 2 files changed, 88 insertions(+), 1 deletion(-)
> create mode 100644 MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c
>
> diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> index 98bc17f..5532323 100644
> --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> @@ -7,6 +7,7 @@
> #
> # Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
> # Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
> +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -25,7 +26,7 @@
> #
> # The following information is for reference only and not required by the build tools.
> #
> -# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only) AARCH64
> +# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only) AARCH64 RISCV64
> #
>
> [Sources]
> @@ -49,6 +50,9 @@
> [Sources.ARM, Sources.AARCH64]
> Arm/DxeLoadFunc.c
>
> +[Sources.RISCV64]
> + RiscV64/DxeLoadFunc.c
> +
> [Packages]
> MdePkg/MdePkg.dec
> MdeModulePkg/MdeModulePkg.dec
> @@ -56,6 +60,9 @@
> [Packages.ARM, Packages.AARCH64]
> ArmPkg/ArmPkg.dec
>
> +[Packages.RISCV64]
> + RiscVPkg/RiscVPkg.dec
> +
> [LibraryClasses]
> PcdLib
> MemoryAllocationLib
> @@ -75,6 +82,10 @@
> [LibraryClasses.ARM, LibraryClasses.AARCH64]
> ArmMmuLib
>
> +[LibraryClasses.RISCV64]
> + RiscVPlatformDxeIplLib
> + RiscVOpensbiLib
> +
> [Ppis]
> gEfiDxeIplPpiGuid ## PRODUCES
> gEfiPeiDecompressPpiGuid ## PRODUCES
> diff --git a/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c b/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c
> new file mode 100644
> index 0000000..934dfa5
> --- /dev/null
> +++ b/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c
> @@ -0,0 +1,76 @@
> +/** @file
> + RISC-V specific functionality for DxeLoad.
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +**/
> +
> +#include "DxeIpl.h"
> +#include "Library/RiscVPlatformDxeIpl.h"
> +
> +typedef
> +VOID*
> +(EFIAPI *DXEENTRYPOINT) (
> + IN VOID *HobStart
> + );
> +
> +/**
> + Transfers control to DxeCore.
> +
> + This function performs a CPU architecture specific operations to execute
> + the entry point of DxeCore with the parameters of HobList.
> + It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
> +
> + @param DxeCoreEntryPoint The entry point of DxeCore.
> + @param HobList The start of HobList passed to DxeCore.
> +
> +**/
> +VOID
> +HandOffToDxeCore (
> + IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
> + IN EFI_PEI_HOB_POINTERS HobList
> + )
> +{
> + VOID *BaseOfStack;
> + VOID *TopOfStack;
> + EFI_STATUS Status;
> + //
> + //
> + // Allocate 128KB for the Stack
> + //
> + BaseOfStack = AllocatePages (EFI_SIZE_TO_PAGES (STACK_SIZE));
> + ASSERT (BaseOfStack != NULL);
> +
> + //
> + // Compute the top of the stack we were allocated. Pre-allocate a UINTN
> + // for safety.
> + //
> + TopOfStack = (VOID *) ((UINTN) BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT);
> + TopOfStack = ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT);
> +
> + //
> + // End of PEI phase signal
> + //
> + Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore.
> + //
> + UpdateStackHob ((EFI_PHYSICAL_ADDRESS)(UINTN) BaseOfStack, STACK_SIZE);
> +
> + DEBUG ((EFI_D_INFO, "DXE Core new stack at %x, stack pointer at %x\n", BaseOfStack, TopOfStack));
> +
> + //
> + // Transfer the control to the entry point of DxeCore.
> + //
> + RiscVPlatformHandOffToDxeCore (BaseOfStack, TopOfStack, DxeCoreEntryPoint, HobList);
> +}
> +
> --
> 2.7.4
>
>
>
>
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