[edk2-devel] [PATCH v2 3/3] SimicsIch10Pkg: Fix GCC build issues
Agyeman, Prince
prince.agyeman at intel.com
Wed Sep 11 16:40:10 UTC 2019
From: "Agyeman, Prince" <prince.agyeman at intel.com>
Removed Status variable as the SmmClear
function always returns EFI_SUCCESS.
Refer to the Smmclear function for
details
Removed SpiBaseAddress variable as this
address was never used in the SendSpiCmd function.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2162
Cc: David Wei <david.y.wei at intel.com>
Cc: Liming Gao <liming.gao at intel.com>
Cc: Ankit Sinha <ankit.sinha at intel.com>
Cc: Agyeman Prince <prince.agyeman at intel.com>
Cc: Kubacki Michael A <michael.a.kubacki at intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone at intel.com>
Signed-off-by: Prince Agyeman <prince.agyeman at intel.com>
---
.../LibraryPrivate/BasePchSpiCommonLib/SpiCommon.c | 3 ---
.../SimicsIch10Pkg/SmmControl/RuntimeDxe/SmmControl2Dxe.c | 7 ++-----
2 files changed, 2 insertions(+), 8 deletions(-)
diff --git a/Silicon/Intel/SimicsIch10Pkg/LibraryPrivate/BasePchSpiCommonLib/SpiCommon.c b/Silicon/Intel/SimicsIch10Pkg/LibraryPrivate/BasePchSpiCommonLib/SpiCommon.c
index bd08b2453b..3e7dffedfb 100644
--- a/Silicon/Intel/SimicsIch10Pkg/LibraryPrivate/BasePchSpiCommonLib/SpiCommon.c
+++ b/Silicon/Intel/SimicsIch10Pkg/LibraryPrivate/BasePchSpiCommonLib/SpiCommon.c
@@ -637,7 +637,6 @@ SendSpiCmd (
EFI_STATUS Status;
UINT32 Index;
SPI_INSTANCE *SpiInstance;
- UINTN SpiBaseAddress;
UINTN PchSpiBar0;
UINT32 HardwareSpiAddr;
UINT32 FlashRegionSize;
@@ -648,9 +647,7 @@ SendSpiCmd (
Status = EFI_SUCCESS;
SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
- SpiBaseAddress = SpiInstance->PchSpiBase;
PchSpiBar0 = AcquireSpiBar0 (SpiInstance);
- SpiBaseAddress = SpiInstance->PchSpiBase;
ABase = SpiInstance->PchAcpiBase;
//
diff --git a/Silicon/Intel/SimicsIch10Pkg/SmmControl/RuntimeDxe/SmmControl2Dxe.c b/Silicon/Intel/SimicsIch10Pkg/SmmControl/RuntimeDxe/SmmControl2Dxe.c
index 268b04d25a..cc2d00b785 100644
--- a/Silicon/Intel/SimicsIch10Pkg/SmmControl/RuntimeDxe/SmmControl2Dxe.c
+++ b/Silicon/Intel/SimicsIch10Pkg/SmmControl/RuntimeDxe/SmmControl2Dxe.c
@@ -131,7 +131,6 @@ SmmControl2DxeTrigger (
IN UINTN ActivationInterval OPTIONAL
)
{
- EFI_STATUS Status;
//
// No support for queued or periodic activation.
//
@@ -141,7 +140,7 @@ SmmControl2DxeTrigger (
///
/// Clear any pending the APM SMI
///
- Status = SmmClear();
+ SmmClear();
//
// The so-called "Advanced Power Management Status Port Register" is in fact
// a generic data passing register, between the caller and the SMI
@@ -181,8 +180,6 @@ SmmControl2DxeClear (
IN BOOLEAN Periodic OPTIONAL
)
{
- EFI_STATUS Status;
-
if (Periodic) {
return EFI_INVALID_PARAMETER;
}
@@ -201,7 +198,7 @@ SmmControl2DxeClear (
//
// So, nothing to do here.
//
- Status = SmmClear();
+ SmmClear();
return EFI_SUCCESS;
}
--
2.19.1.windows.1
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