[edk2-devel] [edk2-platforms][PATCH V1 02/12] ClevoOpenBoardPkg: Remove package contents
Chiu, Chasel
chasel.chiu at intel.com
Mon Sep 23 08:23:44 UTC 2019
Reviewed-by: Chasel Chiu <chasel.chiu at intel.com>
> -----Original Message-----
> From: devel at edk2.groups.io <devel at edk2.groups.io> On Behalf Of Kubacki,
> Michael A
> Sent: Saturday, September 21, 2019 2:40 AM
> To: devel at edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu at intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone at intel.com>; Sinha, Ankit <ankit.sinha at intel.com>;
> Jeremy Soller <jeremy at system76.com>
> Subject: [edk2-devel] [edk2-platforms][PATCH V1 02/12] ClevoOpenBoardPkg:
> Remove package contents
>
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2207
>
> The N1xxWU board contents will be moved to KabylakeOpenBoardPkg
> to reduce code duplication between ClevoOpenBoardPkg and
> KabylakeOpenBoardPkg.
>
> Cc: Chasel Chiu <chasel.chiu at intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone at intel.com>
> Cc: Ankit Sinha <ankit.sinha at intel.com>
> Cc: Jeremy Soller <jeremy at system76.com>
> Signed-off-by: Michael Kubacki <michael.a.kubacki at intel.com>
> ---
> Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec
> | 305 ----
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc
> | 385 ----
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgBuildOption.dsc
> | 151 --
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgConfig.dsc
> | 132 --
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc
> | 265 ---
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclude.f
> df |
> 48 -
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf
> | 716 --------
> Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
> | 69 -
> Platform/Intel/ClevoOpenBoardPkg/Features/PciHotPlug/PciHotPlug.inf
> | 59 -
>
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib/Dx
> eTbtPolicyLib.inf | 67 -
>
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTbtCom
> monLib/TbtCommonLib.inf |
> 62 -
>
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/Pei
> TbtPolicyLib.inf | 56 -
>
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/Private/PeiDTbtInit
> Lib/PeiDTbtInitLib.inf | 41 -
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtDxe.inf
> | 49 -
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf
> | 44 -
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
> | 77 -
>
> Platform/Intel/ClevoOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGpio
> ExpanderLib.inf |
> 33 -
>
> Platform/Intel/ClevoOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cAccessLib.i
> nf | 36 -
>
> Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSeria
> lPortLibSpiFlash.inf | 50 -
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilicon
> PolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf | 43 -
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilicon
> PolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf | 146 --
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BasePlatformHookLib/
> BasePlatformHookLib.inf |
> 51 -
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeBoar
> dAcpiTableLib.inf |
> 47 -
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeMulti
> BoardAcpiSupportLib.inf |
> 48 -
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmBoa
> rdAcpiEnableLib.inf |
> 47 -
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmMul
> tiBoardAcpiSupportLib.inf |
> 48 -
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoardI
> nitPostMemLib.inf |
> 53 -
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoardI
> nitPreMemLib.inf |
> 132 --
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMultiB
> oardInitPostMemLib.inf |
> 55 -
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMultiB
> oardInitPreMemLib.inf |
> 137 --
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platform/Intel/MinPla
> tformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf | 67 -
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPolicy
> UpdateLib/DxeSiliconPolicyUpdateLib.inf | 49 -
> Platform/Intel/ClevoOpenBoardPkg/Features/PciHotPlug/PciHotPlug.h
> | 130 --
>
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Acpi/TbtNvsAreaD
> ef.h |
> 62 -
>
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/DxeTbtPoli
> cyLib.h | 46
> -
>
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/PeiTbtPolic
> yLib.h | 41 -
>
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/TbtCommo
> nLib.h |
> 241 ---
>
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Ppi/PeiTbtPolicy.h
> | 29 -
>
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Private/Library/Pei
> DTbtInitLib.h | 108 --
>
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Private/Library/Pei
> TbtCommonInitLib.h | 41 -
>
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Protocol/DxeTbtPo
> licy.h | 110
> --
>
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Protocol/TbtNvsAr
> ea.h |
> 42 -
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/TbtBoardInfo.h
> | 22 -
>
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/TbtPolicyCommon
> Definition.h |
> 77 -
>
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib/Dx
> eTbtPolicyLibrary.h | 22 -
>
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/Pei
> TbtPolicyLibrary.h | 17 -
>
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmiHandl
> er.h |
> 179 --
> Platform/Intel/ClevoOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef.h
> | 116 --
> Platform/Intel/ClevoOpenBoardPkg/Include/IoExpander.h
> | 67 -
> Platform/Intel/ClevoOpenBoardPkg/Include/Library/GpioExpanderLib.h
> | 122 --
> Platform/Intel/ClevoOpenBoardPkg/Include/Library/I2cAccessLib.h
> | 33 -
> Platform/Intel/ClevoOpenBoardPkg/Include/PchHsioPtssTables.h
> | 51 -
> Platform/Intel/ClevoOpenBoardPkg/Include/Protocol/GlobalNvsArea.h
> | 47 -
> Platform/Intel/ClevoOpenBoardPkg/Include/SioRegs.h
> | 157 --
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilicon
> PolicyUpdateLibFsp/PeiPchPolicyUpdate.h | 28
> -
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilicon
> PolicyUpdateLibFsp/PeiSaPolicyUpdate.h | 30
> -
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/N1xxWUId.h
> | 13 -
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xxW
> UInitLib.h |
> 42 -
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPolicy
> UpdateLib/DxeGopPolicyInit.h | 39 -
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPolicy
> UpdateLib/DxeSaPolicyInit.h | 64 -
> Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/AcpiGnvsInit.c
> | 95 -
> Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c
> | 307 ----
> Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/UpdateDsdt.c
> | 776 --------
> Platform/Intel/ClevoOpenBoardPkg/Features/PciHotPlug/PciHotPlug.c
> | 351 ----
>
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib/Dx
> eTbtPolicyLib.c | 160 --
>
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTbtCom
> monLib/TbtCommonLib.c |
> 315 ----
>
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/Pei
> TbtPolicyLib.c | 204 ---
>
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/Private/PeiDTbtInit
> Lib/PeiDTbtInitLib.c | 566 ------
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtDxe.c
> | 228 ---
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiTbtInit.c
> | 193 --
>
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmiHandl
> er.c |
> 1610 -----------------
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.c
> | 1764 ------------------
>
> Platform/Intel/ClevoOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGpio
> ExpanderLib.c |
> 306 ----
>
> Platform/Intel/ClevoOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cAccessLib.c
> | 115 --
>
> Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSeria
> lPortLibSpiFlash.c | 320 ----
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilicon
> PolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.c | 103 --
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilicon
> PolicyUpdateLibFsp/PcieDeviceTable.c | 115
> --
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilicon
> PolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c | 87
> -
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilicon
> PolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c | 186
> --
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilicon
> PolicyUpdateLibFsp/PeiPchPolicyUpdate.c | 153
> --
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilicon
> PolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c |
> 248 ---
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilicon
> PolicyUpdateLibFsp/PeiSaPolicyUpdate.c | 84
> -
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilicon
> PolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c |
> 75 -
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BasePlatformHookLib/
> BasePlatformHookLib.c |
> 662 -------
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeBoar
> dAcpiTableLib.c |
> 36 -
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeMulti
> BoardAcpiSupportLib.c |
> 43 -
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeN1xx
> WUAcpiTableLib.c |
> 74 -
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmBoa
> rdAcpiEnableLib.c |
> 62 -
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmMul
> tiBoardAcpiSupportLib.c |
> 81 -
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmN1x
> xWUAcpiEnableLib.c |
> 39 -
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmSilic
> onAcpiEnableLib.c |
> 168 --
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxWUG
> pioTable.c |
> 370 ----
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxWUH
> daVerbTables.c |
> 232 ---
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxWUH
> sioPtssTables.c |
> 105 --
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxWUS
> pdTable.c |
> 426 -----
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoardI
> nitPostMemLib.c |
> 39 -
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoardI
> nitPreMemLib.c |
> 105 --
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMultiB
> oardInitPostMemLib.c |
> 40 -
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMultiB
> oardInitPreMemLib.c |
> 82 -
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xxW
> UDetect.c |
> 66 -
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xxW
> UInitPostMemLib.c |
> 209 ---
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xxW
> UInitPreMemLib.c |
> 236 ---
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platform/Intel/MinPla
> tformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c | 640 -------
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPolicy
> UpdateLib/DxeGopPolicyInit.c | 175
> --
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPolicy
> UpdateLib/DxeSaPolicyUpdate.c | 65
> -
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPolicy
> UpdateLib/DxeSiliconPolicyUpdateLib.c | 54 -
> Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/ALS.ASL
> | 37 -
> Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl
> | 21 -
> Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/CPU.asl
> | 246 ---
> Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.ASL
> | 121 --
> Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl
> | 850 ---------
> Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.asl
> | 33 -
> Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/LPC_DEV.ASL
> | 199 --
> Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/LpcB.asl
> | 88 -
> Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PCI_DRC.ASL
> | 116 --
> Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciTree.asl
> | 306 ----
> Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl
> | 1129 ------------
>
> Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGnvs.a
> sl |
> 8 -
> Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Video.asl
> | 27 -
>
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/AcpiTables/Rtd3SptPcieTbt.
> asl |
> 403 -----
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/AcpiTables/Tbt.asl
> | 1894 --------------------
> Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Acpi/TbtNvs.asl
> | 56 -
> Platform/Intel/ClevoOpenBoardPkg/Include/Acpi/GlobalNvs.asl
> | 114 --
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/build_config.cfg
> | 33 -
> 124 files changed, 23595 deletions(-)
>
> diff --git a/Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec
> b/Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec
> deleted file mode 100644
> index 28aedfef59..0000000000
> --- a/Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec
> +++ /dev/null
> @@ -1,305 +0,0 @@
> -## @file
> -# Clevo board declaration file.
> -#
> -# The DEC files are used by the utilities that parse DSC and
> -# INF files to generate AutoGen.c and AutoGen.h files
> -# for the build infrastructure.
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -##
> -[Defines]
> -DEC_SPECIFICATION = 0x00010017
> -PACKAGE_NAME = OpenBoardPkg
> -PACKAGE_VERSION = 0.1
> -PACKAGE_GUID = D04CCA80-5F71-478D-9A26-72BC751D0106
> -
> -[Includes]
> -Include
> -N1xxWU/Include
> -Features/Tbt/Include
> -
> -[Guids]
> -gBoardModuleTokenSpaceGuid = {0x72d1fff7, 0xa42a,
> 0x4219, {0xb9, 0x95, 0x5a, 0x67, 0x53, 0x6e, 0xa4, 0x2a}}
> -gTianoLogoGuid = {0x7BB28B99, 0x61BB,
> 0x11D5, {0x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}}
> -gSpiFlashDebugHobGuid = {0xcaaaf418, 0x38a5,
> 0x4d49, {0xbe, 0x74, 0xe6, 0x06, 0xe4, 0x02, 0x6d, 0x25}}
> -gTbtInfoHobGuid = {0x74a81eaa, 0x033c,
> 0x4783, {0xbe, 0x2b, 0x84, 0x85, 0x74, 0xa6, 0x97, 0xb7}}
> -gPlatformModuleTokenSpaceGuid = {0x69d13bf0, 0xaf91,
> 0x4d96, {0xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0}}
> -
> -[Protocols]
> -gTbtNvsAreaProtocolGuid = {0x4d6a54d1, 0xcd56, 0x47f3,
> {0x93, 0x6e, 0x7e, 0x51, 0xd9, 0x31, 0x15, 0x4f}}
> -gDxeTbtPolicyProtocolGuid = {0x196bf9e3, 0x20d7, 0x4b7b,
> {0x89, 0xf9, 0x31, 0xc2, 0x72, 0x08, 0xc9, 0xb9}}
> -
> -[Ppis]
> -gPeiTbtPolicyPpiGuid = {0xd7e7e1e6, 0xcbec, 0x4f5f,
> {0xae, 0xd3, 0xfd, 0xc0, 0xa8, 0xb0, 0x7e, 0x25}}
> -gPeiTbtPolicyBoardInitDonePpiGuid = {0x970f9c60, 0x8547, 0x49d7,
> { 0xa4, 0xb, 0x1e, 0xc4, 0xbc, 0x4e, 0xe8, 0x9b}}
> -
> -[LibraryClasses]
> -
> -[PcdsFixedAtBuild, PcdsPatchableInModule]
> -
> -[PcdsFixedAtBuild]
> -
> -gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange|0x0010|UINT16|0x1
> 0001004
> -gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding|0x3c03|UINT16|0x
> 10001005
> -
> -gBoardModuleTokenSpaceGuid.PcdLpcSioIndexPort|0x4e|UINT16|0x900000
> 18
> -gBoardModuleTokenSpaceGuid.PcdLpcSioDataPort|0x4f|UINT16|0x9000001
> F
> -
> -gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort|0x164E|UINT16
> |0x9000001C
> -gBoardModuleTokenSpaceGuid.PcdSioBaseAddress|0x0680|UINT16|0x9000
> 001D
> -
> -gBoardModuleTokenSpaceGuid.PcdLpcSioIndexDefaultPort|0x164E|UINT16|
> 0x90000021
> -gBoardModuleTokenSpaceGuid.PcdLpcSioDataDefaultPort|0x164F|UINT16|0
> x90000022
> -
> -## Tbt SW_SMI_DTBT_ENUMERATEgSetupVariableGuid
> -gBoardModuleTokenSpaceGuid.PcdSwSmiDTbtEnumerate|0xF7|UINT8|0x00
> 0000110
> -
> -gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition|0x01|UINT8|0x90
> 000015
> -
> -gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageBase|0x00000000
> |UINT32|0x90000030
> -gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageSize|0x00000000|
> UINT32|0x90000031
> -gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageOffset|0x0000000
> 0|UINT32|0x90000032
> -
> -[PcdsDynamic]
> -
> -# Board GPIO Table
> -gBoardModuleTokenSpaceGuid.PcdBoardGpioTable|0|UINT32|0x00000040
> -gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize|0|UINT16|0x00000
> 041
> -gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2|0|UINT32|0x00000042
> -gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2Size|0|UINT16|0x0000
> 0043
> -gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem|0|UINT32|0x00
> 0000113
> -gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMemSize|0|UINT16|
> 0x000000114
> -
> -# Board Expander GPIO Table
> -gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable|0|UINT32|0x000000
> 44
> -gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize|0|UINT16|0x000
> 00045
> -gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable2|0|UINT32|0x00000
> 046
> -gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable2Size|0|UINT16|0x00
> 000047
> -
> -# TouchPanel & SDHC CD GPIO Table
> -gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel|0|UINT32|0
> x00000048
> -
> -# PCH-LP HSIO PTSS Table
> -gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1|0|UINT32|0x0
> 000004A
> -gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2|0|UINT32|0x0
> 000004B
> -gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size|0|UINT16|
> 0x0000004C
> -gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size|0|UINT16|
> 0x0000004D
> -gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1|0|UINT32|0x00
> 00004E
> -gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2|0|UINT32|0x00
> 00004F
> -gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size|0|UINT16|
> 0x00000050
> -gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size|0|UINT16|
> 0x00000051
> -
> -# PCH-H HSIO PTSS Table
> -gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1|0|UINT32|0x00
> 000052
> -gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2|0|UINT32|0x00
> 000053
> -gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size|0|UINT16|
> 0x00000054
> -gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size|0|UINT16|
> 0x00000055
> -gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1|0|UINT32|0x00
> 000056
> -gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2|0|UINT32|0x00
> 000057
> -gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size|0|UINT16|0
> x00000058
> -gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size|0|UINT16|0
> x00000059
> -
> -# HDA Verb Table
> -gBoardModuleTokenSpaceGuid.PcdHdaVerbTable|0|UINT32|0x0000005A
> -gBoardModuleTokenSpaceGuid.PcdHdaVerbTable2|0|UINT32|0x0000005B
> -gBoardModuleTokenSpaceGuid.PcdExtHdaVerbTable|0|UINT32|0x0000005C
> -gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable1|0|UINT32|0x00
> 00005D
> -gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable2|0|UINT32|0x00
> 00005E
> -gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable3|0|UINT32|0x00
> 00005F
> -gBoardModuleTokenSpaceGuid.PcdDisplayAudioHdaVerbTable|0|UINT32|0x
> 00000060
> -
> -# SA Misc Configuration
> -gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd|0|UINT8|0x00000066
> -gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment|0|UINT16|
> 0x00000067
> -gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit|0|UINT16|0x00000101
> -
> -# DRAM Configuration
> -gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor|0|UINT32|0x000000
> 68
> -gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget|0|UINT32|0x00000069
> -gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap|0|UINT32|0x0000006A
> -gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize|0|UINT16|0x000000
> 6B
> -gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram|0|UINT32|0x000
> 0006C
> -gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize|0|UINT16|0x
> 0000006D
> -gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl|FALSE|BO
> OLEAN|0x0000006E
> -gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved|FALSE|BOOLEAN|
> 0x0000006F
> -gBoardModuleTokenSpaceGuid.PcdMrcSpdData|0|UINT32|0x00000070
> -gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize|0|UINT16|0x00000071
> -
> -# PEG RESET GPIO
> -gBoardModuleTokenSpaceGuid.PcdPegGpioResetControl|FALSE|BOOLEAN|0
> x00000072
> -gBoardModuleTokenSpaceGuid.PcdPegGpioResetSupoort|FALSE|BOOLEAN|
> 0x00000073
> -gBoardModuleTokenSpaceGuid.PcdPegResetGpioPad|0|UINT32|0x0000007
> 4
> -gBoardModuleTokenSpaceGuid.PcdPegResetGpioActive|FALSE|BOOLEAN|0x
> 00000075
> -gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo|0|UINT32|0x0000007
> 9
> -gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo|0|UINT8|0x00
> 00007A
> -gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo|0|UINT32|0x00000
> 07B
> -gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive|FALSE|BOOLEAN|0x
> 0000007C
> -gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo|0|UINT8|0x
> 0000007D
> -gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo|0|UINT32|0x00
> 00007E
> -gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive|FALSE|BOOLEAN|
> 0x0000007F
> -
> -# SPD Address Table
> -gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0|0|UINT8|0x00000
> 099
> -gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1|0|UINT8|0x00000
> 09A
> -gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2|0|UINT8|0x00000
> 09B
> -gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3|0|UINT8|0x00000
> 09C
> -
> -# CA Vref Configuration
> -gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig|0|UINT8|0x0000009D
> -
> -# Root Port Clock Info
> -gBoardModuleTokenSpaceGuid.PcdRootPort0ClkInfo|0|UINT64|0x0000009E
> -gBoardModuleTokenSpaceGuid.PcdRootPort1ClkInfo|0|UINT64|0x0000009F
> -gBoardModuleTokenSpaceGuid.PcdRootPort2ClkInfo|0|UINT64|0x000000A0
> -gBoardModuleTokenSpaceGuid.PcdRootPort3ClkInfo|0|UINT64|0x000000A1
> -gBoardModuleTokenSpaceGuid.PcdRootPort4ClkInfo|0|UINT64|0x000000A2
> -gBoardModuleTokenSpaceGuid.PcdRootPort5ClkInfo|0|UINT64|0x000000A3
> -gBoardModuleTokenSpaceGuid.PcdRootPort6ClkInfo|0|UINT64|0x000000A4
> -gBoardModuleTokenSpaceGuid.PcdRootPort7ClkInfo|0|UINT64|0x000000A5
> -gBoardModuleTokenSpaceGuid.PcdRootPort8ClkInfo|0|UINT64|0x000000A6
> -gBoardModuleTokenSpaceGuid.PcdRootPort9ClkInfo|0|UINT64|0x000000A7
> -gBoardModuleTokenSpaceGuid.PcdRootPort10ClkInfo|0|UINT64|0x000000A
> 8
> -gBoardModuleTokenSpaceGuid.PcdRootPort11ClkInfo|0|UINT64|0x000000A
> 9
> -gBoardModuleTokenSpaceGuid.PcdRootPort12ClkInfo|0|UINT64|0x000000A
> A
> -gBoardModuleTokenSpaceGuid.PcdRootPort13ClkInfo|0|UINT64|0x000000A
> B
> -gBoardModuleTokenSpaceGuid.PcdRootPort14ClkInfo|0|UINT64|0x000000A
> C
> -gBoardModuleTokenSpaceGuid.PcdRootPort15ClkInfo|0|UINT64|0x000000A
> D
> -gBoardModuleTokenSpaceGuid.PcdRootPort16ClkInfo|0|UINT64|0x000000A
> E
> -gBoardModuleTokenSpaceGuid.PcdRootPort17ClkInfo|0|UINT64|0x000000A
> F
> -gBoardModuleTokenSpaceGuid.PcdRootPort18ClkInfo|0|UINT64|0x000000B
> 0
> -gBoardModuleTokenSpaceGuid.PcdRootPort19ClkInfo|0|UINT64|0x000000B
> 1
> -gBoardModuleTokenSpaceGuid.PcdRootPort20ClkInfo|0|UINT64|0x000000B
> 2
> -gBoardModuleTokenSpaceGuid.PcdRootPort21ClkInfo|0|UINT64|0x000000B
> 3
> -gBoardModuleTokenSpaceGuid.PcdRootPort22ClkInfo|0|UINT64|0x000000B
> 4
> -gBoardModuleTokenSpaceGuid.PcdRootPort23ClkInfo|0|UINT64|0x000000B
> 5
> -gBoardModuleTokenSpaceGuid.PcdRootPort24ClkInfo|0|UINT64|0x000000B
> 6
> -gBoardModuleTokenSpaceGuid.PcdRootPort25ClkInfo|0|UINT64|0x000000B
> 7
> -gBoardModuleTokenSpaceGuid.PcdRootPort26ClkInfo|0|UINT64|0x000000B
> 8
> -gBoardModuleTokenSpaceGuid.PcdRootPort27ClkInfo|0|UINT64|0x000000B
> 9
> -gBoardModuleTokenSpaceGuid.PcdRootPort28ClkInfo|0|UINT64|0x000000B
> A
> -gBoardModuleTokenSpaceGuid.PcdRootPort29ClkInfo|0|UINT64|0x000000B
> B
> -gBoardModuleTokenSpaceGuid.PcdRootPort30ClkInfo|0|UINT64|0x000000B
> C
> -gBoardModuleTokenSpaceGuid.PcdRootPort31ClkInfo|0|UINT64|0x000000B
> D
> -gBoardModuleTokenSpaceGuid.PcdRootPortLanClkInfo|0|UINT64|0x000000
> BE
> -
> -# USB 2.0 Port AFE
> -gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe|0|UINT32|0x000000BF
> -gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe|0|UINT32|0x000000C0
> -gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe|0|UINT32|0x000000C1
> -gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe|0|UINT32|0x000000C2
> -gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe|0|UINT32|0x000000C3
> -gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe|0|UINT32|0x000000C4
> -gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe|0|UINT32|0x000000C5
> -gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe|0|UINT32|0x000000C6
> -gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe|0|UINT32|0x000000C7
> -gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe|0|UINT32|0x000000C8
> -gBoardModuleTokenSpaceGuid.PcdUsb20Port10Afe|0|UINT32|0x000000C9
> -gBoardModuleTokenSpaceGuid.PcdUsb20Port11Afe|0|UINT32|0x000000CA
> -gBoardModuleTokenSpaceGuid.PcdUsb20Port12Afe|0|UINT32|0x000000CB
> -gBoardModuleTokenSpaceGuid.PcdUsb20Port13Afe|0|UINT32|0x000000CC
> -gBoardModuleTokenSpaceGuid.PcdUsb20Port14Afe|0|UINT32|0x000000CD
> -gBoardModuleTokenSpaceGuid.PcdUsb20Port15Afe|0|UINT32|0x000000CE
> -
> -# USB 2.0 Port Over Current Pin
> -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0|0|UINT8|0x
> 000000CF
> -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1|0|UINT8|0x
> 000000D0
> -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2|0|UINT8|0x
> 000000D1
> -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3|0|UINT8|0x
> 000000D2
> -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4|0|UINT8|0x
> 000000D3
> -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5|0|UINT8|0x
> 000000D4
> -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6|0|UINT8|0x
> 000000D5
> -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7|0|UINT8|0x
> 000000D6
> -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8|0|UINT8|0x
> 000000D7
> -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9|0|UINT8|0x
> 000000D8
> -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10|0|UINT8|0
> x000000D9
> -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11|0|UINT8|0
> x000000DA
> -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12|0|UINT8|0
> x000000DB
> -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13|0|UINT8|0
> x000000DC
> -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort14|0|UINT8|0
> x000000DD
> -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort15|0|UINT8|0
> x000000DE
> -
> -# USB 3.0 Port Over Current Pin
> -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0|0|UINT8|0x
> 000000DF
> -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1|0|UINT8|0x
> 000000E0
> -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2|0|UINT8|0x
> 000000E1
> -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3|0|UINT8|0x
> 000000E2
> -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4|0|UINT8|0x
> 000000E3
> -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5|0|UINT8|0x
> 000000E4
> -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort6|0|UINT8|0x
> 000000E5
> -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort7|0|UINT8|0x
> 000000E6
> -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort8|0|UINT8|0x
> 000000E7
> -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort9|0|UINT8|0x
> 000000E8
> -
> -# TBT
> -gBoardModuleTokenSpaceGuid.PcdDTbtBootOn |0|UINT8|0x000000E9
> -gBoardModuleTokenSpaceGuid.PcdDTbtUsbOn |0|UINT8|0x000000EA
> -gBoardModuleTokenSpaceGuid.PcdDTbtGpio3ForcePwr
> |0|UINT8|0x000000EB
> -gBoardModuleTokenSpaceGuid.PcdDTbtGpio3ForcePwrDly
> |0|UINT16|0x000000ED
> -gBoardModuleTokenSpaceGuid.PcdDTbtControllerEn |0|UINT8|0x000000EE
> -gBoardModuleTokenSpaceGuid.PcdDTbtControllerType
> |0|UINT8|0x000000EF
> -gBoardModuleTokenSpaceGuid.PcdDTbtPcieRpNumber
> |0|UINT8|0x000000F0
> -gBoardModuleTokenSpaceGuid.PcdDTbtGpioAccessType
> |0|UINT8|0x000000F1
> -gBoardModuleTokenSpaceGuid.PcdExpander |0|UINT8|0x000000F2
> -gBoardModuleTokenSpaceGuid.PcdDTbtGpioLevel |0|BOOLEAN|0x000000F3
> -gBoardModuleTokenSpaceGuid.PcdDTbtForcepowerGpioPad
> |0|UINT32|0x000000F4
> -gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad
> |0|UINT32|0x000000F5
> -gBoardModuleTokenSpaceGuid.PcdDTbtAcpiGpeSignature
> |0|UINT32|0x000000F6
> -gBoardModuleTokenSpaceGuid.PcdDTbtAcpiGpeSignaturePorting
> |0|BOOLEAN|0x000000F7
> -gBoardModuleTokenSpaceGuid.PcdDTbtSecurityMode
> |0|UINT8|0x000000F8
> -gBoardModuleTokenSpaceGuid.PcdDTbtGpio5Filter |0|UINT8|0x000000F9
> -gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport
> |0|UINT8|0x000000FA
> -gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI |0|UINT8|0x000000FB
> -gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify |0|UINT8|0x000000FC
> -gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq|0|UINT8|0x000000FD
> -gBoardModuleTokenSpaceGuid.PcdDTbtAspm |0|UINT8|0x000000FE
> -gBoardModuleTokenSpaceGuid.PcdDTbtLtr | 0 | UINT8| 0x00000116
> -gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch |0|UINT8|0x000000FF
> -gBoardModuleTokenSpaceGuid.PcdRtd3Tbt |0|UINT8|0x00000100
> -gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq |0|UINT8|0x0000010A
> -gBoardModuleTokenSpaceGuid.PcdDTbtWin10Support
> |0|UINT8|0x000000102
> -gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReqDelay
> |0|UINT16|0x00000103
> -gBoardModuleTokenSpaceGuid.PcdRtd3TbtOffDelay |0|UINT16|0x00000104
> -gBoardModuleTokenSpaceGuid.PcdDTbtPcieExtraBusRsvd
> |0|UINT8|0x00000105
> -gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemRsvd
> |0|UINT16|0x00000106
> -gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax
> |0|UINT8|0x00000107
> -gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd
> |0|UINT16|0x00000108
> -gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax
> |0|UINT8|0x00000109
> -gBoardModuleTokenSpaceGuid.PcdPchPcieRootPortHpe|0|UINT32|0x00000
> 117
> -
> -# UCMC GPIO Table
> -gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTable|0|UINT32|0x0000
> 00111
> -gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize|0|UINT16|0x0
> 00000112
> -
> -# Misc
> -gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent|FALSE|BOOLEAN|0x0
> 00000EC
> -
> -gBoardModuleTokenSpaceGuid.PcdPs2KbMsEnable|1|UINT8|0x40000009
> -gBoardModuleTokenSpaceGuid.PcdAcpiSleepState|1|UINT8|0x40000002
> -gBoardModuleTokenSpaceGuid.PcdAcpiHibernate|1|UINT8|0x40000003
> -gBoardModuleTokenSpaceGuid.PcdLowPowerS0Idle|0|UINT8|0x40000004
> -gBoardModuleTokenSpaceGuid.PcdPciExpNative|0|UINT8|0x40000005
> -gBoardModuleTokenSpaceGuid.PcdNativeAspmEnable|1|UINT8|0x4000000
> 6
> -gBoardModuleTokenSpaceGuid.PcdDisableActiveTripPoints|1|UINT8|0x400
> 0000A
> -gBoardModuleTokenSpaceGuid.PcdDisablePassiveTripPoints|0|UINT8|0x400
> 0000B
> -gBoardModuleTokenSpaceGuid.PcdDisableCriticalTripPoints|1|UINT8|0x400
> 0000C
> -# 0: Type-C
> -# 1: Stacked-Jack
> -gBoardModuleTokenSpaceGuid.PcdAudioConnector|0|UINT8|0x40000012
> -gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress|0|UINT64|0x40000013
> -gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid|{0x22, 0x61, 0xd4,
> 0x4a, 0xeb, 0xff, 0x52, 0x4a, 0xbf, 0xb0, 0x51, 0x8c, 0xfc, 0xa0, 0x2d,
> 0xb0}|VOID*|0x40000014
> -
> -[PcdsDynamicEx]
> -
> -[PcdsDynamic, PcdsDynamicEx]
> -
> -[PcdsPatchableInModule]
> -
> -[PcdsFeatureFlag]
> - gBoardModuleTokenSpaceGuid.PcdIntelGopEnable
> |TRUE|BOOLEAN|0xF0000062
> -
> - gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport
> |TRUE|BOOLEAN|0xF0000000
> -
> - gBoardModuleTokenSpaceGuid.PcdTbtEnable
> |FALSE|BOOLEAN|0x000000115
> diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc
> deleted file mode 100644
> index 516685c514..0000000000
> --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc
> +++ /dev/null
> @@ -1,385 +0,0 @@
> -## @file
> -# Clevo N1xxWU board description file.
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -##
> -[Defines]
> - #
> - # Set platform specific package/folder name, same as passed from
> PREBUILD script.
> - # PLATFORM_PACKAGE would be the same as PLATFORM_NAME as well
> as package build folder
> - # DEFINE only takes effect at R9 DSC and FDF.
> - #
> - DEFINE PLATFORM_PACKAGE = MinPlatformPkg
> - DEFINE PLATFORM_SI_PACKAGE = KabylakeSiliconPkg
> - DEFINE PLATFORM_SI_BIN_PACKAGE =
> KabylakeSiliconBinPkg
> - DEFINE PLATFORM_FSP_BIN_PACKAGE =
> KabylakeFspBinPkg
> - DEFINE PLATFORM_BOARD_PACKAGE =
> ClevoOpenBoardPkg
> - DEFINE BOARD = N1xxWU
> - DEFINE PROJECT =
> $(PLATFORM_BOARD_PACKAGE)/$(BOARD)
> -
> - #
> - # Platform On/Off features are defined here
> - #
> - !include OpenBoardPkgConfig.dsc
> -
> -###############################################################
> #################
> -#
> -# Defines Section - statements that will be processed to create a Makefile.
> -#
> -###############################################################
> #################
> -[Defines]
> - PLATFORM_NAME = $(PLATFORM_PACKAGE)
> - PLATFORM_GUID =
> 7324F33D-4E96-4F8B-A550-544DE6162AB7
> - PLATFORM_VERSION = 0.1
> - DSC_SPECIFICATION = 0x00010005
> - OUTPUT_DIRECTORY = Build/$(PROJECT)
> - SUPPORTED_ARCHITECTURES = IA32|X64
> - BUILD_TARGETS = DEBUG|RELEASE
> - SKUID_IDENTIFIER = ALL
> -
> -
> - FLASH_DEFINITION =
> $(PROJECT)/OpenBoardPkg.fdf
> -
> - FIX_LOAD_TOP_MEMORY_ADDRESS = 0x0
> - DEFINE TOP_MEMORY_ADDRESS = 0x0
> -
> - #
> - # Default value for OpenBoardPkg.fdf use
> - #
> - DEFINE BIOS_SIZE_OPTION = SIZE_60
> -
> -###############################################################
> #################
> -#
> -# SKU Identification section - list of all SKU IDs supported by this
> -# Platform.
> -#
> -###############################################################
> #################
> -[SkuIds]
> - 0|DEFAULT # The entry: 0|DEFAULT is reserved and
> always required.
> - 0x60|N1xxWU
> -
> -###############################################################
> #################
> -#
> -# Library Class section - list of all Library Classes needed by this Platform.
> -#
> -###############################################################
> #################
> -
> -!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc
> -!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc
> -!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc
> -
> -[LibraryClasses.common]
> -
> - PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf
> -
> ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/Pei
> ReportFvLib.inf
> -
> -
> PciHostBridgeLib|$(PLATFORM_PACKAGE)/Pci/Library/PciHostBridgeLibSimple
> /PciHostBridgeLibSimple.inf
> -
> PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSim
> ple/PciSegmentInfoLibSimple.inf
> -
> PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformB
> ootManagerLib/DxePlatformBootManagerLib.inf
> -
> I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cA
> ccessLib.inf
> -
> GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpande
> rLib/BaseGpioExpanderLib.inf
> -
> -
> PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHo
> okLib.inf
> -
> -
> FspWrapperHobProcessLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiF
> spWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf
> -
> PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapper
> PlatformSecLib/SecFspWrapperPlatformSecLib.inf
> -
> -
> FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/Bas
> eFspWrapperApiLib.inf
> -
> FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestL
> ib/PeiFspWrapperApiTestLib.inf
> -
> -
> FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFsp
> WrapperPlatformLib/PeiFspWrapperPlatformLib.inf
> -
> SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitLib
> Fsp/PeiSiliconPolicyInitLibFsp.inf
> -
> SiliconPolicyUpdateLib|$(PROJECT)/FspWrapper/Library/PeiSiliconPolicyUpda
> teLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
> -
> -
> ConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseConfigBlockLib/BaseC
> onfigBlockLib.inf
> -
> SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/SiliconInitLib/SiliconInitLib.i
> nf
> -
> -
> BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/BoardInitLibNull/B
> oardInitLibNull.inf
> -
> TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNu
> ll/TestPointCheckLibNull.inf
> -
> -# Tbt
> -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
> -
> TbtCommonLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiDx
> eSmmTbtCommonLib/TbtCommonLib.inf
> -
> DxeTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/DxeTb
> tPolicyLib/DxeTbtPolicyLib.inf
> -!endif
> -#
> -# Silicon Init Package
> -#
> -!include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc
> -
> -[LibraryClasses.IA32.SEC]
> -
> SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.in
> f
> - DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
> -
> TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/S
> ecTestPointCheckLib.inf
> -
> SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLi
> bNull/SecBoardInitLibNull.inf
> -
> -[LibraryClasses.IA32]
> - #
> - # PEI phase common
> - #
> -
> SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.in
> f
> -
> DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxe
> DebugLibReportStatusCode.inf
> -
> FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFsp
> WrapperPlatformLib/PeiFspWrapperPlatformLib.inf
> -!if $(TARGET) == DEBUG
> -
> TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/P
> eiTestPointCheckLib.inf
> -!endif
> -
> TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointLi
> b.inf
> -
> MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/Mult
> iBoardInitSupportLib/PeiMultiBoardInitSupportLib.inf
> -
> BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSup
> portLib/PeiMultiBoardInitSupportLib.inf
> -
> -# Tbt
> -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
> -
> PeiTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiTbt
> PolicyLib/PeiTbtPolicyLib.inf
> -
> PeiDTbtInitLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Private/
> PeiDTbtInitLib/PeiDTbtInitLib.inf
> -!endif
> -#
> -# Silicon Init Package
> -#
> -!include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc
> -
> -[LibraryClasses.X64]
> - #
> - # DXE phase common
> - #
> -
> FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/DxeFsp
> WrapperPlatformLib/DxeFspWrapperPlatformLib.inf
> -!if $(TARGET) == DEBUG
> -
> TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/D
> xeTestPointCheckLib.inf
> -!endif
> -
> TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPointL
> ib.inf
> -
> MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/Mult
> iBoardInitSupportLib/DxeMultiBoardInitSupportLib.inf
> -
> BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSup
> portLib/DxeMultiBoardInitSupportLib.inf
> -
> MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoard
> AcpiSupportLib/DxeMultiBoardAcpiSupportLib.inf
> -
> BoardAcpiTableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSup
> portLib/DxeMultiBoardAcpiSupportLib.inf
> -
> -
> SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/DxeSiliconPolicyInitLib
> /DxeSiliconPolicyInitLib.inf
> -
> SiliconPolicyUpdateLib|$(PROJECT)/Policy/Library/DxeSiliconPolicyUpdateLib/
> DxeSiliconPolicyUpdateLib.inf
> -
> -#
> -# Silicon Init Package
> -#
> -!include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc
> -
> -[LibraryClasses.X64.DXE_SMM_DRIVER]
> -
> SpiFlashCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/SmmSpiFlashCo
> mmonLib/SmmSpiFlashCommonLib.inf
> -!if $(TARGET) == DEBUG
> -
> TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/S
> mmTestPointCheckLib.inf
> -!endif
> -
> TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestPoin
> tLib.inf
> -
> MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoard
> AcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf
> -
> BoardAcpiEnableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSu
> pportLib/SmmMultiBoardAcpiSupportLib.inf
> -
> -[LibraryClasses.X64.DXE_RUNTIME_DRIVER]
> -
> ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeResetSys
> temLib/DxeRuntimeResetSystemLib.inf
> -
> -!include OpenBoardPkgPcd.dsc
> -
> -[Components.IA32]
> -
> -#
> -# Common
> -#
> -!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc
> -
> - #
> - # Core
> - #
> -
> MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf
> {
> - <LibraryClasses>
> - DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
> - }
> -
> - #
> - # FSP wrapper SEC Core
> - #
> - UefiCpuPkg/SecCore/SecCore.inf {
> - <LibraryClasses>
> - #PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> - PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> - }
> -
> -#
> -# Silicon
> -#
> -!include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc
> -
> -#
> -# Platform
> -#
> - $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
> -
> $(PROJECT)/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformIn
> itPei/PlatformInitPreMem.inf {
> - <LibraryClasses>
> -!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport == FALSE
> -
> BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
> -!else
> -
> NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
> -!endif
> - }
> - IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf {
> - <LibraryClasses>
> -
> SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitLib
> Dependency/PeiPreMemSiliconPolicyInitLibDependency.inf
> - }
> -
> $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMe
> m.inf{
> - <LibraryClasses>
> - # #
> - # Hook a library constructor to update some policy fields when policy
> installed.
> - #
> -
> NULL|$(PROJECT)/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemS
> iliconPolicyNotifyLib.inf
> - }
> -
> -
> $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.in
> f {
> - <LibraryClasses>
> -!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport == FALSE
> -
> BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
> -!else
> -
> NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
> -!endif
> - }
> -
> - IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf {
> - <LibraryClasses>
> -
> SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitLib
> Dependency/PeiPostMemSiliconPolicyInitLibDependency.inf
> - }
> -
> $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMe
> m.inf
> -
> -#
> -# Security
> -#
> -
> -!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
> - $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf
> -!endif
> -
> - IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf
> -
> IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSam
> plePei.inf
> -
> -# Tbt
> -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
> - $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf
> -!endif
> -
> -[Components.X64]
> -
> -#
> -# Common
> -#
> -!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc
> -
> - UefiCpuPkg/CpuDxe/CpuDxe.inf
> - MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
> -
> - MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
> - MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
> - MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> -
> MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.
> inf
> - MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
> -
> - #
> - # Shell
> - #
> - ShellPkg/Application/Shell/Shell.inf {
> - <PcdsFixedAtBuild>
> - gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
> - <LibraryClasses>
> -
> NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comma
> ndsLib.inf
> -
> NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comma
> ndsLib.inf
> -
> NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comma
> ndsLib.inf
> -
> NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Comm
> andsLib.inf
> -
> NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1Comm
> andsLib.inf
> -
> NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Com
> mandsLib.inf
> -
> NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1C
> ommandsLib.inf
> -
> NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2C
> ommandsLib.inf
> -
> ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComma
> ndLib.inf
> -
> HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingL
> ib.inf
> -
> BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgC
> ommandLib.inf
> -
> ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
> - ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
> - }
> -
> -#
> -# Silicon
> -#
> -!include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc
> -
> -# Tbt
> -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
> - $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf
> - $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf
> - $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf
> -!endif
> -
> -#
> -# Platform
> -#
> - $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf
> - $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
> - IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf
> -
> -
> $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig
> .inf
> -
> - $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf
> - $(PLATFORM_PACKAGE)/Test/TestPointDumpApp/TestPointDumpApp.inf
> -
> -#
> -# OS Boot
> -#
> -!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
> - $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf {
> - <LibraryClasses>
> -!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport == FALSE
> -
> BoardAcpiTableLib|$(PROJECT)/Library/BoardAcpiLib/DxeBoardAcpiTableLib.i
> nf
> -!else
> -
> NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf
> -!endif
> - }
> - $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf {
> - <LibraryClasses>
> -!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport == FALSE
> -
> BoardAcpiTableLib|$(PROJECT)/Library/BoardAcpiLib/DxeBoardAcpiTableLib.i
> nf
> -!else
> -
> NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf
> -!endif
> - }
> - $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf {
> - <LibraryClasses>
> -!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport == FALSE
> -
> BoardAcpiEnableLib|$(PROJECT)/Library/BoardAcpiLib/SmmBoardAcpiEnabl
> eLib.inf
> -!else
> -
> NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
> -!endif
> - }
> -
> - $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
> -
> $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
> -
> - UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf {
> - <PcdsPatchableInModule>
> - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80080046
> - <LibraryClasses>
> -!if $(TARGET) == DEBUG
> -
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.i
> nf
> -!endif
> - }
> -
> -!endif
> -
> -#
> -# Security
> -#
> - $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf
> -
> -!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
> - $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
> -!endif
> -
> - IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf
> -
> -#
> -# Other
> -#
> - $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf
> -
> -!include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc
> -!include OpenBoardPkgBuildOption.dsc
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgBuildOption.d
> sc
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgBuildOption.d
> sc
> deleted file mode 100644
> index 31e7f41c65..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgBuildOption.d
> sc
> +++ /dev/null
> @@ -1,151 +0,0 @@
> -## @file
> -# Clevo N1xxWU board build option configuration.
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -##
> -
> -[BuildOptions]
> -# Define Build Options both for EDK and EDKII drivers.
> -
> -
> - DEFINE DSC_S3_BUILD_OPTIONS =
> -
> - DEFINE DSC_CSM_BUILD_OPTIONS =
> -
> -!if gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE
> - DEFINE DSC_ACPI_BUILD_OPTIONS = -DACPI_SUPPORT=1
> -!else
> - DEFINE DSC_ACPI_BUILD_OPTIONS =
> -!endif
> -
> - DEFINE BIOS_GUARD_BUILD_OPTIONS =
> -
> - DEFINE OVERCLOCKING_BUILD_OPTION =
> -
> - DEFINE FSP_BINARY_BUILD_OPTIONS =
> -
> - DEFINE FSP_WRAPPER_BUILD_OPTIONS = -DFSP_WRAPPER_FLAG
> -
> - DEFINE SKIP_FSP_TEMPRAM_INIT_AND_EXIT_OPTIONS =
> -
> - DEFINE RESTRICTED_OPTION =
> -
> -
> - DEFINE SV_BUILD_OPTIONS =
> -
> - DEFINE TEST_MENU_BUILD_OPTION =
> -
> -!if gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable == FALSE
> - DEFINE OPTIMIZE_DISABLE_OPTIONS = -Od -GL-
> -!else
> - DEFINE OPTIMIZE_DISABLE_OPTIONS =
> -!endif
> -
> - DEFINE UP_SERVER_SUPPORT_BUILD_OPTIONS =
> -
> -
> - DEFINE TPM_BUILD_OPTION =
> -
> - DEFINE TPM2_BUILD_OPTION =
> -
> - DEFINE DSC_TBT_BUILD_OPTIONS =
> -
> - DEFINE DSC_DCTT_BUILD_OPTIONS =
> -
> - DEFINE EMB_BUILD_OPTIONS =
> -
> - DEFINE DSC_MEMORY_DOWN_BUILD_OPTIONS = -DMEM_DOWN_FLAG=1
> -
> - DEFINE DSC_KBCEMUL_BUILD_OPTIONS =
> -
> - DEFINE BOOT_GUARD_BUILD_OPTIONS =
> -
> - DEFINE SECURE_BOOT_BUILD_OPTIONS =
> -
> - DEFINE USBTYPEC_BUILD_OPTION =
> -
> - DEFINE CAPSULE_BUILD_OPTIONS =
> -
> - DEFINE PERFORMANCE_BUILD_OPTION =
> -
> - DEFINE DEBUGUSEUSB_BUILD_OPTION =
> -
> - DEFINE DISABLE_NEW_DEPRECATED_INTERFACES_BUILD_OPTION =
> -DDISABLE_NEW_DEPRECATED_INTERFACES=1
> -
> - DEFINE SINITBIN_BUILD_OPTION =
> -
> - DEFINE MINTREE_FLAG_BUILD_OPTION = -DMINTREE_FLAG=1
> -
> -DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =
> $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OVERCLOCKING_BUILD_OPTION)
> $(PERFORMANCE_BUILD_OPTION) $(EMB_BUILD_OPTIONS)
> $(BIOS_GUARD_BUILD_OPTIONS) $(DSC_TBT_BUILD_OPTIONS)
> -DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(BOOT_GUARD_BUILD_OPTIONS)
> $(DSC_MEMORY_DOWN_BUILD_OPTIONS) $(DEBUGUSEUSB_BUILD_OPTION)
> $(DSC_S3_BUILD_OPTIONS)
> -DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(FSP_BINARY_BUILD_OPTIONS)
> $(FSP_WRAPPER_BUILD_OPTIONS)
> $(SKIP_FSP_TEMPRAM_INIT_AND_EXIT_OPTIONS)
> -DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(DSC_KBCEMUL_BUILD_OPTIONS)
> $(CAPSULE_BUILD_OPTIONS) $(SECURE_BOOT_BUILD_OPTIONS)
> $(DSC_CSM_BUILD_OPTIONS)
> $(DISABLE_NEW_DEPRECATED_INTERFACES_BUILD_OPTION)
> -DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(TPM2_BUILD_OPTION)
> $(TPM_BUILD_OPTION) $(DSC_DCTT_BUILD_OPTIONS)
> -DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(DSC_ACPI_BUILD_OPTIONS)
> $(UP_SERVER_SUPPORT_BUILD_OPTIONS) $(USBTYPEC_BUILD_OPTION)
> $(SINITBIN_BUILD_OPTION) $(MINTREE_FLAG_BUILD_OPTION)
> -
> -[BuildOptions.Common.EDKII]
> -
> -#
> -# For IA32 Global Build Flag
> -#
> - *_*_IA32_CC_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D
> PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI
> - *_*_IA32_VFRPP_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> - *_*_IA32_APP_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> - *_*_IA32_ASLPP_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> - *_*_IA32_ASLCC_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> - *_*_IA32_NASM_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> -
> -#
> -# For IA32 Specific Build Flag
> -#
> -GCC: *_*_IA32_PP_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> -GCC: *_*_IA32_CC_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D
> PI_SPECIFICATION_VERSION=0x00010015 -Wno-unused
> -Wl,--allow-multiple-definition
> -MSFT: *_*_IA32_ASM_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> -MSFT: *_*_IA32_CC_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D
> PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI
> -MSFT: *_*_IA32_VFRPP_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
> -MSFT: *_*_IA32_APP_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
> -MSFT: *_*_IA32_ASLPP_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
> -MSFT: *_*_IA32_ASLCC_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
> -
> -#
> -# For X64 Global Build Flag
> -#
> - *_*_X64_CC_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D
> PI_SPECIFICATION_VERSION=0x00010015
> - *_*_X64_VFRPP_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> - *_*_X64_APP_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> - *_*_X64_ASLPP_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> - *_*_X64_ASLCC_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> - *_*_X64_NASM_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> -
> -
> -#
> -# For X64 Specific Build Flag
> -#
> -GCC: *_*_X64_PP_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> -GCC: *_*_X64_CC_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D
> PI_SPECIFICATION_VERSION=0x00010015 -Wno-unused
> -Wl,--allow-multiple-definition
> -MSFT: *_*_X64_ASM_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> -MSFT: *_*_X64_CC_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D
> PI_SPECIFICATION_VERSION=0x00010015
> -MSFT: *_*_X64_VFRPP_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
> -MSFT: *_*_X64_APP_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
> -MSFT: *_*_X64_ASLPP_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> -MSFT: *_*_X64_ASLCC_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> -
> -
> -# Force PE/COFF sections to be aligned at 4KB boundaries to support page
> level protection
> -[BuildOptions.common.EDKII.DXE_SMM_DRIVER,
> BuildOptions.common.EDKII.SMM_CORE]
> - MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
> - GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
> -
> -# Force PE/COFF sections to be aligned at 4KB boundaries to support
> MemoryAttribute table
> -[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
> - MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
> - GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
> -
> -# Force PE/COFF sections to be aligned at 4KB boundaries to support NX
> protection
> -[BuildOptions.common.EDKII.DXE_DRIVER,
> BuildOptions.common.EDKII.DXE_CORE,
> BuildOptions.common.EDKII.UEFI_DRIVER,
> BuildOptions.common.EDKII.UEFI_APPLICATION]
> - #MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
> - #GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgConfig.dsc
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgConfig.dsc
> deleted file mode 100644
> index ea759776fb..0000000000
> --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgConfig.dsc
> +++ /dev/null
> @@ -1,132 +0,0 @@
> -## @file
> -# Clevo N1xxWU board configuration.
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -##
> -
> -[PcdsFixedAtBuild]
> - #
> - # Please select BootStage here.
> - # Stage 1 - enable debug (system deadloop after debug init)
> - # Stage 2 - mem init (system deadloop after mem init)
> - # Stage 3 - boot to shell only
> - # Stage 4 - boot to OS
> - # Stage 5 - boot to OS with security boot enabled
> - #
> - gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4
> -
> -[PcdsFeatureFlag]
> - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
> - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
> - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
> - gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE
> - gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE
> -
> -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 1
> - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE
> -!endif
> -
> -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 2
> - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
> - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE
> -!endif
> -
> -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 3
> - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
> - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE
> -!endif
> -
> -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 4
> - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
> -!endif
> -
> -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5
> - gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE
> - gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE
> -!endif
> -
> - gBoardModuleTokenSpaceGuid.PcdTbtEnable|FALSE
> - #
> - # More fine granularity control below:
> - #
> - gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport|TRUE
> -
> -#
> -# TRUE is ENABLE. FALSE is DISABLE.
> -#
> -
> -#
> -# BIOS build switches configuration
> -#
> - gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE
> -
> -# CPU
> - gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE
> - gSiPkgTokenSpaceGuid.PcdTxtEnable|TRUE #Set to FALSE for GCC Build
> @todo Convert TXT ASM to NASM
> - gSiPkgTokenSpaceGuid.PcdBiosGuardEnable|TRUE
> -
> -# SA
> - gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE
> - gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE
> - gSiPkgTokenSpaceGuid.PcdSgEnable|TRUE
> - gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE
> - gSiPkgTokenSpaceGuid.PcdSkycamEnable|TRUE
> - gSiPkgTokenSpaceGuid.PcdGmmEnable|TRUE
> - gSiPkgTokenSpaceGuid.PcdSaOcEnable|TRUE
> - gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE
> - gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE
> -
> -# ME
> - gSiPkgTokenSpaceGuid.PcdAmtEnable|TRUE
> - gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE
> - gSiPkgTokenSpaceGuid.PcdPttEnable|TRUE
> - gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE
> -
> - gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE
> - gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE
> - gSiPkgTokenSpaceGuid.PcdBootGuardEnable|TRUE
> - gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE
> - gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE
> - gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE
> - gSiPkgTokenSpaceGuid.PcdEvLoaderEnable|FALSE
> - gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE
> - gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE
> - gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE
> - gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE
> - gSiPkgTokenSpaceGuid.PcdSerialGpioEnable|TRUE
> - gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE
> - gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE
> - gSiPkgTokenSpaceGuid.PcdSoftwareGuardEnable|TRUE
> - gSiPkgTokenSpaceGuid.PcdSsaFlagEnable|FALSE
> - gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE
> - gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE
> -
> -#
> -# Override some PCDs for specific build requirements.
> -#
> - #
> - # Disable USB debug message when Source Level Debug is enabled
> - # because they cannot be enabled at the same time.
> - #
> -
> - gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE
> - gSiPkgTokenSpaceGuid.PcdTxtEnable|FALSE
> - gSiPkgTokenSpaceGuid.PcdTxtEnable|FALSE
> -
> - !if $(TARGET) == DEBUG
> - gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE
> - !else
> - gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE
> - !endif
> -
> - !if $(TARGET) == DEBUG
> - gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE
> - !else
> - gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE
> - !endif
> -
> - gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc
> deleted file mode 100644
> index 83cbd18557..0000000000
> --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc
> +++ /dev/null
> @@ -1,265 +0,0 @@
> -## @file
> -# Clevo N1xxWU board PCD configuration.
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -##
> -
> -###############################################################
> #################
> -#
> -# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> -#
> -###############################################################
> #################
> -[PcdsFeatureFlag.common]
> - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
> -
> gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSection
> First|FALSE
> -!if $(TARGET) == RELEASE
> - gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
> -!else
> - gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
> -!endif
> - gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
> -
> - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE
> -
> - gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
> -
> -[PcdsFixedAtBuild.common]
> - gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
> -
> -!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
> - gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
> -
> gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140
> -!endif
> -
> -!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable == TRUE
> -
> gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1
> -!endif
> -
> - gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
> - gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
> - gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1
> -
> - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
> - gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|0x10000000
> - gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000
> - gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
> - gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000
> - gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
> -
> - gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize |
> 0x00026000
> -
> - gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000
> - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000
> - gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800
> -
> gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x40
> 0
> -
> - gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
> - gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE
> - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
> -!if $(TARGET) == RELEASE
> - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
> - gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
> -!else
> - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
> -
> gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALS
> E
> - gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
> -!endif
> -
> gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(T
> OP_MEMORY_ADDRESS)
> - gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0
> - gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01
> - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000
> -
> -
> gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|TR
> UE
> -
> - #
> - # 8MB Default
> - #
> - gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000
> -
> - #
> - # 16MB TSEG in Debug build only.
> - #
> - !if $(TARGET) == DEBUG
> - gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000
> - !endif
> -
> - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0x0
> - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|0x1F
> - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2
> - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x44
> - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80
> - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x40
> - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x1800
> - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08
> - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC
> -
> - !if $(TARGET) == RELEASE
> -
> gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402
> - !else
> -
> gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188
> B
> - !endif
> -
> - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b
> - !if $(TARGET) == RELEASE
> - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70
> - !else
> - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0
> - !endif
> -
> - #
> - # FSP Base address PCD will be updated in FDF basing on flash map.
> - #
> - gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0
> - gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0
> -
> - ## Specifies max supported number of Logical Processors.
> - # @Prompt Configure max supported number of Logical Processorss
> - gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|12
> -
> - ## Specifies the size of the microcode Region.
> - # @Prompt Microcode Region size.
> - gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0
> -
> - ## Specifies timeout value in microseconds for the BSP to detect all APs
> for the first time.
> - # @Prompt Timeout for the BSP to detect all APs for the first time.
> - gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000
> -
> - ## Specifies the AP wait loop state during POST phase.
> - # The value is defined as below.
> - # 1: Place AP in the Hlt-Loop state.
> - # 2: Place AP in the Mwait-Loop state.
> - # 3: Place AP in the Run-Loop state.
> - # @Prompt The AP wait loop state.
> - gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
> -
> - #
> - # The PCDs are used to control the Windows SMM Security Mitigations
> Table - Protection Flags
> - #
> - # BIT0: If set, expresses that for all synchronous SMM entries,SMM will
> validate that input and output buffers lie entirely within the expected fixed
> memory regions.
> - # BIT1: If set, expresses that for all synchronous SMM entries, SMM will
> validate that input and output pointers embedded within the fixed
> communication buffer only refer to address ranges \
> - # that lie entirely within the expected fixed memory regions.
> - # BIT2: Firmware setting this bit is an indication that it will not allow
> reconfiguration of system resources via non-architectural mechanisms.
> - # BIT3-31: Reserved
> - #
> - gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07
> -
> - #
> - # See HstiFeatureBit.h for the definition
> - #
> - gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2
> - gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
> -
> -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 1
> - gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03,
> 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00}
> -!endif
> -
> -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 2
> - gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03,
> 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00}
> -!endif
> -
> -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 3
> - gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03,
> 0x07, 0x03, 0x05, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00}
> -!endif
> -
> -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 4
> - gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03,
> 0x07, 0x03, 0x05, 0x1F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00}
> -!endif
> -
> -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 5
> - gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03,
> 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00}
> -!endif
> -
> -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 6
> - gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03,
> 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00}
> -!endif
> -
> -[PcdsFixedAtBuild.IA32]
> - gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
> - gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148
> - gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000
> - gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000
> -
> -[PcdsFixedAtBuild.X64]
> - # Default platform supported RFC 4646 languages: (American) English
> -
> gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-
> US"
> -
> -[PcdsPatchableInModule.common]
> - gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208
> -
> - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
> -
> -!if $(TARGET) == DEBUG
> - gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1
> -!endif
> -
> -[PcdsDynamicHii.X64.DEFAULT]
> -
> gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGloba
> lVariableGuid|0x0|5 # Variable: L"Timeout"
> -
> gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupp
> ort"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
> -
> -!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
> -
> gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGloba
> lVariableGuid|0x0|1 # Variable: L"Timeout"
> -!endif
> -
> -[PcdsDynamicDefault]
> - #
> - # FSP Base address PCD will be updated in FDF basing on flash map.
> - #
> - gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0
> - # Platform will pre-allocate UPD buffer and pass it to FspWrapper
> - # Those dummy address will be patched before FspWrapper executing
> - gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0xFFFFFFFF
> - gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0xFFFFFFFF
> -
> -[PcdsDynamicDefault.common.DEFAULT]
> - gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0
> - gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0
> - gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE
> - gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE
> - #
> - # Set video to native resolution as Windows 8 WHCK requirement.
> - #
> - gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x0
> - gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x0
> -
> -
> gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0
> -
> -[PcdsDynamicDefault.common.DEFAULT]
> - # gEfiTpmDeviceInstanceTpm20DtpmGuid
> - gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x5a, 0xf2, 0x6b,
> 0x28, 0xc3, 0xc2, 0x8c, 0x40, 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17}
> - gEfiSecurityPkgTokenSpaceGuid.PcdTcg2HashAlgorithmBitmap|0
> - gEfiSecurityPkgTokenSpaceGuid.PcdTpm2HashMask|0x0000001F
> - gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|1
> -
> - # Tbt
> - gBoardModuleTokenSpaceGuid.PcdDTbtControllerEn | 0x1
> - gBoardModuleTokenSpaceGuid.PcdDTbtControllerType | 0x1
> - gBoardModuleTokenSpaceGuid.PcdDTbtPcieRpNumber | 0x1
> - gBoardModuleTokenSpaceGuid.PcdDTbtGpioAccessType | 0x2
> - gBoardModuleTokenSpaceGuid.PcdExpander | 0x0
> - gBoardModuleTokenSpaceGuid.PcdDTbtGpioLevel | 0x1
> - gBoardModuleTokenSpaceGuid.PcdDTbtForcepowerGpioPad | 13
> - gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad |
> 0x02010011
> - gBoardModuleTokenSpaceGuid.PcdDTbtAcpiGpeSignature | 0
> - gBoardModuleTokenSpaceGuid.PcdDTbtAcpiGpeSignaturePorting | 0
> - gBoardModuleTokenSpaceGuid.PcdDTbtSecurityMode | 0x1
> - #gBoardModuleTokenSpaceGuid.PcdDTbtGpio5Filter | 0x0
> - gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport | 0x0
> - gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI | 0x1
> - gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify | 0x1
> - gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq| 0x1
> - gBoardModuleTokenSpaceGuid.PcdDTbtAspm | 0x0
> - gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch | 0x0
> - gBoardModuleTokenSpaceGuid.PcdRtd3Tbt | 0x1
> - gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq | 0x1
> - gBoardModuleTokenSpaceGuid.PcdDTbtWin10Support | 0x0
> - gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReqDelay | 0x0
> - gBoardModuleTokenSpaceGuid.PcdRtd3TbtOffDelay | 5000
> - gBoardModuleTokenSpaceGuid.PcdDTbtPcieExtraBusRsvd | 56
> - gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemRsvd | 100
> - gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax | 26
> - gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd | 100
> - gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax | 28
> - gBoardModuleTokenSpaceGuid.PcdPchPcieRootPortHpe| 0x00000001
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclud
> e.fdf
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclud
> e.fdf
> deleted file mode 100644
> index d48f8c7a2a..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclud
> e.fdf
> +++ /dev/null
> @@ -1,48 +0,0 @@
> -## @file
> -# Flash map layout file for the Clevo N1xxWU board.
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -##
> -
> -#==============================================================
> ===================#
> -# 6 M BIOS - for FSP wrapper
> -#==============================================================
> ===================#
> -DEFINE FLASH_BASE
> = 0xFFA20000 #
> -DEFINE FLASH_SIZE
> = 0x005E0000 #
> -DEFINE FLASH_BLOCK_SIZE
> = 0x00010000 #
> -DEFINE FLASH_NUM_BLOCKS
> = 0x0000005E #
> -#==============================================================
> ===================#
> -
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset
> = 0x00000000 # Flash addr (0xFFA20000)
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize
> = 0x00040000 #
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset =
> 0x00000000 # Flash addr (0xFFA20000)
> -SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
> = 0x0001E000 #
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset
> = 0x0001E000 # Flash addr (0xFFA3E000)
> -SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> = 0x00002000 #
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset
> = 0x00020000 # Flash addr (0xFFA40000)
> -SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> = 0x00020000 #
> -SET gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageOffset
> = 0x00040000 # Flash addr (0xFFA60000)
> -SET gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageSize
> = 0x00010000 #
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset
> = 0x00050000 # Flash addr (0xFFA70000)
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
> = 0x00060000 #
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset =
> 0x000B0000 # Flash addr (0xFFAD0000)
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize =
> 0x00070000 #
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset
> = 0x00120000 # Flash addr (0xFFB40000)
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
> = 0x00090000 #
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset
> = 0x001B0000 # Flash addr (0xFFBD0000)
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
> = 0x00140000 #
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset
> = 0x002F0000 # Flash addr (0xFFD10000)
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
> = 0x000B0000 #
> -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
> = 0x003A0000 # Flash addr (0xFFDC0000)
> -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
> = 0x000A0000 #
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset
> = 0x00440000 # Flash addr (0xFFE60000)
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
> = 0x00060000 #
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset
> = 0x004A0000 # Flash addr (0xFFEC0000)
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
> = 0x000BC000 #
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset
> = 0x0055C000 # Flash addr (0xFFF7C000)
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
> = 0x00004000 #
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset
> = 0x00560000 # Flash addr (0xFFF80000)
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
> = 0x00080000 #
> diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf
> deleted file mode 100644
> index c21ffbc4ca..0000000000
> --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf
> +++ /dev/null
> @@ -1,716 +0,0 @@
> -## @file
> -# Clevo N1xxWU board flash file.
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -##
> -
> -[Defines]
> - !include $(PROJECT)/Include/Fdf/FlashMapInclude.fdf
> -
> -###############################################################
> #################
> -#
> -# FD Section
> -# The [FD] Section is made up of the definition statements and a
> -# description of what goes into the Flash Device Image. Each FD section
> -# defines one flash "device" image. A flash device image may be one of
> -# the following: Removable media bootable image (like a boot floppy
> -# image,) an Option ROM image (that would be "flashed" into an add-in
> -# card,) a System "Flash" image (that would be burned into a system's
> -# flash) or an Update ("Capsule") image that will be used to update and
> -# existing system flash.
> -#
> -###############################################################
> #################
> -[FD.N1xxWU]
> -#
> -# FD Tokens, BaseAddress, Size, ErasePolarity, BlockSize, and NumBlocks,
> cannot be
> -# assigned with PCD values. Instead, it uses the definitions for its variety,
> which
> -# are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and
> FLASH_NUM_BLOCKS.
> -#
> -BaseAddress = $(FLASH_BASE) |
> gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress #The base address
> of the FLASH Device.
> -Size = $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdFlashAreaSize
> #The size in bytes of the FLASH Device
> -ErasePolarity = 1
> -BlockSize = $(FLASH_BLOCK_SIZE)
> -NumBlocks = $(FLASH_NUM_BLOCKS)
> -
> -DEFINE SIPKG_DXE_SMM_BIN = INF
> -DEFINE SIPKG_PEI_BIN = INF
> -
> -# Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase,
> because macro expression is not supported.
> -# So, PlatformSecLib uses PcdFlashAreaBaseAddress +
> PcdNemCodeCacheBase to get the real CodeCache base address.
> -SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase =
> $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset)
> -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =
> $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) +
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
> -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
> -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60
> -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress =
> $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) +
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset = 0x60
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =
> gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =
> gSiPkgTokenSpaceGuid.PcdFlashAreaSize
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =
> $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) +
> $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset)
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =
> $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) +
> $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset)
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =
> $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) +
> $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset)
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =
> gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =
> gSiPkgTokenSpaceGuid.PcdFlashAreaSize
> -###############################################################
> #################
> -#
> -# Following are lists of FD Region layout which correspond to the locations
> of different
> -# images within the flash device.
> -#
> -# Regions must be defined in ascending order and may not overlap.
> -#
> -# A Layout Region start with a eight digit hex offset (leading "0x" required)
> followed by
> -# the pipe "|" character, followed by the size of the region, also in hex with
> the leading
> -# "0x" characters. Like:
> -# Offset|Size
> -# PcdOffsetCName|PcdSizeCName
> -# RegionType <FV, DATA, or FILE>
> -# Fv Size can be adjusted
> -#
> -###############################################################
> #################
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMde
> ModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
> -gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMd
> eModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
> -#NV_VARIABLE_STORE
> -DATA = {
> - ## This is the EFI_FIRMWARE_VOLUME_HEADER
> - # ZeroVector []
> - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> - # FileSystemGuid
> - 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
> - 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
> - # FvLength: 0x40000
> - 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
> - #Signature "_FVH" #Attributes
> - 0x5F, 0x46, 0x56, 0x48, 0xFF, 0xFE, 0x04, 0x00,
> - #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
> - #
> - # Be careful on CheckSum field.
> - #
> - 0x48, 0x00, 0x32, 0x09, 0x00, 0x00, 0x00, 0x02,
> - #Blockmap[0]: 4 Blocks 0x10000 Bytes / Block
> - 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
> - #Blockmap[1]: End
> - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> - ## This is the VARIABLE_STORE_HEADER
> -!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE
> - # Signature: gEfiAuthenticatedVariableGuid = { 0xaaf32c78, 0x947b,
> 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
> - 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
> - 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
> -!else
> - # Signature: gEfiVariableGuid = { 0xddcf3616, 0x3275, 0x4164, { 0x98,
> 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
> - 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
> - 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
> -!endif
> - #Size: 0x1E000
> (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48
> (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x1DFB8
> - # This can speed up the Variable Dispatch a bit.
> - 0xB8, 0xDF, 0x01, 0x00,
> - #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1:
> UINT32
> - 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> -}
> -
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfi
> MdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> -gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfi
> MdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> -#NV_FTW_WORKING
> -DATA = {
> - # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =
> gEdkiiWorkingBlockSignatureGuid =
> - # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f,
> 0x1b, 0x95 }}
> - 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
> - 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
> - # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1,
> Reserved
> - 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
> - # WriteQueueSize: UINT64
> - 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> -}
> -
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMd
> eModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> -gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiM
> deModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> -#NV_FTW_SPARE
> -
> -gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageOffset|gBoardMo
> duleTokenSpaceGuid.PcdFlashNvDebugMessageSize
> -gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageBase|gBoardMod
> uleTokenSpaceGuid.PcdFlashNvDebugMessageSize
> -#DEBUG_MESSAGE_AREA
> -
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatform
> PkgTokenSpaceGuid.PcdFlashFvAdvancedSize
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformPk
> gTokenSpaceGuid.PcdFlashFvAdvancedSize
> -FV = FvAdvanced
> -
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPk
> gTokenSpaceGuid.PcdFlashFvSecuritySize
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformPkgT
> okenSpaceGuid.PcdFlashFvSecuritySize
> -FV = FvSecurity
> -
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkg
> TokenSpaceGuid.PcdFlashFvOsBootSize
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|gMinPlatformPkgT
> okenSpaceGuid.PcdFlashFvOsBootSize
> -FV = FvOsBoot
> -
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformP
> kgTokenSpaceGuid.PcdFlashFvUefiBootSize
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformPkg
> TokenSpaceGuid.PcdFlashFvUefiBootSize
> -FV = FvUefiBoot
> -
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatfor
> mPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatfor
> mPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
> -FV = FvPostMemory
> -
> -gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.P
> cdFlashMicrocodeFvSize
> -gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.Pc
> dFlashMicrocodeFvSize
> -#Microcode
> -FV = FvMicrocode
> -
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTo
> kenSpaceGuid.PcdFlashFvFspSSize
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgToke
> nSpaceGuid.PcdFlashFvFspSSize
> -# FSP_S Section
> -FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_S.fd
> -
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgT
> okenSpaceGuid.PcdFlashFvFspMSize
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkgTok
> enSpaceGuid.PcdFlashFvFspMSize
> -# FSP_M Section
> -FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_M.fd
> -
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTo
> kenSpaceGuid.PcdFlashFvFspTSize
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|gMinPlatformPkgTok
> enSpaceGuid.PcdFlashFvFspTSize
> -# FSP_T Section
> -FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_T.fd
> -
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatfor
> mPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatform
> PkgTokenSpaceGuid.PcdFlashFvPreMemorySize
> -FV = FvPreMemory
> -
> -###############################################################
> #################
> -#
> -# FV Section
> -#
> -# [FV] section is used to define what components or modules are placed
> within a flash
> -# device file. This section also defines order the components and modules
> are positioned
> -# within the image. The [FV] section consists of define statements, set
> statements and
> -# module statements.
> -#
> -###############################################################
> #################
> -[FV.FvMicrocode]
> -BlockSize = $(FLASH_BLOCK_SIZE)
> -FvAlignment = 16
> -ERASE_POLARITY = 1
> -MEMORY_MAPPED = TRUE
> -STICKY_WRITE = TRUE
> -LOCK_CAP = TRUE
> -LOCK_STATUS = FALSE
> -WRITE_DISABLED_CAP = TRUE
> -WRITE_ENABLED_CAP = TRUE
> -WRITE_STATUS = TRUE
> -WRITE_LOCK_CAP = TRUE
> -WRITE_LOCK_STATUS = TRUE
> -READ_DISABLED_CAP = TRUE
> -READ_ENABLED_CAP = TRUE
> -READ_STATUS = FALSE
> -READ_LOCK_CAP = TRUE
> -READ_LOCK_STATUS = TRUE
> -
> -INF RuleOverride = MICROCODE
> $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf
> -
> -[FV.FvPreMemory]
> -BlockSize = $(FLASH_BLOCK_SIZE)
> -FvAlignment = 16
> -ERASE_POLARITY = 1
> -MEMORY_MAPPED = TRUE
> -STICKY_WRITE = TRUE
> -LOCK_CAP = TRUE
> -LOCK_STATUS = TRUE
> -WRITE_DISABLED_CAP = TRUE
> -WRITE_ENABLED_CAP = TRUE
> -WRITE_STATUS = TRUE
> -WRITE_LOCK_CAP = TRUE
> -WRITE_LOCK_STATUS = TRUE
> -READ_DISABLED_CAP = TRUE
> -READ_ENABLED_CAP = TRUE
> -READ_STATUS = TRUE
> -READ_LOCK_CAP = TRUE
> -READ_LOCK_STATUS = TRUE
> -FvNameGuid = FC8FE6B5-CD9B-411E-BD8F-31824D0CDE3D
> -
> -INF UefiCpuPkg/SecCore/SecCore.inf
> -INF MdeModulePkg/Core/Pei/PeiMain.inf
> -!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf
> -
> -INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
> -INF
> $(PROJECT)/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformIn
> itPei/PlatformInitPreMem.inf
> -INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
> -INF
> $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMe
> m.inf
> -
> -[FV.FvPostMemoryUncompact]
> -BlockSize = $(FLASH_BLOCK_SIZE)
> -FvAlignment = 16
> -ERASE_POLARITY = 1
> -MEMORY_MAPPED = TRUE
> -STICKY_WRITE = TRUE
> -LOCK_CAP = TRUE
> -LOCK_STATUS = TRUE
> -WRITE_DISABLED_CAP = TRUE
> -WRITE_ENABLED_CAP = TRUE
> -WRITE_STATUS = TRUE
> -WRITE_LOCK_CAP = TRUE
> -WRITE_LOCK_STATUS = TRUE
> -READ_DISABLED_CAP = TRUE
> -READ_ENABLED_CAP = TRUE
> -READ_STATUS = TRUE
> -READ_LOCK_CAP = TRUE
> -READ_LOCK_STATUS = TRUE
> -FvNameGuid = 7C4DCFC6-AECA-4707-85B9-FD4B2EEA49E7
> -
> -!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePostMemoryInclude.fdf
> -
> -# Init Board Config PCD
> -INF
> $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.in
> f
> -INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
> -INF
> $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMe
> m.inf
> -
> -!if gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable == TRUE
> -FILE FREEFORM = 4ad46122-ffeb-4a52-bfb0-518cfca02db0 {
> - SECTION RAW = N1xxWU/Gop/Vbt.bin
> - SECTION UI = "Vbt"
> -}
> -FILE FREEFORM = 7BB28B99-61BB-11D5-9A5D-0090273FC14D {
> - SECTION RAW = MdeModulePkg/Logo/Logo.bmp
> -}
> -!endif # PcdPeiDisplayEnable
> -
> -[FV.FvPostMemory]
> -BlockSize = $(FLASH_BLOCK_SIZE)
> -FvAlignment = 16
> -ERASE_POLARITY = 1
> -MEMORY_MAPPED = TRUE
> -STICKY_WRITE = TRUE
> -LOCK_CAP = TRUE
> -LOCK_STATUS = TRUE
> -WRITE_DISABLED_CAP = TRUE
> -WRITE_ENABLED_CAP = TRUE
> -WRITE_STATUS = TRUE
> -WRITE_LOCK_CAP = TRUE
> -WRITE_LOCK_STATUS = TRUE
> -READ_DISABLED_CAP = TRUE
> -READ_ENABLED_CAP = TRUE
> -READ_STATUS = TRUE
> -READ_LOCK_CAP = TRUE
> -READ_LOCK_STATUS = TRUE
> -FvNameGuid = 9DFE49DB-8EF0-4D9C-B273-0036144DE917
> -
> -FILE FV_IMAGE = 244FAAF4-FAE1-4892-8B7D-7EF84CBFA709 {
> - SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF
> PROCESSING_REQUIRED = TRUE {
> - SECTION FV_IMAGE = FvPostMemoryUncompact
> - }
> -}
> -
> -[FV.FvUefiBootUncompact]
> -BlockSize = $(FLASH_BLOCK_SIZE)
> -FvAlignment = 16
> -ERASE_POLARITY = 1
> -MEMORY_MAPPED = TRUE
> -STICKY_WRITE = TRUE
> -LOCK_CAP = TRUE
> -LOCK_STATUS = TRUE
> -WRITE_DISABLED_CAP = TRUE
> -WRITE_ENABLED_CAP = TRUE
> -WRITE_STATUS = TRUE
> -WRITE_LOCK_CAP = TRUE
> -WRITE_LOCK_STATUS = TRUE
> -READ_DISABLED_CAP = TRUE
> -READ_ENABLED_CAP = TRUE
> -READ_STATUS = TRUE
> -READ_LOCK_CAP = TRUE
> -READ_LOCK_STATUS = TRUE
> -FvNameGuid = A881D567-6CB0-4eee-8435-2E72D33E45B5
> -
> -!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreUefiBootInclude.fdf
> -
> -INF UefiCpuPkg/CpuDxe/CpuDxe.inf
> -INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
> -
> -INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
> -INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
> -INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> -INF
> MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.
> inf
> -INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
> -
> -INF ShellPkg/Application/Shell/Shell.inf
> -
> -INF
> $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
> -INF IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf
> -
> -INF $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf
> -
> -[FV.FvUefiBoot]
> -BlockSize = $(FLASH_BLOCK_SIZE)
> -FvAlignment = 16
> -ERASE_POLARITY = 1
> -MEMORY_MAPPED = TRUE
> -STICKY_WRITE = TRUE
> -LOCK_CAP = TRUE
> -LOCK_STATUS = TRUE
> -WRITE_DISABLED_CAP = TRUE
> -WRITE_ENABLED_CAP = TRUE
> -WRITE_STATUS = TRUE
> -WRITE_LOCK_CAP = TRUE
> -WRITE_LOCK_STATUS = TRUE
> -READ_DISABLED_CAP = TRUE
> -READ_ENABLED_CAP = TRUE
> -READ_STATUS = TRUE
> -READ_LOCK_CAP = TRUE
> -READ_LOCK_STATUS = TRUE
> -FvNameGuid = 0496D33D-EA79-495C-B65D-ABF607184E3B
> -
> -FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
> - SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF
> PROCESSING_REQUIRED = TRUE {
> - SECTION FV_IMAGE = FvUefiBootUncompact
> - }
> - }
> -
> -[FV.FvOsBootUncompact]
> -BlockSize = $(FLASH_BLOCK_SIZE)
> -FvAlignment = 16
> -ERASE_POLARITY = 1
> -MEMORY_MAPPED = TRUE
> -STICKY_WRITE = TRUE
> -LOCK_CAP = TRUE
> -LOCK_STATUS = TRUE
> -WRITE_DISABLED_CAP = TRUE
> -WRITE_ENABLED_CAP = TRUE
> -WRITE_STATUS = TRUE
> -WRITE_LOCK_CAP = TRUE
> -WRITE_LOCK_STATUS = TRUE
> -READ_DISABLED_CAP = TRUE
> -READ_ENABLED_CAP = TRUE
> -READ_STATUS = TRUE
> -READ_LOCK_CAP = TRUE
> -READ_LOCK_STATUS = TRUE
> -FvNameGuid = A0F04529-B715-44C6-BCA4-2DEBDD01EEEC
> -
> -!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf
> -
> -INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
> -
> -!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
> -INF
> $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf
> -INF
> $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
> -INF $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
> -
> -INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf
> -INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf
> -
> -INF RuleOverride = DRIVER_ACPITABLE
> $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
> -
> -INF
> $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig
> .inf
> -
> -!endif
> -
> -[FV.FvLateSilicon]
> -BlockSize = $(FLASH_BLOCK_SIZE)
> -FvAlignment = 16
> -ERASE_POLARITY = 1
> -MEMORY_MAPPED = TRUE
> -STICKY_WRITE = TRUE
> -LOCK_CAP = TRUE
> -LOCK_STATUS = TRUE
> -WRITE_DISABLED_CAP = TRUE
> -WRITE_ENABLED_CAP = TRUE
> -WRITE_STATUS = TRUE
> -WRITE_LOCK_CAP = TRUE
> -WRITE_LOCK_STATUS = TRUE
> -READ_DISABLED_CAP = TRUE
> -READ_ENABLED_CAP = TRUE
> -READ_STATUS = TRUE
> -READ_LOCK_CAP = TRUE
> -READ_LOCK_STATUS = TRUE
> -FvNameGuid = 97F09B89-9E83-4DDC-A3D1-10C4AF539D1E
> -
> -!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
> -$(SIPKG_DXE_SMM_BIN)
> $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxe.inf
> -$(SIPKG_DXE_SMM_BIN)
> $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf
> -
> -$(SIPKG_DXE_SMM_BIN)
> $(PLATFORM_SI_PACKAGE)/SystemAgent/SmmAccess/Dxe/SmmAccess.inf
> -
> -$(SIPKG_DXE_SMM_BIN)
> $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSmiDispatcher.inf
> -$(SIPKG_DXE_SMM_BIN)
> $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmControl.inf
> -$(SIPKG_DXE_SMM_BIN)
> $(PLATFORM_SI_PACKAGE)/Pch/Spi/Smm/PchSpiSmm.inf
> -$(SIPKG_DXE_SMM_BIN)
> $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Smm/PchInitSmm.inf
> -
> -INF RuleOverride = ACPITABLE
> $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaAcpiTables.inf
> -INF RuleOverride = ACPITABLE
> $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf
> -
> -!endif
> -
> -[FV.FvOsBoot]
> -BlockSize = $(FLASH_BLOCK_SIZE)
> -FvAlignment = 16
> -ERASE_POLARITY = 1
> -MEMORY_MAPPED = TRUE
> -STICKY_WRITE = TRUE
> -LOCK_CAP = TRUE
> -LOCK_STATUS = TRUE
> -WRITE_DISABLED_CAP = TRUE
> -WRITE_ENABLED_CAP = TRUE
> -WRITE_STATUS = TRUE
> -WRITE_LOCK_CAP = TRUE
> -WRITE_LOCK_STATUS = TRUE
> -READ_DISABLED_CAP = TRUE
> -READ_ENABLED_CAP = TRUE
> -READ_STATUS = TRUE
> -READ_LOCK_CAP = TRUE
> -READ_LOCK_STATUS = TRUE
> -FvNameGuid = 13BF8810-75FD-4B1A-91E6-E16C4201F80A
> -
> -FILE FV_IMAGE = B9020753-84A8-4BB6-947C-CE7D41F5CE39 {
> - SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF
> PROCESSING_REQUIRED = TRUE {
> - SECTION FV_IMAGE = FvOsBootUncompact
> - }
> - }
> -
> -FILE FV_IMAGE = D4632741-510C-44E3-BE21-C3D6D7881485 {
> - SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF
> PROCESSING_REQUIRED = TRUE {
> - SECTION FV_IMAGE = FvLateSilicon
> - }
> - }
> -
> -[FV.FvSecurityPreMemory]
> -BlockSize = $(FLASH_BLOCK_SIZE)
> -FvAlignment = 16 #FV alignment and FV attributes
> setting.
> -ERASE_POLARITY = 1
> -MEMORY_MAPPED = TRUE
> -STICKY_WRITE = TRUE
> -LOCK_CAP = TRUE
> -LOCK_STATUS = TRUE
> -WRITE_DISABLED_CAP = TRUE
> -WRITE_ENABLED_CAP = TRUE
> -WRITE_STATUS = TRUE
> -WRITE_LOCK_CAP = TRUE
> -WRITE_LOCK_STATUS = TRUE
> -READ_DISABLED_CAP = TRUE
> -READ_ENABLED_CAP = TRUE
> -READ_STATUS = TRUE
> -READ_LOCK_CAP = TRUE
> -READ_LOCK_STATUS = TRUE
> -FvNameGuid = 9B7FA59D-71C6-4A36-906E-9725EA6ADD5B
> -
> -!include
> $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPreMemoryInclude.fdf
> -
> -INF
> IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSam
> plePei.inf
> -
> -INF IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf
> -
> -[FV.FvSecurityPostMemory]
> -BlockSize = $(FLASH_BLOCK_SIZE)
> -FvAlignment = 16 #FV alignment and FV attributes
> setting.
> -ERASE_POLARITY = 1
> -MEMORY_MAPPED = TRUE
> -STICKY_WRITE = TRUE
> -LOCK_CAP = TRUE
> -LOCK_STATUS = TRUE
> -WRITE_DISABLED_CAP = TRUE
> -WRITE_ENABLED_CAP = TRUE
> -WRITE_STATUS = TRUE
> -WRITE_LOCK_CAP = TRUE
> -WRITE_LOCK_STATUS = TRUE
> -READ_DISABLED_CAP = TRUE
> -READ_ENABLED_CAP = TRUE
> -READ_STATUS = TRUE
> -READ_LOCK_CAP = TRUE
> -READ_LOCK_STATUS = TRUE
> -FvNameGuid = 4199E560-54AE-45E5-91A4-F7BC3804E14A
> -
> -!include
> $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPostMemoryInclude.fdf
> -
> -!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
> -INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf
> -!endif
> -
> -[FV.FvSecurityLate]
> -BlockSize = $(FLASH_BLOCK_SIZE)
> -FvAlignment = 16
> -ERASE_POLARITY = 1
> -MEMORY_MAPPED = TRUE
> -STICKY_WRITE = TRUE
> -LOCK_CAP = TRUE
> -LOCK_STATUS = TRUE
> -WRITE_DISABLED_CAP = TRUE
> -WRITE_ENABLED_CAP = TRUE
> -WRITE_STATUS = TRUE
> -WRITE_LOCK_CAP = TRUE
> -WRITE_LOCK_STATUS = TRUE
> -READ_DISABLED_CAP = TRUE
> -READ_ENABLED_CAP = TRUE
> -READ_STATUS = TRUE
> -READ_LOCK_CAP = TRUE
> -READ_LOCK_STATUS = TRUE
> -FvNameGuid = F753FE9A-EEFD-485B-840B-E032D538102C
> -
> -!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityLateInclude.fdf
> -
> -INF IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf
> -
> -!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
> -
> -INF $(PLATFORM_SI_PACKAGE)/Hsti/Dxe/HstiSiliconDxe.inf
> -
> -!endif
> -
> -!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
> -
> -INF
> $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf
> -
> -!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
> -INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
> -!endif
> -
> -!endif
> -
> -[FV.FvSecurity]
> -BlockSize = $(FLASH_BLOCK_SIZE)
> -FvAlignment = 16
> -ERASE_POLARITY = 1
> -MEMORY_MAPPED = TRUE
> -STICKY_WRITE = TRUE
> -LOCK_CAP = TRUE
> -LOCK_STATUS = TRUE
> -WRITE_DISABLED_CAP = TRUE
> -WRITE_ENABLED_CAP = TRUE
> -WRITE_STATUS = TRUE
> -WRITE_LOCK_CAP = TRUE
> -WRITE_LOCK_STATUS = TRUE
> -READ_DISABLED_CAP = TRUE
> -READ_ENABLED_CAP = TRUE
> -READ_STATUS = TRUE
> -READ_LOCK_CAP = TRUE
> -READ_LOCK_STATUS = TRUE
> -FvNameGuid = 5A9A8B4E-149A-4CB2-BDC7-C8D62DE2C8CF
> -
> -FILE FV_IMAGE = 757CC075-1428-423D-A73C-22639706C119 {
> - SECTION FV_IMAGE = FvSecurityPreMemory
> - }
> -
> -FILE FV_IMAGE = 80BB8482-44D5-4BEC-82B5-8D87A933830B {
> - SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF
> PROCESSING_REQUIRED = TRUE {
> - SECTION FV_IMAGE = FvSecurityPostMemory
> - }
> - }
> -
> -FILE FV_IMAGE = C83522D9-80A1-4D95-8C25-3F1370497406 {
> - SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF
> PROCESSING_REQUIRED = TRUE {
> - SECTION FV_IMAGE = FvSecurityLate
> - }
> - }
> -
> -[FV.FvAdvancedPreMem]
> -FvAlignment = 16
> -ERASE_POLARITY = 1
> -MEMORY_MAPPED = TRUE
> -STICKY_WRITE = TRUE
> -LOCK_CAP = TRUE
> -LOCK_STATUS = TRUE
> -WRITE_DISABLED_CAP = TRUE
> -WRITE_ENABLED_CAP = TRUE
> -WRITE_STATUS = TRUE
> -WRITE_LOCK_CAP = TRUE
> -WRITE_LOCK_STATUS = TRUE
> -READ_DISABLED_CAP = TRUE
> -READ_ENABLED_CAP = TRUE
> -READ_STATUS = TRUE
> -READ_LOCK_CAP = TRUE
> -READ_LOCK_STATUS = TRUE
> -FvNameGuid = 6053D78A-457E-4490-A237-31D0FBE2F305
> -
> -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
> -INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf
> -!endif
> -
> -[FV.FvAdvancedPostMem]
> -FvAlignment = 16
> -ERASE_POLARITY = 1
> -MEMORY_MAPPED = TRUE
> -STICKY_WRITE = TRUE
> -LOCK_CAP = TRUE
> -LOCK_STATUS = TRUE
> -WRITE_DISABLED_CAP = TRUE
> -WRITE_ENABLED_CAP = TRUE
> -WRITE_STATUS = TRUE
> -WRITE_LOCK_CAP = TRUE
> -WRITE_LOCK_STATUS = TRUE
> -READ_DISABLED_CAP = TRUE
> -READ_ENABLED_CAP = TRUE
> -READ_STATUS = TRUE
> -READ_LOCK_CAP = TRUE
> -READ_LOCK_STATUS = TRUE
> -FvNameGuid = BE3DF86F-E464-44A3-83F7-0D27E6B88C27
> -
> -[FV.FvAdvancedLate]
> -FvAlignment = 16
> -ERASE_POLARITY = 1
> -MEMORY_MAPPED = TRUE
> -STICKY_WRITE = TRUE
> -LOCK_CAP = TRUE
> -LOCK_STATUS = TRUE
> -WRITE_DISABLED_CAP = TRUE
> -WRITE_ENABLED_CAP = TRUE
> -WRITE_STATUS = TRUE
> -WRITE_LOCK_CAP = TRUE
> -WRITE_LOCK_STATUS = TRUE
> -READ_DISABLED_CAP = TRUE
> -READ_ENABLED_CAP = TRUE
> -READ_STATUS = TRUE
> -READ_LOCK_CAP = TRUE
> -READ_LOCK_STATUS = TRUE
> -FvNameGuid = 11F6E304-43F9-4B2F-90AB-B8FFEAD6205D
> -
> -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
> -INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf
> -INF $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf
> -INF
> $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf
> -!endif
> -
> -[FV.FvAdvanced]
> -BlockSize = $(FLASH_BLOCK_SIZE)
> -FvAlignment = 16
> -ERASE_POLARITY = 1
> -MEMORY_MAPPED = TRUE
> -STICKY_WRITE = TRUE
> -LOCK_CAP = TRUE
> -LOCK_STATUS = TRUE
> -WRITE_DISABLED_CAP = TRUE
> -WRITE_ENABLED_CAP = TRUE
> -WRITE_STATUS = TRUE
> -WRITE_LOCK_CAP = TRUE
> -WRITE_LOCK_STATUS = TRUE
> -READ_DISABLED_CAP = TRUE
> -READ_ENABLED_CAP = TRUE
> -READ_STATUS = TRUE
> -READ_LOCK_CAP = TRUE
> -READ_LOCK_STATUS = TRUE
> -FvNameGuid = B23E7388-9953-45C7-9201-0473DDE5487A
> -
> -FILE FV_IMAGE = 35E7406A-5842-4F2B-BC62-19022C12AF74 {
> - SECTION FV_IMAGE = FvAdvancedPreMem
> - }
> -
> -FILE FV_IMAGE = F5DCB34F-27EA-48AC-9406-C894F6D587CA {
> - SECTION FV_IMAGE = FvAdvancedPostMem
> - }
> -
> -FILE FV_IMAGE = 5248467B-B87B-4E74-AC02-398AF4BCB712 {
> - SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF
> PROCESSING_REQUIRED = TRUE {
> - SECTION FV_IMAGE = FvAdvancedLate
> - }
> - }
> -
> -###############################################################
> #################
> -#
> -# Rules are use with the [FV] section's module INF type to define
> -# how an FFS file is created for a given INF file. The following Rule are the
> default
> -# rules for the different module type. User can add the customized rules to
> define the
> -# content of the FFS file.
> -#
> -###############################################################
> #################
> -
> -!include $(PLATFORM_PACKAGE)/Include/Fdf/RuleInclude.fdf
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
> b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
> deleted file mode 100644
> index f7f4bd2e3d..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
> +++ /dev/null
> @@ -1,69 +0,0 @@
> -### @file
> -# Component information file for board ACPI initialization.
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -###
> -
> -[Defines]
> - INF_VERSION = 0x00010005
> - BASE_NAME = BoardAcpiDxe
> - FILE_GUID =
> E269E77D-6163-4F5D-8E59-21EAF114D307
> - MODULE_TYPE = DXE_DRIVER
> - VERSION_STRING = 1.0
> - ENTRY_POINT = InstallAcpiBoard
> -
> -[Sources.common]
> - BoardAcpiDxe.c
> - AcpiGnvsInit.c
> - UpdateDsdt.c
> - Dsdt/DSDT.ASL
> -
> -[Packages]
> - MdePkg/MdePkg.dec
> - MdeModulePkg/MdeModulePkg.dec
> - UefiCpuPkg/UefiCpuPkg.dec
> - MinPlatformPkg/MinPlatformPkg.dec
> - PcAtChipsetPkg/PcAtChipsetPkg.dec
> - ClevoOpenBoardPkg/OpenBoardPkg.dec
> - KabylakeSiliconPkg/SiPkg.dec
> -
> -[LibraryClasses]
> - UefiDriverEntryPoint
> - BaseLib
> - DebugLib
> - IoLib
> - PcdLib
> - UefiBootServicesTableLib
> - UefiRuntimeServicesTableLib
> - BaseMemoryLib
> - HobLib
> - AslUpdateLib
> - BoardAcpiTableLib
> -
> -[Protocols]
> - gEfiAcpiTableProtocolGuid ## CONSUMES
> - gEfiFirmwareVolume2ProtocolGuid ## CONSUMES
> - gEfiMpServiceProtocolGuid ## CONSUMES
> - gEfiGlobalNvsAreaProtocolGuid
> -
> -[Pcd]
> - gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress
> -
> - gBoardModuleTokenSpaceGuid.PcdAcpiSleepState
> - gBoardModuleTokenSpaceGuid.PcdAcpiHibernate
> - gBoardModuleTokenSpaceGuid.PcdLowPowerS0Idle
> - gBoardModuleTokenSpaceGuid.PcdDisableActiveTripPoints
> - gBoardModuleTokenSpaceGuid.PcdDisablePassiveTripPoints
> - gBoardModuleTokenSpaceGuid.PcdDisableCriticalTripPoints
> -
> -[Depex]
> - gEfiAcpiTableProtocolGuid AND
> - gEfiFirmwareVolume2ProtocolGuid AND
> - gEfiPciRootBridgeIoProtocolGuid AND
> - gEfiVariableArchProtocolGuid AND
> - gEfiVariableWriteArchProtocolGuid
> -
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/PciHotPlug/PciHotPlug.inf
> b/Platform/Intel/ClevoOpenBoardPkg/Features/PciHotPlug/PciHotPlug.inf
> deleted file mode 100644
> index e50763336b..0000000000
> --- a/Platform/Intel/ClevoOpenBoardPkg/Features/PciHotPlug/PciHotPlug.inf
> +++ /dev/null
> @@ -1,59 +0,0 @@
> -### @file
> -# Performs specific PCI-EXPRESS device resource configuration.
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -###
> -
> -[Defines]
> - INF_VERSION = 0x00010017
> - BASE_NAME = PciHotPlug
> - FILE_GUID =
> 3022E512-B94A-4F12-806D-7EF1177899D8
> - VERSION_STRING = 1.0
> - MODULE_TYPE = DXE_DRIVER
> - ENTRY_POINT = PciHotPlug
> -#
> -# The following information is for reference only and not required by the
> build tools.
> -#
> -# VALID_ARCHITECTURES = IA32 X64 EBC
> -#
> -
> -[LibraryClasses]
> - UefiDriverEntryPoint
> - UefiBootServicesTableLib
> - UefiRuntimeServicesTableLib
> - BaseMemoryLib
> - MemoryAllocationLib
> - DevicePathLib
> - DebugLib
> - UefiLib
> - HobLib
> - PchPcieRpLib
> - ConfigBlockLib
> - TbtCommonLib
> -
> -[Packages]
> - MdePkg/MdePkg.dec
> - MinPlatformPkg/MinPlatformPkg.dec
> - ClevoOpenBoardPkg/OpenBoardPkg.dec
> - KabylakeSiliconPkg/SiPkg.dec
> -
> -[Sources]
> - PciHotPlug.c
> - PciHotPlug.h
> -
> -[Protocols]
> - gEfiPciHotPlugInitProtocolGuid ## PRODUCES
> - gSaPolicyProtocolGuid ## CONSUMES
> -
> -[Guids]
> - gEfiHobListGuid ## CONSUMES
> - gPcieRpConfigGuid ## CONSUMES
> -
> -[Pcd]
> - gBoardModuleTokenSpaceGuid.PcdPchPcieRootPortHpe
> -
> -[Depex]
> - gDxeTbtPolicyProtocolGuid
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib/
> DxeTbtPolicyLib.inf
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib/
> DxeTbtPolicyLib.inf
> deleted file mode 100644
> index ceeca81a50..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib/
> DxeTbtPolicyLib.inf
> +++ /dev/null
> @@ -1,67 +0,0 @@
> -## @file
> -# Component description file for Tbt functionality
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -##
> -
> -
> -[Defines]
> -INF_VERSION = 0x00010017
> -BASE_NAME = DxeTbtPolicyLib
> -FILE_GUID = 28ABF346-4E52-4BD3-b1FF-63BA7563C9D4
> -VERSION_STRING = 1.0
> -MODULE_TYPE = BASE
> -LIBRARY_CLASS = DxeTbtPolicyLib
> -
> -
> -[LibraryClasses]
> -BaseMemoryLib
> -UefiRuntimeServicesTableLib
> -UefiBootServicesTableLib
> -DebugLib
> -PostCodeLib
> -HobLib
> -
> -[Packages]
> - MdePkg/MdePkg.dec
> - MdeModulePkg/MdeModulePkg.dec
> - MinPlatformPkg/MinPlatformPkg.dec
> - ClevoOpenBoardPkg/OpenBoardPkg.dec
> - KabylakeSiliconPkg/SiPkg.dec
> -
> -[Pcd]
> -gBoardModuleTokenSpaceGuid.PcdDTbtSecurityMode ##
> CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtGpio5Filter ## CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport ##
> CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI ##
> CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify ## CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq ## CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtAspm ##
> CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch ## CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdRtd3Tbt ##
> CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq ## CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtWin10Support ##
> CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReqDelay ## CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdRtd3TbtOffDelay ## CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtPcieExtraBusRsvd ## CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemRsvd ##
> CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax ##
> CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd ##
> CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax ##
> CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtPcieRpNumber ##
> CONSUMES
> -
> -
> -[Sources]
> -DxeTbtPolicyLib.c
> -
> -
> -[Guids]
> -gEfiEndOfDxeEventGroupGuid
> -#gSetupVariableGuid
> -gTbtInfoHobGuid
> -
> -[Protocols]
> -gDxeTbtPolicyProtocolGuid
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTbtC
> ommonLib/TbtCommonLib.inf
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTbtC
> ommonLib/TbtCommonLib.inf
> deleted file mode 100644
> index b7277c1c57..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTbtC
> ommonLib/TbtCommonLib.inf
> +++ /dev/null
> @@ -1,62 +0,0 @@
> -### @file
> -# Component information file for Thunderbolt common library
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -###
> -
> -[Defines]
> - INF_VERSION = 0x00010017
> - BASE_NAME = TbtCommonLib
> - FILE_GUID =
> 5F03614E-CB56-40B1-9989-A09E25BBA294
> - VERSION_STRING = 1.0
> - MODULE_TYPE = BASE
> - LIBRARY_CLASS = TbtCommonLib
> -#
> -# The following information is for reference only and not required by the
> build tools.
> -#
> -# VALID_ARCHITECTURES = IA32 X64 EBC
> -#
> -
> -[LibraryClasses]
> - DebugLib
> - PchPcieRpLib
> - PciSegmentLib
> - TimerLib
> - BaseLib
> - GpioLib
> - GpioExpanderLib
> -
> -[Packages]
> - MdePkg/MdePkg.dec
> - MdeModulePkg/MdeModulePkg.dec
> - MinPlatformPkg/MinPlatformPkg.dec
> - ClevoOpenBoardPkg/OpenBoardPkg.dec
> - KabylakeSiliconPkg/SiPkg.dec
> -
> -[Pcd]
> -gBoardModuleTokenSpaceGuid.PcdDTbtSecurityMode ##
> CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtGpio5Filter ##
> CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport ##
> CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI ##
> CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify ##
> CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq ##
> CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtAspm ##
> CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch ##
> CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdRtd3Tbt ##
> CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq ## CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtWin10Support ##
> CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReqDelay ## CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdRtd3TbtOffDelay ## CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtPcieExtraBusRsvd ## CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemRsvd ##
> CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax ##
> CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd ##
> CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax ##
> CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtPcieRpNumber
> -
> -[Sources]
> - TbtCommonLib.c
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/P
> eiTbtPolicyLib.inf
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/P
> eiTbtPolicyLib.inf
> deleted file mode 100644
> index 8f554c8aa7..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/P
> eiTbtPolicyLib.inf
> +++ /dev/null
> @@ -1,56 +0,0 @@
> -## @file
> -# Component description file for Tbt policy
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -##
> -
> -
> -[Defines]
> -INF_VERSION = 0x00010017
> -BASE_NAME = PeiTbtPolicyLib
> -FILE_GUID = 4A95FDBB-2535-49eb-9A79-D56D24257106
> -VERSION_STRING = 1.0
> -MODULE_TYPE = PEIM
> -LIBRARY_CLASS = PeiTbtPolicyLib
> -
> -
> -[LibraryClasses]
> -BaseMemoryLib
> -PeiServicesLib
> -PeiServicesTablePointerLib
> -MemoryAllocationLib
> -DebugLib
> -PostCodeLib
> -HobLib
> -GpioLib
> -
> -[Packages]
> - MdePkg/MdePkg.dec
> - MdeModulePkg/MdeModulePkg.dec
> - MinPlatformPkg/MinPlatformPkg.dec
> - ClevoOpenBoardPkg/OpenBoardPkg.dec
> - KabylakeSiliconPkg/SiPkg.dec
> - IntelSiliconPkg/IntelSiliconPkg.dec
> -
> -[Pcd]
> -gBoardModuleTokenSpaceGuid.PcdDTbtControllerEn ##
> CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtControllerType ##
> CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtPcieRpNumber ##
> CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtBootOn ##
> CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtUsbOn ##
> CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtGpio3ForcePwr ##
> CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtGpio3ForcePwrDly ##
> CONSUMES
> -gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad ##
> CONSUMES
> -
> -[Sources]
> -PeiTbtPolicyLib.c
> -
> -[Guids]
> -gTbtInfoHobGuid
> -
> -[Ppis]
> -gEfiPeiReadOnlyVariable2PpiGuid
> -gPeiTbtPolicyPpiGuid
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/Private/PeiDTbtI
> nitLib/PeiDTbtInitLib.inf
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/Private/PeiDTbtI
> nitLib/PeiDTbtInitLib.inf
> deleted file mode 100644
> index e33601618a..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/Private/PeiDTbtI
> nitLib/PeiDTbtInitLib.inf
> +++ /dev/null
> @@ -1,41 +0,0 @@
> -### @file
> -# Component description file for PEI DTBT Init library.
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -###
> -
> -[Defines]
> - INF_VERSION = 0x00010017
> - BASE_NAME = PeiDTbtInitLib
> - FILE_GUID =
> 06768A8D-8152-403f-83C1-59584FD2B438
> - VERSION_STRING = 1.0
> - MODULE_TYPE = PEIM
> - LIBRARY_CLASS = PeiDTbtInitLib
> -
> -[LibraryClasses]
> - PeiServicesLib
> - DebugLib
> - PcdLib
> - TbtCommonLib
> - PciSegmentLib
> - PeiTbtPolicyLib
> - PchPmcLib
> -
> -[Packages]
> - MdePkg/MdePkg.dec
> - MdeModulePkg/MdeModulePkg.dec
> - MinPlatformPkg/MinPlatformPkg.dec
> - ClevoOpenBoardPkg/OpenBoardPkg.dec
> - KabylakeSiliconPkg/SiPkg.dec
> -
> -[Ppis]
> - gPeiTbtPolicyPpiGuid ## CONSUMES
> -
> -[Pcd]
> - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
> -
> -[Sources]
> - PeiDTbtInitLib.c
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtDxe.inf
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtDxe.inf
> deleted file mode 100644
> index 6ec93bf03a..0000000000
> --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtDxe.inf
> +++ /dev/null
> @@ -1,49 +0,0 @@
> -### @file
> -# Thunderbolt initialization in DXE.
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -###
> -
> -[Defines]
> - INF_VERSION = 0x00010017
> - BASE_NAME = TbtDxe
> - FILE_GUID =
> 19C9762C-3A88-41B0-906F-8C4C2895A887
> - VERSION_STRING = 1.0
> - MODULE_TYPE = DXE_DRIVER
> - ENTRY_POINT = TbtDxeEntryPoint
> -
> -[LibraryClasses]
> - DebugLib
> - BaseMemoryLib
> - UefiBootServicesTableLib
> - UefiRuntimeServicesTableLib
> - UefiDriverEntryPoint
> - HobLib
> - UefiLib
> - TbtCommonLib
> - DxeTbtPolicyLib
> - AslUpdateLib
> -
> -[Packages]
> - MdePkg/MdePkg.dec
> - MdeModulePkg/MdeModulePkg.dec
> - MinPlatformPkg/MinPlatformPkg.dec
> - ClevoOpenBoardPkg/OpenBoardPkg.dec
> - KabylakeSiliconPkg/SiPkg.dec
> -
> -[Sources]
> - TbtDxe.c
> -
> -[Protocols]
> - gTbtNvsAreaProtocolGuid ## CONSUMES
> - gDxeTbtPolicyProtocolGuid
> -
> -[Guids]
> - gTbtInfoHobGuid ## CONSUMES
> -
> -[Depex]
> - gEfiVariableWriteArchProtocolGuid AND
> - gEfiVariableArchProtocolGuid
> \ No newline at end of file
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf
> deleted file mode 100644
> index d15c571784..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf
> +++ /dev/null
> @@ -1,44 +0,0 @@
> -### @file
> -# Thunderbolt initialization in PEI.
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -###
> -
> -[Defines]
> - INF_VERSION = 0x00010017
> - BASE_NAME = PeiTbtInit
> - FILE_GUID =
> 90BF2BFB-F998-4cbc-AD72-008D4D047A4B
> - VERSION_STRING = 1.0
> - MODULE_TYPE = PEIM
> - ENTRY_POINT = TbtInitEntryPoint
> -
> -[LibraryClasses]
> - PeimEntryPoint
> - DebugLib
> - HobLib
> - PeiServicesLib
> - PeiTbtPolicyLib
> - PeiDTbtInitLib
> -
> -[Packages]
> - MdePkg/MdePkg.dec
> - MdeModulePkg/MdeModulePkg.dec
> - MinPlatformPkg/MinPlatformPkg.dec
> - ClevoOpenBoardPkg/OpenBoardPkg.dec
> - KabylakeSiliconPkg/SiPkg.dec
> -
> -[Sources]
> - PeiTbtInit.c
> -
> -[Guids]
> - gTbtInfoHobGuid ## CONSUMES
> -
> -[Ppis]
> - gEfiEndOfPeiSignalPpiGuid ## CONSUMES
> - gPeiTbtPolicyBoardInitDonePpiGuid ## CONSUMES
> -
> -[Depex]
> - gEfiPeiMemoryDiscoveredPpiGuid
> \ No newline at end of file
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
> deleted file mode 100644
> index c08608ae76..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
> +++ /dev/null
> @@ -1,77 +0,0 @@
> -### @file
> -# Thunderbolt SMM initialization module.
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -###
> -
> -[Defines]
> - INF_VERSION = 0x00010017
> - BASE_NAME = TbtSmm
> - FILE_GUID =
> 5BDCD685-D80A-42E6-9867-A84CCE7F828E
> - VERSION_STRING = 1.0
> - MODULE_TYPE = DXE_SMM_DRIVER
> - PI_SPECIFICATION_VERSION = 1.10
> - ENTRY_POINT = TbtSmmEntryPoint
> -
> -[LibraryClasses]
> - UefiDriverEntryPoint
> - BaseLib
> - BaseMemoryLib
> - DebugLib
> - UefiRuntimeServicesTableLib
> - UefiBootServicesTableLib
> - IoLib
> - PciExpressLib
> - HobLib
> - ReportStatusCodeLib
> - PciSegmentLib
> - UefiLib
> - SmmServicesTableLib
> - GpioLib
> - PchInfoLib
> - TbtCommonLib
> - PchPmcLib
> -
> -[Packages]
> - MdePkg/MdePkg.dec
> - MdeModulePkg/MdeModulePkg.dec
> - MinPlatformPkg/MinPlatformPkg.dec
> - ClevoOpenBoardPkg/OpenBoardPkg.dec
> - KabylakeSiliconPkg/SiPkg.dec
> -
> -[Pcd]
> - gBoardModuleTokenSpaceGuid.PcdSwSmiDTbtEnumerate ## CONSUMES
> - gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength ## CONSUMES
> -
> -[FixedPcd]
> - gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES
> -
> -[Sources]
> - TbtSmiHandler.h
> - TbtSmiHandler.c
> - TbtSmm.c
> -
> -[Protocols]
> - gTbtNvsAreaProtocolGuid ## CONSUMES
> - gEfiSmmSxDispatch2ProtocolGuid ## CONSUMES
> - gEfiSmmSwDispatch2ProtocolGuid ## CONSUMES
> - gEfiSmmVariableProtocolGuid ## CONSUMES
> - gDxeTbtPolicyProtocolGuid
> -
> -[Guids]
> - gTbtInfoHobGuid ## CONSUMES
> -
> -[Pcd]
> - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
> -
> -[Depex]
> - gEfiSmmBase2ProtocolGuid AND
> - gEfiSmmSxDispatch2ProtocolGuid AND
> - gEfiSmmSwDispatch2ProtocolGuid AND
> - gEfiGlobalNvsAreaProtocolGuid AND
> - gEfiVariableWriteArchProtocolGuid AND
> - gEfiVariableArchProtocolGuid AND
> - gEfiSmmVariableProtocolGuid
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGp
> ioExpanderLib.inf
> b/Platform/Intel/ClevoOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGp
> ioExpanderLib.inf
> deleted file mode 100644
> index 4c2478155e..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGp
> ioExpanderLib.inf
> +++ /dev/null
> @@ -1,33 +0,0 @@
> -### @file
> -# Library producing Gpio Expander functionality.
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -###
> -
> -[Defines]
> - INF_VERSION = 0x00010017
> - BASE_NAME = BaseGpioExpanderLib
> - FILE_GUID =
> D10AE2A4-782E-427E-92FB-BB74505ED329
> - VERSION_STRING = 1.0
> - MODULE_TYPE = BASE
> - LIBRARY_CLASS = GpioExpanderLib
> -
> -[LibraryClasses]
> - BaseLib
> - IoLib
> - DebugLib
> - TimerLib
> - PchSerialIoLib
> - I2cAccessLib
> -
> -[Packages]
> - MdePkg/MdePkg.dec
> - MinPlatformPkg/MinPlatformPkg.dec
> - ClevoOpenBoardPkg/OpenBoardPkg.dec
> - KabylakeSiliconPkg/SiPkg.dec
> -
> -[Sources]
> - BaseGpioExpanderLib.c
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cAccessLi
> b.inf
> b/Platform/Intel/ClevoOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cAccessLi
> b.inf
> deleted file mode 100644
> index bbbc74cf90..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cAccessLi
> b.inf
> +++ /dev/null
> @@ -1,36 +0,0 @@
> -### @file
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -###
> -
> -[Defines]
> - INF_VERSION = 0x00010017
> - BASE_NAME = PeiI2cAccessLib
> - FILE_GUID =
> 72CD3A7B-FEA5-4F5E-9165-4DD12187BB13
> - VERSION_STRING = 1.0
> - MODULE_TYPE = BASE
> - LIBRARY_CLASS = PeiI2cAccessLib
> -#
> -# The following information is for reference only and not required by the
> build tools.
> -#
> -# VALID_ARCHITECTURES = IA32 X64 IPF EBC
> -#
> -
> -[LibraryClasses]
> - BaseLib
> - BaseMemoryLib
> - DebugLib
> - TimerLib
> -
> -[Packages]
> - MdePkg/MdePkg.dec
> - MinPlatformPkg/MinPlatformPkg.dec
> - ClevoOpenBoardPkg/OpenBoardPkg.dec
> - SecurityPkg/SecurityPkg.dec
> - KabylakeSiliconPkg/SiPkg.dec
> -
> -[Sources]
> - PeiI2cAccessLib.c
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSer
> ialPortLibSpiFlash.inf
> b/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSe
> rialPortLibSpiFlash.inf
> deleted file mode 100644
> index b81ce9dd7a..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSer
> ialPortLibSpiFlash.inf
> +++ /dev/null
> @@ -1,50 +0,0 @@
> -### @file
> -# Component description file for Serial I/O Port library to write to SPI flash.
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -##
> -
> -[Defines]
> - INF_VERSION = 0x00010005
> - BASE_NAME = PeiSerialPortLibFlash
> - FILE_GUID =
> 35A3BA89-04BE-409C-A3CA-DEF6B510F80F
> - VERSION_STRING = 1.1
> - MODULE_TYPE = PEIM
> - LIBRARY_CLASS = SerialPortLib|PEIM PEI_CORE
> -#
> -# The following information is for reference only and not required by the
> build tools.
> -#
> -# VALID_ARCHITECTURES = IA32 X64 IPF
> -#
> -
> -[LibraryClasses]
> - BaseLib
> - BaseMemoryLib
> - HobLib
> - PcdLib
> - PeiServicesLib
> - SpiLib
> -
> -[Packages]
> - MdePkg/MdePkg.dec
> - MdeModulePkg/MdeModulePkg.dec
> - MinPlatformPkg/MinPlatformPkg.dec
> - KabylakeSiliconPkg/SiPkg.dec
> - ClevoOpenBoardPkg/OpenBoardPkg.dec
> -
> -[Sources]
> - PeiSerialPortLibSpiFlash.c
> -
> -[Ppis]
> - gPchSpiPpiGuid
> -
> -[Guids]
> - gSpiFlashDebugHobGuid
> -
> -[Pcd]
> - gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
> ## CONSUMES
> - gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageBase
> ## CONSUMES
> - gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageSize
> ## CONSUMES
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilico
> nPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilic
> onPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf
> deleted file mode 100644
> index 13c12655f6..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilico
> nPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf
> +++ /dev/null
> @@ -1,43 +0,0 @@
> -## @file
> -# Component information file for Silicon Policy Notify Library.
> -# This library implements constructor function to register notify call back
> -# when policy PPI installed.
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -##
> -
> -[Defines]
> - INF_VERSION = 0x00010005
> - BASE_NAME = PeiPreMemSiliconPolicyNotifyLib
> - FILE_GUID =
> 6D231E12-C088-47C8-8B16-61F07293EEF8
> - MODULE_TYPE = PEIM
> - VERSION_STRING = 1.0
> - LIBRARY_CLASS = NULL
> - CONSTRUCTOR =
> PeiPreMemSiliconPolicyNotifyLibConstructor
> -
> -[LibraryClasses]
> - BaseLib
> -
> -[Packages]
> - MdePkg/MdePkg.dec
> - KabylakeOpenBoardPkg/OpenBoardPkg.dec
> - KabylakeSiliconPkg/SiPkg.dec
> -
> -[Sources]
> - PeiPreMemSiliconPolicyNotifyLib.c
> -
> -[Guids]
> - gSaMiscPeiPreMemConfigGuid
> -
> -[Ppis]
> - gSiPreMemPolicyPpiGuid
> -
> -[Pcd]
> - # SPD Address Table
> - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0
> - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1
> - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2
> - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilico
> nPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilic
> onPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
> deleted file mode 100644
> index b9b9232692..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilico
> nPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
> +++ /dev/null
> @@ -1,146 +0,0 @@
> -## @file
> -# FSP wrapper silicon policy update library.
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -##
> -
> -###############################################################
> #################
> -#
> -# Defines Section - statements that will be processed to create a Makefile.
> -#
> -###############################################################
> #################
> -[Defines]
> - INF_VERSION = 0x00010005
> - BASE_NAME = SiliconPolicyUpdateLibFsp
> - FILE_GUID =
> 4E83003B-49A9-459E-AAA6-1CA3C6D04FB2
> - MODULE_TYPE = PEIM
> - VERSION_STRING = 1.0
> - LIBRARY_CLASS = SiliconPolicyUpdateLib
> -
> -
> -#
> -# The following information is for reference only and not required by the
> build tools.
> -#
> -# VALID_ARCHITECTURES = IA32 X64
> -#
> -
> -###############################################################
> #################
> -#
> -# Sources Section - list of files that are required for the build to succeed.
> -#
> -###############################################################
> #################
> -
> -[Sources]
> - PeiFspPolicyUpdateLib.c
> - PeiPchPolicyUpdatePreMem.c
> - PeiPchPolicyUpdate.c
> - PeiSaPolicyUpdatePreMem.c
> - PeiSaPolicyUpdate.c
> - PeiFspMiscUpdUpdateLib.c
> - PcieDeviceTable.c
> -
> -###############################################################
> #################
> -#
> -# Package Dependency Section - list of Package files that are required for
> -# this module.
> -#
> -###############################################################
> #################
> -
> -[Packages]
> - MdePkg/MdePkg.dec
> - MdeModulePkg/MdeModulePkg.dec
> - IntelFsp2Pkg/IntelFsp2Pkg.dec
> - IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
> - IntelSiliconPkg/IntelSiliconPkg.dec
> - KabylakeSiliconPkg/SiPkg.dec
> - KabylakeFspBinPkg/KabylakeFspBinPkg.dec
> - ClevoOpenBoardPkg/OpenBoardPkg.dec
> - MinPlatformPkg/MinPlatformPkg.dec
> -
> -[LibraryClasses.IA32]
> - FspWrapperApiLib
> - OcWdtLib
> - PchResetLib
> - FspWrapperPlatformLib
> - BaseMemoryLib
> - CpuPlatformLib
> - DebugLib
> - HobLib
> - IoLib
> - PcdLib
> - PostCodeLib
> - SmbusLib
> - MmPciLib
> - ConfigBlockLib
> - PeiSaPolicyLib
> - PchGbeLib
> - PchInfoLib
> - PchHsioLib
> - PchPcieRpLib
> - MemoryAllocationLib
> - CpuMailboxLib
> - DebugPrintErrorLevelLib
> - SiPolicyLib
> - PchGbeLib
> - TimerLib
> - GpioLib
> - PeiLib
> -
> -[Pcd]
> - gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ##
> CONSUMES
> - gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ##
> CONSUMES
> - gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ##
> CONSUMES
> - gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ##
> CONSUMES
> - gBoardModuleTokenSpaceGuid.PcdMrcSpdData
> - gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize
> - gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig
> - gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl
> - gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved
> -
> - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ##
> CONSUMES
> - gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable ##
> CONSUMES
> - gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber ##
> CONSUMES
> - gSiPkgTokenSpaceGuid.PcdSmmbaseSwSmi ##
> CONSUMES
> - gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit ##
> CONSUMES
> -
> - gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1
> - gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2
> - gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size
> - gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size
> - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1
> - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2
> - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size
> - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size
> -
> - gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1
> - gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2
> - gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size
> - gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size
> - gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1
> - gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2
> - gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size
> - gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size
> -
> - gBoardModuleTokenSpaceGuid.PcdHdaVerbTable
> - gBoardModuleTokenSpaceGuid.PcdHdaVerbTable2
> - gBoardModuleTokenSpaceGuid.PcdExtHdaVerbTable
> - gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable1
> - gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable2
> - gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable3
> - gBoardModuleTokenSpaceGuid.PcdDisplayAudioHdaVerbTable
> -
> - gBoardModuleTokenSpaceGuid.PcdAudioConnector
> -
> - gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid
> -
> -[Guids]
> - gFspNonVolatileStorageHobGuid ## CONSUMES
> - gTianoLogoGuid ## CONSUMES
> - gEfiMemoryOverwriteControlDataGuid
> -
> -[Depex]
> - gEdkiiVTdInfoPpiGuid
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BasePlatformHookLib
> /BasePlatformHookLib.inf
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BasePlatformHookLi
> b/BasePlatformHookLib.inf
> deleted file mode 100644
> index c4ea31bff2..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BasePlatformHookLib
> /BasePlatformHookLib.inf
> +++ /dev/null
> @@ -1,51 +0,0 @@
> -### @file
> -# Platform Hook Library instance for Clevo N1xxWU board.
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -###
> -
> -[Defines]
> - INF_VERSION = 0x00010017
> - BASE_NAME = BasePlatformHookLib
> - FILE_GUID =
> E22ADCC6-ED90-4A90-9837-C8E7FF9E963D
> - VERSION_STRING = 1.0
> - MODULE_TYPE = BASE
> - LIBRARY_CLASS = PlatformHookLib
> -#
> -# The following information is for reference only and not required by the
> build tools.
> -#
> -# VALID_ARCHITECTURES = IA32 X64 IPF EBC
> -#
> -
> -[LibraryClasses]
> - BaseLib
> - IoLib
> - MmPciLib
> - PciLib
> - PchCycleDecodingLib
> -
> -[Packages]
> - MdePkg/MdePkg.dec
> - MdeModulePkg/MdeModulePkg.dec
> - MinPlatformPkg/MinPlatformPkg.dec
> - ClevoOpenBoardPkg/OpenBoardPkg.dec
> - KabylakeSiliconPkg/SiPkg.dec
> -
> -[Pcd]
> - gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ##
> CONSUMES
> - gBoardModuleTokenSpaceGuid.PcdLpcSioIndexPort ##
> CONSUMES
> - gBoardModuleTokenSpaceGuid.PcdLpcSioDataPort ##
> CONSUMES
> - gBoardModuleTokenSpaceGuid.PcdLpcSioIndexDefaultPort ##
> CONSUMES
> - gBoardModuleTokenSpaceGuid.PcdLpcSioDataDefaultPort ##
> CONSUMES
> -
> -[FixedPcd]
> - gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort ##
> CONSUMES
> - gBoardModuleTokenSpaceGuid.PcdSioBaseAddress ##
> CONSUMES
> - gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange
> ## CONSUMES
> - gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding ##
> CONSUMES
> -
> -[Sources]
> - BasePlatformHookLib.c
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeBo
> ardAcpiTableLib.inf
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeBo
> ardAcpiTableLib.inf
> deleted file mode 100644
> index 06e703e12d..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeBo
> ardAcpiTableLib.inf
> +++ /dev/null
> @@ -1,47 +0,0 @@
> -### @file
> -# Clevo N1xxWU board DXE ACPI table functionality.
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -###
> -
> -[Defines]
> - INF_VERSION = 0x00010017
> - BASE_NAME = DxeBoardAcpiTableLib
> - FILE_GUID =
> 6562E0AE-90D8-4D41-8C97-81286B4BE7D2
> - VERSION_STRING = 1.0
> - MODULE_TYPE = BASE
> - LIBRARY_CLASS = BoardAcpiTableLib
> -
> -#
> -# The following information is for reference only and not required by the
> build tools.
> -#
> -# VALID_ARCHITECTURES = IA32 X64 IPF EBC
> -#
> -
> -[LibraryClasses]
> - BaseLib
> - IoLib
> - PciLib
> - AslUpdateLib
> -
> -[Packages]
> - MdePkg/MdePkg.dec
> - MdeModulePkg/MdeModulePkg.dec
> - MinPlatformPkg/MinPlatformPkg.dec
> - ClevoOpenBoardPkg/OpenBoardPkg.dec
> - KabylakeSiliconPkg/SiPkg.dec
> -
> -[Pcd]
> - gBoardModuleTokenSpaceGuid.PcdPs2KbMsEnable
> - gMinPlatformPkgTokenSpaceGuid.PcdPciExpNative
> - gMinPlatformPkgTokenSpaceGuid.PcdNativeAspmEnable
> - gMinPlatformPkgTokenSpaceGuid.PcdLowPowerS0Idle
> - gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress
> -
> -[Sources]
> - DxeN1xxWUAcpiTableLib.c
> - DxeBoardAcpiTableLib.c
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeMu
> ltiBoardAcpiSupportLib.inf
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeMu
> ltiBoardAcpiSupportLib.inf
> deleted file mode 100644
> index c505909ad3..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeMu
> ltiBoardAcpiSupportLib.inf
> +++ /dev/null
> @@ -1,48 +0,0 @@
> -### @file
> -# Clevo N1xxWU multi-board DXE ACPI table support functionality.
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -###
> -
> -[Defines]
> - INF_VERSION = 0x00010017
> - BASE_NAME =
> DxeN1xxWUMultiBoardAcpiTableLib
> - FILE_GUID =
> 8E6A3B38-53E0-48C0-970F-058F380FCB80
> - VERSION_STRING = 1.0
> - MODULE_TYPE = BASE
> - LIBRARY_CLASS = NULL
> - CONSTRUCTOR =
> DxeN1xxWUMultiBoardAcpiSupportLibConstructor
> -
> -#
> -# The following information is for reference only and not required by the
> build tools.
> -#
> -# VALID_ARCHITECTURES = IA32 X64 IPF EBC
> -#
> -
> -[LibraryClasses]
> - BaseLib
> - IoLib
> - PciLib
> - AslUpdateLib
> -
> -[Packages]
> - MdePkg/MdePkg.dec
> - MdeModulePkg/MdeModulePkg.dec
> - MinPlatformPkg/MinPlatformPkg.dec
> - ClevoOpenBoardPkg/OpenBoardPkg.dec
> - KabylakeSiliconPkg/SiPkg.dec
> -
> -[Pcd]
> - gBoardModuleTokenSpaceGuid.PcdPs2KbMsEnable
> - gBoardModuleTokenSpaceGuid.PcdPciExpNative
> - gBoardModuleTokenSpaceGuid.PcdNativeAspmEnable
> - gBoardModuleTokenSpaceGuid.PcdLowPowerS0Idle
> - gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress
> -
> -[Sources]
> - DxeN1xxWUAcpiTableLib.c
> - DxeMultiBoardAcpiSupportLib.c
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmB
> oardAcpiEnableLib.inf
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmB
> oardAcpiEnableLib.inf
> deleted file mode 100644
> index 8752fbb43f..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmB
> oardAcpiEnableLib.inf
> +++ /dev/null
> @@ -1,47 +0,0 @@
> -### @file
> -# Clevo N1xxWU board SMM ACPI table enable/disable functionality.
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -###
> -
> -[Defines]
> - INF_VERSION = 0x00010017
> - BASE_NAME = SmmBoardAcpiEnableLib
> - FILE_GUID =
> 549E69AE-D3B3-485B-9C17-AF16E20A58AD
> - VERSION_STRING = 1.0
> - MODULE_TYPE = BASE
> - LIBRARY_CLASS = BoardAcpiEnableLib
> -
> -#
> -# The following information is for reference only and not required by the
> build tools.
> -#
> -# VALID_ARCHITECTURES = IA32 X64 IPF EBC
> -#
> -
> -[LibraryClasses]
> - BaseLib
> - IoLib
> - PciLib
> - MmPciLib
> - PchCycleDecodingLib
> -
> -[Packages]
> - MdePkg/MdePkg.dec
> - MdeModulePkg/MdeModulePkg.dec
> - MinPlatformPkg/MinPlatformPkg.dec
> - ClevoOpenBoardPkg/OpenBoardPkg.dec
> - KabylakeSiliconPkg/SiPkg.dec
> -
> -[Pcd]
> - gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition ##
> CONSUMES
> -
> -[Protocols]
> -
> -[Sources]
> - SmmN1xxWUAcpiEnableLib.c
> - SmmSiliconAcpiEnableLib.c
> - SmmBoardAcpiEnableLib.c
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmM
> ultiBoardAcpiSupportLib.inf
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmM
> ultiBoardAcpiSupportLib.inf
> deleted file mode 100644
> index 3c4cfaccd3..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmM
> ultiBoardAcpiSupportLib.inf
> +++ /dev/null
> @@ -1,48 +0,0 @@
> -### @file
> -# SMM multi-board ACPI support functionality.
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -###
> -
> -[Defines]
> - INF_VERSION = 0x00010017
> - BASE_NAME =
> SmmN1xxWUMultiBoardAcpiSupportLib
> - FILE_GUID =
> 8929A54E-7ED8-4AB3-BEBB-C0367BDBBFF5
> - VERSION_STRING = 1.0
> - MODULE_TYPE = BASE
> - LIBRARY_CLASS = NULL
> - CONSTRUCTOR =
> SmmN1xxWUMultiBoardAcpiSupportLibConstructor
> -
> -#
> -# The following information is for reference only and not required by the
> build tools.
> -#
> -# VALID_ARCHITECTURES = IA32 X64 IPF EBC
> -#
> -
> -[LibraryClasses]
> - BaseLib
> - IoLib
> - PciLib
> - MmPciLib
> - PchCycleDecodingLib
> -
> -[Packages]
> - MdePkg/MdePkg.dec
> - MdeModulePkg/MdeModulePkg.dec
> - MinPlatformPkg/MinPlatformPkg.dec
> - ClevoOpenBoardPkg/OpenBoardPkg.dec
> - KabylakeSiliconPkg/SiPkg.dec
> -
> -[Pcd]
> - gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition ##
> CONSUMES
> -
> -[Protocols]
> -
> -[Sources]
> - SmmN1xxWUAcpiEnableLib.c
> - SmmSiliconAcpiEnableLib.c
> - SmmMultiBoardAcpiSupportLib.c
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoar
> dInitPostMemLib.inf
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoar
> dInitPostMemLib.inf
> deleted file mode 100644
> index 01225c9114..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoar
> dInitPostMemLib.inf
> +++ /dev/null
> @@ -1,53 +0,0 @@
> -## @file
> -# Component information file for N1xxWUInitLib in PEI post memory phase.
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -##
> -
> -[Defines]
> - INF_VERSION = 0x00010005
> - BASE_NAME = PeiBoardPostMemInitLib
> - FILE_GUID =
> 7fcc3900-d38d-419f-826b-72481e8b5509
> - MODULE_TYPE = BASE
> - VERSION_STRING = 1.0
> - LIBRARY_CLASS = BoardInitLib
> -
> -[LibraryClasses]
> - BaseLib
> - DebugLib
> - BaseMemoryLib
> - MemoryAllocationLib
> - GpioExpanderLib
> - PcdLib
> - SiliconInitLib
> -
> -[Packages]
> - MinPlatformPkg/MinPlatformPkg.dec
> - ClevoOpenBoardPkg/OpenBoardPkg.dec
> - MdePkg/MdePkg.dec
> - MdeModulePkg/MdeModulePkg.dec
> - KabylakeSiliconPkg/SiPkg.dec
> -
> -[Sources]
> - PeiN1xxWUInitPostMemLib.c
> - N1xxWUGpioTable.c
> - N1xxWUHdaVerbTables.c
> - PeiBoardInitPostMemLib.c
> -
> -[FixedPcd]
> -
> -[Pcd]
> - gBoardModuleTokenSpaceGuid.PcdBoardGpioTable
> - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize
> - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel
> -
> - gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable
> - gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize
> -
> - gBoardModuleTokenSpaceGuid.PcdHdaVerbTable
> -
> - gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTable
> - gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoar
> dInitPreMemLib.inf
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoar
> dInitPreMemLib.inf
> deleted file mode 100644
> index 22797cd80f..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoar
> dInitPreMemLib.inf
> +++ /dev/null
> @@ -1,132 +0,0 @@
> -## @file
> -# Component information file for PEI N1xxWU Board Init Pre-Mem Library
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -##
> -
> -[Defines]
> - INF_VERSION = 0x00010005
> - BASE_NAME = PeiBoardInitPreMemLib
> - FILE_GUID =
> ec3675bc-1470-417d-826e-37378140213d
> - MODULE_TYPE = BASE
> - VERSION_STRING = 1.0
> - LIBRARY_CLASS = BoardInitLib
> -
> -[LibraryClasses]
> - BaseLib
> - DebugLib
> - BaseMemoryLib
> - MemoryAllocationLib
> - PcdLib
> - SiliconInitLib
> -
> -[Packages]
> - MinPlatformPkg/MinPlatformPkg.dec
> - ClevoOpenBoardPkg/OpenBoardPkg.dec
> - MdePkg/MdePkg.dec
> - MdeModulePkg/MdeModulePkg.dec
> - KabylakeSiliconPkg/SiPkg.dec
> -
> -[Sources]
> - PeiN1xxWUDetect.c
> - PeiN1xxWUInitPreMemLib.c
> - N1xxWUHsioPtssTables.c
> - N1xxWUSpdTable.c
> - PeiBoardInitPreMemLib.c
> -
> -[Pcd]
> - gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort
> -
> - # PCH-LP HSIO PTSS Table
> - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1
> - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2
> - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size
> - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size
> -
> - # PCH-H HSIO PTSS Table
> - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1
> - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2
> - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size
> - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size
> -
> - # SA Misc Config
> - gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd
> - gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor
> - gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget
> - gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap
> - gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize
> - gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram
> - gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize
> - gBoardModuleTokenSpaceGuid.PcdMrcSpdData
> - gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize
> -
> - # PEG Reset By GPIO
> - gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo
> - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo
> - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo
> - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive
> - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo
> - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo
> - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive
> -
> -
> - # SPD Address Table
> - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0
> - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1
> - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2
> - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3
> -
> - # CA Vref Configuration
> -
> - # Root Port Clock Info
> - gBoardModuleTokenSpaceGuid.PcdRootPort0ClkInfo
> - gBoardModuleTokenSpaceGuid.PcdRootPort4ClkInfo
> - gBoardModuleTokenSpaceGuid.PcdRootPort5ClkInfo
> - gBoardModuleTokenSpaceGuid.PcdRootPort7ClkInfo
> - gBoardModuleTokenSpaceGuid.PcdRootPort8ClkInfo
> - gBoardModuleTokenSpaceGuid.PcdRootPort9ClkInfo
> - gBoardModuleTokenSpaceGuid.PcdRootPortLanClkInfo
> -
> - # USB 2.0 Port AFE
> - gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe
> - gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe
> - gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe
> - gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe
> - gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe
> - gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe
> - gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe
> - gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe
> - gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe
> - gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe
> -
> - # USB 2.0 Port Over Current Pin
> - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0
> - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1
> - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2
> - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3
> - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4
> - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5
> - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6
> - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7
> - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8
> - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9
> - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10
> - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11
> - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12
> - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13
> -
> - # USB 3.0 Port Over Current Pin
> - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0
> - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1
> - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2
> - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3
> - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4
> - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5
> -
> - # Misc
> - gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent
> -
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMult
> iBoardInitPostMemLib.inf
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMult
> iBoardInitPostMemLib.inf
> deleted file mode 100644
> index 47efb21a79..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMult
> iBoardInitPostMemLib.inf
> +++ /dev/null
> @@ -1,55 +0,0 @@
> -## @file
> -# Component information file for N1xxWUInitLib in PEI post memory phase.
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -##
> -
> -[Defines]
> - INF_VERSION = 0x00010005
> - BASE_NAME = PeiN1xxWUMultiBoardInitLib
> - FILE_GUID =
> C7D39F17-E5BA-41D9-8DFE-FF9017499280
> - MODULE_TYPE = BASE
> - VERSION_STRING = 1.0
> - LIBRARY_CLASS = NULL
> - CONSTRUCTOR =
> PeiN1xxWUMultiBoardInitLibConstructor
> -
> -[LibraryClasses]
> - BaseLib
> - DebugLib
> - BaseMemoryLib
> - MemoryAllocationLib
> - GpioExpanderLib
> - PcdLib
> - SiliconInitLib
> - MultiBoardInitSupportLib
> -
> -[Packages]
> - MinPlatformPkg/MinPlatformPkg.dec
> - ClevoOpenBoardPkg/OpenBoardPkg.dec
> - MdePkg/MdePkg.dec
> - MdeModulePkg/MdeModulePkg.dec
> - KabylakeSiliconPkg/SiPkg.dec
> -
> -[Sources]
> - PeiN1xxWUInitPostMemLib.c
> - N1xxWUGpioTable.c
> - N1xxWUHdaVerbTables.c
> - PeiMultiBoardInitPostMemLib.c
> -
> -[FixedPcd]
> -
> -[Pcd]
> - gBoardModuleTokenSpaceGuid.PcdBoardGpioTable
> - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize
> - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel
> -
> - gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable
> - gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize
> -
> - gBoardModuleTokenSpaceGuid.PcdHdaVerbTable
> -
> - gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTable
> - gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMult
> iBoardInitPreMemLib.inf
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMult
> iBoardInitPreMemLib.inf
> deleted file mode 100644
> index 0f6be110c0..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMult
> iBoardInitPreMemLib.inf
> +++ /dev/null
> @@ -1,137 +0,0 @@
> -## @file
> -# Component information file for PEI N1xxWU Board Init Pre-Mem Library
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -##
> -
> -[Defines]
> - INF_VERSION = 0x00010005
> - BASE_NAME =
> PeiN1xxWUMultiBoardInitPreMemLib
> - FILE_GUID =
> EA05BD43-136F-45EE-BBBA-27D75817574F
> - MODULE_TYPE = BASE
> - VERSION_STRING = 1.0
> - LIBRARY_CLASS = NULL
> - CONSTRUCTOR =
> PeiN1xxWUMultiBoardInitPreMemLibConstructor
> -
> -[LibraryClasses]
> - BaseLib
> - DebugLib
> - BaseMemoryLib
> - MemoryAllocationLib
> - PcdLib
> - SiliconInitLib
> - MultiBoardInitSupportLib
> -
> -[Packages]
> - MinPlatformPkg/MinPlatformPkg.dec
> - ClevoOpenBoardPkg/OpenBoardPkg.dec
> - MdePkg/MdePkg.dec
> - MdeModulePkg/MdeModulePkg.dec
> - KabylakeSiliconPkg/SiPkg.dec
> -
> -[Sources]
> - PeiN1xxWUInitPreMemLib.c
> - N1xxWUHsioPtssTables.c
> - N1xxWUSpdTable.c
> - PeiMultiBoardInitPreMemLib.c
> - PeiN1xxWUDetect.c
> -
> -[Pcd]
> - gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort
> -
> - # PCH-LP HSIO PTSS Table
> - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1
> - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2
> - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size
> - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size
> -
> - # PCH-H HSIO PTSS Table
> - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1
> - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2
> - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size
> - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size
> -
> - # SA Misc Config
> - gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd
> - gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor
> - gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget
> - gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap
> - gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize
> - gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram
> - gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize
> - gBoardModuleTokenSpaceGuid.PcdMrcSpdData
> - gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize
> - gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig
> - gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl
> - gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved
> -
> - # PEG Reset By GPIO
> - gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo
> - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo
> - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo
> - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive
> - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo
> - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo
> - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive
> -
> -
> - # SPD Address Table
> - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0
> - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1
> - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2
> - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3
> -
> - # CA Vref Configuration
> -
> - # Root Port Clock Info
> - gBoardModuleTokenSpaceGuid.PcdRootPort0ClkInfo
> - gBoardModuleTokenSpaceGuid.PcdRootPort4ClkInfo
> - gBoardModuleTokenSpaceGuid.PcdRootPort5ClkInfo
> - gBoardModuleTokenSpaceGuid.PcdRootPort7ClkInfo
> - gBoardModuleTokenSpaceGuid.PcdRootPort8ClkInfo
> - gBoardModuleTokenSpaceGuid.PcdRootPort9ClkInfo
> - gBoardModuleTokenSpaceGuid.PcdRootPortLanClkInfo
> -
> - # USB 2.0 Port AFE
> - gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe
> - gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe
> - gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe
> - gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe
> - gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe
> - gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe
> - gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe
> - gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe
> - gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe
> - gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe
> -
> - # USB 2.0 Port Over Current Pin
> - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0
> - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1
> - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2
> - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3
> - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4
> - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5
> - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6
> - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7
> - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8
> - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9
> - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10
> - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11
> - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12
> - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13
> -
> - # USB 3.0 Port Over Current Pin
> - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0
> - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1
> - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2
> - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3
> - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4
> - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5
> -
> - # Misc
> - gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent
> -
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platform/Intel/Min
> PlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platform/Intel/Min
> PlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
> deleted file mode 100644
> index 76dd67d1a8..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platform/Intel/Min
> PlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
> +++ /dev/null
> @@ -1,67 +0,0 @@
> -### @file
> -# Component information file for the Platform Init Pre-Memory PEI module.
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -###
> -
> -[Defines]
> - INF_VERSION = 0x00010017
> - BASE_NAME = PlatformInitPreMem
> - FILE_GUID =
> EEEE611D-F78F-4FB9-B868-55907F169280
> - VERSION_STRING = 1.0
> - MODULE_TYPE = PEIM
> - ENTRY_POINT = PlatformInitPreMemEntryPoint
> -
> -[LibraryClasses]
> - BaseMemoryLib
> - BoardInitLib
> - DebugLib
> - HobLib
> - IoLib
> - MemoryAllocationLib
> - MtrrLib
> - PeimEntryPoint
> - PeiServicesLib
> - ReportFvLib
> - TestPointCheckLib
> - TimerLib
> -
> -[Packages]
> - MinPlatformPkg/MinPlatformPkg.dec
> - MdeModulePkg/MdeModulePkg.dec
> - MdePkg/MdePkg.dec
> - UefiCpuPkg/UefiCpuPkg.dec
> -
> -[Pcd]
> - gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode
> ## CONSUMES
> - gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ##
> CONSUMES
> - gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ##
> CONSUMES
> - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit ##
> CONSUMES
> - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit ##
> CONSUMES
> -
> -[FixedPcd]
> - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize
> ## CONSUMES
> - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize
> ## CONSUMES
> - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize
> ## CONSUMES
> - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize
> ## CONSUMES
> - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize
> ## CONSUMES
> -
> -[Sources]
> - PlatformInitPreMem.c
> -
> -[Ppis]
> - gEfiPeiMemoryDiscoveredPpiGuid
> - gEfiPeiMasterBootModePpiGuid ## PRODUCES
> - gEfiPeiBootInRecoveryModePpiGuid ## PRODUCES
> - gEfiPeiReadOnlyVariable2PpiGuid
> - gPeiBaseMemoryTestPpiGuid
> - gPeiPlatformMemorySizePpiGuid
> -
> -[Guids]
> - gEfiMemoryTypeInformationGuid
> -
> -[Depex]
> - gEfiPeiReadOnlyVariable2PpiGuid
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPoli
> cyUpdateLib/DxeSiliconPolicyUpdateLib.inf
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPoli
> cyUpdateLib/DxeSiliconPolicyUpdateLib.inf
> deleted file mode 100644
> index dd7047b9cf..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPoli
> cyUpdateLib/DxeSiliconPolicyUpdateLib.inf
> +++ /dev/null
> @@ -1,49 +0,0 @@
> -## @file
> -# Component information file for DXE silicon policy update library
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -##
> -
> -[Defines]
> - INF_VERSION = 0x00010005
> - BASE_NAME = DxeSiliconUpdateLib
> - FILE_GUID =
> C523609D-E354-416B-B24F-33468D4BD21D
> - MODULE_TYPE = DXE_DRIVER
> - VERSION_STRING = 1.0
> - LIBRARY_CLASS = SiliconUpdateLib
> -
> -[LibraryClasses]
> - BaseLib
> - PcdLib
> - DebugLib
> -
> -[Packages]
> - MdePkg/MdePkg.dec
> - KabylakeSiliconPkg/SiPkg.dec
> - MinPlatformPkg/MinPlatformPkg.dec
> - ClevoOpenBoardPkg/OpenBoardPkg.dec
> -
> -[Sources]
> - DxeSiliconPolicyUpdateLib.c
> - DxeGopPolicyInit.c
> - DxeSaPolicyUpdate.c
> -
> -[Pcd]
> - gBoardModuleTokenSpaceGuid.PcdIntelGopEnable
> - gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid
> -
> -[Protocols]
> - gEfiFirmwareVolume2ProtocolGuid ## CONSUMES
> - gSaPolicyProtocolGuid ## CONSUMES
> - gDxeSiPolicyProtocolGuid ## PRODUCES
> - gGopPolicyProtocolGuid ## PRODUCES
> -
> -[Guids]
> - gMiscDxeConfigGuid
> -
> -[Depex]
> - gEfiVariableArchProtocolGuid
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/PciHotPlug/PciHotPlug.h
> b/Platform/Intel/ClevoOpenBoardPkg/Features/PciHotPlug/PciHotPlug.h
> deleted file mode 100644
> index 53274c17c5..0000000000
> --- a/Platform/Intel/ClevoOpenBoardPkg/Features/PciHotPlug/PciHotPlug.h
> +++ /dev/null
> @@ -1,130 +0,0 @@
> -/**@file
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#ifndef _PCI_HOT_PLUG_H_
> -#define _PCI_HOT_PLUG_H_
> -
> -//
> -// External include files do NOT need to be explicitly specified in real EDKII
> -// environment
> -//
> -#include <Base.h>
> -#include <Library/UefiBootServicesTableLib.h>
> -#include <Library/UefiRuntimeServicesTableLib.h>
> -#include <Library/DebugLib.h>
> -#include <Library/BaseMemoryLib.h>
> -#include <Library/MemoryAllocationLib.h>
> -#include <IndustryStandard/Acpi10.h>
> -#include <Protocol/PciHotPlugInit.h>
> -#include <Protocol/PciRootBridgeIo.h>
> -#include <Library/DevicePathLib.h>
> -#include <Library/UefiLib.h>
> -#include <Guid/HobList.h>
> -#include <Library/HobLib.h>
> -#include <Protocol/SaPolicy.h>
> -
> -#define PCI_HOT_PLUG_DRIVER_PRIVATE_SIGNATURE SIGNATURE_32 ('G', 'U',
> 'L', 'P')
> -
> -#define ACPI \
> - { \
> - { ACPI_DEVICE_PATH, ACPI_DP, { (UINT8) (sizeof
> (ACPI_HID_DEVICE_PATH)), (UINT8) \
> - ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) } }, EISA_PNP_ID (0x0A03), 0 \
> - }
> -
> -#define PCI(device, function) \
> - { \
> - { HARDWARE_DEVICE_PATH, HW_PCI_DP, { (UINT8) (sizeof
> (PCI_DEVICE_PATH)), (UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) } }, \
> - (UINTN) function, (UINTN) device \
> - }
> -
> -#define END \
> - { \
> - END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE,
> { END_DEVICE_PATH_LENGTH, 0 } \
> - }
> -
> -#define LPC(eisaid, function) \
> - { \
> - { ACPI_DEVICE_PATH, ACPI_DP, { (UINT8) (sizeof
> (ACPI_HID_DEVICE_PATH)), (UINT8) \
> - ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) } }, EISA_PNP_ID (eisaid),
> function \
> - }
> -
> -typedef struct PCIE_HOT_PLUG_DEVICE_PATH {
> - ACPI_HID_DEVICE_PATH PciRootBridgeNode;
> - PCI_DEVICE_PATH PciRootPortNode;
> - EFI_DEVICE_PATH_PROTOCOL EndDeviceNode;
> -} PCIE_HOT_PLUG_DEVICE_PATH;
> -
> -typedef struct {
> - UINTN Signature;
> - EFI_HANDLE Handle; // Handle for protocol this
> driver installs on
> - EFI_PCI_HOT_PLUG_INIT_PROTOCOL HotPlugInitProtocol;
> -} PCI_HOT_PLUG_INSTANCE;
> -
> -/**
> - This procedure returns a list of Root Hot Plug controllers that require
> - initialization during boot process
> -
> - @param[in] This The pointer to the instance of the
> EFI_PCI_HOT_PLUG_INIT protocol.
> - @param[out] HpcCount The number of Root HPCs returned.
> - @param[out] HpcList The list of Root HPCs. HpcCount defines the
> number of elements in this list.
> -
> - @retval EFI_SUCCESS.
> -**/
> -EFI_STATUS
> -EFIAPI
> -GetRootHpcList (
> - IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,
> - OUT UINTN *PhpcCount,
> - OUT EFI_HPC_LOCATION **PhpcList
> - );
> -
> -/**
> - This procedure Initializes one Root Hot Plug Controller
> - This process may casue initialization of its subordinate buses
> -
> - @param[in] This The pointer to the instance of the
> EFI_PCI_HOT_PLUG_INIT protocol.
> - @param[in] HpcDevicePath The Device Path to the HPC that is being
> initialized.
> - @param[in] HpcPciAddress The address of the Hot Plug Controller
> function on the PCI bus.
> - @param[in] Event The event that should be signaled when
> the Hot Plug Controller initialization is complete. Set to NULL if the caller
> wants to wait until the entire initialization process is complete. The event
> must be of the type EFI_EVT_SIGNAL.
> - @param[out] HpcState The state of the Hot Plug Controller
> hardware. The type EFI_Hpc_STATE is defined in section 3.1.
> -
> - @retval EFI_SUCCESS.
> -**/
> -EFI_STATUS
> -EFIAPI
> -InitializeRootHpc (
> - IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,
> - IN EFI_DEVICE_PATH_PROTOCOL *PhpcDevicePath,
> - IN UINT64 PhpcPciAddress,
> - IN EFI_EVENT Event, OPTIONAL
> - OUT EFI_HPC_STATE *PhpcState
> - );
> -
> -/**
> - Returns the resource padding required by the PCI bus that is controlled
> by the specified Hot Plug Controller.
> -
> - @param[in] This The pointer to the instance of the
> EFI_PCI_HOT_PLUG_INIT protocol. initialized.
> - @param[in] HpcDevicePath The Device Path to the Hot Plug
> Controller.
> - @param[in] HpcPciAddress The address of the Hot Plug Controller
> function on the PCI bus.
> - @param[out] HpcState The state of the Hot Plug Controller
> hardware. The type EFI_HPC_STATE is defined in section 3.1.
> - @param[out] Padding This is the amount of resource padding
> required by the PCI bus under the control of the specified Hpc. Since the
> caller does not know the size of this buffer, this buffer is allocated by the
> callee and freed by the caller.
> - @param[out] Attribute Describes how padding is accounted for.
> -
> - @retval EFI_SUCCESS.
> -**/
> -EFI_STATUS
> -EFIAPI
> -GetResourcePadding (
> - IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,
> - IN EFI_DEVICE_PATH_PROTOCOL *PhpcDevicePath,
> - IN UINT64 PhpcPciAddress,
> - OUT EFI_HPC_STATE *PhpcState,
> - OUT VOID **Padding,
> - OUT EFI_HPC_PADDING_ATTRIBUTES *Attributes
> - );
> -
> -#endif
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Acpi/TbtNvsArea
> Def.h
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Acpi/TbtNvsAre
> aDef.h
> deleted file mode 100644
> index e988bdd712..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Acpi/TbtNvsArea
> Def.h
> +++ /dev/null
> @@ -1,62 +0,0 @@
> -/**@file
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> - //
> - // Define TBT NVS Area operation region.
> - //
> -#ifndef _TBT_NVS_AREA_DEF_H_
> -#define _TBT_NVS_AREA_DEF_H_
> -
> -#pragma pack (push,1)
> -typedef struct {
> - UINT8 ThunderboltSmiFunction; ///< Offset 0
> Thunderbolt(TM) SMI Function Number
> - UINT8 ThunderboltHotSmi; ///< Offset 1
> SMI on Hot Plug for TBT devices
> - UINT8 TbtWin10Support; ///< Offset 2
> TbtWin10Support
> - UINT8 TbtGpioFilter; ///< Offset 3
> Gpio filter to detect USB Hotplug event
> - UINT8 ThunderboltHotNotify; ///< Offset 4
> Notify on Hot Plug for TBT devices
> - UINT8 TbtSelector; ///< Offset 5
> Thunderbolt(TM) Root port selector
> - UINT8 WAKFinished; ///< Offset 6
> WAK Finished
> - UINT8 DiscreteTbtSupport; ///< Offset 7
> Thunderbolt(TM) support
> - UINT8 TbtAcpiRemovalSupport; ///< Offset 8
> TbtAcpiRemovalSupport
> - UINT32 TbtFrcPwrEn; ///< Offset 9
> TbtFrcPwrEn
> - UINT32 TbtFrcPwrGpioNo0; ///< Offset 13
> TbtFrcPwrGpioNo
> - UINT8 TbtFrcPwrGpioLevel0; ///< Offset 17
> TbtFrcPwrGpioLevel
> - UINT32 TbtCioPlugEventGpioNo0; ///< Offset 18
> TbtCioPlugEventGpioNo
> - UINT32 TbtPcieRstGpioNo0; ///< Offset 22
> TbtPcieRstGpioNo
> - UINT8 TbtPcieRstGpioLevel0; ///< Offset 26
> TbtPcieRstGpioLevel
> - UINT8 CurrentDiscreteTbtRootPort; ///< Offset 27
> Current Port that has plug event
> - UINT8 RootportSelected0; ///< Offset 28
> Root port Selected by the User
> - UINT8 RootportSelected0Type; ///< Offset 29
> Root port Type
> - UINT8 RootportSelected1; ///< Offset 30
> Root port Selected by the User
> - UINT8 RootportSelected1Type; ///< Offset 31
> Root port Type
> - UINT8 RootportEnabled0; ///< Offset 32
> Root port Enabled by the User
> - UINT8 RootportEnabled1; ///< Offset 33
> Root port Enabled by the User
> - UINT32 TbtFrcPwrGpioNo1; ///< Offset 34
> TbtFrcPwrGpioNo
> - UINT8 TbtFrcPwrGpioLevel1; ///< Offset 38
> TbtFrcPwrGpioLevel
> - UINT32 TbtCioPlugEventGpioNo1; ///< Offset 39
> TbtCioPlugEventGpioNo
> - UINT32 TbtPcieRstGpioNo1; ///< Offset 43
> TbtPcieRstGpioNo
> - UINT8 TbtPcieRstGpioLevel1; ///< Offset 47
> TbtPcieRstGpioLevel
> - UINT8 TBtCommonGpioSupport; ///< Offset
> 48 Set if Single GPIO is used for Multi/Different Controller Hot plug
> support
> - UINT8 CurrentDiscreteTbtRootPortType; ///< Offset 49
> Root Port type for which SCI Triggered
> - UINT8 TrOsup; ///< Offset 50
> Titan Ridge Osup command
> - UINT8 TbtAcDcSwitch; ///< Offset 51
> TBT Dynamic AcDc L1
> - UINT8 DTbtControllerEn0; ///< Offset 52
> DTbtController0 is enabled or not.
> - UINT8 DTbtControllerEn1; ///< Offset 53
> DTbtController1 is enabled or not.
> - UINT8 TbtAspm; ///< Offset 54
> ASPM setting for all the PCIe device in TBT daisy chain.
> - UINT8 TbtL1SubStates; ///< Offset 55
> L1 SubState for for all the PCIe device in TBT daisy chain.
> - UINT8 TbtSetClkReq; ///< Offset 56
> CLK REQ for all the PCIe device in TBT daisy chain.
> - UINT8 TbtLtr; ///< Offset 57
> LTR for for all the PCIe device in TBT daisy chain.
> - UINT8 TbtPtm; ///< Offset 58
> PTM for for all the PCIe device in TBT daisy chain.
> - UINT8 TbtWakeupSupport; ///< Offset 59
> Send Go2SxNoWake or GoSxWake according to TbtWakeupSupport
> - UINT16 Rtd3TbtOffDelay; ///< Offset 60
> Rtd3TbtOffDelay TBT RTD3 Off Delay
> - UINT8 TbtSxWakeSwitchLogicEnable; ///< Offset 62
> TbtSxWakeSwitchLogicEnable Set True if TBT_WAKE_N will be routed to PCH
> WakeB at Sx entry point. HW logic is required.
> - UINT8 Rtd3TbtSupport; ///< Offset 63
> Enable Rtd3 support for TBT. Corresponding to Rtd3Tbt in Setup.
> - UINT8 Rtd3TbtClkReq; ///< Offset 64
> Enable TBT RTD3 CLKREQ mask.
> - UINT16 Rtd3TbtClkReqDelay; ///< Offset 65
> TBT RTD3 CLKREQ mask delay.
> -} TBT_NVS_AREA;
> -
> -#pragma pack(pop)
> -#endif
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/DxeTbtP
> olicyLib.h
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/DxeTbtP
> olicyLib.h
> deleted file mode 100644
> index 3ac3d88a33..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/DxeTbtP
> olicyLib.h
> +++ /dev/null
> @@ -1,46 +0,0 @@
> -/** @file
> - Prototype of the DxeTbtPolicyLib library.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -#ifndef _DXE_TBT_POLICY_LIB_H_
> -#define _DXE_TBT_POLICY_LIB_H_
> -
> -/**
> - Install TBT Policy.
> -
> - @param[in] ImageHandle Image handle of this driver.
> -
> - @retval EFI_SUCCESS The policy is installed.
> - @retval EFI_OUT_OF_RESOURCES Insufficient resources to
> create buffer
> -
> -**/
> -EFI_STATUS
> -EFIAPI
> -InstallTbtPolicy (
> - IN EFI_HANDLE ImageHandle
> - );
> -
> -/**
> - Update Tbt Policy Callback.
> -
> - @param[in] Event A pointer to the Event that triggered the
> callback.
> - @param[in] Context A pointer to private data registered with the
> callback function.
> -
> -**/
> -VOID
> -EFIAPI
> -UpdateTbtPolicyCallback (
> - VOID
> - );
> -
> -/**
> - Print DXE TBT Policy
> -**/
> -VOID
> -TbtPrintDxePolicyConfig (
> - VOID
> - );
> -#endif // _DXE_TBT_POLICY_LIB_H_
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/PeiTbtPo
> licyLib.h
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/PeiTbtPo
> licyLib.h
> deleted file mode 100644
> index cf9ca8f0c8..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/PeiTbtPo
> licyLib.h
> +++ /dev/null
> @@ -1,41 +0,0 @@
> -/** @file
> - Prototype of the PeiTbtPolicyLib library.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -#ifndef _PEI_TBT_POLICY_LIB_H_
> -#define _PEI_TBT_POLICY_LIB_H_
> -
> -/**
> - Install Tbt Policy
> -
> - @retval EFI_SUCCESS The policy is installed.
> - @retval EFI_OUT_OF_RESOURCES Insufficient resources to
> create buffer
> -
> -**/
> -EFI_STATUS
> -EFIAPI
> -InstallPeiTbtPolicy (
> - VOID
> - );
> -
> -/**
> - Update PEI TBT Policy
> -**/
> -VOID
> -EFIAPI
> -UpdatePeiTbtPolicy (
> - VOID
> - );
> -
> -/**
> - Print PEI TBT Policy
> -**/
> -VOID
> -EFIAPI
> -TbtPrintPeiPolicyConfig (
> - VOID
> - );
> -#endif // _DXE_TBT_POLICY_LIB_H_
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/TbtCom
> monLib.h
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/TbtCom
> monLib.h
> deleted file mode 100644
> index 90966fa4cc..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/TbtCom
> monLib.h
> +++ /dev/null
> @@ -1,241 +0,0 @@
> -/**@file
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -#ifndef _TBT_COMMON_LIB_H_
> -#define _TBT_COMMON_LIB_H_
> -
> -#include <Library/BaseLib.h>
> -#include <Library/PciSegmentLib.h>
> -#include <Library/GpioExpanderLib.h>
> -
> -#define DTBT_CONTROLLER 0x00
> -#define DTBT_TYPE_PCH 0x01
> -#define DTBT_TYPE_PEG 0x02
> -#define TBT2PCIE_DTBT_R 0x548
> -#define PCIE2TBT_DTBT_R 0x54C
> -
> -//
> -// Thunderbolt FW OS capability
> -//
> -#define NO_OS_NATIVE_SUPPORT 0
> -#define OS_NATIVE_SUPPORT_ONLY 1
> -#define OS_NATIVE_SUPPORT_RTD3 2
> -
> -#define DTBT_SAVE_STATE_OFFSET BIT0 // Bits 0-3 is for DTBT (only bit 0 is
> in use)
> -/**
> -Get Tbt2Pcie Register Offset
> -
> - at retval Register Register Variable
> -**/
> -
> -#define GET_TBT2PCIE_REGISTER_ADDRESS(Segment, Bus, Device, Function,
> RegisterAddress) \
> -RegisterAddress = PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device,
> Function, TBT2PCIE_DTBT_R); \
> -
> -/**
> -Get Pcie2Tbt Register Offset
> -
> - at retval Register Register Variable
> -**/
> -
> -#define GET_PCIE2TBT_REGISTER_ADDRESS(Segment, Bus, Device, Function,
> RegisterAddress) \
> -RegisterAddress = PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device,
> Function, PCIE2TBT_DTBT_R); \
> -
> -#define PCIE2TBT_VLD_B BIT0
> -#define TBT2PCIE_DON_R BIT0
> -#define TBT_MAIL_BOX_DELAY (100*1000)
> -#define TBT_5S_TIMEOUT 50
> -#define TBT_1S_TIMEOUT 10
> -#define TBT_3S_TIMEOUT 30
> -
> -#define PCIE2TBT_GO2SX (0x02 << 1)
> -#define PCIE2TBT_GO2SX_NO_WAKE (0x03 << 1)
> -#define PCIE2TBT_SX_EXIT_TBT_CONNECTED (0x04 << 1)
> -#define PCIE2TBT_SX_EXIT_NO_TBT_CONNECTED (0x05 << 1)
> -#define PCIE2TBT_OS_UP (0x06 << 1)
> -#define PCIE2TBT_SET_SECURITY_LEVEL (0x08 << 1)
> -#define PCIE2TBT_GET_SECURITY_LEVEL (0x09 << 1)
> -#define PCIE2TBT_CM_AUTH_MODE_ENTER (0x10 << 1)
> -#define PCIE2TBT_CM_AUTH_MODE_EXIT (0x11 << 1)
> -#define PCIE2TBT_BOOT_ON (0x18 << 1)
> -#define PCIE2TBT_BOOT_OFF (0x19 << 1)
> -#define PCIE2TBT_USB_ON (0x19 << 1)
> -#define PCIE2TBT_GET_ENUMERATION_METHOD (0x1A << 1)
> -#define PCIE2TBT_SET_ENUMERATION_METHOD (0x1B << 1)
> -#define PCIE2TBT_POWER_CYCLE (0x1C << 1)
> -#define PCIE2TBT_PREBOOTACL (0x1E << 1)
> -#define CONNECT_TOPOLOGY_COMMAND (0x1F << 1)
> -
> -#define RESET_HR_BIT BIT0
> -#define ENUMERATE_HR_BIT BIT1
> -#define AUTO 0x0
> -
> -//
> -//Thunder Bolt Device IDs
> -//
> -
> -//
> -// Alpine Ridge HR device IDs
> -//
> -#define AR_HR_2C 0x1576
> -#define AR_HR_4C 0x1578
> -#define AR_XHC 0x15B5
> -#define AR_XHC_4C 0x15B6
> -#define AR_HR_LP 0x15C0
> -//
> -// Alpine Ridge C0 HR device IDs
> -//
> -#define AR_HR_C0_2C 0x15DA
> -#define AR_HR_C0_4C 0x15D3
> -//
> -// Titan Ridge HR device IDs
> -//
> -#define TR_HR_2C 0x15E7
> -#define TR_HR_4C 0x15EA
> -//
> -//End of Thunderbolt(TM) Device IDs
> -//
> -
> -typedef struct _DEV_ID {
> - UINT8 Segment;
> - UINT8 Bus;
> - UINT8 Dev;
> - UINT8 Fun;
> -} DEV_ID;
> -
> -//@todo Seems to only be used by Platform/TBT/Smm/TbtSmm.inf
> -//@todo should refactor this to only be present in that driver
> -//@todo also definitions like this should never be in a .h file anyway
> -//@todo this is a quick hack to get things compiling for now
> -#ifdef __GNUC__
> -#pragma GCC diagnostic warning "-Wunused-variable"
> -#endif
> -
> -/**
> -Based on the Security Mode Selection, BIOS drives FORCE_PWR.
> -
> - at param[in] GpioNumber
> - at param[in] Value
> -**/
> -VOID
> -ForceDtbtPower(
> - IN UINT8 GpioAccessType,
> - IN UINT8 Expander,
> - IN UINT32 GpioNumber,
> - IN BOOLEAN Value
> -);
> -
> -/**
> - Get Security Level.
> - @param[in] Bus Bus number for Host Router (DTBT)
> - @param[in] Device Device number for Host Router (DTBT)
> - @param[in] Function Function number for Host Router (DTBT)
> - @param[in] Timeout Time out with 100 ms garnularity
> -**/
> -UINT8
> -GetSecLevel (
> - IN UINT8 Bus,
> - IN UINT8 Device,
> - IN UINT8 Function,
> - IN UINT8 Command,
> - IN UINT32 Timeout
> - );
> -
> -/**
> - Set Security Level.
> - @param[in] Data Security State
> - @param[in] Bus Bus number for Host Router (DTBT)
> - @param[in] Device Device number for Host Router (DTBT)
> - @param[in] Function Function number for Host Router (DTBT)
> - @param[in] Timeout Time out with 100 ms garnularity
> -**/
> -BOOLEAN
> -SetSecLevel (
> - IN UINT8 Data,
> - IN UINT8 Bus,
> - IN UINT8 Device,
> - IN UINT8 Function,
> - IN UINT8 Command,
> - IN UINT32 Timeout
> - );
> -
> -/**
> -Execute TBT Mail Box Command
> -
> - at param[in] Command TBT Command
> - at param[in] Bus Bus number for Host Router (DTBT)
> - at param[in] Device Device number for Host Router (DTBT)
> - at param[in] Function Function number for Host Router (DTBT)
> - at param[in] Timeout Time out with 100 ms garnularity
> - at Retval true if command executes succesfully
> -**/
> -BOOLEAN
> -TbtSetPcie2TbtCommand(
> - IN UINT8 Command,
> - IN UINT8 Bus,
> - IN UINT8 Device,
> - IN UINT8 Function,
> - IN UINT32 Timeout
> -);
> -/**
> - Check connected TBT controller is supported or not by DeviceID
> -
> - @param[in] DeviceID DeviceID of of TBT controller
> -
> -
> - @retval TRUE Valid DeviceID
> - @retval FALSE Invalid DeviceID
> -**/
> -
> -BOOLEAN
> -IsTbtHostRouter (
> - IN UINT16 DeviceID
> - );
> -
> -/**
> - Get Pch/Peg Pcie Root Port Device and Function Number for TBT by Root
> Port physical Number
> -
> - @param[in] RpNumber Root port physical number.
> (0-based)
> - @param[out] RpDev Return corresponding root port
> device number.
> - @param[out] RpFun Return corresponding root port
> function number.
> -
> - @retval EFI_SUCCESS Root port device and function is
> retrieved
> -**/
> -EFI_STATUS
> -EFIAPI
> -GetDTbtRpDevFun(
> - IN BOOLEAN Type,
> - IN UINTN RpNumber,
> - OUT UINTN *RpDev,
> - OUT UINTN *RpFunc
> - );
> -
> -/**
> - Internal function to Wait for Tbt2PcieDone Bit.to Set or clear
> - @param[in] CommandOffsetAddress Tbt2Pcie Register Address
> - @param[in] TimeOut Time out with 100 ms
> garnularity
> - @param[in] Tbt2PcieDone Wait condition (wait for Bit
> to Clear/Set)
> - @param[out] *Tbt2PcieValue Function Register value
> -**/
> -BOOLEAN
> -InternalWaitforCommandCompletion (
> - IN UINT64 CommandOffsetAddress,
> - IN UINT32 TimeOut,
> - IN BOOLEAN Tbt2PcieDone,
> - OUT UINT32 *Tbt2PcieValue
> - );
> -
> -VOID
> -GetRootporttoSetResourcesforTbt (
> - IN UINTN RpIndex,
> - OUT UINT8 *RsvdExtraBusNum,
> - OUT UINT16 *RsvdPcieMegaMem,
> - OUT UINT8 *PcieMemAddrRngMax,
> - OUT UINT16 *RsvdPciePMegaMem,
> - OUT UINT8 *PciePMemAddrRngMax,
> - OUT BOOLEAN *SetResourceforTbt
> - );
> -
> -#endif
> \ No newline at end of file
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Ppi/PeiTbtPolicy.
> h
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Ppi/PeiTbtPolicy.
> h
> deleted file mode 100644
> index 09b74df889..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Ppi/PeiTbtPolicy.
> h
> +++ /dev/null
> @@ -1,29 +0,0 @@
> -/** @file
> -TBT PEI Policy
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -#ifndef _PEI_TBT_POLICY_H_
> -#define _PEI_TBT_POLICY_H_
> -
> -#include <TbtPolicyCommonDefinition.h>
> -
> -#pragma pack(push, 1)
> -
> -#define PEI_TBT_POLICY_REVISION 1
> -
> -/**
> - TBT PEI configuration\n
> - <b>Revision 1</b>:
> - - Initial version.
> -**/
> -typedef struct _PEI_TBT_POLICY {
> - DTBT_COMMON_CONFIG DTbtCommonConfig;
> ///< dTbt Common Configuration
> - DTBT_CONTROLLER_CONFIG DTbtControllerConfig; ///<
> dTbt Controller Configuration
> -} PEI_TBT_POLICY;
> -
> -#pragma pack(pop)
> -
> -#endif
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Private/Library/P
> eiDTbtInitLib.h
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Private/Library/
> PeiDTbtInitLib.h
> deleted file mode 100644
> index dd31099a7d..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Private/Library/P
> eiDTbtInitLib.h
> +++ /dev/null
> @@ -1,108 +0,0 @@
> -/**@file
> - PEI DTBT Init Dispatch library Header file
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -#ifndef __PEI_DTBT_INIT_LIB_H__
> -#define __PEI_DTBT_INIT_LIB_H__
> -
> -#include <Ppi/PeiTbtPolicy.h>
> -
> -/**
> - set tPCH25 Timing to 10 ms for DTBT.
> -
> - @param[in] PEI_TBT_POLICY PeiTbtConfig
> -
> - @retval EFI_SUCCESS The function completes successfully
> - @retval EFI_UNSUPPORTED dTBT is not supported.
> -**/
> -EFI_STATUS
> -EFIAPI
> -DTbtSetTPch25Timing (
> - IN PEI_TBT_POLICY *PeiTbtConfig
> -);
> -
> -/**
> - Do ForcePower for DTBT Controller
> -
> - @param[in] PEI_TBT_POLICY PeiTbtConfig
> -
> - @retval EFI_SUCCESS The function completes successfully
> - @retval EFI_UNSUPPORTED dTBT is not supported.
> -**/
> -EFI_STATUS
> -EFIAPI
> -DTbtForcePower (
> - IN PEI_TBT_POLICY *PeiTbtConfig
> -);
> -
> -/**
> - Clear VGA Registers for DTBT.
> -
> - @param[in] PEI_TBT_POLICY PeiTbtConfig
> -
> - @retval EFI_SUCCESS The function completes successfully
> - @retval EFI_UNSUPPORTED dTBT is not supported.
> -**/
> -EFI_STATUS
> -EFIAPI
> -DTbtClearVgaRegisters (
> - IN PEI_TBT_POLICY *PeiTbtConfig
> -);
> -
> -/**
> - Exectue Mail box command "Boot On".
> -
> - @param[in] PEI_TBT_POLICY PeiTbtConfig
> -
> - @retval EFI_SUCCESS The function completes successfully
> - @retval EFI_UNSUPPORTED dTBT is not supported.
> -**/
> -EFI_STATUS
> -EFIAPI
> -DTbtBootOn (
> - IN PEI_TBT_POLICY *PeiTbtConfig
> -);
> -
> -/**
> - Exectue Mail box command "USB On".
> -
> - @param[in] PEI_TBT_POLICY PeiTbtConfig
> -
> - @retval EFI_SUCCESS The function completes successfully
> - @retval EFI_UNSUPPORTED dTBT is not supported.
> -**/
> -EFI_STATUS
> -EFIAPI
> -DTbtUsbOn (
> - IN PEI_TBT_POLICY *PeiTbtConfig
> -);
> -
> -/**
> - Exectue Mail box command "Sx Exit".
> -
> - @param[in] PEI_TBT_POLICY PeiTbtConfig
> -
> - @retval EFI_SUCCESS The function completes successfully
> - @retval EFI_UNSUPPORTED dTBT is not supported.
> -**/
> -EFI_STATUS
> -EFIAPI
> -DTbtSxExitFlow (
> - IN PEI_TBT_POLICY *PeiTbtConfig
> -);
> -/**
> - Initialize Thunderbolt(TM)
> -
> - @retval EFI_SUCCESS The function completes successfully
> - @retval others
> -**/
> -EFI_STATUS
> -EFIAPI
> -TbtInit (
> - VOID
> -);
> -
> -#endif
> \ No newline at end of file
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Private/Library/P
> eiTbtCommonInitLib.h
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Private/Library/
> PeiTbtCommonInitLib.h
> deleted file mode 100644
> index 718e858b70..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Private/Library/P
> eiTbtCommonInitLib.h
> +++ /dev/null
> @@ -1,41 +0,0 @@
> -/**@file
> - PEI TBT Common Init Dispatch library Header file
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -#ifndef __PEI_TBT_COMMON_INIT_LIB_H__
> -#define __PEI_TBT_COMMON_INIT_LIB_H__
> -
> -#include <Library/PeiServicesLib.h>
> -#include <Library/DebugLib.h>
> -#include <Library/MemoryAllocationLib.h>
> -#include <Library/BaseMemoryLib.h>
> -#include <Library/GpioLib.h>
> -#include <Library/TimerLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/PciSegmentLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/TbtCommonLib.h>
> -#include <IndustryStandard/Pci22.h>
> -#include <Library/PchPmcLib.h>
> -
> -VOID
> -TbtSetSxMode(
> -IN BOOLEAN Type,
> -IN UINT8 Bus,
> -IN UINT8 Device,
> -IN UINT8 Function,
> -IN UINT8 TbtBootOn
> -);
> -
> -VOID
> -TbtClearVgaRegisters(
> -IN UINTN Segment,
> -IN UINTN Bus,
> -IN UINTN Device,
> -IN UINTN Function
> -);
> -
> -#endif
> \ No newline at end of file
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Protocol/DxeTbt
> Policy.h
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Protocol/DxeTbt
> Policy.h
> deleted file mode 100644
> index 5167661c02..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Protocol/DxeTbt
> Policy.h
> +++ /dev/null
> @@ -1,110 +0,0 @@
> -/** @file
> -TBT DXE Policy
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -#ifndef _DXE_TBT_POLICY_H_
> -#define _DXE_TBT_POLICY_H_
> -
> -#include <TbtPolicyCommonDefinition.h>
> -
> -#pragma pack(push, 1)
> -
> -#define DXE_TBT_POLICY_REVISION 1
> -
> -//
> -// TBT Common Data Structure
> -//
> -typedef struct _TBT_COMMON_CONFIG{
> - /**
> - TBT Security Level
> - <b>0: SL0 No Security</b>, 1: SL1 User Authorization, 2: SL2 Secure
> Connect, 3: SL3 Display Port and USB
> - **/
> - UINT32 SecurityMode : 3;
> - /**
> - BIOS W/A for Hot plug of 12V USB devices cause electrical noise on PCH
> GPIOs
> - <b>0: Disabled</b>, 1: Enabled
> - **/
> - UINT32 Gpio5Filter : 1;
> - /**
> - Send Go2SxNoWake or GoSxWake according to TbtWakeupSupport
> - <b>0: Disabled</b>, 1: Enabled
> - **/
> - UINT32 TbtWakeupSupport : 1;
> - /**
> - SMI TBT enumeration
> - <b>0: Disabled</b>, 1: Enabled
> - **/
> - UINT32 TbtHotSMI : 1;
> - /**
> - Notify PCIe RP after Hot-Plug/Hot-Unplug occurred.
> - <b>0: Disabled</b>, 1: Enabled
> - **/
> - UINT32 TbtHotNotify : 1;
> - /**
> - CLK REQ for all the PCIe device in TBT daisy chain.
> - <b>0: Disabled</b>, 1: Enabled
> - **/
> - UINT32 TbtSetClkReq : 1;
> - /**
> - ASPM setting for all the PCIe device in TBT daisy chain.
> - <b>0: Disabled</b>, 1: L0s, 2: L1, 3: L0sL1
> - **/
> - UINT32 TbtAspm : 2;
> - /**
> - LTR for for all the PCIe device in TBT daisy chain.
> - <b>0: Disabled</b>, 1: Enabled
> - **/
> - UINT32 TbtLtr : 1;
> - /**
> - TBT Dynamic AC/DC L1.
> - <b>0: Disabled</b>, 1: Enabled
> - **/
> - UINT32 TbtAcDcSwitch : 1;
> - /**
> - TBT RTD3 Support.
> - <b>0: Disabled</b>, 1: Enabled
> - **/
> - UINT32 Rtd3Tbt : 1;
> - /**
> - TBT ClkReq for RTD3 Flow.
> - <b>0: Disabled</b>, 1: Enabled
> - **/
> - UINT32 Rtd3TbtClkReq : 1;
> - /**
> - TBT Win10support for Tbt FW execution mode.
> - <b>0: Disabled</b>, 1: Native, 2: Native + RTD3
> - **/
> - UINT32 Win10Support : 2;
> - UINT32 Rsvd0 : 17; ///< Reserved bits
> - UINT16 Rtd3TbtClkReqDelay;
> - UINT16 Rtd3TbtOffDelay;
> -} TBT_COMMON_CONFIG;
> -
> -//
> -// dTBT Resource Data Structure
> -//
> -typedef struct _DTBT_RESOURCE_CONFIG{
> - UINT8 DTbtPcieExtraBusRsvd; ///< Preserve Bus resource for PCIe
> RP that connect to dTBT Host Router
> - UINT16 DTbtPcieMemRsvd; ///< Preserve MEM resource for
> PCIe RP that connect to dTBT Host Router
> - UINT8 DTbtPcieMemAddrRngMax; ///< Alignment of Preserve MEM
> resource for PCIe RP that connect to dTBT Host Router
> - UINT16 DTbtPciePMemRsvd; ///< Preserve PMEM resource for
> PCIe RP that connect to dTBT Host Router
> - UINT8 DTbtPciePMemAddrRngMax; ///< Alignment of Preserve
> PMEM resource for PCIe RP that connect to dTBT Host Router
> - UINT8 Reserved[1]; ///< Reserved for DWORD alignment
> -} DTBT_RESOURCE_CONFIG;
> -
> -/**
> - TBT DXE configuration\n
> - <b>Revision 1</b>:
> - - Initial version.
> -**/
> -typedef struct _DXE_TBT_POLICY_PROTOCOL {
> - TBT_COMMON_CONFIG TbtCommonConfig;
> ///< Tbt Common Information
> - DTBT_RESOURCE_CONFIG DTbtResourceConfig; ///< dTbt Resource
> Configuration
> -} DXE_TBT_POLICY_PROTOCOL;
> -
> -#pragma pack(pop)
> -
> -#endif
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Protocol/TbtNvs
> Area.h
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Protocol/TbtNvs
> Area.h
> deleted file mode 100644
> index e57381e12c..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Protocol/TbtNvs
> Area.h
> +++ /dev/null
> @@ -1,42 +0,0 @@
> -/** @file
> - This file defines the TBT NVS Area Protocol.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#ifndef _TBT_NVS_AREA_H_
> -#define _TBT_NVS_AREA_H_
> -
> -//
> -// Platform NVS Area definition
> -//
> -#include <Acpi\TbtNvsAreaDef.h>
> -
> -//
> -// Includes
> -//
> -#define TBT_NVS_DEVICE_ENABLE 1
> -#define TBT_NVS_DEVICE_DISABLE 0
> -
> -//
> -// Forward reference for pure ANSI compatibility
> -//
> -typedef struct _TBT_NVS_AREA_PROTOCOL TBT_NVS_AREA_PROTOCOL;
> -
> -///
> -/// Extern the GUID for protocol users.
> -///
> -extern EFI_GUID gTbtNvsAreaProtocolGuid;
> -
> -#define TBT_NVS_AREA_REVISION_1 1
> -
> -//
> -// Platform NVS Area Protocol
> -//
> -typedef struct _TBT_NVS_AREA_PROTOCOL {
> - TBT_NVS_AREA *Area;
> -} TBT_NVS_AREA_PROTOCOL;
> -
> -#endif // _TBT_NVS_AREA_H_
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/TbtBoardInfo.h
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/TbtBoardInfo.h
> deleted file mode 100644
> index 13319a9cec..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/TbtBoardInfo.h
> +++ /dev/null
> @@ -1,22 +0,0 @@
> -/** @file
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -#ifndef _TBT_INFO_GUID_H_
> -#define _TBT_INFO_GUID_H_
> -#include <TbtPolicyCommonDefinition.h>
> -
> -#pragma pack(1)
> -//
> -// TBT Info HOB
> -//
> -typedef struct _TBT_INFO_HOB {
> - EFI_HOB_GUID_TYPE EfiHobGuidType;
> - DTBT_COMMON_CONFIG DTbtCommonConfig;
> ///< dTbt Common Configuration
> - DTBT_CONTROLLER_CONFIG DTbtControllerConfig;
> ///< dTbt Controller Configuration
> -} TBT_INFO_HOB;
> -#pragma pack()
> -
> -#endif
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/TbtPolicyComm
> onDefinition.h
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/TbtPolicyComm
> onDefinition.h
> deleted file mode 100644
> index eb4c79317d..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/TbtPolicyComm
> onDefinition.h
> +++ /dev/null
> @@ -1,77 +0,0 @@
> -/** @file
> -TBT Policy Common definition.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -#ifndef _TBT_POLICY_COMMON_H_
> -#define _TBT_POLICY_COMMON_H_
> -
> -#include <Library/GpioLib.h>
> -#include <IndustryStandard/Pci22.h>
> -
> -#define TYPE_PCIE 0x01
> -#define TYPE_PEG 0x02
> -
> -#pragma pack(push, 1)
> -
> -//
> -// dTBT Force Power GPIO Data Structure
> -//
> -typedef struct _DTBT_FORCE_POWER_GPIO_CONFIG {
> - UINT8 GpioAccessType; ///< Where the GPIO comes
> from [a.k.a how to access the GPIO],Where the GPIO comes from. 0: Disabled;
> 1: PCH, 2: I/O Expander
> - UINT8 Expander; ///< Applicable to
> GpioAccessType = IoExpander {TCA6424A} type
> - GPIO_PAD GpioPad; ///< GPIO Pad Number
> - BOOLEAN GpioLevel; ///< 0 = Active Low; 1 =
> Active High
> - UINT8 Reserved[1]; ///< Reserved for DWORD
> alignment
> -} DTBT_FORCE_POWER_GPIO_CONFIG;
> -
> -//
> -// dTBT CIO Plug Event GPIO Data Structure
> -//
> -typedef struct _DTBT_CIO_PLUG_EVENT_GPIO_CONFIG {
> - GPIO_PAD GpioPad; ///< GPIO Pad Number
> - UINT32 AcpiGpeSignature; ///< AcpiPlatform driver
> will change the XTBT method to the _Lxx or _Exx that we assign in this item.
> - BOOLEAN AcpiGpeSignaturePorting; ///< 0 = No porting
> required(for 2-tier GPI GPE event architecture), 1 = Porting required(for
> 1-tier GPI GPE event architecture)
> - UINT8 Reserved[3]; ///< Reserved for DWORD
> alignment
> -} DTBT_CIO_PLUG_EVENT_GPIO_CONFIG;
> -
> -//
> -// dTBT PCIE Reset GPIO Data Structure
> -//
> -typedef struct _DTBT_PCIE_RESET_GPIO_CONFIG {
> - GPIO_PAD GpioPad; ///< GPIO Pad Number
> - BOOLEAN GpioLevel; ///< 0 = Active Low; 1 =
> Active High
> - UINT8 Reserved[3]; ///< Reserved for DWORD
> alignment
> -} DTBT_PCIE_RESET_GPIO_CONFIG;
> -
> -//
> -// dTBT Controller Data Structure
> -//
> -typedef struct _DTBT_CONTROLLER_CONFIG{
> - UINT8 DTbtControllerEn; ///<
> Enable/Disable DTbtController.
> - UINT8 Type; ///< 01-Pcie
> RP, 02- PEG,Reserved. <Specific according to Board Design>
> - UINT8 PcieRpNumber; ///< RP
> Number/ PEG Port (0,1,2) that connecet to dTBT controller. <Specific
> according to Board Design>
> - DTBT_FORCE_POWER_GPIO_CONFIG ForcePwrGpio; ///< The
> GPIO pin that can force dTBT Power On. <Specific according to Board Design>
> - DTBT_CIO_PLUG_EVENT_GPIO_CONFIG CioPlugEventGpio; ///< The GPIO
> pin that can generate Hot-Plug event. <Specific according to Board Design>
> - DTBT_PCIE_RESET_GPIO_CONFIG PcieRstGpio; ///< The GPIO
> pin that is use to perform Reset when platform enters to Sx, it is required for
> platforms where PCI_RST pin connected to Tbt is controlled with GPIO
> <Specific according to Board Design>
> - UINT8 Reserved[1]; ///< Reserved
> for DWORD alignment
> -} DTBT_CONTROLLER_CONFIG;
> -
> -//
> -// dTBT Controller Data Structure
> -//
> -typedef struct _DTBT_COMMON_CONFIG{
> - UINT8 TbtBootOn; ///< Send
> BootOn Mailbox command when TbtBootOn is enabled.
> - UINT8 TbtUsbOn; ///< Send UsbOn
> Mailbox command when TbtBootOn is enabled.
> - UINT8 Gpio3ForcePwr; ///< Force GPIO to
> power on or not
> - UINT16 Gpio3ForcePwrDly; ///< The delay
> time after do ForcePwr
> - BOOLEAN DTbtSharedGpioConfiguration; ///< Multiple DTBT
> controllers share the same GPIO pin <Specific according to Board Design>
> - BOOLEAN PcieRstSupport; ///< 0 = Not
> Support, 1 = Supported. it is required for platforms where PCI_RST pin
> connected to Tbt is controlled with GPIO
> - UINT8 Reserved[1]; ///< Reserved for
> DWORD alignment
> -} DTBT_COMMON_CONFIG;
> -
> -#pragma pack(pop)
> -
> -#endif
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib/
> DxeTbtPolicyLibrary.h
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib/
> DxeTbtPolicyLibrary.h
> deleted file mode 100644
> index 75bc01e29a..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib/
> DxeTbtPolicyLibrary.h
> +++ /dev/null
> @@ -1,22 +0,0 @@
> -/** @file
> - Header file for the DxeTBTPolicy library.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -#ifndef _DXE_TBT_POLICY_LIBRARY_H_
> -#define _DXE_TBT_POLICY_LIBRARY_H_
> -
> -#include <Uefi.h>
> -#include <Library/DebugLib.h>
> -#include <Library/UefiLib.h>
> -#include <Library/UefiRuntimeServicesTableLib.h>
> -#include <Library/UefiBootServicesTableLib.h>
> -#include <Library/BaseMemoryLib.h>
> -#include <Library/MemoryAllocationLib.h>
> -#include <ConfigBlock.h>
> -#include <Library/ConfigBlockLib.h>
> -#include <Guid/EventGroup.h>
> -
> -#endif // _DXE_TBT_POLICY_LIBRARY_H_
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/P
> eiTbtPolicyLibrary.h
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/P
> eiTbtPolicyLibrary.h
> deleted file mode 100644
> index 38c5d60fab..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/P
> eiTbtPolicyLibrary.h
> +++ /dev/null
> @@ -1,17 +0,0 @@
> -/** @file
> - Header file for the PeiTBTPolicy library.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -#ifndef _PEI_TBT_POLICY_LIBRARY_H_
> -#define _PEI_TBT_POLICY_LIBRARY_H_
> -
> -#include <Library/DebugLib.h>
> -#include <Library/PeiServicesTablePointerLib.h>
> -#include <Library/PeiServicesLib.h>
> -#include <Library/BaseMemoryLib.h>
> -#include <Library/MemoryAllocationLib.h>
> -
> -#endif // _PEI_TBT_POLICY_LIBRARY_H_
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmiHan
> dler.h
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmiHan
> dler.h
> deleted file mode 100644
> index 7b06a037da..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmiHan
> dler.h
> +++ /dev/null
> @@ -1,179 +0,0 @@
> -/**@file
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -#ifndef _TBT_SMI_HANDLER_H_
> -#define _TBT_SMI_HANDLER_H_
> -
> -#include <Library/TbtCommonLib.h>
> -#include <Library/IoLib.h>
> -#include <IndustryStandard/Pci.h>
> -
> -#ifdef PROGRESS_CODE
> -#undef PROGRESS_CODE
> -#endif
> -
> -#define MAX_TBT_DEPTH 6
> -
> -#define P2P_BRIDGE (((PCI_CLASS_BRIDGE) << 8) |
> (PCI_CLASS_BRIDGE_P2P))
> -
> -#define BAR_ALIGN(v, a) ((((v) - 1) | (a)) + 1)
> -
> -#define CMD_BUS_MASTER BIT2
> -#define CMD_BM_IO (CMD_BUS_MASTER | BIT0)
> -#define CMD_BM_MEM (CMD_BUS_MASTER | BIT1)
> -#define CMD_BM_MEM_IO (CMD_BUS_MASTER | BIT1 | BIT0)
> -
> -#define DEF_CACHE_LINE_SIZE 0x20
> -#define DEF_RES_IO_PER_DEV 4
> -#define DEF_RES_MEM_PER_DEV 32
> -#define DEF_RES_PMEM_PER_DEV 32
> -
> -#define DOCK_BUSSES 8
> -
> -#define DISBL_IO_REG1C 0x01F1
> -#define DISBL_MEM32_REG20 0x0000FFF0
> -#define DISBL_PMEM_REG24 0x0001FFF1
> -
> -#define count(x) (sizeof (x) / sizeof ((x)[0]))
> -
> -#define PCIE_CAP_ID_SSID_SSVID 0x0D
> -#define INVALID_PCI_DEVICE 0xFFFFFFFF
> -#define PCI_TBT_VESC_REG2 0x510
> -
> -typedef struct _PortInfo {
> - UINT8 IoBase;
> - UINT8 IoLimit;
> - UINT16 MemBase;
> - UINT16 MemLimit;
> - UINT64 PMemBase64;
> - UINT64 PMemLimit64;
> - UINT8 BusNumLimit;
> - UINT8 ConfedEP;
> -} PORT_INFO;
> -
> -typedef struct _MEM_REGS {
> - UINT32 Base;
> - UINT32 Limit;
> -} MEM_REGS;
> -
> -typedef struct _PMEM_REGS {
> - UINT64 Base64;
> - UINT64 Limit64;
> -} PMEM_REGS;
> -
> -typedef struct _IO_REGS {
> - UINT16 Base;
> - UINT16 Limit;
> -} IO_REGS;
> -
> -typedef struct _BRDG_RES_CONFIG {
> - UINT8 Cmd;
> - UINT8 Cls;
> - UINT8 IoBase;
> - UINT8 IoLimit;
> - UINT16 MemBase;
> - UINT16 MemLimit;
> - UINT64 PMemBase64;
> - UINT64 PMemLimit64;
> -} BRDG_RES_CONFIG;
> -
> -typedef struct _BRDG_CONFIG {
> - DEV_ID DevId;
> - UINT8 PBus;
> - UINT8 SBus;
> - UINT8 SubBus;
> - BOOLEAN IsDSBridge;
> - BRDG_RES_CONFIG Res;
> -} BRDG_CONFIG;
> -
> -enum {
> - HR_US_PORT,
> - HR_DS_PORT0,
> - HR_DS_PORT3,
> - HR_DS_PORT4,
> - HR_DS_PORT5,
> - HR_DS_PORT6,
> - MAX_CFG_PORTS
> -};
> -
> -enum {
> - HR_DS_PORT1 = HR_DS_PORT3
> -};
> -
> -//
> -// Alpine Ridge
> -//
> -enum {
> - AR_DS_PORT1 = HR_DS_PORT3,
> - AR_DS_PORT2,
> - AR_DS_PORT3,
> - AR_DS_PORT4
> -};
> -
> -typedef struct _HR_CONFIG {
> - UINT16 DeviceId;
> - UINT8 HRBus;
> - UINT8 MinDSNumber;
> - UINT8 MaxDSNumber;
> - UINT8 BridgeLoops;
> -} HR_CONFIG;
> -
> -STATIC const BRDG_RES_CONFIG NOT_IN_USE_BRIDGE = {
> - CMD_BUS_MASTER,
> - 0,
> - DISBL_IO_REG1C & 0xFF,
> - DISBL_IO_REG1C >> 8,
> - DISBL_MEM32_REG20 & 0xFFFF,
> - DISBL_MEM32_REG20 >> 16,
> - DISBL_PMEM_REG24 & 0xFFFF,
> - DISBL_PMEM_REG24 >> 16
> -};
> -
> -typedef union _BRDG_CIO_MAP_REG {
> - UINT32 AB_REG;
> - struct {
> - UINT32 NumOfDSPorts : 5;
> - UINT32 CioPortMap : 27;
> - } Bits;
> -} BRDG_CIO_MAP_REG;
> -
> -//
> -// Functions
> -//
> -VOID
> -ThunderboltCallback (
> - IN UINT8 Type
> - );
> -
> -VOID
> -TbtDisablePCIDevicesAndBridges (
> - IN UINT8 Type
> - );
> -
> -VOID
> -EndOfThunderboltCallback(
> - IN UINTN RpSegment,
> - IN UINTN RpBus,
> - IN UINTN RpDevice,
> - IN UINTN RpFunction
> -);
> -
> -VOID
> -ConfigureTbtAspm(
> - IN UINT8 Type,
> - IN UINT16 Aspm
> -);
> -
> -UINT8
> -PcieFindCapId (
> - IN UINT8 Segment,
> - IN UINT8 Bus,
> - IN UINT8 Device,
> - IN UINT8 Function,
> - IN UINT8 CapId
> - );
> -
> -#endif
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef.h
> b/Platform/Intel/ClevoOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef.h
> deleted file mode 100644
> index 5d096db346..0000000000
> --- a/Platform/Intel/ClevoOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef.h
> +++ /dev/null
> @@ -1,116 +0,0 @@
> -/** @file
> - ACPI DSDT table
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> - // Define a Global region of ACPI NVS Region that may be used for any
> - // type of implementation. The starting offset and size will be fixed
> - // up by the System BIOS during POST. Note that the Size must be a
> word
> - // in size to be fixed up correctly.
> -
> -#ifndef _GLOBAL_NVS_AREA_DEF_H_
> -#define _GLOBAL_NVS_AREA_DEF_H_
> -
> -#pragma pack (push,1)
> -typedef struct {
> - //
> - // Miscellaneous Dynamic Registers:
> - //
> - UINT16 OperatingSystem; ///< Offset 0
> Operating System
> - UINT8 SmiFunction; ///< Offset 2
> SMI Function Call (ASL to SMI via I/O Trap)
> - UINT32 Port80DebugValue; ///< Offset 3
> Port 80 Debug Port Value
> - UINT8 PowerState; ///< Offset 7
> Power State (AC Mode = 1)
> - //
> - // Thermal Policy Registers:
> - //
> - UINT8 EnableDigitalThermalSensor; ///< Offset 8
> Digital Thermal Sensor Enable
> - UINT8 DigitalThermalSensorSmiFunction; ///< Offset 9
> DTS SMI Function Call
> - //
> - // CPU Identification Registers:
> - //
> - UINT8 ApicEnable; ///< Offset 10
> APIC Enabled by SBIOS (APIC Enabled = 1)
> - UINT8 ThreadCount; ///< Offset 11
> Number of Enabled Threads
> - //
> - // PCIe Hot Plug
> - //
> - UINT8 PcieOSCControl; ///< Offset 12
> PCIE OSC Control
> - UINT8 NativePCIESupport; ///< Offset 13
> Native PCIE Setup Value
> - //
> - // Global Variables
> - //
> - UINT8 DisplaySupportFlag; ///< Offset 14
> _DOS Display Support Flag.
> - UINT8 InterruptModeFlag; ///< Offset 15
> Global IOAPIC/8259 Interrupt Mode Flag.
> - UINT8 L01Counter; ///< Offset 16
> Global L01 Counter.
> - UINT8 LtrEnable[24]; ///< Offset 17
> Latency Tolerance Reporting Enable
> - ///< Offset 18
> Latency Tolerance Reporting Enable
> - ///< Offset 19
> Latency Tolerance Reporting Enable
> - ///< Offset 20
> Latency Tolerance Reporting Enable
> - ///< Offset 21
> Latency Tolerance Reporting Enable
> - ///< Offset 22
> Latency Tolerance Reporting Enable
> - ///< Offset 23
> Latency Tolerance Reporting Enable
> - ///< Offset 24
> Latency Tolerance Reporting Enable
> - ///< Offset 25
> Latency Tolerance Reporting Enable
> - ///< Offset 26
> Latency Tolerance Reporting Enable
> - ///< Offset 27
> Latency Tolerance Reporting Enable
> - ///< Offset 28
> Latency Tolerance Reporting Enable
> - ///< Offset 29
> Latency Tolerance Reporting Enable
> - ///< Offset 30
> Latency Tolerance Reporting Enable
> - ///< Offset 31
> Latency Tolerance Reporting Enable
> - ///< Offset 32
> Latency Tolerance Reporting Enable
> - ///< Offset 33
> Latency Tolerance Reporting Enable
> - ///< Offset 34
> Latency Tolerance Reporting Enable
> - ///< Offset 35
> Latency Tolerance Reporting Enable
> - ///< Offset 36
> Latency Tolerance Reporting Enable
> - ///< Offset 37
> Latency Tolerance Reporting Enable
> - ///< Offset 38
> Latency Tolerance Reporting Enable
> - ///< Offset 39
> Latency Tolerance Reporting Enable
> - ///< Offset 40
> Latency Tolerance Reporting Enable
> - UINT8 ObffEnable[24]; ///< Offset 41
> Optimized Buffer Flush and Fill
> - ///< Offset 42
> Optimized Buffer Flush and Fill
> - ///< Offset 43
> Optimized Buffer Flush and Fill
> - ///< Offset 44
> Optimized Buffer Flush and Fill
> - ///< Offset 45
> Optimized Buffer Flush and Fill
> - ///< Offset 46
> Optimized Buffer Flush and Fill
> - ///< Offset 47
> Optimized Buffer Flush and Fill
> - ///< Offset 48
> Optimized Buffer Flush and Fill
> - ///< Offset 49
> Optimized Buffer Flush and Fill
> - ///< Offset 50
> Optimized Buffer Flush and Fill
> - ///< Offset 51
> Optimized Buffer Flush and Fill
> - ///< Offset 52
> Optimized Buffer Flush and Fill
> - ///< Offset 53
> Optimized Buffer Flush and Fill
> - ///< Offset 54
> Optimized Buffer Flush and Fill
> - ///< Offset 55
> Optimized Buffer Flush and Fill
> - ///< Offset 56
> Optimized Buffer Flush and Fill
> - ///< Offset 57
> Optimized Buffer Flush and Fill
> - ///< Offset 58
> Optimized Buffer Flush and Fill
> - ///< Offset 59
> Optimized Buffer Flush and Fill
> - ///< Offset 60
> Optimized Buffer Flush and Fill
> - ///< Offset 61
> Optimized Buffer Flush and Fill
> - ///< Offset 62
> Optimized Buffer Flush and Fill
> - ///< Offset 63
> Optimized Buffer Flush and Fill
> - ///< Offset 64
> Optimized Buffer Flush and Fill
> - UINT8 Rtd3Support; ///< Offset 65
> Runtime D3 support.
> - UINT8 LowPowerS0Idle; ///< Offset 66
> Low Power S0 Idle Enable
> - UINT8 VirtualGpioButtonSxBitmask; ///< Offset 67
> Virtual GPIO button Notify Sleep State Change
> - UINT8 PstateCapping; ///< Offset 68
> P-state Capping
> - UINT8 Ps2MouseEnable; ///< Offset 69
> Ps2 Mouse Enable
> - UINT8 Ps2KbMsEnable; ///< Offset 70
> Ps2 Keyboard and Mouse Enable
> - //
> - // Driver Mode
> - //
> - UINT32 GpioIrqRoute; ///< Offset 71
> GPIO IRQ
> - UINT8 PL1LimitCS; ///< Offset 75
> set PL1 limit when entering CS
> - UINT16 PL1LimitCSValue; ///< Offset 76
> PL1 limit value
> - UINT8 TenSecondPowerButtonEnable; ///< Offset 78
> 10sec Power button support
> - UINT8 PciDelayOptimizationEcr; ///< Offset 79
> Pci Delay Optimization Ecr
> - UINT8 TbtSupport; ///< Offset 80
> Thunderbolt(TM) support
> - UINT8 TbtNativeOsHotPlug; ///< Offset 81
> TbtNativeOsHotPlug
> - UINT8 TbtSelector; ///< Offset 82
> Thunderbolt(TM) Root port selector
> - UINT8 TbtSelector1; ///< Offset 83
> Thunderbolt(TM) Root port selector
> -} EFI_GLOBAL_NVS_AREA;
> -
> -#pragma pack(pop)
> -#endif
> diff --git a/Platform/Intel/ClevoOpenBoardPkg/Include/IoExpander.h
> b/Platform/Intel/ClevoOpenBoardPkg/Include/IoExpander.h
> deleted file mode 100644
> index 0f313e429a..0000000000
> --- a/Platform/Intel/ClevoOpenBoardPkg/Include/IoExpander.h
> +++ /dev/null
> @@ -1,67 +0,0 @@
> -/** @file
> - GPIO definition table for N1xxWU
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#ifndef _IO_EXPANDER_H_
> -#define _IO_EXPANDER_H_
> -
> -typedef struct {
> - UINT32 IoExpanderNumber : 1; // IO Expander Number (0/1)
> - UINT32 GpioPinNumber : 5; // GPIO Pin Number (0 to 23)
> - UINT32 GpioDirection : 1; // GPIO Pin Direction (Input/Output)
> - UINT32 GpioLevel : 1; // GPIO Pin Output Level (High/Low)
> - UINT32 GpioInversion : 1; // GPIO Pin Inversion
> (Enabled/Disabled)
> - UINT32 Reserved : 23; // Reserved
> -} IO_EXPANDER_GPIO_CONFIG;
> -
> -//SKL PCH LP GPIO Expander Number
> -#define IO_EXPANDER_0 0
> -#define IO_EXPANDER_1 1
> -
> -//SKL PCH LP GPIO Pin Mapping
> -#define IO_EXPANDER_GPIO_0 0 // P00
> -#define IO_EXPANDER_GPIO_1 1 // P01
> -#define IO_EXPANDER_GPIO_2 2 // P02
> -#define IO_EXPANDER_GPIO_3 3 // P03
> -#define IO_EXPANDER_GPIO_4 4 // P04
> -#define IO_EXPANDER_GPIO_5 5 // P05
> -#define IO_EXPANDER_GPIO_6 6 // P06
> -#define IO_EXPANDER_GPIO_7 7 // P07
> -#define IO_EXPANDER_GPIO_8 8 // P10
> -#define IO_EXPANDER_GPIO_9 9 // P11
> -#define IO_EXPANDER_GPIO_10 10 // P12
> -#define IO_EXPANDER_GPIO_11 11 // P13
> -#define IO_EXPANDER_GPIO_12 12 // P14
> -#define IO_EXPANDER_GPIO_13 13 // P15
> -#define IO_EXPANDER_GPIO_14 14 // P16
> -#define IO_EXPANDER_GPIO_15 15 // P17
> -#define IO_EXPANDER_GPIO_16 16 // P20
> -#define IO_EXPANDER_GPIO_17 17 // P21
> -#define IO_EXPANDER_GPIO_18 18 // P22
> -#define IO_EXPANDER_GPIO_19 19 // P23
> -#define IO_EXPANDER_GPIO_20 20 // P24
> -#define IO_EXPANDER_GPIO_21 21 // P25
> -#define IO_EXPANDER_GPIO_22 22 // P26
> -#define IO_EXPANDER_GPIO_23 23 // P27
> -
> -//SKL PCH LP GPIO Expander GPIO Direction
> -#define IO_EXPANDER_GPIO_OUTPUT 0
> -#define IO_EXPANDER_GPIO_INPUT 1
> -
> -//SKL PCH LP GPIO Expaner GPIO Output Level
> -#define IO_EXPANDER_GPO_LEVEL_LOW 0
> -#define IO_EXPANDER_GPO_LEVEL_HIGH 1
> -
> -//SKL PCH LP GPIO Expaner GPIO Inversion Status
> -#define IO_EXPANDER_GPI_INV_DISABLED 0
> -#define IO_EXPANDER_GPI_INV_ENABLED 1
> -#define IO_EXPANDER_GPIO_RESERVED 0x00
> -
> -//GPIO Table Terminator
> -#define END_OF_GPIO_TABLE 0xFFFFFFFF
> -
> -#endif
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Include/Library/GpioExpanderLib.h
> b/Platform/Intel/ClevoOpenBoardPkg/Include/Library/GpioExpanderLib.h
> deleted file mode 100644
> index dc75a7decb..0000000000
> --- a/Platform/Intel/ClevoOpenBoardPkg/Include/Library/GpioExpanderLib.h
> +++ /dev/null
> @@ -1,122 +0,0 @@
> -/** @file
> - Support for IO expander TCA6424.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#ifndef _GPIO_EXPANDER_LIB_H_
> -#define _GPIO_EXPANDER_LIB_H_
> -
> -#include <Uefi.h>
> -#include <Library/DebugLib.h>
> -#include <Library/TimerLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/UefiLib.h>
> -#include <PchAccess.h>
> -#include <Library/PchSerialIoLib.h>
> -
> -/**
> - Set the Direction value for the given Expander Gpio pin.
> -
> - This function is to Set the direction value for the GPIO
> - Pin within the giving Expander.
> -
> - @param[in] Expander Expander Value with in the Contoller
> - @param[in] Pin Pin with in the Expnader Value
> - @param[in] Value none
> -**/
> -VOID
> -GpioExpSetDirection (
> - IN UINT8 Expander,
> - IN UINT8 Pin,
> - IN UINT8 Direction
> - );
> -/**
> - Set the input value for the given Expander Gpio pin.
> -
> - This function is to get the input value for the GPIO
> - Pin within the giving Expander.
> -
> - @param[in] Expander Expander Value with in the Contoller
> - @param[in] Pin Pin with in the Expnader Value
> - @param[in] Value none
> -
> -**/
> -VOID
> -GpioExpSetPolarity (
> - IN UINT8 Expander,
> - IN UINT8 Pin,
> - IN UINT8 Polarity
> - );
> -/**
> - Set the Output value for the given Expander Gpio pin.
> -
> - This function is to Set the Output value for the GPIO
> - Pin within the giving Expander.
> -
> - @param[in] Expander Expander Value with in the Contoller
> - @param[in] Pin Pin with in the Expnader Value
> - @param[in] Value none
> -
> -**/
> -VOID
> -GpioExpSetOutput (
> - IN UINT8 Expander,
> - IN UINT8 Pin,
> - IN UINT8 Value
> - );
> -/**
> - Returns the data from register value giving in the input.
> -
> - This function is to get the data from the Expander
> - Registers by following the I2C Protocol communication
> -
> -
> - @param[in] Bar0 Bar address of the SerialIo Controller
> - @param[in] Address Expander Value with in the Contoller
> - @param[in] Register Address of Input/Output/Configure/Polarity
> - registers with in the Expander
> -
> - @retval UINT8 Value returned from the register
> -**/
> -UINT8
> -GpioExpGetInput (
> - IN UINT8 Expander,
> - IN UINT8 Pin
> - );
> -
> -/**
> - Configures all registers of a single IO Expander in one go.
> -
> - @param[in] Expander Expander number (0/1)
> - @param[in] Direction Bit-encoded direction values. BIT0 is for pin0,
> etc. 0=output, 1=input
> - @param[in] Polarity Bit-encoded input inversion values. BIT0 is for
> pin0, etc. 0=normal, 1=inversion
> - @param[in] Output Bit-encoded output state, ignores polarity,
> only applicable if direction=INPUT. BIT0 is for pin0, etc. 0=low, 1=high
> -
> -**/
> -VOID
> -GpioExpBulkConfig (
> - IN UINT8 Expander,
> - IN UINT32 Direction,
> - IN UINT32 Polarity,
> - IN UINT32 Output
> - );
> -
> -/**
> - Returns the Controller on which GPIO expander is present.
> -
> - This function returns the Controller value
> -
> - @param[out] Controller Pointer to a Controller value on
> - which I2C expander is
> configured.
> -
> - @retval EFI_SUCCESS non.
> -**/
> -EFI_STATUS
> -GpioExpGetController (
> - OUT UINT8 *Controller
> - );
> -
> -#endif
> diff --git a/Platform/Intel/ClevoOpenBoardPkg/Include/Library/I2cAccessLib.h
> b/Platform/Intel/ClevoOpenBoardPkg/Include/Library/I2cAccessLib.h
> deleted file mode 100644
> index e36699e8e9..0000000000
> --- a/Platform/Intel/ClevoOpenBoardPkg/Include/Library/I2cAccessLib.h
> +++ /dev/null
> @@ -1,33 +0,0 @@
> -/** @file
> - Support for IO expander TCA6424.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#ifndef _I2C_ACCESS_LIB_H_
> -#define _I2C_ACCESS_LIB_H_
> -
> -#include <Uefi.h>
> -#include <Library/DebugLib.h>
> -#include <Library/TimerLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/UefiLib.h>
> -#include <PchAccess.h>
> -#include <Library/PchSerialIoLib.h>
> -
> -#define WAIT_1_SECOND 1600000000 //1.6 * 10^9
> -
> -EFI_STATUS
> -I2cWriteRead (
> - IN UINTN MmioBase,
> - IN UINT8 SlaveAddress,
> - IN UINT8 WriteLength,
> - IN UINT8 *WriteBuffer,
> - IN UINT8 ReadLength,
> - IN UINT8 *ReadBuffer,
> - IN UINT64 TimeBudget
> - );
> -
> -#endif
> \ No newline at end of file
> diff --git a/Platform/Intel/ClevoOpenBoardPkg/Include/PchHsioPtssTables.h
> b/Platform/Intel/ClevoOpenBoardPkg/Include/PchHsioPtssTables.h
> deleted file mode 100644
> index a2003002cf..0000000000
> --- a/Platform/Intel/ClevoOpenBoardPkg/Include/PchHsioPtssTables.h
> +++ /dev/null
> @@ -1,51 +0,0 @@
> -/** @file*
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#ifndef PCH_HSIO_PTSSTABLES_H_
> -#define PCH_HSIO_PTSSTABLES_H_
> -
> -#include <PchAccess.h>
> -
> -///
> -/// SATA PTSS Topology Types
> -///
> -typedef enum {
> - PchSataTopoUnknown = 0x00,
> - PchSataTopoIsata,
> - PchSataTopoDirectConnect,
> - PchSataTopoFlex,
> - PchSataTopoM2
> -} PCH_SATA_TOPOLOGY;
> -
> -///
> -/// PCIe PTSS Topology Types
> -///
> -typedef enum {
> - PchPcieTopoUnknown = 0x00,
> - PchPcieTopox1,
> - PchPcieTopox4,
> - PchPcieTopoSataE,
> - PchPcieTopoM2
> -} PCH_PCIE_TOPOLOGY;
> -
> -///
> -/// The PCH_SBI_PTSS_HSIO_TABLE block describes HSIO PTSS settings for
> PCH.
> -///
> -typedef struct {
> - UINT8 LaneNum;
> - UINT8 PhyMode;
> - UINT16 Offset;
> - UINT32 Value;
> - UINT32 BitMask;
> -} PCH_SBI_PTSS_HSIO_TABLE;
> -
> -typedef struct {
> - PCH_SBI_PTSS_HSIO_TABLE PtssTable;
> - UINT16 Topology;
> -} HSIO_PTSS_TABLES;
> -
> -#endif // PCH_HSIO_PTSSTABLES_H_
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Include/Protocol/GlobalNvsArea.h
> b/Platform/Intel/ClevoOpenBoardPkg/Include/Protocol/GlobalNvsArea.h
> deleted file mode 100644
> index b10547b6b9..0000000000
> --- a/Platform/Intel/ClevoOpenBoardPkg/Include/Protocol/GlobalNvsArea.h
> +++ /dev/null
> @@ -1,47 +0,0 @@
> -/** @file
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#ifndef _GLOBAL_NVS_AREA_H_
> -#define _GLOBAL_NVS_AREA_H_
> -
> -//
> -// Includes
> -//
> -#define GLOBAL_NVS_DEVICE_ENABLE 1
> -#define GLOBAL_NVS_DEVICE_DISABLE 0
> -
> -//
> -// Forward reference for pure ANSI compatibility
> -//
> -
> -typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL
> EFI_GLOBAL_NVS_AREA_PROTOCOL;
> -
> -//
> -// Global NVS Area Protocol GUID
> -//
> -#define EFI_GLOBAL_NVS_AREA_PROTOCOL_GUID \
> -{ 0x74e1e48, 0x8132, 0x47a1, 0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc }
> -
> -#define GLOBAL_NVS_AREA_REVISION 16
> -//
> -// Extern the GUID for protocol users.
> -//
> -extern EFI_GUID gEfiGlobalNvsAreaProtocolGuid;
> -
> -//
> -// Global NVS Area definition
> -//
> -#include <Acpi/GlobalNvsAreaDef.h>
> -
> -//
> -// Global NVS Area Protocol
> -//
> -typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL {
> - EFI_GLOBAL_NVS_AREA *Area;
> -} EFI_GLOBAL_NVS_AREA_PROTOCOL;
> -
> -#endif
> diff --git a/Platform/Intel/ClevoOpenBoardPkg/Include/SioRegs.h
> b/Platform/Intel/ClevoOpenBoardPkg/Include/SioRegs.h
> deleted file mode 100644
> index cf636b798c..0000000000
> --- a/Platform/Intel/ClevoOpenBoardPkg/Include/SioRegs.h
> +++ /dev/null
> @@ -1,157 +0,0 @@
> -/** @file
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#ifndef _SIO_REG_H_
> -#define _SIO_REG_H_
> -
> -#define REG_LOGICAL_DEVICE 0x07
> -#define ACTIVATE 0x30
> -
> -#define BASE_ADDRESS_HIGH0 0x60
> -#define BASE_ADDRESS_LOW0 0x61
> -#define BASE_ADDRESS_HIGH1 0x62
> -#define BASE_ADDRESS_LOW1 0x63
> -#define BASE_ADDRESS_HIGH2 0x64
> -#define BASE_ADDRESS_LOW2 0x65
> -#define BASE_ADDRESS_HIGH3 0x66
> -#define BASE_ADDRESS_LOW3 0x67
> -#define PRIMARY_INTERRUPT_SELECT 0x70
> -#define WAKEUP_ON_IRQ_EN 0x70
> -#define INTERRUPT_TYPE 0x71
> -#define DMA_CHANNEL_SELECT0 0x74
> -#define DMA_CHANNEL_SELECT1 0x75
> -
> -
> -
> -//
> -//Port address for PILOT - III
> -//
> -#define PILOTIII_CHIP_ID 0x03
> -#define PILOTIII_SIO_INDEX_PORT 0x04E
> -#define PILOTIII_SIO_DATA_PORT (PILOTIII_SIO_INDEX_PORT+1)
> -
> -#define PILOTIII_UNLOCK 0x5A
> -#define PILOTIII_LOCK 0xA5
> -
> -//
> -// logical device in PILOT-III
> -//
> -#define PILOTIII_SIO_PSR 0x00
> -#define PILOTIII_SIO_COM2 0x01
> -#define PILOTIII_SIO_COM1 0x02
> -#define PILOTIII_SIO_SWCP 0x03
> -#define PILOTIII_SIO_GPIO 0x04
> -#define PILOTIII_SIO_WDT 0x05
> -#define PILOTIII_SIO_KCS3 0x08
> -#define PILOTIII_SIO_KCS4 0x09
> -#define PILOTIII_SIO_KCS5 0x0A
> -#define PILOTIII_SIO_BT 0x0B
> -#define PILOTIII_SIO_SMIC 0x0C
> -#define PILOTIII_SIO_MAILBOX 0x0D
> -#define PILOTIII_SIO_RTC 0x0E
> -#define PILOTIII_SIO_SPI 0x0F
> -#define PILOTIII_SIO_TAP 0x10
> -//
> -// Regisgers for Pilot-III
> -//
> -#define PILOTIII_CHIP_ID_REG 0x20
> -#define PILOTIII_LOGICAL_DEVICE REG_LOGICAL_DEVICE
> -#define PILOTIII_ACTIVATE ACTIVATE
> -#define PILOTIII_BASE_ADDRESS_HIGH0 BASE_ADDRESS_HIGH0
> -#define PILOTIII_BASE_ADDRESS_LOW0 BASE_ADDRESS_LOW0
> -#define PILOTIII_BASE_ADDRESS_HIGH1 BASE_ADDRESS_HIGH1
> -#define PILOTIII_BASE_ADDRESS_LOW1 BASE_ADDRESS_LOW1
> -#define PILOTIII_PRIMARY_INTERRUPT_SELECT
> PRIMARY_INTERRUPT_SELECT
> -
> -//
> -// Port address for PC8374
> -//
> -#define PC8374_SIO_INDEX_PORT 0x02E
> -#define PC8374_SIO_DATA_PORT (PC8374_SIO_INDEX_PORT+1)
> -
> -//
> -// Logical device in PC8374
> -//
> -#define PC8374_SIO_FLOPPY 0x00
> -#define PC8374_SIO_PARA 0x01
> -#define PC8374_SIO_COM2 0x02
> -#define PC8374_SIO_COM1 0x03
> -#define PC8374_SIO_MOUSE 0x05
> -#define PC8374_SIO_KYBD 0x06
> -#define PC8374_SIO_GPIO 0x07
> -
> -//
> -// Registers specific for PC8374
> -//
> -#define PC8374_CLOCK_SELECT 0x2D
> -#define PC8374_CLOCK_CONFIG 0x29
> -
> -//
> -// Registers for PC8374
> -//
> -#define PC8374_LOGICAL_DEVICE REG_LOGICAL_DEVICE
> -#define PC8374_ACTIVATE ACTIVATE
> -#define PC8374_BASE_ADDRESS_HIGH0 BASE_ADDRESS_HIGH0
> -#define PC8374_BASE_ADDRESS_LOW0 BASE_ADDRESS_LOW0
> -#define PC8374_PRIMARY_INTERRUPT_SELECT
> PRIMARY_INTERRUPT_SELECT
> -#define PC8374_DMA_CHANNEL_SELECT DMA_CHANNEL_SELECT0
> -
> -#define PC87427_SERVERIO_CNF2 0x22
> -
> -
> -//
> -// Pilot III Mailbox Data Register definitions
> -//
> -#define MBDAT00_OFFSET 0x00
> -#define MBDAT01_OFFSET 0x01
> -#define MBDAT02_OFFSET 0x02
> -#define MBDAT03_OFFSET 0x03
> -#define MBDAT04_OFFSET 0x04
> -#define MBDAT05_OFFSET 0x05
> -#define MBDAT06_OFFSET 0x06
> -#define MBDAT07_OFFSET 0x07
> -#define MBDAT08_OFFSET 0x08
> -#define MBDAT09_OFFSET 0x09
> -#define MBDAT10_OFFSET 0x0A
> -#define MBDAT11_OFFSET 0x0B
> -#define MBDAT12_OFFSET 0x0C
> -#define MBDAT13_OFFSET 0x0D
> -#define MBDAT14_OFFSET 0x0E
> -#define MBDAT15_OFFSET 0x0F
> -#define MBST0_OFFSET 0x10
> -#define MBST1_OFFSET 0x11
> -#define MBBINT_OFFSET 0x12
> -
> -//
> -// Mailbox Bit definitions...
> -//
> -#define MBBINT_MBBIST_BIT 0x80
> -// If both are there, use the default one
> -//
> -#define W83527_EXIST BIT2
> -#define PC8374_EXIST BIT1
> -#define PILOTIII_EXIST BIT0
> -#define DEFAULT_SIO PILOTIII_EXIST
> -#define DEFAULT_KDB PC8374_EXIST
> -
> -#define IPMI_DEFAULT_SMM_IO_BASE 0xca2
> -//
> -// For Pilot III
> -//
> -
> -#define PILOTIII_SWC_BASE_ADDRESS 0xA00
> -#define PILOTIII_PM1b_EVT_BLK_BASE_ADDRESS 0x0A80
> -#define PILOTIII_PM1b_CNT_BLK_BASE_ADDRESS 0x0A84
> -#define PILOTIII_GPE1_BLK_BASE_ADDRESS 0x0A86
> -#define PILOTIII_KCS3_DATA_BASE_ADDRESS 0x0CA4
> -#define PILOTIII_KCS3_CMD_BASE_ADDRESS 0x0CA5
> -#define PILOTIII_KCS4_DATA_BASE_ADDRESS 0x0CA2
> -#define PILOTIII_KCS4_CMD_BASE_ADDRESS 0x0CA3
> -#define PILOTIII_MAILBOX_BASE_ADDRESS 0x0600
> -#define PILOTIII_MAILBOX_MASK 0xFFE0
> -#define BMC_KCS_BASE_ADDRESS 0x0CA0
> -#endif
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilico
> nPolicyUpdateLibFsp/PeiPchPolicyUpdate.h
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilic
> onPolicyUpdateLibFsp/PeiPchPolicyUpdate.h
> deleted file mode 100644
> index 9f6b236e42..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilico
> nPolicyUpdateLibFsp/PeiPchPolicyUpdate.h
> +++ /dev/null
> @@ -1,28 +0,0 @@
> -/** @file
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#ifndef _PEI_PCH_POLICY_UPDATE_H_
> -#define _PEI_PCH_POLICY_UPDATE_H_
> -
> -//
> -// External include files do NOT need to be explicitly specified in real EDKII
> -// environment
> -//
> -#include <PiPei.h>
> -
> -#include <Library/DebugLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/PciLib.h>
> -#include <Ppi/SiPolicy.h>
> -#include <Library/MmPciLib.h>
> -#include <Library/ConfigBlockLib.h>
> -
> -#include <FspEas.h>
> -#include <FspmUpd.h>
> -#include <FspsUpd.h>
> -
> -#endif
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilico
> nPolicyUpdateLibFsp/PeiSaPolicyUpdate.h
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilic
> onPolicyUpdateLibFsp/PeiSaPolicyUpdate.h
> deleted file mode 100644
> index c006dbcd68..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilico
> nPolicyUpdateLibFsp/PeiSaPolicyUpdate.h
> +++ /dev/null
> @@ -1,30 +0,0 @@
> -/** @file
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#ifndef _PEI_SA_POLICY_UPDATE_H_
> -#define _PEI_SA_POLICY_UPDATE_H_
> -
> -//
> -// External include files do NOT need to be explicitly specified in real EDKII
> -// environment
> -//
> -#include <SaPolicyCommon.h>
> -#include <Library/DebugPrintErrorLevelLib.h>
> -#include <CpuRegs.h>
> -#include <Library/CpuPlatformLib.h>
> -#include "PeiPchPolicyUpdate.h"
> -#include <Library/PcdLib.h>
> -#include <CpuAccess.h>
> -
> -#include <FspEas.h>
> -#include <FspmUpd.h>
> -#include <FspsUpd.h>
> -
> -extern EFI_GUID gTianoLogoGuid;
> -
> -#endif
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/N1xxWUId.h
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/N1xxWUId.h
> deleted file mode 100644
> index 684b31f051..0000000000
> --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/N1xxWUId.h
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/** @file
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#ifndef _N1_XX_WU_ID_H_
> -#define _N1_XX_WU_ID_H_
> -
> -#define BoardIdN1xxWU 0x60
> -
> -#endif // _PEI_N1_XX_WU_BOARD_INIT_LIB_H_
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xx
> WUInitLib.h
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xx
> WUInitLib.h
> deleted file mode 100644
> index ddb873aaa2..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xx
> WUInitLib.h
> +++ /dev/null
> @@ -1,42 +0,0 @@
> -/** @file
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#ifndef _PEI_N1_XX_WU_BOARD_INIT_LIB_H_
> -#define _PEI_N1_XX_WU_BOARD_INIT_LIB_H_
> -
> -#include <Uefi.h>
> -#include <Library/BaseLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/MemoryAllocationLib.h>
> -#include <Library/DebugLib.h>
> -#include <Library/GpioLib.h>
> -#include <Ppi/SiPolicy.h>
> -#include <PchHsioPtssTables.h>
> -#include <IoExpander.h>
> -
> -#include <N1xxWUId.h>
> -
> -extern const UINT8 mDqByteMapSklRvp3[2][6][2];
> -extern const UINT8 mDqsMapCpu2DramSklRvp3[2][8];
> -extern const UINT8 mSkylakeRvp3Spd110[];
> -extern const UINT16 mSkylakeRvp3Spd110Size;
> -extern HSIO_PTSS_TABLES PchLpHsioPtss_Bx_N1xxWU[];
> -extern UINT16 PchLpHsioPtss_Bx_N1xxWU_Size;
> -extern HSIO_PTSS_TABLES PchLpHsioPtss_Cx_N1xxWU[];
> -extern UINT16 PchLpHsioPtss_Cx_N1xxWU_Size;
> -
> -extern HDAUDIO_VERB_TABLE HdaVerbTableAlc286Rvp3;
> -extern GPIO_INIT_CONFIG mGpioTableN1xxWUUcmcDevice[];
> -extern UINT16 mGpioTableN1xxWUUcmcDeviceSize;
> -
> -extern IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpander[];
> -extern UINT16 mGpioTableIoExpanderSize;
> -extern GPIO_INIT_CONFIG mGpioTableN1xxWUTouchpanel;
> -extern GPIO_INIT_CONFIG mGpioTableN1xxWU[];
> -extern UINT16 mGpioTableN1xxWUSize;
> -
> -#endif // _PEI_N1_XX_WU_BOARD_INIT_LIB_H_
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPoli
> cyUpdateLib/DxeGopPolicyInit.h
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPoli
> cyUpdateLib/DxeGopPolicyInit.h
> deleted file mode 100644
> index f4ab1a5bca..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPoli
> cyUpdateLib/DxeGopPolicyInit.h
> +++ /dev/null
> @@ -1,39 +0,0 @@
> -/** @file
> -Header file for the GopPolicyInitDxe Driver.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -#ifndef _GOP_POLICY_INIT_DXE_H_
> -#define _GOP_POLICY_INIT_DXE_H_
> -
> -#include <Protocol/FirmwareVolume2.h>
> -#include <Library/UefiLib.h>
> -#include <Library/BaseLib.h>
> -#include <Library/MemoryAllocationLib.h>
> -#include <Library/DxeServicesTableLib.h>
> -#include <Library/UefiBootServicesTableLib.h>
> -#include <Library/UefiRuntimeServicesTableLib.h>
> -#include <Library/BaseMemoryLib.h>
> -#include <Library/DebugLib.h>
> -#include <Library/PcdLib.h>
> -
> -
> -/**
> -Initialize GOP DXE Policy
> -
> - at param[in] ImageHandle Image handle of this driver.
> -
> - at retval EFI_SUCCESS Initialization complete.
> - at retval EFI_UNSUPPORTED The chipset is unsupported by this
> driver.
> - at retval EFI_OUT_OF_RESOURCES Do not have enough resources to
> initialize the driver.
> - at retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
> -**/
> -EFI_STATUS
> -EFIAPI
> -GopPolicyInitDxe(
> - IN EFI_HANDLE ImageHandle
> - );
> -
> -#endif
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPoli
> cyUpdateLib/DxeSaPolicyInit.h
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPoli
> cyUpdateLib/DxeSaPolicyInit.h
> deleted file mode 100644
> index bb4b4369ad..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPoli
> cyUpdateLib/DxeSaPolicyInit.h
> +++ /dev/null
> @@ -1,64 +0,0 @@
> -/** @file
> - Header file for the SaPolicyInitDxe Driver.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -#ifndef _SA_POLICY_INIT_DXE_H_
> -#define _SA_POLICY_INIT_DXE_H_
> -
> -#include <Library/BaseMemoryLib.h>
> -#include <Library/MemoryAllocationLib.h>
> -#include <Library/DebugLib.h>
> -#include <Library/UefiBootServicesTableLib.h>
> -#include <Protocol/SaPolicy.h>
> -#include <Library/DxeSaPolicyLib.h>
> -
> -#include <SaAccess.h>
> -
> -
> -/**
> - <b>SA DXE Policy Driver Entry Point</b> \n
> - - <b>Introduction</b> \n
> - System Agent DXE drivers behavior can be controlled by platform policy
> without modifying reference code directly.
> - Platform policy Protocol is initialized with default settings in this
> funciton.
> - This policy Protocol has to be initialized prior to System Agent
> initialization DXE drivers execution.
> -
> - - @pre
> - - Runtime variable service should be ready if policy initialization
> required.
> -
> - - @result
> - SA_POLICY_PROTOCOL will be installed successfully and ready for
> System Agent reference code use.
> -
> - - <b>Porting Recommendations</b> \n
> - Policy should be initialized basing on platform design or user selection
> (like BIOS Setup Menu)
> -
> - @param[in] ImageHandle - Image handle of this driver.
> -
> - @retval EFI_SUCCESS Initialization complete.
> - @exception EFI_UNSUPPORTED The chipset is unsupported by this
> driver.
> - @retval EFI_OUT_OF_RESOURCES Do not have enough resources to
> initialize the driver.
> - @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
> -**/
> -EFI_STATUS
> -EFIAPI
> -SaPolicyInitDxe (
> - IN EFI_HANDLE ImageHandle
> - );
> -
> -/**
> - Get data for platform policy from setup options.
> -
> - @param[in] SaPolicy The pointer to get SA Policy
> protocol instance
> -
> - @retval EFI_SUCCESS Operation success.
> -
> -**/
> -EFI_STATUS
> -EFIAPI
> -UpdateDxeSaPolicy (
> - IN OUT SA_POLICY_PROTOCOL *SaPolicy
> - );
> -
> -#endif
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/AcpiGnvsInit.c
> b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/AcpiGnvsInit.c
> deleted file mode 100644
> index 7c10cf8f73..0000000000
> --- a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/AcpiGnvsInit.c
> +++ /dev/null
> @@ -1,95 +0,0 @@
> -/** @file
> - Acpi Gnvs Init Library.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <Uefi.h>
> -#include <Library/IoLib.h>
> -#include <Library/PciLib.h>
> -#include <Library/DebugLib.h>
> -#include <Library/BaseMemoryLib.h>
> -#include <Library/UefiBootServicesTableLib.h>
> -
> -#include <PchAccess.h>
> -#include <Protocol/GlobalNvsArea.h>
> -#include <Protocol/MpService.h>
> -
> -/**
> - at brief
> - Global NVS initialize.
> -
> - @param[in] GlobalNvs - Pointer of Global NVS area
> -
> - @retval EFI_SUCCESS - Allocate Global NVS completed.
> - @retval EFI_OUT_OF_RESOURCES - Failed to allocate required page for
> GNVS.
> -**/
> -EFI_STATUS
> -EFIAPI
> -AcpiGnvsInit (
> - IN OUT VOID **GlobalNvs
> - )
> -{
> - UINTN Pages;
> - EFI_PHYSICAL_ADDRESS Address;
> - EFI_STATUS Status;
> - EFI_GLOBAL_NVS_AREA_PROTOCOL *GNVS;
> - EFI_MP_SERVICES_PROTOCOL *MpService;
> - UINTN NumberOfCPUs;
> - UINTN NumberOfEnabledCPUs;
> -
> - Pages = EFI_SIZE_TO_PAGES (sizeof (EFI_GLOBAL_NVS_AREA));
> - Address = 0xffffffff; // allocate address below 4G.
> -
> - Status = gBS->AllocatePages (
> - AllocateMaxAddress,
> - EfiACPIMemoryNVS,
> - Pages,
> - &Address
> - );
> - ASSERT_EFI_ERROR (Status);
> - if (EFI_ERROR(Status)) {
> - return Status;
> - }
> -
> - //
> - // Locate the MP services protocol
> - // Find the MP Protocol. This is an MP platform, so MP protocol must be
> there.
> - //
> - Status = gBS->LocateProtocol (
> - &gEfiMpServiceProtocolGuid,
> - NULL,
> - (VOID **) &MpService
> - );
> - ASSERT_EFI_ERROR (Status);
> -
> - //
> - // Determine the number of processors
> - //
> - MpService->GetNumberOfProcessors (
> - MpService,
> - &NumberOfCPUs,
> - &NumberOfEnabledCPUs
> - );
> -
> - *GlobalNvs = (VOID *) (UINTN) Address;
> - SetMem (*GlobalNvs, sizeof (EFI_GLOBAL_NVS_AREA), 0);
> -
> - //
> - // GNVS default value init here...
> - //
> - GNVS = (EFI_GLOBAL_NVS_AREA_PROTOCOL *) &Address;
> -
> - GNVS->Area->ThreadCount = (UINT8)NumberOfEnabledCPUs;
> -
> - //
> - // Miscellaneous
> - //
> - GNVS->Area->PL1LimitCS = 0;
> - GNVS->Area->PL1LimitCSValue = 4500;
> -
> - return EFI_SUCCESS;
> -}
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c
> b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c
> deleted file mode 100644
> index 4f248006bf..0000000000
> --- a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c
> +++ /dev/null
> @@ -1,307 +0,0 @@
> -/** @file
> - Board ACPI DXE initialization.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <Base.h>
> -#include <Uefi.h>
> -#include <IndustryStandard/Acpi.h>
> -#include <Library/UefiLib.h>
> -#include <Library/UefiBootServicesTableLib.h>
> -#include <Library/UefiRuntimeServicesTableLib.h>
> -#include <Library/DebugLib.h>
> -#include <Library/BaseMemoryLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/PciLib.h>
> -#include <Library/BoardAcpiTableLib.h>
> -#include <Library/MemoryAllocationLib.h>
> -#include <Library/AslUpdateLib.h>
> -
> -#include <Protocol/GlobalNvsArea.h>
> -#include <Protocol/FirmwareVolume2.h>
> -#include <Protocol/AcpiTable.h>
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED EFI_GLOBAL_NVS_AREA_PROTOCOL
> mGlobalNvsArea;
> -
> -/**
> - at brief
> - Global NVS initialize.
> -
> - @param[in] GlobalNvs - Pointer of Global NVS area
> -
> - @retval EFI_SUCCESS - Allocate Global NVS completed.
> - @retval EFI_OUT_OF_RESOURCES - Failed to allocate required page for
> GNVS.
> -**/
> -EFI_STATUS
> -EFIAPI
> -AcpiGnvsInit (
> - IN OUT VOID **GlobalNvs
> - );
> -
> -VOID
> -UpdateDsdt (
> - IN VOID *Table
> - );
> -
> -//
> -// Function implementations
> -//
> -
> -/**
> - Locate the first instance of a protocol. If the protocol requested is an
> - FV protocol, then it will return the first FV that contains the ACPI table
> - storage file.
> -
> - @param[in] Protocol The protocol to find.
> - @param[in] Instance Return pointer to the first instance of
> the protocol.
> - @param[in] Type TRUE if the desired protocol is a FV
> protocol.
> -
> - @retval EFI_SUCCESS The function completed successfully.
> - @retval EFI_NOT_FOUND The protocol could not be located.
> - @retval EFI_OUT_OF_RESOURCES There are not enough resources to
> find the protocol.
> -**/
> -EFI_STATUS
> -LocateSupportProtocol (
> - IN EFI_GUID *Protocol,
> - IN EFI_GUID
> *gEfiAcpiMultiTableStorageGuid,
> - OUT VOID **Instance,
> - IN BOOLEAN Type
> - )
> -{
> - EFI_STATUS Status;
> - EFI_HANDLE *HandleBuffer;
> - UINTN NumberOfHandles;
> - EFI_FV_FILETYPE FileType;
> - UINT32 FvStatus;
> - EFI_FV_FILE_ATTRIBUTES Attributes;
> - UINTN Size;
> - UINTN Index;
> -
> - //
> - // Locate protocol.
> - //
> - Status = gBS->LocateHandleBuffer (
> - ByProtocol,
> - Protocol,
> - NULL,
> - &NumberOfHandles,
> - &HandleBuffer
> - );
> - if (EFI_ERROR (Status)) {
> - //
> - // Defined errors at this time are not found and out of resources.
> - //
> - return Status;
> - }
> -
> - //
> - // Looking for FV with ACPI storage file
> - //
> - for (Index = 0; Index < NumberOfHandles; Index++) {
> -
> - //
> - // Get the protocol on this handle
> - // This should not fail because of LocateHandleBuffer
> - //
> - Status = gBS->HandleProtocol (
> - HandleBuffer[Index],
> - Protocol,
> - Instance
> - );
> - ASSERT_EFI_ERROR (Status);
> -
> - if (!Type) {
> -
> - //
> - // Not looking for the FV protocol, so find the first instance of the
> - // protocol. There should not be any errors because our handle
> buffer
> - // should always contain at least one or LocateHandleBuffer would
> have
> - // returned not found.
> - //
> - break;
> - }
> -
> - //
> - // See if it has the ACPI storage file
> - //
> - Size = 0;
> - FvStatus = 0;
> - Status = ((EFI_FIRMWARE_VOLUME2_PROTOCOL *)
> (*Instance))->ReadFile (
> -
> *Instance,
> -
> gEfiAcpiMultiTableStorageGuid,
> -
> NULL,
> -
> &Size,
> -
> &FileType,
> -
> &Attributes,
> -
> &FvStatus
> - );
> -
> - //
> - // If we found it, then we are done
> - //
> - if (Status == EFI_SUCCESS) {
> - break;
> - }
> - }
> -
> - //
> - // Our exit status is determined by the success of the previous operations
> - // If the protocol was found, Instance already points to it.
> - //
> - //
> - // Free any allocated buffers
> - //
> - FreePool (HandleBuffer);
> -
> - return Status;
> -}
> -
> -EFI_STATUS
> -PublishAcpiTablesFromFv (
> - IN EFI_GUID *gEfiAcpiMultiTableStorageGuid
> - )
> -{
> - EFI_STATUS Status;
> - EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
> - EFI_ACPI_COMMON_HEADER *CurrentTable;
> - UINT32 FvStatus;
> - UINTN Size;
> - EFI_ACPI_TABLE_VERSION Version;
> - UINTN TableHandle;
> - INTN Instance;
> - EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
> -
> - Instance = 0;
> - TableHandle = 0;
> - CurrentTable = NULL;
> - FwVol = NULL;
> -
> - //
> - // Find the AcpiSupport protocol
> - //
> - Status = LocateSupportProtocol (
> - &gEfiAcpiTableProtocolGuid,
> - gEfiAcpiMultiTableStorageGuid,
> - (VOID **) &AcpiTable,
> - FALSE
> - );
> - ASSERT_EFI_ERROR (Status);
> -
> - //
> - // Locate the firmware volume protocol
> - //
> - Status = LocateSupportProtocol (
> - &gEfiFirmwareVolume2ProtocolGuid,
> - gEfiAcpiMultiTableStorageGuid,
> - (VOID **) &FwVol,
> - TRUE
> - );
> -
> - //
> - // Read tables from the storage file.
> - //
> -
> - while (Status == EFI_SUCCESS) {
> - Status = FwVol->ReadSection (
> - FwVol,
> - gEfiAcpiMultiTableStorageGuid,
> - EFI_SECTION_RAW,
> - Instance,
> - (VOID **) &CurrentTable,
> - &Size,
> - &FvStatus
> - );
> -
> - if (!EFI_ERROR (Status)) {
> -
> - //
> - // Perform any table specific updates.
> - //
> - if (CurrentTable->Signature ==
> EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) {
> - UpdateDsdt (CurrentTable);
> - }
> - BoardUpdateAcpiTable (CurrentTable, &Version);
> -
> - //
> - // Add the table
> - //
> - TableHandle = 0;
> -
> - if (Version != EFI_ACPI_TABLE_VERSION_NONE) {
> - Status = AcpiTable->InstallAcpiTable (
> - AcpiTable,
> - CurrentTable,
> - CurrentTable->Length,
> - &TableHandle
> - );
> - }
> -
> - ASSERT_EFI_ERROR (Status);
> -
> - //
> - // Increment the instance
> - //
> - Instance++;
> - CurrentTable = NULL;
> - }
> - }
> -
> - //
> - // Finished
> - //
> - return EFI_SUCCESS;
> -}
> -
> -/**
> - ACPI Platform driver installation function.
> -
> - @param[in] ImageHandle Handle for this drivers loaded image
> protocol.
> - @param[in] SystemTable EFI system table.
> -
> - @retval EFI_SUCCESS The driver installed without error.
> - @retval EFI_ABORTED The driver encountered an error and
> could not complete installation of
> - the ACPI tables.
> -
> -**/
> -EFI_STATUS
> -EFIAPI
> -InstallAcpiBoard (
> - IN EFI_HANDLE ImageHandle,
> - IN EFI_SYSTEM_TABLE *SystemTable
> - )
> -{
> - EFI_STATUS Status;
> - EFI_HANDLE Handle;
> -
> - AcpiGnvsInit((VOID **) &mGlobalNvsArea.Area);
> -
> - //
> - // This PCD set must be done before PublishAcpiTablesFromFv.
> - // The PCD data will be used there.
> - //
> - PcdSet64S (PcdAcpiGnvsAddress, (UINT64)(UINTN)mGlobalNvsArea.Area);
> -
> - //
> - // Platform ACPI Tables
> - //
> - PublishAcpiTablesFromFv (&gEfiCallerIdGuid);
> -
> - //
> - // This protocol publish must be done after PublishAcpiTablesFromFv.
> - // The NVS data is be updated there.
> - //
> - Handle = NULL;
> - Status = gBS->InstallMultipleProtocolInterfaces (
> - &Handle,
> - &gEfiGlobalNvsAreaProtocolGuid,
> - &mGlobalNvsArea,
> - NULL
> - );
> - ASSERT_EFI_ERROR (Status);
> -
> - return EFI_SUCCESS;
> -}
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/UpdateDsdt.c
> b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/UpdateDsdt.c
> deleted file mode 100644
> index 41f0b8c113..0000000000
> --- a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/UpdateDsdt.c
> +++ /dev/null
> @@ -1,776 +0,0 @@
> -/** @file
> - Performs board DSDT ACPI table updates.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <Uefi.h>
> -#include <Library/IoLib.h>
> -#include <Library/PciLib.h>
> -#include <Library/DebugLib.h>
> -#include <Library/BaseMemoryLib.h>
> -#include <Library/UefiBootServicesTableLib.h>
> -
> -#include <Protocol/GlobalNvsArea.h>
> -extern GLOBAL_REMOVE_IF_UNREFERENCED
> EFI_GLOBAL_NVS_AREA_PROTOCOL mGlobalNvsArea;
> -
> -VOID
> -UpdateDsdt (
> - IN VOID *Table
> - )
> -{
> - UINT8 *CurrPtr;
> - UINT8 *TmpDsdtPointer;
> - UINT8 *DsdtPointer;
> - UINT32 *Signature;
> - UINT8 *Operation;
> - UINT32 *Address;
> - UINT8 *Value;
> - UINT16 *Size;
> - BOOLEAN EnterDock = FALSE;
> -
> - UINT8 MaximumDsdtPointLength;
> -
> - MaximumDsdtPointLength = 20;
> -
> - //
> - // Fix up the AML code in the DSDT affected by end user options.
> - // Fix up the following ASL Code:
> - // (1) ACPI Global NVS Memory Base and Size.
> - // (2) ACPI Graphics NVS Memory Base and Size.
> - // (3) SMBus I/O Base.
> - // (4) Thermal Management Methods.
> - //
> - //
> - // Loop through the ASL looking for values that we must fix up.
> - //
> - CurrPtr = (UINT8 *) Table;
> - for (DsdtPointer = CurrPtr;
> - DsdtPointer <= (CurrPtr + ((EFI_ACPI_COMMON_HEADER *)
> CurrPtr)->Length);
> - DsdtPointer++
> - ) {
> - Signature = (UINT32 *) DsdtPointer;
> - switch (*Signature) {
> - //
> - // GNVS operation region
> - //
> - case (SIGNATURE_32 ('G', 'N', 'V', 'S')):
> - //
> - // Conditional match. For Region Objects, the Operator will
> always be the
> - // byte immediately before the specific name. Therefore,
> subtract 1 to check
> - // the Operator.
> - //
> - Operation = DsdtPointer - 1;
> - if (*Operation == AML_EXT_REGION_OP) {
> - Address = (UINT32 *) (DsdtPointer + 6);
> - *Address = (UINT32) (UINTN) mGlobalNvsArea.Area;
> - Size = (UINT16 *) (DsdtPointer + 11);
> - *Size = sizeof (EFI_GLOBAL_NVS_AREA);
> - }
> - break;
> -
> - //
> - // _AC0 method
> - //
> - case (SIGNATURE_32 ('_', 'A', 'C', '0')):
> - //
> - // Conditional match. _AC0 is >63 and <4095 bytes, so the
> package length is 2 bytes.
> - // Therefore, subtract 3 to check the Operator.
> - //
> - Operation = DsdtPointer - 3;
> - if (*Operation == AML_METHOD_OP) {
> - //
> - // Check if we want _AC0 enabled
> - //
> - if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
> - Signature = (UINT32 *) DsdtPointer;
> - *Signature = SIGNATURE_32 ('X', 'A', 'C', '0');
> - }
> - }
> - break;
> -
> - //
> - // _AL0 method
> - //
> - case (SIGNATURE_32 ('_', 'A', 'L', '0')):
> - //
> - // Conditional match. For Name Objects, the Operator will
> always be the byte
> - // immediately before the specific name. Therefore, subtract 1
> to check the
> - // Operator.
> - //
> - Operation = DsdtPointer - 1;
> - if (*Operation == AML_NAME_OP) {
> -
> - //
> - // Check if we want _AL0 enabled
> - //
> - if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
> - Signature = (UINT32 *) DsdtPointer;
> - *Signature = SIGNATURE_32 ('X', 'A', 'L', '0');
> - }
> - }
> - break;
> -
> - //
> - // _AC1 method
> - //
> - case (SIGNATURE_32 ('_', 'A', 'C', '1')):
> - //
> - // Conditional match. _AC1 is < 63 bytes, so the package
> length is 1 byte.
> - // Therefore, subtract 2 to check the Operator.
> - //
> - Operation = DsdtPointer - 2;
> - if (*Operation == AML_METHOD_OP) {
> -
> - //
> - // Check if we want _AC1 enabled
> - //
> - if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
> - Signature = (UINT32 *) DsdtPointer;
> - *Signature = SIGNATURE_32 ('X', 'A', 'C', '1');
> - }
> - }
> - break;
> -
> - //
> - // _AL1 method
> - //
> - case (SIGNATURE_32 ('_', 'A', 'L', '1')):
> - //
> - // Conditional match. For Name Objects, the Operator will
> always be the byte
> - // immediately before the specific name. Therefore, subtract 1
> to check the
> - // Operator.
> - //
> - Operation = DsdtPointer - 1;
> - if (*Operation == AML_NAME_OP) {
> -
> - //
> - // Check if we want _AL1 enabled
> - //
> - if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
> - Signature = (UINT32 *) DsdtPointer;
> - *Signature = SIGNATURE_32 ('X', 'A', 'L', '1');
> - }
> - }
> - break;
> -
> - //
> - // _AC2 method
> - //
> - case (SIGNATURE_32 ('_', 'A', 'C', '2')):
> - //
> - // Conditional match. _AC2 is < 63 bytes, so the package
> length is 1 byte.
> - // Therefore, subtract 2 to check the Operator.
> - //
> - Operation = DsdtPointer - 2;
> - if (*Operation == AML_METHOD_OP) {
> -
> - //
> - // Check if we want _AC2 enabled
> - //
> - if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
> - Signature = (UINT32 *) DsdtPointer;
> - *Signature = SIGNATURE_32 ('X', 'A', 'C', '2');
> - }
> - }
> - break;
> -
> - //
> - // _AL2 method
> - //
> - case (SIGNATURE_32 ('_', 'A', 'L', '2')):
> - //
> - // Conditional match. For Name Objects, the Operator will
> always be the byte
> - // immediately before the specific name. Therefore, subtract 1
> to check the
> - // Operator.
> - //
> - Operation = DsdtPointer - 1;
> - if (*Operation == AML_NAME_OP) {
> -
> - //
> - // Check if we want _AL2 enabled
> - //
> - if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
> - Signature = (UINT32 *) DsdtPointer;
> - *Signature = SIGNATURE_32 ('X', 'A', 'L', '2');
> - }
> - }
> - break;
> -
> - //
> - // _AC3 method
> - //
> - case (SIGNATURE_32 ('_', 'A', 'C', '3')):
> - //
> - // Conditional match. _AC3 is < 63 bytes, so the package
> length is 1 byte.
> - // Therefore, subtract 2 to check the Operator.
> - //
> - Operation = DsdtPointer - 2;
> - if (*Operation == AML_METHOD_OP) {
> -
> - //
> - // Check if we want _AC3 enabled
> - //
> - if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
> - Signature = (UINT32 *) DsdtPointer;
> - *Signature = SIGNATURE_32 ('X', 'A', 'C', '3');
> - }
> - }
> - break;
> -
> - //
> - // _AL3 method
> - //
> - case (SIGNATURE_32 ('_', 'A', 'L', '3')):
> - //
> - // Conditional match. For Name Objects, the Operator will
> always be the byte
> - // immediately before the specific name. Therefore, subtract 1
> to check the
> - // Operator.
> - //
> - Operation = DsdtPointer - 1;
> - if (*Operation == AML_NAME_OP) {
> -
> - //
> - // Check if we want _AL3 enabled
> - //
> - if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
> - Signature = (UINT32 *) DsdtPointer;
> - *Signature = SIGNATURE_32 ('X', 'A', 'L', '3');
> - }
> - }
> - break;
> -
> - //
> - // _AC4 method
> - //
> - case (SIGNATURE_32 ('_', 'A', 'C', '4')):
> - //
> - // Conditional match. _AC4 is < 63 bytes, so the package
> length is 1 byte.
> - // Therefore, subtract 2 to check the Operator.
> - //
> - Operation = DsdtPointer - 2;
> - if (*Operation == AML_METHOD_OP) {
> -
> - //
> - // Check if we want _AC4 enabled
> - //
> - if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
> - Signature = (UINT32 *) DsdtPointer;
> - *Signature = SIGNATURE_32 ('X', 'A', 'C', '4');
> - }
> - }
> - break;
> -
> - //
> - // _AL4 method
> - //
> - case (SIGNATURE_32 ('_', 'A', 'L', '4')):
> - //
> - // Conditional match. For Name Objects, the Operator will
> always be the byte
> - // immediately before the specific name. Therefore, subtract 1
> to check the
> - // Operator.
> - //
> - Operation = DsdtPointer - 1;
> - if (*Operation == AML_NAME_OP) {
> -
> - //
> - // Check if we want _AL4 enabled
> - //
> - if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
> - Signature = (UINT32 *) DsdtPointer;
> - *Signature = SIGNATURE_32 ('X', 'A', 'L', '4');
> - }
> - }
> - break;
> -
> - //
> - // _AC5 method
> - //
> - case (SIGNATURE_32 ('_', 'A', 'C', '5')):
> - //
> - // Conditional match. _AC5 is < 63 bytes, so the package
> length is 1 byte.
> - // Therefore, subtract 2 to check the Operator.
> - //
> - Operation = DsdtPointer - 2;
> - if (*Operation == AML_METHOD_OP) {
> -
> - //
> - // Check if we want _AC5 enabled
> - //
> - if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
> - Signature = (UINT32 *) DsdtPointer;
> - *Signature = SIGNATURE_32 ('X', 'A', 'C', '5');
> - }
> - }
> - break;
> -
> - //
> - // _AL5 method
> - //
> - case (SIGNATURE_32 ('_', 'A', 'L', '5')):
> - //
> - // Conditional match. For Name Objects, the Operator will
> always be the byte
> - // immediately before the specific name. Therefore, subtract 1
> to check the
> - // Operator.
> - //
> - Operation = DsdtPointer - 1;
> - if (*Operation == AML_NAME_OP) {
> -
> - //
> - // Check if we want _AL5 enabled
> - //
> - if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
> - Signature = (UINT32 *) DsdtPointer;
> - *Signature = SIGNATURE_32 ('X', 'A', 'L', '5');
> - }
> - }
> - break;
> -
> - //
> - // _AC6 method
> - //
> - case (SIGNATURE_32 ('_', 'A', 'C', '6')):
> - //
> - // Conditional match. _AC6 is < 63 bytes, so the package
> length is 1 byte.
> - // Therefore, subtract 2 to check the Operator.
> - //
> - Operation = DsdtPointer - 2;
> - if (*Operation == AML_METHOD_OP) {
> -
> - //
> - // Check if we want _AC6 enabled
> - //
> - if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
> - Signature = (UINT32 *) DsdtPointer;
> - *Signature = SIGNATURE_32 ('X', 'A', 'C', '6');
> - }
> - }
> - break;
> -
> - //
> - // _AL6 method
> - //
> - case (SIGNATURE_32 ('_', 'A', 'L', '6')):
> - //
> - // Conditional match. For Name Objects, the Operator will
> always be the byte
> - // immediately before the specific name. Therefore, subtract 1
> to check the
> - // Operator.
> - //
> - Operation = DsdtPointer - 1;
> - if (*Operation == AML_NAME_OP) {
> -
> - //
> - // Check if we want _AL6 enabled
> - //
> - if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
> - Signature = (UINT32 *) DsdtPointer;
> - *Signature = SIGNATURE_32 ('X', 'A', 'L', '6');
> - }
> - }
> - break;
> -
> - //
> - // _AC7 method
> - //
> - case (SIGNATURE_32 ('_', 'A', 'C', '7')):
> - //
> - // Conditional match. _AC7 is < 63 bytes, so the package
> length is 1 byte.
> - // Therefore, subtract 2 to check the Operator.
> - //
> - Operation = DsdtPointer - 2;
> - if (*Operation == AML_METHOD_OP) {
> -
> - //
> - // Check if we want _AC7 enabled
> - //
> - if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
> - Signature = (UINT32 *) DsdtPointer;
> - *Signature = SIGNATURE_32 ('X', 'A', 'C', '7');
> - }
> - }
> - break;
> -
> - //
> - // _AL7 method
> - //
> - case (SIGNATURE_32 ('_', 'A', 'L', '7')):
> - //
> - // Conditional match. For Name Objects, the Operator will
> always be the byte
> - // immediately before the specific name. Therefore, subtract 1
> to check the
> - // Operator.
> - //
> - Operation = DsdtPointer - 1;
> - if (*Operation == AML_NAME_OP) {
> -
> - //
> - // Check if we want _AL7 enabled
> - //
> - if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
> - Signature = (UINT32 *) DsdtPointer;
> - *Signature = SIGNATURE_32 ('X', 'A', 'L', '7');
> - }
> - }
> - break;
> -
> - //
> - // _AC8 method
> - //
> - case (SIGNATURE_32 ('_', 'A', 'C', '8')):
> - //
> - // Conditional match. _AC8 is < 63 bytes, so the package
> length is 1 byte.
> - // Therefore, subtract 2 to check the Operator.
> - //
> - Operation = DsdtPointer - 2;
> - if (*Operation == AML_METHOD_OP) {
> -
> - //
> - // Check if we want _AC8 enabled
> - //
> - if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
> - Signature = (UINT32 *) DsdtPointer;
> - *Signature = SIGNATURE_32 ('X', 'A', 'C', '8');
> - }
> - }
> - break;
> -
> - //
> - // _AL8 method
> - //
> - case (SIGNATURE_32 ('_', 'A', 'L', '8')):
> - //
> - // Conditional match. For Name Objects, the Operator will
> always be the byte
> - // immediately before the specific name. Therefore, subtract 1
> to check the
> - // Operator.
> - //
> - Operation = DsdtPointer - 1;
> - if (*Operation == AML_NAME_OP) {
> -
> - //
> - // Check if we want _AL8 enabled
> - //
> - if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
> - Signature = (UINT32 *) DsdtPointer;
> - *Signature = SIGNATURE_32 ('X', 'A', 'L', '8');
> - }
> - }
> - break;
> -
> - //
> - // _AC9 method
> - //
> - case (SIGNATURE_32 ('_', 'A', 'C', '9')):
> - //
> - // Conditional match. _AC9 is < 63 bytes, so the package
> length is 1 byte.
> - // Therefore, subtract 2 to check the Operator.
> - //
> - Operation = DsdtPointer - 2;
> - if (*Operation == AML_METHOD_OP) {
> -
> - //
> - // Check if we want _AC9 enabled
> - //
> - if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
> - Signature = (UINT32 *) DsdtPointer;
> - *Signature = SIGNATURE_32 ('X', 'A', 'C', '9');
> - }
> - }
> - break;
> -
> - //
> - // _AL9 method
> - //
> - case (SIGNATURE_32 ('_', 'A', 'L', '9')):
> - //
> - // Conditional match. For Name Objects, the Operator will
> always be the byte
> - // immediately before the specific name. Therefore, subtract 1
> to check the
> - // Operator.
> - //
> - Operation = DsdtPointer - 1;
> - if (*Operation == AML_NAME_OP) {
> -
> - //
> - // Check if we want _AL9 enabled
> - //
> - if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
> - Signature = (UINT32 *) DsdtPointer;
> - *Signature = SIGNATURE_32 ('X', 'A', 'L', '9');
> - }
> - }
> - break;
> -
> - //
> - // _PSL method
> - //
> - case (SIGNATURE_32 ('_', 'P', 'S', 'L')):
> - //
> - // Conditional match. _PSL is < 256 bytes, so the package
> length is 1 byte.
> - // Therefore, subtract 2 to check the Operator.
> - //
> - Operation = DsdtPointer - 3;
> - if (*Operation == AML_METHOD_OP) {
> -
> - //
> - // Check if we want _PSL enabled
> - //
> - if (PcdGet8 (PcdDisablePassiveTripPoints) == 0) {
> - Signature = (UINT32 *) DsdtPointer;
> - *Signature = SIGNATURE_32 ('X', 'P', 'S', 'L');
> - }
> - }
> - break;
> -
> - //
> - // _PSV method
> - //
> - case (SIGNATURE_32 ('_', 'P', 'S', 'V')):
> - //
> - // Conditional match. _PSV is < 256 bytes, so the package
> length is 1 byte.
> - // Therefore, subtract 2 to check the Operator.
> - //
> - Operation = DsdtPointer - 3;
> - if (*Operation == AML_METHOD_OP) {
> -
> - //
> - // Check if we want _PSV enabled
> - //
> - if (PcdGet8 (PcdDisablePassiveTripPoints) == 0) {
> - Signature = (UINT32 *) DsdtPointer;
> - *Signature = SIGNATURE_32 ('X', 'P', 'S', 'V');
> - }
> - }
> - break;
> -
> - //
> - // _CRT method
> - //
> - case (SIGNATURE_32 ('_', 'C', 'R', 'T')):
> - //
> - // Conditional match. _CRT is < 256 bytes, so the package
> length is 1 byte.
> - // Subtract 3 to check the Operator for CRB, subract 2 for Harris
> Beach.
> - //
> - Operation = DsdtPointer - 3;
> - if (*Operation == AML_METHOD_OP) {
> -
> - //
> - // Check if we want _CRT enabled
> - //
> - if (PcdGet8 (PcdDisableCriticalTripPoints) == 0) {
> - Signature = (UINT32 *) DsdtPointer;
> - *Signature = SIGNATURE_32 ('X', 'C', 'R', 'T');
> - }
> - }
> - break;
> -
> - //
> - // _TC1 method
> - //
> - case (SIGNATURE_32 ('_', 'T', 'C', '1')):
> - //
> - // Conditional match. _TC1 is < 256 bytes, so the package
> length is 1 byte.
> - // Therefore, subtract 2 to check the Operator.
> - //
> - Operation = DsdtPointer - 2;
> - if (*Operation == AML_METHOD_OP) {
> -
> - //
> - // Check if we want _TC1 enabled
> - //
> - if (PcdGet8 (PcdDisablePassiveTripPoints) == 0) {
> - Signature = (UINT32 *) DsdtPointer;
> - *Signature = SIGNATURE_32 ('X', 'T', 'C', '1');
> - }
> - }
> - break;
> -
> - //
> - // _TC2 method
> - //
> - case (SIGNATURE_32 ('_', 'T', 'C', '2')):
> - //
> - // Conditional match. _TC2 is < 256 bytes, so the package
> length is 1 byte.
> - // Therefore, subtract 2 to check the Operator.
> - //
> - Operation = DsdtPointer - 2;
> - if (*Operation == AML_METHOD_OP) {
> -
> - //
> - // Check if we want _TC2 enabled
> - //
> - if (PcdGet8 (PcdDisablePassiveTripPoints) == 0) {
> - Signature = (UINT32 *) DsdtPointer;
> - *Signature = SIGNATURE_32 ('X', 'T', 'C', '2');
> - }
> - }
> - break;
> -
> - //
> - // _TSP method
> - //
> - case (SIGNATURE_32 ('_', 'T', 'S', 'P')):
> - //
> - // Conditional match. _TSP is < 256 bytes, so the package
> length is 1 byte.
> - // Therefore, subtract 2 to check the Operator.
> - //
> - Operation = DsdtPointer - 2;
> - if (*Operation == AML_METHOD_OP) {
> -
> - //
> - // Check if we want _TSP enabled
> - //
> - if (PcdGet8 (PcdDisablePassiveTripPoints) == 0) {
> - Signature = (UINT32 *) DsdtPointer;
> - *Signature = SIGNATURE_32 ('X', 'T', 'S', 'P');
> - }
> - }
> - break;
> -
> - //
> - // Update SS3 Name with Setup value
> - //
> - case (SIGNATURE_32 ('S', 'S', '3', '_')):
> - Operation = DsdtPointer - 1;
> - if (*Operation == AML_NAME_OP) {
> - Value = (UINT8 *) DsdtPointer + 4;
> - *Value = PcdGet8 (PcdAcpiSleepState);
> - }
> - break;
> - //
> - // Update SS4 Name with Setup value
> - //
> - case (SIGNATURE_32 ('S', 'S', '4', '_')):
> - Operation = DsdtPointer - 1;
> - if (*Operation == AML_NAME_OP) {
> - Value = (UINT8 *) DsdtPointer + 4;
> - *Value = PcdGet8 (PcdAcpiHibernate);
> - }
> - break;
> - //
> - // _EJ0 method
> - //
> - case (SIGNATURE_32 ('_', 'E', 'J', '0')):
> - if (PcdGet8 (PcdLowPowerS0Idle)) {
> - //
> - // Remove _EJ0 for SOC
> - //
> - if (*(DsdtPointer-3) == AML_METHOD_OP) {
> - Signature = (UINT32 *) DsdtPointer;
> - *Signature = SIGNATURE_32 ('X', 'E', 'J', '0');
> - EnterDock = TRUE;
> - }
> - }
> - break;
> - //
> - // _STA method for Device (\_SB.PCI0.DOCK)
> - //
> - case (SIGNATURE_32 ('_', 'S', 'T', 'A')):
> - if (PcdGet8 (PcdLowPowerS0Idle)) {
> - //
> - // Remove _STA in (\_SB.PCI0.DOCK) for SOC
> - //
> - if ((*(DsdtPointer-3) == AML_METHOD_OP) && (EnterDock)) {
> - Signature = (UINT32 *) DsdtPointer;
> - *Signature = SIGNATURE_32 ('X', 'S', 'T', 'A');
> - EnterDock = FALSE;
> - }
> - }
> - break;
> - //
> - // _UPC method for Device (\_SB.PCI0.XHC.RHUB)
> - //
> - case (SIGNATURE_32('H', 'S', '1', '3')):
> - for (TmpDsdtPointer = DsdtPointer;
> - TmpDsdtPointer <= DsdtPointer +
> MaximumDsdtPointLength;
> - TmpDsdtPointer++){
> - Signature = (UINT32 *) TmpDsdtPointer;
> - switch (*Signature) {
> - case(SIGNATURE_32('U', 'P', 'C', 'P')):
> - Value = (UINT8 *)((UINT32 *)TmpDsdtPointer + 2);
> - break;
> - default:
> - //
> - // Do nothing.
> - //
> - break;
> - }
> - }
> - break;
> -
> -
> - //
> - // _DCK method
> - //
> - case (SIGNATURE_32 ('_', 'D', 'C', 'K')):
> - if (PcdGet8 (PcdLowPowerS0Idle)) {
> - //
> - // Remove _DCK for SOC
> - //
> - if (*(DsdtPointer-3) == AML_METHOD_OP) {
> - Signature = (UINT32 *) DsdtPointer;
> - *Signature = SIGNATURE_32 ('X', 'D', 'C', 'K');
> - }
> - }
> - break;
> -
> - //
> - // mask _DEP from CPU's scope if CS disabled.
> - //
> - case (SIGNATURE_32 ('P', 'R', '0', '0')):
> - case (SIGNATURE_32 ('P', 'R', '0', '1')):
> - case (SIGNATURE_32 ('P', 'R', '0', '2')):
> - case (SIGNATURE_32 ('P', 'R', '0', '3')):
> - case (SIGNATURE_32 ('P', 'R', '0', '4')):
> - case (SIGNATURE_32 ('P', 'R', '0', '5')):
> - case (SIGNATURE_32 ('P', 'R', '0', '6')):
> - case (SIGNATURE_32 ('P', 'R', '0', '7')):
> - case (SIGNATURE_32 ('P', 'R', '0', '8')):
> - case (SIGNATURE_32 ('P', 'R', '0', '9')):
> - case (SIGNATURE_32 ('P', 'R', '1', '0')):
> - case (SIGNATURE_32 ('P', 'R', '1', '1')):
> - case (SIGNATURE_32 ('P', 'R', '1', '2')):
> - case (SIGNATURE_32 ('P', 'R', '1', '3')):
> - case (SIGNATURE_32 ('P', 'R', '1', '4')):
> - case (SIGNATURE_32 ('P', 'R', '1', '5')):
> -
> - if (PcdGet8 (PcdLowPowerS0Idle) == 0) {
> - for (TmpDsdtPointer = DsdtPointer; TmpDsdtPointer <=
> DsdtPointer + MaximumDsdtPointLength; TmpDsdtPointer++){
> - Signature = (UINT32 *) TmpDsdtPointer;
> - switch (*Signature) {
> - case(SIGNATURE_32('_', 'D', 'E', 'P')):
> - *(UINT8 *) TmpDsdtPointer = 'X';
> - break;
> - default:
> - //
> - // Do nothing.
> - //
> - break;
> - }
> - }
> - }
> - break;
> -
> - //
> - // _EDL name
> - //
> - case (SIGNATURE_32 ('_', 'E', 'D', 'L')):
> - if (PcdGet8 (PcdLowPowerS0Idle)) {
> - //
> - // Remove _EDL for SOC
> - //
> - if (*(DsdtPointer-1) == AML_NAME_OP) {
> - Signature = (UINT32 *) DsdtPointer;
> - *Signature = SIGNATURE_32 ('X', 'E', 'D', 'L');
> - }
> - }
> - break;
> -
> - default:
> - //
> - // Do nothing.
> - //
> - break;
> - }
> - }
> -}
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/PciHotPlug/PciHotPlug.c
> b/Platform/Intel/ClevoOpenBoardPkg/Features/PciHotPlug/PciHotPlug.c
> deleted file mode 100644
> index 05f128d719..0000000000
> --- a/Platform/Intel/ClevoOpenBoardPkg/Features/PciHotPlug/PciHotPlug.c
> +++ /dev/null
> @@ -1,351 +0,0 @@
> -/** @file
> - Performs specific PCI-EXPRESS device resource configuration.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -//
> -// Statements that include other files
> -//
> -#include "PciHotPlug.h"
> -#include <Ppi/SiPolicy.h>
> -#include <TbtBoardInfo.h>
> -#include <Library/PchPcieRpLib.h>
> -#include <Library/TbtCommonLib.h>
> -
> -#define PCIE_NUM (20)
> -#define PEG_NUM (3)
> -#define PADDING_BUS (1)
> -#define PADDING_NONPREFETCH_MEM (1)
> -#define PADDING_PREFETCH_MEM (1)
> -#define PADDING_IO (1)
> -#define PADDING_NUM (PADDING_BUS + PADDING_NONPREFETCH_MEM +
> PADDING_PREFETCH_MEM + PADDING_IO)
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED EFI_HPC_LOCATION
> mPcieLocation[PCIE_NUM + PEG_NUM];
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED UINTN mHpcCount = 0;
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED PCIE_HOT_PLUG_DEVICE_PATH
> mHotplugPcieDevicePathTemplate = {
> - ACPI,
> - PCI(0xFF, 0xFF), // Dummy Device no & Function no
> - END
> -};
> -
> -/**
> - Entry point for the driver.
> -
> - This routine reads the PlatformType GPI on FWH and produces a protocol
> - to be consumed by the chipset driver to effect those settings.
> -
> - @param[in] ImageHandle An image handle.
> - @param[in] SystemTable A pointer to the system table.
> -
> - @retval EFI_SUCCESS.
> -**/
> -EFI_STATUS
> -EFIAPI
> -PciHotPlug (
> - IN EFI_HANDLE ImageHandle,
> - IN EFI_SYSTEM_TABLE *SystemTable
> - )
> -{
> - EFI_STATUS Status;
> - PCI_HOT_PLUG_INSTANCE *PciHotPlug;
> - UINTN Index;
> - UINTN RpDev;
> - UINTN RpFunc;
> - PCIE_HOT_PLUG_DEVICE_PATH *HotplugPcieDevicePath;
> - UINT32 PcieRootPortHpeData = 0;
> -
> - DEBUG ((DEBUG_INFO, "PciHotPlug Entry\n"));
> -
> - PcieRootPortHpeData = PcdGet32 (PcdPchPcieRootPortHpe);
> - //
> - // PCH Rootports Hotplug device path creation
> - //
> - for (Index = 0; Index < PCIE_NUM; Index++) {
> - if (((PcieRootPortHpeData >> Index) & BIT0) == BIT0) { // Check the
> Rootport no's hotplug is set
> - Status = GetPchPcieRpDevFun (Index, &RpDev, &RpFunc); // Get the
> actual device/function no corresponding to the Rootport no provided
> - ASSERT_EFI_ERROR (Status);
> -
> - HotplugPcieDevicePath = NULL;
> - HotplugPcieDevicePath = AllocatePool (sizeof
> (PCIE_HOT_PLUG_DEVICE_PATH));
> - ASSERT (HotplugPcieDevicePath != NULL);
> - if (HotplugPcieDevicePath == NULL) {
> - return EFI_OUT_OF_RESOURCES;
> - }
> - CopyMem (HotplugPcieDevicePath,
> &mHotplugPcieDevicePathTemplate, sizeof (PCIE_HOT_PLUG_DEVICE_PATH));
> - HotplugPcieDevicePath->PciRootPortNode.Device = (UINT8) RpDev; //
> Update real Device no
> - HotplugPcieDevicePath->PciRootPortNode.Function = (UINT8) RpFunc;
> // Update real Function no
> -
> - mPcieLocation[mHpcCount].HpcDevicePath =
> (EFI_DEVICE_PATH_PROTOCOL *)HotplugPcieDevicePath;
> - mPcieLocation[mHpcCount].HpbDevicePath =
> (EFI_DEVICE_PATH_PROTOCOL *)HotplugPcieDevicePath;
> - mHpcCount++;
> -
> - DEBUG ((DEBUG_INFO, "(%02d) PciHotPlug (PCH RP#) : Bus 0x00,
> Device 0x%x, Function 0x%x is added to the Hotplug Device Path list \n",
> mHpcCount, RpDev, RpFunc));
> - }
> - }
> -
> -
> - PciHotPlug = AllocatePool (sizeof (PCI_HOT_PLUG_INSTANCE));
> - ASSERT (PciHotPlug != NULL);
> - if (PciHotPlug == NULL) {
> - return EFI_OUT_OF_RESOURCES;
> - }
> -
> - //
> - // Initialize driver private data.
> - //
> - ZeroMem (PciHotPlug, sizeof (PCI_HOT_PLUG_INSTANCE));
> -
> - PciHotPlug->Signature =
> PCI_HOT_PLUG_DRIVER_PRIVATE_SIGNATURE;
> - PciHotPlug->HotPlugInitProtocol.GetRootHpcList = GetRootHpcList;
> - PciHotPlug->HotPlugInitProtocol.InitializeRootHpc = InitializeRootHpc;
> - PciHotPlug->HotPlugInitProtocol.GetResourcePadding =
> GetResourcePadding;
> -
> - Status = gBS->InstallProtocolInterface (
> - &PciHotPlug->Handle,
> - &gEfiPciHotPlugInitProtocolGuid,
> - EFI_NATIVE_INTERFACE,
> - &PciHotPlug->HotPlugInitProtocol
> - );
> - ASSERT_EFI_ERROR (Status);
> -
> - return EFI_SUCCESS;
> -}
> -
> -
> -/**
> - This procedure returns a list of Root Hot Plug controllers that require
> - initialization during boot process
> -
> - @param[in] This The pointer to the instance of the
> EFI_PCI_HOT_PLUG_INIT protocol.
> - @param[out] HpcCount The number of Root HPCs returned.
> - @param[out] HpcList The list of Root HPCs. HpcCount defines the
> number of elements in this list.
> -
> - @retval EFI_SUCCESS.
> -**/
> -EFI_STATUS
> -EFIAPI
> -GetRootHpcList (
> - IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,
> - OUT UINTN *HpcCount,
> - OUT EFI_HPC_LOCATION **HpcList
> - )
> -{
> - *HpcCount = mHpcCount;
> - *HpcList = mPcieLocation;
> -
> - return EFI_SUCCESS;
> -}
> -
> -
> -/**
> - This procedure Initializes one Root Hot Plug Controller
> - This process may casue initialization of its subordinate buses
> -
> - @param[in] This The pointer to the instance of the
> EFI_PCI_HOT_PLUG_INIT protocol.
> - @param[in] HpcDevicePath The Device Path to the HPC that is being
> initialized.
> - @param[in] HpcPciAddress The address of the Hot Plug Controller
> function on the PCI bus.
> - @param[in] Event The event that should be signaled when
> the Hot Plug Controller initialization is complete. Set to NULL if the caller
> wants to wait until the entire initialization process is complete. The event
> must be of the type EFI_EVT_SIGNAL.
> - @param[out] HpcState The state of the Hot Plug Controller
> hardware. The type EFI_Hpc_STATE is defined in section 3.1.
> -
> - @retval EFI_SUCCESS.
> -**/
> -EFI_STATUS
> -EFIAPI
> -InitializeRootHpc (
> - IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,
> - IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,
> - IN UINT64 HpcPciAddress,
> - IN EFI_EVENT Event, OPTIONAL
> - OUT EFI_HPC_STATE *HpcState
> - )
> -{
> - if (Event) {
> - gBS->SignalEvent (Event);
> - }
> -
> - *HpcState = EFI_HPC_STATE_INITIALIZED;
> -
> - return EFI_SUCCESS;
> -}
> -
> -
> -/**
> - Returns the resource padding required by the PCI bus that is controlled
> by the specified Hot Plug Controller.
> -
> - @param[in] This The pointer to the instance of the
> EFI_PCI_HOT_PLUG_INIT protocol. initialized.
> - @param[in] HpcDevicePath The Device Path to the Hot Plug
> Controller.
> - @param[in] HpcPciAddress The address of the Hot Plug Controller
> function on the PCI bus.
> - @param[out] HpcState The state of the Hot Plug Controller
> hardware. The type EFI_HPC_STATE is defined in section 3.1.
> - @param[out] Padding This is the amount of resource padding
> required by the PCI bus under the control of the specified Hpc. Since the
> caller does not know the size of this buffer, this buffer is allocated by the
> callee and freed by the caller.
> - @param[out] Attribute Describes how padding is accounted for.
> -
> - @retval EFI_SUCCESS.
> -**/
> -EFI_STATUS
> -EFIAPI
> -GetResourcePadding (
> - IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,
> - IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,
> - IN UINT64 HpcPciAddress,
> - OUT EFI_HPC_STATE *HpcState,
> - OUT VOID **Padding,
> - OUT EFI_HPC_PADDING_ATTRIBUTES *Attributes
> - )
> -{
> - EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *PaddingResource;
> - EFI_STATUS Status;
> - UINT8 RsvdExtraBusNum = 0;
> - UINT16 RsvdPcieMegaMem = 10;
> - UINT8 PcieMemAddrRngMax = 0;
> - UINT16 RsvdPciePMegaMem = 10;
> - UINT8 PciePMemAddrRngMax = 0;
> - UINT8 RsvdTbtExtraBusNum = 0;
> - UINT16 RsvdTbtPcieMegaMem = 10;
> - UINT8 TbtPcieMemAddrRngMax = 0;
> - UINT16 RsvdTbtPciePMegaMem = 10;
> - UINT8 TbtPciePMemAddrRngMax = 0;
> - UINT8 RsvdPcieKiloIo = 4;
> - BOOLEAN SetResourceforTbt = FALSE;
> - UINTN RpIndex;
> - UINTN RpDev;
> - UINTN RpFunc;
> -
> -DEBUG ((DEBUG_INFO, "GetResourcePadding : Start \n"));
> -
> - PaddingResource = AllocatePool (PADDING_NUM * sizeof
> (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof
> (EFI_ACPI_END_TAG_DESCRIPTOR));
> - ASSERT (PaddingResource != NULL);
> - if (PaddingResource == NULL) {
> - return EFI_OUT_OF_RESOURCES;
> - }
> -
> - *Padding = (VOID *) PaddingResource;
> -
> - RpDev = (UINTN) ((HpcPciAddress >> 16) & 0xFF);
> - RpFunc = (UINTN) ((HpcPciAddress >> 8) & 0xFF);
> -
> - // Get the actual Rootport no corresponding to the device/function no
> provided
> - if (RpDev == SA_PEG_DEV_NUM) {
> - // PEG
> - RpIndex = PCIE_NUM + RpFunc;
> - DEBUG ((DEBUG_INFO, "GetResourcePadding : PEG Rootport no %02d
> Bus 0x00, Device 0x%x, Function 0x%x \n", (RpIndex-PCIE_NUM), RpDev,
> RpFunc));
> - } else {
> - // PCH
> - Status = GetPchPcieRpNumber (RpDev, RpFunc, &RpIndex);
> - DEBUG ((DEBUG_INFO, "GetResourcePadding : PCH Rootport no %02d
> Bus 0x00, Device 0x%x, Function 0x%x \n", RpIndex, RpDev, RpFunc));
> - }
> -
> - GetRootporttoSetResourcesforTbt(RpIndex, &RsvdTbtExtraBusNum,
> &RsvdTbtPcieMegaMem ,&TbtPcieMemAddrRngMax ,&RsvdTbtPciePMegaM
> em ,&TbtPciePMemAddrRngMax, &SetResourceforTbt);
> - if (SetResourceforTbt) {
> - RsvdExtraBusNum = RsvdTbtExtraBusNum;
> - RsvdPcieMegaMem = RsvdTbtPcieMegaMem;
> - PcieMemAddrRngMax = TbtPcieMemAddrRngMax;
> - RsvdPciePMegaMem = RsvdTbtPciePMegaMem;
> - PciePMemAddrRngMax = TbtPciePMemAddrRngMax;
> - }
> -
> - //
> - // Padding for bus
> - //
> - ZeroMem (PaddingResource, PADDING_NUM * sizeof
> (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof
> (EFI_ACPI_END_TAG_DESCRIPTOR));
> - *Attributes = EfiPaddingPciBus;
> -
> - PaddingResource->Desc = 0x8A;
> - PaddingResource->Len = 0x2B;
> - PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS;
> - PaddingResource->GenFlag = 0x0;
> - PaddingResource->SpecificFlag = 0;
> - PaddingResource->AddrRangeMin = 0;
> - PaddingResource->AddrRangeMax = 0;
> - PaddingResource->AddrLen = RsvdExtraBusNum;
> -
> - //
> - // Padding for non-prefetchable memory
> - //
> - PaddingResource++;
> - PaddingResource->Desc = 0x8A;
> - PaddingResource->Len = 0x2B;
> - PaddingResource->ResType =
> ACPI_ADDRESS_SPACE_TYPE_MEM;
> - PaddingResource->GenFlag = 0x0;
> - if (SetResourceforTbt) {
> - PaddingResource->AddrSpaceGranularity = 32;
> - } else {
> - PaddingResource->AddrSpaceGranularity = 32;
> - }
> - PaddingResource->SpecificFlag = 0;
> - //
> - // Pad non-prefetchable
> - //
> - PaddingResource->AddrRangeMin = 0;
> - PaddingResource->AddrLen = RsvdPcieMegaMem * 0x100000;
> - if (SetResourceforTbt) {
> - PaddingResource->AddrRangeMax = (1 << PcieMemAddrRngMax) - 1;
> - } else {
> - PaddingResource->AddrRangeMax = 1;
> - }
> -
> - //
> - // Padding for prefetchable memory
> - //
> - PaddingResource++;
> - PaddingResource->Desc = 0x8A;
> - PaddingResource->Len = 0x2B;
> - PaddingResource->ResType =
> ACPI_ADDRESS_SPACE_TYPE_MEM;
> - PaddingResource->GenFlag = 0x0;
> - if (SetResourceforTbt) {
> - PaddingResource->AddrSpaceGranularity = 32;
> - } else {
> - PaddingResource->AddrSpaceGranularity = 32;
> - }
> - PaddingResource->SpecificFlag = 06;
> - //
> - // Padding for prefetchable memory
> - //
> - PaddingResource->AddrRangeMin = 0;
> - if (SetResourceforTbt) {
> - PaddingResource->AddrLen = RsvdPciePMegaMem * 0x100000;
> - } else {
> - PaddingResource->AddrLen = RsvdPcieMegaMem * 0x100000;
> - }
> - //
> - // Pad 16 MB of MEM
> - //
> - if (SetResourceforTbt) {
> - PaddingResource->AddrRangeMax = (1 << PciePMemAddrRngMax) - 1;
> - } else {
> - PaddingResource->AddrRangeMax = 1;
> - }
> - //
> - // Alignment
> - //
> - // Padding for I/O
> - //
> - PaddingResource++;
> - PaddingResource->Desc = 0x8A;
> - PaddingResource->Len = 0x2B;
> - PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
> - PaddingResource->GenFlag = 0x0;
> - PaddingResource->SpecificFlag = 0;
> - PaddingResource->AddrRangeMin = 0;
> - PaddingResource->AddrLen = RsvdPcieKiloIo * 0x400;
> - //
> - // Pad 4K of IO
> - //
> - PaddingResource->AddrRangeMax = 1;
> - //
> - // Alignment
> - //
> - // Terminate the entries.
> - //
> - PaddingResource++;
> - ((EFI_ACPI_END_TAG_DESCRIPTOR *) PaddingResource)->Desc =
> ACPI_END_TAG_DESCRIPTOR;
> - ((EFI_ACPI_END_TAG_DESCRIPTOR *) PaddingResource)->Checksum = 0x0;
> -
> - *HpcState = EFI_HPC_STATE_INITIALIZED | EFI_HPC_STATE_ENABLED;
> -
> - return EFI_SUCCESS;
> -}
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib/
> DxeTbtPolicyLib.c
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib/
> DxeTbtPolicyLib.c
> deleted file mode 100644
> index b221e26d8e..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib/
> DxeTbtPolicyLib.c
> +++ /dev/null
> @@ -1,160 +0,0 @@
> -/** @file
> - This file is DxeTbtPolicyLib library.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -#include <DxeTbtPolicyLibrary.h>
> -#include <TbtBoardInfo.h>
> -#include <Protocol/DxeTbtPolicy.h>
> -#include <Guid/HobList.h>
> -#include <Library/HobLib.h>
> -
> -/**
> -Update Tbt Policy Callback
> -Need to add PCDs for setup options
> -**/
> -
> -VOID
> -EFIAPI
> -UpdateTbtPolicyCallback (
> - VOID
> - )
> -{
> -
> - EFI_STATUS Status;
> - DXE_TBT_POLICY_PROTOCOL *DxeTbtConfig;
> -
> - DxeTbtConfig = NULL;
> - Status = EFI_NOT_FOUND;
> - DEBUG ((DEBUG_INFO, "UpdateTbtPolicyCallback\n"));
> -
> - Status = gBS->LocateProtocol (
> - &gDxeTbtPolicyProtocolGuid,
> - NULL,
> - (VOID **) &DxeTbtConfig
> - );
> - if (EFI_ERROR (Status)) {
> - DEBUG ((DEBUG_ERROR, " gDxeTbtPolicyProtocolGuid Not
> installed!!!\n"));
> - } else {
> - DxeTbtConfig->DTbtResourceConfig.DTbtPcieExtraBusRsvd = PcdGet8
> (PcdDTbtPcieExtraBusRsvd);
> - DxeTbtConfig->DTbtResourceConfig.DTbtPcieMemRsvd =
> PcdGet16 (PcdDTbtPcieMemRsvd);
> - DxeTbtConfig->DTbtResourceConfig.DTbtPcieMemAddrRngMax =
> PcdGet8 (PcdDTbtPcieMemAddrRngMax);
> - DxeTbtConfig->DTbtResourceConfig.DTbtPciePMemRsvd =
> PcdGet16 (PcdDTbtPciePMemRsvd);
> - DxeTbtConfig->DTbtResourceConfig.DTbtPciePMemAddrRngMax =
> PcdGet8 (PcdDTbtPciePMemAddrRngMax);
> -
> - DxeTbtConfig->TbtCommonConfig.TbtAspm = PcdGet8
> (PcdDTbtAspm);
> - DxeTbtConfig->TbtCommonConfig.TbtHotNotify = PcdGet8
> (PcdDTbtHotNotify);
> - DxeTbtConfig->TbtCommonConfig.TbtHotSMI = PcdGet8
> (PcdDTbtHotSMI);
> - DxeTbtConfig->TbtCommonConfig.TbtSetClkReq = PcdGet8
> (PcdDTbtSetClkReq);
> - DxeTbtConfig->TbtCommonConfig.TbtWakeupSupport = PcdGet8
> (PcdDTbtWakeupSupport);
> - DxeTbtConfig->TbtCommonConfig.SecurityMode = PcdGet8
> (PcdDTbtSecurityMode);
> -
> - DxeTbtConfig->TbtCommonConfig.Gpio5Filter = PcdGet8
> (PcdDTbtGpio5Filter);
> - DxeTbtConfig->TbtCommonConfig.TbtAcDcSwitch = PcdGet8
> (PcdDTbtAcDcSwitch);
> -
> - DxeTbtConfig->TbtCommonConfig.Rtd3Tbt = PcdGet8
> (PcdRtd3Tbt);
> - DxeTbtConfig->TbtCommonConfig.Rtd3TbtOffDelay = PcdGet16
> (PcdRtd3TbtOffDelay);
> - DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReq = PcdGet8
> (PcdRtd3TbtClkReq);
> - DxeTbtConfig->TbtCommonConfig.Win10Support = PcdGet8
> (PcdDTbtWin10Support);
> - }
> -
> - return;
> -}
> -
> -/**
> - Print DXE TBT Policy
> -**/
> -VOID
> -TbtPrintDxePolicyConfig (
> - VOID
> - )
> -{
> - EFI_STATUS Status;
> - DXE_TBT_POLICY_PROTOCOL *DxeTbtConfig;
> -
> - DEBUG ((DEBUG_INFO, "TbtPrintDxePolicyConfig Start\n"));
> -
> - DxeTbtConfig = NULL;
> - Status = EFI_NOT_FOUND;
> - Status = gBS->LocateProtocol (
> - &gDxeTbtPolicyProtocolGuid,
> - NULL,
> - (VOID **) &DxeTbtConfig
> - );
> - if (EFI_ERROR (Status)) {
> - DEBUG ((DEBUG_ERROR, " gDxeTbtPolicyProtocolGuid Not
> installed!!!\n"));
> - }
> - ASSERT_EFI_ERROR (Status);
> - //
> - // Print DTBT Policy
> - //
> - DEBUG ((DEBUG_ERROR, " ========================= DXE TBT POLICY
> ========================= \n"));
> - DEBUG ((DEBUG_INFO,
> "DxeTbtConfig->DTbtResourceConfig.DTbtPcieExtraBusRsvd = %x\n",
> DxeTbtConfig->DTbtResourceConfig.DTbtPcieExtraBusRsvd));
> - DEBUG ((DEBUG_INFO,
> "DxeTbtConfig->DTbtResourceConfig.DTbtPcieMemRsvd = %x\n",
> DxeTbtConfig->DTbtResourceConfig.DTbtPcieMemRsvd));
> - DEBUG ((DEBUG_INFO,
> "DxeTbtConfig->DTbtResourceConfig.DTbtPcieMemAddrRngMax = %x\n",
> DxeTbtConfig->DTbtResourceConfig.DTbtPcieMemAddrRngMax));
> - DEBUG ((DEBUG_INFO,
> "DxeTbtConfig->DTbtResourceConfig.DTbtPciePMemRsvd = %x\n",
> DxeTbtConfig->DTbtResourceConfig.DTbtPciePMemRsvd));
> - DEBUG ((DEBUG_INFO,
> "DxeTbtConfig->DTbtResourceConfig.DTbtPciePMemAddrRngMax = %x\n",
> DxeTbtConfig->DTbtResourceConfig.DTbtPciePMemAddrRngMax));
> -
> -
> - //
> - // Print TBT Common Policy
> - //
> - DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtAspm =
> %x\n", DxeTbtConfig->TbtCommonConfig.TbtAspm));
> - DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtHotNotify =
> %x\n", DxeTbtConfig->TbtCommonConfig.TbtHotNotify));
> - DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtHotSMI =
> %x\n", DxeTbtConfig->TbtCommonConfig.TbtHotSMI));
> - DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtLtr = %x\n",
> DxeTbtConfig->TbtCommonConfig.TbtLtr));
> - DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtSetClkReq =
> %x\n", DxeTbtConfig->TbtCommonConfig.TbtSetClkReq));
> - DEBUG ((DEBUG_INFO,
> "DxeTbtConfig->TbtCommonConfig.TbtWakeupSupport = %x\n",
> DxeTbtConfig->TbtCommonConfig.TbtWakeupSupport));
> - DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.SecurityMode
> = %x\n", DxeTbtConfig->TbtCommonConfig.SecurityMode));
> - DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Gpio5Filter =
> %x\n", DxeTbtConfig->TbtCommonConfig.Gpio5Filter));
> - DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtAcDcSwitch
> = %x\n", DxeTbtConfig->TbtCommonConfig.TbtAcDcSwitch));
> - DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Rtd3Tbt =
> %x\n", DxeTbtConfig->TbtCommonConfig.Rtd3Tbt));
> - DEBUG ((DEBUG_INFO,
> "DxeTbtConfig->TbtCommonConfig.Rtd3TbtOffDelay = %x\n",
> DxeTbtConfig->TbtCommonConfig.Rtd3TbtOffDelay));
> - DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReq
> = %x\n", DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReq));
> - DEBUG ((DEBUG_INFO,
> "DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReqDelay = %x\n",
> DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReqDelay));
> - DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Win10Support
> = %x\n", DxeTbtConfig->TbtCommonConfig.Win10Support));
> -
> - return;
> -}
> -
> -/**
> - Install Tbt Policy
> -
> - @param[in] ImageHandle Image handle of this driver.
> -
> - @retval EFI_SUCCESS The policy is installed.
> - @retval EFI_OUT_OF_RESOURCES Insufficient resources to
> create buffer
> -
> -**/
> -EFI_STATUS
> -EFIAPI
> -InstallTbtPolicy (
> - IN EFI_HANDLE ImageHandle
> - )
> -{
> - EFI_STATUS Status;
> - DXE_TBT_POLICY_PROTOCOL *DxeTbtPolicy;
> -
> - DEBUG ((DEBUG_INFO, "Install DXE TBT Policy\n"));
> -
> - DxeTbtPolicy = NULL;
> - //Alloc memory for DxeTbtPolicy
> - DxeTbtPolicy = (DXE_TBT_POLICY_PROTOCOL *) AllocateZeroPool (sizeof
> (DXE_TBT_POLICY_PROTOCOL));
> - if (DxeTbtPolicy == NULL) {
> - return EFI_OUT_OF_RESOURCES;
> - }
> -
> - Status = gBS->InstallProtocolInterface (
> - &ImageHandle,
> - &gDxeTbtPolicyProtocolGuid,
> - EFI_NATIVE_INTERFACE,
> - DxeTbtPolicy
> - );
> - if (EFI_ERROR (Status)) {
> - DEBUG ((DEBUG_ERROR, "Install Tbt Secure Boot List protocol
> failed\n"));
> - }
> - return Status;
> -}
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTbtC
> ommonLib/TbtCommonLib.c
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTbtC
> ommonLib/TbtCommonLib.c
> deleted file mode 100644
> index 7afdc25f67..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTbtC
> ommonLib/TbtCommonLib.c
> +++ /dev/null
> @@ -1,315 +0,0 @@
> -/** @file
> - Common Thunderbolt functions.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <Library/DebugLib.h>
> -#include <Uefi/UefiBaseType.h>
> -#include <Library/PchPcieRpLib.h>
> -#include <Library/TbtCommonLib.h>
> -#include <Library/PciSegmentLib.h>
> -#include <Library/TimerLib.h>
> -#include <Library/BaseLib.h>
> -#include <Library/GpioLib.h>
> -
> -
> -/**
> - Selects the proper TBT Root port to assign resources
> - based on the user input value
> -
> - @param[in] SetupData Pointer to Setup data
> -
> - @retval TbtSelectorChosen Rootport number.
> -**/
> -VOID
> -GetRootporttoSetResourcesforTbt (
> - IN UINTN RpIndex,
> - OUT UINT8 *RsvdExtraBusNum,
> - OUT UINT16 *RsvdPcieMegaMem,
> - OUT UINT8 *PcieMemAddrRngMax,
> - OUT UINT16 *RsvdPciePMegaMem,
> - OUT UINT8 *PciePMemAddrRngMax,
> - OUT BOOLEAN *SetResourceforTbt
> - )
> -{
> - UINTN TbtRpNumber;
> - TbtRpNumber = (UINTN) PcdGet8 (PcdDTbtPcieRpNumber);
> -
> - if (RpIndex == (TbtRpNumber - 1)) {
> - *RsvdExtraBusNum = PcdGet8 (PcdDTbtPcieExtraBusRsvd);
> - *RsvdPcieMegaMem = PcdGet16 (PcdDTbtPcieMemRsvd);
> - *PcieMemAddrRngMax = PcdGet8 (PcdDTbtPcieMemAddrRngMax);
> - *RsvdPciePMegaMem = PcdGet16 (PcdDTbtPciePMemRsvd);
> - *PciePMemAddrRngMax = PcdGet8
> (PcdDTbtPciePMemAddrRngMax);
> - *SetResourceforTbt = TRUE;
> - }
> - else {
> - *SetResourceforTbt = FALSE;
> - }
> - }
> -
> -/**
> - Internal function to Wait for Tbt2PcieDone Bit.to Set or clear
> - @param[in] CommandOffsetAddress Tbt2Pcie Register Address
> - @param[in] TimeOut Time out with 100 ms
> garnularity
> - @param[in] Tbt2PcieDone Wait condition (wait for Bit
> to Clear/Set)
> - @param[out] *Tbt2PcieValue Function Register value
> -**/
> -BOOLEAN
> -InternalWaitforCommandCompletion(
> - IN UINT64 CommandOffsetAddress,
> - IN UINT32 TimeOut,
> - IN BOOLEAN Tbt2PcieDone,
> - OUT UINT32 *Tbt2PcieValue
> - )
> -{
> - BOOLEAN ReturnFlag;
> - UINT32 Tbt2PcieCheck;
> -
> - ReturnFlag = FALSE;
> - while (TimeOut-- > 0) {
> - *Tbt2PcieValue = PciSegmentRead32 (CommandOffsetAddress);
> -
> - if (0xFFFFFFFF == *Tbt2PcieValue ) {
> - //
> - // Device is not here return now
> - //
> - ReturnFlag = FALSE;
> - break;
> - }
> -
> - if(Tbt2PcieDone) {
> - Tbt2PcieCheck = *Tbt2PcieValue & TBT2PCIE_DON_R;
> - } else {
> - Tbt2PcieCheck = !(*Tbt2PcieValue & TBT2PCIE_DON_R);
> - }
> -
> - if (Tbt2PcieCheck) {
> - ReturnFlag = TRUE;
> - break;
> - }
> -
> - MicroSecondDelay(TBT_MAIL_BOX_DELAY);
> - }
> - return ReturnFlag;
> -}
> -/**
> - Get Security Level.
> - @param[in] Bus Bus number Host Router (DTBT)
> - @param[in] Device Device number for Host Router (DTBT)
> - @param[in] Function Function number for Host Router (DTBT)
> - @param[in] Command Command for Host Router (DTBT)
> - @param[in] Timeout Time out with 100 ms garnularity
> -**/
> -UINT8
> -GetSecLevel (
> - IN UINT8 Bus,
> - IN UINT8 Device,
> - IN UINT8 Function,
> - IN UINT8 Command,
> - IN UINT32 Timeout
> - )
> -{
> - UINT64 Pcie2Tbt;
> - UINT64 Tbt2Pcie;
> - UINT32 RegisterValue;
> - UINT8 ReturnFlag;
> -
> - ReturnFlag = 0xFF;
> -
> - DEBUG ((DEBUG_INFO, "GetSecLevel() \n"));
> -
> - GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie)
> - GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt)
> -
> - PciSegmentWrite32 (Pcie2Tbt, Command | PCIE2TBT_VLD_B);
> -
> - if(InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, TRUE,
> &RegisterValue)) {
> - ReturnFlag = (UINT8) (0xFF & (RegisterValue >> 8));
> - }
> -
> - PciSegmentWrite32 (Pcie2Tbt, 0);
> -
> - InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, FALSE,
> &RegisterValue);
> - DEBUG ((DEBUG_INFO, "Security Level configured to %x \n", ReturnFlag));
> -
> - return ReturnFlag;
> -}
> -
> -/**
> - Set Security Level.
> - @param[in] Data Security State
> - @param[in] Bus Bus number for Host Router (DTBT)
> - @param[in] Device Device number for Host Router (DTBT)
> - @param[in] Function Function number for Host Router (DTBT)
> - @param[in] Command Command for Host Router (DTBT)
> - @param[in] Timeout Time out with 100 ms garnularity
> -**/
> -BOOLEAN
> -SetSecLevel (
> - IN UINT8 Data,
> - IN UINT8 Bus,
> - IN UINT8 Device,
> - IN UINT8 Function,
> - IN UINT8 Command,
> - IN UINT32 Timeout
> - )
> -{
> - UINT64 Pcie2Tbt;
> - UINT64 Tbt2Pcie;
> - UINT32 RegisterValue;
> - BOOLEAN ReturnFlag;
> -
> - ReturnFlag = FALSE;
> -
> - DEBUG ((DEBUG_INFO, "SetSecLevel() \n"));
> -
> - GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie)
> - GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt)
> -
> - PciSegmentWrite32 (Pcie2Tbt, (Data << 8) | Command | PCIE2TBT_VLD_B);
> -
> - ReturnFlag = InternalWaitforCommandCompletion(Tbt2Pcie, Timeout,
> TRUE, &RegisterValue);
> - DEBUG ((DEBUG_INFO, "RegisterValue %x \n", RegisterValue));
> - PciSegmentWrite32 (Pcie2Tbt, 0);
> -
> - InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, FALSE,
> &RegisterValue);
> - DEBUG ((DEBUG_INFO, "Return value %x \n", ReturnFlag));
> - return ReturnFlag;
> -}
> -
> -/**
> -Based on the Security Mode Selection, BIOS drives FORCE_PWR.
> -
> - at param[in] GpioNumber
> - at param[in] Value
> -**/
> -VOID
> -ForceDtbtPower(
> - IN UINT8 GpioAccessType,
> - IN UINT8 Expander,
> - IN UINT32 GpioNumber,
> - IN BOOLEAN Value
> -)
> -{
> - if (GpioAccessType == 0x01) {
> - // PCH
> - GpioSetOutputValue (GpioNumber, (UINT32)Value);
> - } else if (GpioAccessType == 0x02) {
> - // IoExpander {TCA6424A}
> - GpioExpSetOutput (Expander, (UINT8)GpioNumber, (UINT8)Value);
> - }
> -}
> -
> -/**
> -Execute TBT Mail Box Command
> -
> - at param[in] Command TBT Command
> - at param[in] Bus Bus number for Host Router (DTBT)
> - at param[in] Device Device number for Host Router (DTBT)
> - at param[in] Function Function number for Host Router (DTBT)
> - at param[in] Timeout Time out with 100 ms garnularity
> - at Retval true if command executes succesfully
> -**/
> -BOOLEAN
> -TbtSetPcie2TbtCommand(
> - IN UINT8 Command,
> - IN UINT8 Bus,
> - IN UINT8 Device,
> - IN UINT8 Function,
> - IN UINT32 Timeout
> -)
> -{
> - UINT64 Pcie2Tbt;
> - UINT64 Tbt2Pcie;
> - UINT32 RegisterValue;
> - BOOLEAN ReturnFlag;
> -
> - GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie)
> - GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt)
> -
> - PciSegmentWrite32 (Pcie2Tbt, Command | PCIE2TBT_VLD_B);
> -
> - ReturnFlag = InternalWaitforCommandCompletion(Tbt2Pcie, Timeout,
> TRUE, &RegisterValue);
> -
> - PciSegmentWrite32(Pcie2Tbt, 0);
> -
> - return ReturnFlag;
> -}
> -/**
> - Get Pch/Peg Pcie Root Port Device and Function Number for TBT by Root
> Port physical Number
> -
> - @param[in] RpNumber Root port physical number.
> (0-based)
> - @param[out] RpDev Return corresponding root port
> device number.
> - @param[out] RpFun Return corresponding root port
> function number.
> -
> - @retval EFI_SUCCESS Root port device and function is
> retrieved
> - @retval EFI_INVALID_PARAMETER If Invalid Root Port Number or
> TYPE is Passed
> -**/
> -EFI_STATUS
> -EFIAPI
> -GetDTbtRpDevFun (
> - IN BOOLEAN Type,
> - IN UINTN RpNumber,
> - OUT UINTN *RpDev,
> - OUT UINTN *RpFunc
> - )
> -{
> - EFI_STATUS Status;
> - UINTN TbtRpDev;
> - UINTN TbtRpFunc;
> -
> - Status = EFI_INVALID_PARAMETER; // Update the Status to EFI_SUCCESS if
> valid input found.
> - //
> - // CNL PCH-H can support up to 24 root ports. PEG0,PEG1 and PEG2 will
> be
> - // with device number 0x1 and Function number 0,1 and 2 respectively.
> - //
> - if (Type == DTBT_TYPE_PEG)
> - {
> - //
> - // PEG Rootport
> - //
> - if (RpNumber <= 2) {
> - *RpDev = 0x01;
> - *RpFunc = RpNumber;
> - Status = EFI_SUCCESS;
> - }
> - }
> - if (Type == DTBT_TYPE_PCH)
> - {
> - //
> - // PCH Rootport
> - //
> - if (RpNumber <= 23) {
> - Status = GetPchPcieRpDevFun (RpNumber, &TbtRpDev,
> &TbtRpFunc);
> - *RpDev = TbtRpDev;
> - *RpFunc = TbtRpFunc;
> - }
> - }
> -
> - ASSERT_EFI_ERROR (Status);
> - return Status;
> -}
> -
> -BOOLEAN
> -IsTbtHostRouter (
> - IN UINT16 DeviceID
> - )
> -{
> - switch (DeviceID) {
> - case AR_HR_2C:
> - case AR_HR_4C:
> - case AR_HR_LP:
> - case AR_HR_C0_2C:
> - case AR_HR_C0_4C:
> - case TR_HR_2C:
> - case TR_HR_4C:
> - return TRUE;
> - }
> -
> - return FALSE;
> -} // IsTbtHostRouter
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/P
> eiTbtPolicyLib.c
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/P
> eiTbtPolicyLib.c
> deleted file mode 100644
> index d6105a0c67..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/P
> eiTbtPolicyLib.c
> +++ /dev/null
> @@ -1,204 +0,0 @@
> -/** @file
> - This file is PeiTbtPolicyLib library.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -#include <Library/PeiServicesLib.h>
> -#include <Library/GpioLib.h>
> -#include <PiPei.h>
> -#include <PeiTbtPolicyLibrary.h>
> -#include <Ppi/ReadOnlyVariable2.h>
> -#include <Ppi/PeiTbtPolicy.h>
> -#include <Base.h>
> -#include <GpioConfig.h>
> -
> -/**
> - Update PEI TBT Policy Callback
> -**/
> -VOID
> -EFIAPI
> -UpdatePeiTbtPolicy (
> - VOID
> - )
> -{
> - EFI_STATUS Status;
> - EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
> - PEI_TBT_POLICY *PeiTbtConfig;
> -
> - PeiTbtConfig = NULL;
> - Status = EFI_NOT_FOUND;
> -
> - DEBUG ((DEBUG_INFO, "UpdatePeiTbtPolicy \n"));
> -
> - Status = PeiServicesLocatePpi (
> - &gEfiPeiReadOnlyVariable2PpiGuid,
> - 0,
> - NULL,
> - (VOID **) &VariableServices
> - );
> - ASSERT_EFI_ERROR (Status);
> -
> - Status = PeiServicesLocatePpi (
> - &gPeiTbtPolicyPpiGuid,
> - 0,
> - NULL,
> - (VOID **) &PeiTbtConfig
> - );
> - if (EFI_ERROR(Status)) {
> - DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n"));
> - }
> - ASSERT_EFI_ERROR (Status);
> -
> - //
> - // Update DTBT Policy
> - //
> - PeiTbtConfig-> DTbtControllerConfig.DTbtControllerEn = PcdGet8
> (PcdDTbtControllerEn);
> - if (PcdGet8 (PcdDTbtControllerType) == TYPE_PEG)
> - {
> - PeiTbtConfig-> DTbtControllerConfig.Type = (UINT8) TYPE_PEG;
> - PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber = 1; // PEG RP 1
> (Function no. 0)
> - }
> - else {
> - PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber = PcdGet8
> (PcdDTbtPcieRpNumber);
> - PeiTbtConfig-> DTbtControllerConfig.Type = PcdGet8
> (PcdDTbtControllerType);
> - }
> - PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.GpioPad =
> (GPIO_PAD) PcdGet32 (PcdDTbtCioPlugEventGpioPad);
> - if
> (GpioCheckFor2Tier(PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.G
> pioPad)) {
> -
> PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignaturePorti
> ng = 0;
> -
> PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature =
> SIGNATURE_32('X', 'T', 'B', 'T');
> - }
> - else {
> -
> PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignaturePorti
> ng = 1;
> - //
> - // Update Signature based on platform GPIO.
> - //
> -
> PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature =
> SIGNATURE_32('X', 'T', 'B', 'T');
> - }
> - PeiTbtConfig->DTbtCommonConfig.TbtBootOn = PcdGet8
> (PcdDTbtBootOn);
> - PeiTbtConfig->DTbtCommonConfig.TbtUsbOn = PcdGet8 (PcdDTbtUsbOn);
> - PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr = PcdGet8
> (PcdDTbtGpio3ForcePwr);
> - PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly = PcdGet16
> (PcdDTbtGpio3ForcePwrDly);
> -
> - return;
> -}
> -
> -/**
> - Print PEI TBT Policy
> -**/
> -VOID
> -EFIAPI
> -TbtPrintPeiPolicyConfig (
> - VOID
> - )
> -{
> - DEBUG_CODE_BEGIN ();
> - EFI_STATUS Status;
> - PEI_TBT_POLICY *PeiTbtConfig;
> -
> - PeiTbtConfig = NULL;
> - Status = EFI_NOT_FOUND;
> - DEBUG ((DEBUG_INFO, "TbtPrintPolicyConfig Start\n"));
> -
> - Status = PeiServicesLocatePpi (
> - &gPeiTbtPolicyPpiGuid,
> - 0,
> - NULL,
> - (VOID **) &PeiTbtConfig
> - );
> - if (EFI_ERROR(Status)) {
> - DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n"));
> - }
> - ASSERT_EFI_ERROR (Status);
> -
> - //
> - // Print DTBT Policy
> - //
> - DEBUG ((DEBUG_INFO, "\n------------------------ TBT Policy (PEI) Print BEGIN
> -----------------\n"));
> - DEBUG ((DEBUG_INFO, "Revision : 0x%x\n", PEI_TBT_POLICY_REVISION));
> - DEBUG ((DEBUG_INFO, "------------------------ PEI_TBT_CONFIG
> -----------------\n"));
> - DEBUG ((DEBUG_INFO, " Revision : %d\n", PEI_TBT_POLICY_REVISION));
> -
> - DEBUG ((DEBUG_INFO,
> "PeiTbtConfig->DTbtControllerConfig.DTbtControllerEn = %x\n",
> PeiTbtConfig-> DTbtControllerConfig.DTbtControllerEn));
> - DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.Type = %x\n",
> PeiTbtConfig-> DTbtControllerConfig.Type));
> - DEBUG ((DEBUG_INFO,
> "PeiTbtConfig->DTbtControllerConfig.PcieRpNumber = %x\n", PeiTbtConfig->
> DTbtControllerConfig.PcieRpNumber));
> - DEBUG ((DEBUG_INFO,
> "PeiTbtConfig->DTbtControllerConfig.ForcePwrGpio.GpioPad = %x\n",
> PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioPad));
> - DEBUG ((DEBUG_INFO,
> "PeiTbtConfig->DTbtControllerConfig.ForcePwrGpio.GpioLevel = %x\n",
> PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioLevel));
> - DEBUG ((DEBUG_INFO,
> "PeiTbtConfig->DTbtControllerConfig.PcieRstGpio.GpioPad = %x\n",
> PeiTbtConfig-> DTbtControllerConfig.PcieRstGpio.GpioPad));
> - DEBUG ((DEBUG_INFO,
> "PeiTbtConfig->DTbtControllerConfig.PcieRstGpio.GpioLevel = %x\n",
> PeiTbtConfig-> DTbtControllerConfig.PcieRstGpio.GpioLevel));
> - DEBUG ((DEBUG_INFO,
> "PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.GpioPad = %x\n",
> PeiTbtConfig-> DTbtControllerConfig.CioPlugEventGpio.GpioPad));
> - DEBUG ((DEBUG_INFO,
> "PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature =
> %x\n", PeiTbtConfig->
> DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature));
> - DEBUG ((DEBUG_INFO,
> "PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignaturePor
> ting = %x\n", PeiTbtConfig->
> DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignaturePorting));
> -
> -
> - //
> - // Print DTBT Common Policy
> - //
> - DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.TbtBootOn =
> %x\n", PeiTbtConfig->DTbtCommonConfig.TbtBootOn));
> - DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.TbtUsbOn =
> %x\n", PeiTbtConfig->DTbtCommonConfig.TbtUsbOn));
> - DEBUG ((DEBUG_INFO,
> "PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr = %x\n",
> PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr));
> - DEBUG ((DEBUG_INFO,
> "PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly = %x\n",
> PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly));
> - DEBUG ((DEBUG_INFO,
> "PeiTbtConfig->DTbtCommonConfig.DTbtSharedGpioConfiguration = %x\n",
> PeiTbtConfig->DTbtCommonConfig.DTbtSharedGpioConfiguration));
> - DEBUG ((DEBUG_INFO,
> "PeiTbtConfig->DTbtCommonConfig.PcieRstSupport = %x\n",
> PeiTbtConfig->DTbtCommonConfig.PcieRstSupport));
> -
> - DEBUG ((DEBUG_INFO, "\n------------------------ TBT Policy (PEI) Print END
> -----------------\n"));
> - DEBUG_CODE_END ();
> -
> - return;
> -}
> -
> -/**
> - Install Tbt Policy
> -
> - @retval EFI_SUCCESS The policy is installed.
> - @retval EFI_OUT_OF_RESOURCES Insufficient resources to
> create buffer
> -
> -**/
> -EFI_STATUS
> -EFIAPI
> -InstallPeiTbtPolicy (
> - VOID
> - )
> -{
> - EFI_STATUS Status;
> - EFI_PEI_PPI_DESCRIPTOR *PeiTbtPolicyPpiDesc;
> - PEI_TBT_POLICY *PeiTbtConfig;
> -
> - DEBUG ((DEBUG_INFO, "Install PEI TBT Policy\n"));
> -
> - PeiTbtConfig = NULL;
> -
> - //
> - // Allocate memory for PeiTbtPolicyPpiDesc
> - //
> - PeiTbtPolicyPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool
> (sizeof (EFI_PEI_PPI_DESCRIPTOR));
> - ASSERT (PeiTbtPolicyPpiDesc != NULL);
> - if (PeiTbtPolicyPpiDesc == NULL) {
> - return EFI_OUT_OF_RESOURCES;
> - }
> -
> - //
> - // Allocate memory and initialize all default to zero for PeiTbtPolicy
> - //
> - PeiTbtConfig = (PEI_TBT_POLICY *) AllocateZeroPool (sizeof
> (PEI_TBT_POLICY));
> - ASSERT (PeiTbtConfig != NULL);
> - if (PeiTbtConfig == NULL) {
> - return EFI_OUT_OF_RESOURCES;
> - }
> -
> - //
> - // Initialize PPI
> - //
> - PeiTbtPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
> - PeiTbtPolicyPpiDesc->Guid = &gPeiTbtPolicyPpiGuid;
> - PeiTbtPolicyPpiDesc->Ppi = PeiTbtConfig;
> -
> - Status = PeiServicesInstallPpi (PeiTbtPolicyPpiDesc);
> - ASSERT_EFI_ERROR (Status);
> - if (EFI_ERROR (Status)) {
> - DEBUG ((DEBUG_ERROR, "Install PEI TBT Policy failed\n"));
> - }
> - return Status;
> -}
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/Private/PeiDTbtI
> nitLib/PeiDTbtInitLib.c
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/Private/PeiDTbtI
> nitLib/PeiDTbtInitLib.c
> deleted file mode 100644
> index 9c4bddfc2d..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/Private/PeiDTbtI
> nitLib/PeiDTbtInitLib.c
> +++ /dev/null
> @@ -1,566 +0,0 @@
> -/**@file
> - Thunderbolt(TM) Pei Library
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -#include <Library/PeiServicesLib.h>
> -#include <Library/MemoryAllocationLib.h>
> -#include <Library/BaseMemoryLib.h>
> -#include <Library/DebugLib.h>
> -#include <Library/GpioLib.h>
> -#include <GpioPinsSklLp.h>
> -#include <GpioPinsSklH.h>
> -#include <Library/TimerLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/MmPciLib.h>
> -#include <Library/HobLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/GpioExpanderLib.h>
> -#include <Ppi/ReadOnlyVariable2.h>
> -
> -#include <Base.h>
> -#include <Library/TbtCommonLib.h>
> -#include <TbtBoardInfo.h>
> -#include <IndustryStandard/Pci22.h>
> -#include <Library/PchCycleDecodingLib.h>
> -#include <Ppi/PeiTbtPolicy.h>
> -#include <Library/PciSegmentLib.h>
> -#include <Library/PeiTbtPolicyLib.h>
> -#include <Library/PchPmcLib.h>
> -#include <Private/Library/PeiDTbtInitLib.h>
> -
> -/**
> -Is host router (For dTBT) or End Point (For iTBT) present before sleep
> -
> - at param[in] ControllerType - DTBT_CONTROLLER or ITBT_CONTROLLER
> - at param[in] Controller - Controller begin offset of CMOS
> -
> - at Retval TRUE There is a TBT HostRouter presented before sleep
> - at Retval FALSE There is no TBT HostRouter presented before
> sleep
> -
> -BOOLEAN
> -IsHostRouterPresentBeforeSleep(
> -IN UINT8 ControllerType,
> -IN UINT8 Controller
> -)
> -{
> - UINT8 SavedState;
> -
> - SavedState = (UINT8)GetTbtHostRouterStatus();
> - if (ControllerType == DTBT_CONTROLLER){
> - return ((SavedState & (DTBT_SAVE_STATE_OFFSET << Controller)) ==
> (DTBT_SAVE_STATE_OFFSET << Controller));
> - } else {
> - if (ControllerType == ITBT_CONTROLLER) {
> - return ((SavedState & (ITBT_SAVE_STATE_OFFSET << Controller)) ==
> (ITBT_SAVE_STATE_OFFSET << Controller));
> - }
> - }
> - return 0;
> -}
> -**/
> -
> -/**
> -Execute TBT PCIE2TBT_SX_EXIT_TBT_CONNECTED Mail Box Command for S4
> mode with PreBootAclEnable
> -
> - at param[in] Bus Bus number for Host Router (DTBT)
> - at param[in] Device Device number for Host Router (DTBT)
> - at param[in] Function Function number for Host Router (DTBT)
> - at param[in] Timeout Time out with 100 ms garnularity
> - at Retval true if command executes succesfully
> -**/
> -BOOLEAN
> -TbtSetPcie2TbtSxExitCommandWithPreBootAclEnable(
> - IN UINT8 Bus,
> - IN UINT8 Device,
> - IN UINT8 Function,
> - IN UINT32 Timeout
> -)
> -{
> - UINT64 Pcie2Tbt;
> - UINT64 Tbt2Pcie;
> - UINT32 RegisterValue;
> - BOOLEAN ReturnFlag;
> - UINT32 Command;
> -
> - GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie)
> - GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt)
> -
> -// If PreBootAcl is Enable, we need to enable DATA bit while sending SX EXIT
> MAIL BOX Command
> - Command = (1 << 8) | PCIE2TBT_SX_EXIT_TBT_CONNECTED;
> - PciSegmentWrite32 (Pcie2Tbt, Command | PCIE2TBT_VLD_B);
> -
> - ReturnFlag = InternalWaitforCommandCompletion(Tbt2Pcie, Timeout,
> TRUE, &RegisterValue);
> -
> - PciSegmentWrite32(Pcie2Tbt, 0);
> -
> - return ReturnFlag;
> -}
> -
> -/**
> -Set the Sleep Mode if the HR is up.
> - at param[in] Bus Bus number for Host Router (DTBT)
> - at param[in] Device Device number for Host Router (DTBT)
> - at param[in] Function Function number for Host Router (DTBT)
> -**/
> -VOID
> -TbtSetSxMode(
> -IN UINT8 Bus,
> -IN UINT8 Device,
> -IN UINT8 Function,
> -IN UINT8 TbtBootOn
> -)
> -{
> - UINT64 TbtUsDevId;
> - UINT64 Tbt2Pcie;
> - UINT32 RegVal;
> - UINT32 MaxLoopCount;
> - UINTN Delay;
> - UINT8 RetCode;
> - EFI_BOOT_MODE BootMode;
> - EFI_STATUS Status;
> -
> - TbtUsDevId = PCI_SEGMENT_LIB_ADDRESS(0, Bus, Device, Function, 0);
> - GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie)
> -
> - MaxLoopCount = TBT_5S_TIMEOUT; // Wait 5 sec
> - Delay = 100 * 1000;
> - RetCode = 0x62;
> -
> - Status = PeiServicesGetBootMode(&BootMode);
> - ASSERT_EFI_ERROR(Status);
> -
> - if ((BootMode == BOOT_ON_S4_RESUME) && (TbtBootOn == 2)) {
> - MaxLoopCount = TBT_3S_TIMEOUT;
> - if (!TbtSetPcie2TbtSxExitCommandWithPreBootAclEnable(Bus, Device,
> Function, MaxLoopCount)) {
> - //
> - // Nothing to wait, HR is not responsive
> - //
> - return;
> - }
> - }
> - else {
> - if (!TbtSetPcie2TbtCommand(PCIE2TBT_SX_EXIT_TBT_CONNECTED, Bus,
> Device, Function, MaxLoopCount)) {
> - //
> - // Nothing to wait, HR is not responsive
> - //
> - return;
> - }
> - }
> -
> - DEBUG((DEBUG_INFO, "Wait for Dev ID != 0xFF\n"));
> -
> - while (MaxLoopCount-- > 0) {
> - //
> - // Check what HR still here
> - //
> - RegVal = PciSegmentRead32(Tbt2Pcie);
> - if (0xFFFFFFFF == RegVal) {
> - RetCode = 0x6F;
> - break;
> - }
> - //
> - // Check completion of TBT link
> - //
> - RegVal = PciSegmentRead32(TbtUsDevId);
> - if (0xFFFFFFFF != RegVal) {
> - RetCode = 0x61;
> - break;
> - }
> -
> - MicroSecondDelay(Delay);
> - }
> -
> - DEBUG((DEBUG_INFO, "Return code = 0x%x\n", RetCode));
> -}
> -/**
> - set tPCH25 Timing to 10 ms for DTBT.
> -
> - @param[in] PEI_TBT_POLICY PeiTbtConfig
> -
> - @retval EFI_SUCCESS The function completes successfully
> - @retval EFI_UNSUPPORTED dTBT is not supported.
> -**/
> -EFI_STATUS
> -EFIAPI
> -DTbtSetTPch25Timing (
> - IN PEI_TBT_POLICY *PeiTbtConfig
> -)
> -{
> - DEBUG ((DEBUG_INFO, "DTbtSetTPch25Timing call Inside\n"));
> - UINT32 PchPwrmBase;
> -
> - //
> - //During boot, reboot and wake tPCH25 Timing should be set to 10 ms
> - //
> - PchPwrmBaseGet (&PchPwrmBase);
> - MmioOr32 (
> - (UINTN) (PchPwrmBase + R_PCH_PWRM_CFG),
> - (BIT0 | BIT1)
> - );
> -
> - DEBUG((DEBUG_INFO, "DTbtSetTPch25Timing call Return\n"));
> - return EFI_SUCCESS;
> -}
> -
> -/**
> - Do ForcePower for DTBT Controller
> -
> - @param[in] PEI_TBT_POLICY PeiTbtConfig
> -
> - @retval EFI_SUCCESS The function completes successfully
> - @retval EFI_UNSUPPORTED dTBT is not supported.
> -**/
> -EFI_STATUS
> -EFIAPI
> -DTbtForcePower (
> - IN PEI_TBT_POLICY *PeiTbtConfig
> -)
> -{
> -
> - DEBUG ((DEBUG_INFO, "DTbtForcePower call Inside\n"));
> -
> - if (PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr) {
> - DEBUG((DEBUG_INFO, "ForcePwrGpio.GpioPad = %x \n",
> PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioPad));
> - ForceDtbtPower(PeiTbtConfig->
> DTbtControllerConfig.ForcePwrGpio.GpioAccessType,PeiTbtConfig->
> DTbtControllerConfig.ForcePwrGpio.Expander, PeiTbtConfig->
> DTbtControllerConfig.ForcePwrGpio.GpioPad, PeiTbtConfig->
> DTbtControllerConfig.ForcePwrGpio.GpioLevel);
> - DEBUG((DEBUG_INFO, "ForceDtbtPower asserted \n"));
> -
> MicroSecondDelay(PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly *
> 1000);
> - DEBUG((DEBUG_INFO, "Delay after ForceDtbtPower = 0x%x ms \n",
> PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly));
> - }
> -
> - DEBUG ((DEBUG_INFO, "DTbtForcePower call Return\n"));
> - return EFI_SUCCESS;
> -}
> -
> -/**
> - Clear VGA Registers for DTBT.
> -
> - @param[in] PEI_TBT_POLICY PeiTbtConfig
> -
> - @retval EFI_SUCCESS The function completes successfully
> - @retval EFI_UNSUPPORTED dTBT is not supported.
> -**/
> -EFI_STATUS
> -EFIAPI
> -DTbtClearVgaRegisters (
> - IN PEI_TBT_POLICY *PeiTbtConfig
> -)
> -{
> - UINTN RpDev;
> - UINTN RpFunc;
> - EFI_STATUS Status;
> - UINT64 BridngeBaseAddress;
> - UINT16 Data16;
> -
> - DEBUG ((DEBUG_INFO, "DTbtClearVgaRegisters call Inside\n"));
> -
> - Status = EFI_SUCCESS;
> -
> - Status = GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type,
> PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc);
> - ASSERT_EFI_ERROR(Status);
> - //
> - // VGA Enable and VGA 16-bit decode registers of Bridge control register
> of Root port where
> - // Host router resides should be cleaned
> - //
> -
> - BridngeBaseAddress = PCI_SEGMENT_LIB_ADDRESS(0, 0, (UINT32)RpDev,
> (UINT32)RpFunc, 0);
> - Data16 = PciSegmentRead16(BridngeBaseAddress +
> PCI_BRIDGE_CONTROL_REGISTER_OFFSET);
> - Data16 &= (~(EFI_PCI_BRIDGE_CONTROL_VGA |
> EFI_PCI_BRIDGE_CONTROL_VGA_16));
> - PciSegmentWrite16(BridngeBaseAddress +
> PCI_BRIDGE_CONTROL_REGISTER_OFFSET, Data16);
> -
> - DEBUG ((DEBUG_INFO, "DTbtClearVgaRegisters call Return\n"));
> - return Status;
> -}
> -
> -/**
> - Exectue Mail box command "Boot On".
> -
> - @param[in] PEI_TBT_POLICY PeiTbtConfig
> -
> - @retval EFI_SUCCESS The function completes successfully
> - @retval EFI_UNSUPPORTED dTBT is not supported.
> -**/
> -EFI_STATUS
> -EFIAPI
> -DTbtBootOn(
> - IN PEI_TBT_POLICY *PeiTbtConfig
> -)
> -{
> - EFI_STATUS Status;
> - UINT32 OrgBusNumberConfiguration;
> - UINTN RpDev;
> - UINTN RpFunc;
> -
> - DEBUG((DEBUG_INFO, "DTbtBootOn call Inside\n"));
> -
> - Status = EFI_SUCCESS;
> -
> - Status = GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type,
> PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc);
> - ASSERT_EFI_ERROR(Status);
> - OrgBusNumberConfiguration = PciSegmentRead32
> (PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc,
> PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET));
> - //
> - // Set Sec/Sub buses to 0xF0
> - //
> - PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc,
> PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), 0x00F0F000);
> - //
> - //When Thunderbolt(TM) boot [TbtBootOn] is enabled in bios setup
> we need to do the below:
> - //Bios should send "Boot On" message through PCIE2TBT register
> - //The Boot On command as described above would include the
> command and acknowledge from FW (with the default timeout in BIOS),
> - //once the Boot On command is completed it is guaranteed that the
> AlpineRidge(AR) device is there and the PCI tunneling was done by FW,
> - //next step from BIOS is enumeration using SMI
> - //
> -
> - if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn > 0) {
> - //
> - // Exectue Mail box command "Boot On / Pre-Boot ACL"
> - //
> - //Command may be executed only during boot/reboot and not
> during Sx exit flow
> - if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn == 1) {
> - if (!TbtSetPcie2TbtCommand(PCIE2TBT_BOOT_ON, 0xF0, 0, 0,
> TBT_5S_TIMEOUT)) {
> - //
> - // Nothing to wait, HR is not responsive
> - //
> - DEBUG((DEBUG_INFO, "<TbtPei> DTbtBootOn - Boot On
> message sent failed \n"));
> - }
> - }
> - if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn == 2) {
> - if (!TbtSetPcie2TbtCommand(PCIE2TBT_PREBOOTACL, 0xF0, 0, 0,
> TBT_3S_TIMEOUT)) {
> - //
> - // Nothing to wait, HR is not responsive
> - //
> - DEBUG((DEBUG_INFO, "<TbtPei> DTbtBootOn - Pre-Boot ACL
> message sent failed \n"));
> - }
> - }
> - }
> - //
> - // Reset Sec/Sub buses to original value
> - //
> - PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc,
> PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET),
> OrgBusNumberConfiguration);
> -
> - DEBUG((DEBUG_INFO, "DTbtBootOn call Return\n"));
> - return Status;
> -}
> -
> -/**
> - Exectue Mail box command "USB On".
> -
> - @param[in] PEI_TBT_POLICY PeiTbtConfig
> -
> - @retval EFI_SUCCESS The function completes successfully
> - @retval EFI_UNSUPPORTED dTBT is not supported.
> -**/
> -EFI_STATUS
> -EFIAPI
> -DTbtUsbOn(
> - IN PEI_TBT_POLICY *PeiTbtConfig
> -)
> -{
> - EFI_STATUS Status;
> - UINTN RpDev;
> - UINTN RpFunc;
> - UINT32 OrgBusNumberConfiguration;
> - UINT64 TbtBaseAddress;
> - UINT32 MaxWaitIter;
> - UINT32 RegVal;
> - EFI_BOOT_MODE BootMode;
> -
> - DEBUG((DEBUG_INFO, "DTbtUsbOn call Inside\n"));
> -
> - Status = EFI_SUCCESS;
> -
> - Status = GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type,
> PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc);
> - ASSERT_EFI_ERROR(Status);
> - OrgBusNumberConfiguration =
> PciSegmentRead32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc,
> PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET));
> - //
> - // Set Sec/Sub buses to 0xF0
> - //
> - PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc,
> PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), 0x00F0F000);
> -
> - //
> - //When Thunderbolt(TM) Usb boot [TbtUsbOn] is enabled in bios
> setup we need to do the below:
> - //Bios should send "Usb On" message through PCIE2TBT register
> - //The Usb On command as described above would include the
> command and acknowledge from FW (with the default timeout in BIOS),
> - //once the Usb On command is completed it is guaranteed that the
> AlpineRidge(AR) device is there and the PCI tunneling was done by FW,
> - //next step from BIOS is enumeration using SMI
> - //
> - if (PeiTbtConfig->DTbtCommonConfig.TbtUsbOn) {
> - if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn > 0) {
> - MaxWaitIter = 50; // Wait 5 sec
> - TbtBaseAddress = PCI_SEGMENT_LIB_ADDRESS(0, 0xF0, 0, 0, 0);
> - //
> - // Driver clears the PCIe2TBT Valid bit to support two
> consicutive mailbox commands
> - //
> - PciSegmentWrite32(TbtBaseAddress + PCIE2TBT_DTBT_R, 0);
> - DEBUG((DEBUG_INFO, "TbtBaseAddress + PCIE2TBT_DTBT_R =
> 0x%lx \n", TbtBaseAddress + PCIE2TBT_DTBT_R));
> - while (MaxWaitIter-- > 0) {
> - RegVal = PciSegmentRead32(TbtBaseAddress +
> TBT2PCIE_DTBT_R);
> - if (0xFFFFFFFF == RegVal) {
> - //
> - // Device is not here return now
> - //
> - DEBUG((DEBUG_INFO, "TBT device is not present \n"));
> - break;
> - }
> -
> - if (!(RegVal & TBT2PCIE_DON_R)) {
> - break;
> - }
> - MicroSecondDelay(100 * 1000);
> - }
> - }
> -
> - Status = PeiServicesGetBootMode(&BootMode);
> - ASSERT_EFI_ERROR(Status);
> -
> - //
> - // Exectue Mail box command "Usb On"
> - //
> - //Command may be executed only during boot/reboot and not
> during S3 exit flow
> - //In case of S4 Exit send USB ON cmd only if Host Router was
> inactive/not present during S4 entry
> - if ((BootMode == BOOT_ON_S4_RESUME) ) {
> - // USB_ON cmd not required
> - } else {
> - if (!TbtSetPcie2TbtCommand(PCIE2TBT_USB_ON, 0xF0, 0, 0,
> TBT_5S_TIMEOUT)) {
> - //
> - // Nothing to wait, HR is not responsive
> - //
> - DEBUG((DEBUG_INFO, "<TbtPei> TbtBootSupport - Usb On
> message sent failed \n"));
> - }
> - }
> - }
> - //
> - // Reset Sec/Sub buses to original value
> - //
> - PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc,
> PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET),
> OrgBusNumberConfiguration);
> -
> - DEBUG((DEBUG_INFO, "DTbtUsbOn call return\n"));
> - return Status;
> -}
> -
> -/**
> - Exectue Mail box command "Sx Exit".
> -
> - @param[in] PEI_TBT_POLICY PeiTbtConfig
> -
> - @retval EFI_SUCCESS The function completes successfully
> - @retval EFI_UNSUPPORTED dTBT is not supported.
> -**/
> -EFI_STATUS
> -EFIAPI
> -DTbtSxExitFlow(
> - IN PEI_TBT_POLICY *PeiTbtConfig
> -)
> -{
> - EFI_STATUS Status;
> - UINT32 OrgBusNumberConfiguration;
> - UINTN RpDev;
> - UINTN RpFunc;
> - UINT32 Count;
> -
> - DEBUG((DEBUG_INFO, "DTbtSxExitFlow call Inside\n"));
> -
> - Status = EFI_SUCCESS;
> - Count = 0;
> -
> - Status = GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type,
> PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc);
> - ASSERT_EFI_ERROR(Status);
> - OrgBusNumberConfiguration =
> PciSegmentRead32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc,
> PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET));
> - //
> - // Set Sec/Sub buses to 0xF0
> - //
> - PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc,
> PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), 0x00F0F000);
> -
> - if ( (PeiTbtConfig->DTbtCommonConfig.TbtBootOn == 2)) {
> - //
> - // WA: When system with TBT 3.1 device, resume SX system need
> to wait device ready. In document that maximum time out should be 500ms.
> - //
> - while (PciSegmentRead32(PCI_SEGMENT_LIB_ADDRESS(0, 0xf0, 0x0,
> 0x0, 0x08)) == 0xffffffff) { //End Device will be with Device Number 0x0,
> Function Number 0x0.
> - MicroSecondDelay(STALL_ONE_MICRO_SECOND * 1000); //
> 1000usec
> - Count++;
> - if (Count > 10000) { //Allowing Max Delay of 10 sec for CFL-S
> board.
> - break;
> - }
> - }
> -
> - //
> - // Upon wake, if BIOS saved pre-Sx Host Router state as active
> (system went to sleep with
> - // attached devices), BIOS should:
> - // 1. Execute "Sx_Exit_TBT_Connected" mailbox command.
> - // 2. If procedure above returns true, BIOS should perform "wait
> for fast link bring-up" loop
> - // 3. Continue regular wake flow.
> - //
> - //
> - // Exectue Mail box command and perform "wait for fast link
> bring-up" loop
> - //
> - TbtSetSxMode(0xF0, 0, 0,
> PeiTbtConfig->DTbtCommonConfig.TbtBootOn);
> - }
> - //
> - // Reset Sec/Sub buses to original value
> - //
> - PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc,
> PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET),
> OrgBusNumberConfiguration);
> -
> - DEBUG((DEBUG_INFO, "DTbtSxExitFlow call Return\n"));
> - return Status;
> -}
> -
> -
> -/**
> - Initialize Thunderbolt(TM)
> -
> - @retval EFI_SUCCESS The function completes successfully
> - @retval others
> -**/
> -EFI_STATUS
> -EFIAPI
> -TbtInit (
> - VOID
> - )
> -{
> - EFI_STATUS Status;
> - PEI_TBT_POLICY *PeiTbtConfig;
> -
> - //
> - // Get the TBT Policy
> - //
> - Status = PeiServicesLocatePpi (
> - &gPeiTbtPolicyPpiGuid,
> - 0,
> - NULL,
> - (VOID **) &PeiTbtConfig
> - );
> - if (EFI_ERROR(Status)) {
> - DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n"));
> - }
> - ASSERT_EFI_ERROR (Status);
> - //
> - // Exectue Mail box command "Boot On"
> - //
> - Status = DTbtBootOn (PeiTbtConfig);
> - //
> - // Exectue Mail box command "Usb On"
> - //
> - Status = DTbtUsbOn (PeiTbtConfig);
> - //
> - //During boot, reboot and wake (bits [1:0]) of PCH PM_CFG register
> should be
> - //set to 11b - 10 ms (default value is 0b - 10 us)
> - //
> - Status = DTbtSetTPch25Timing (PeiTbtConfig);
> - //
> - // Configure Tbt Force Power
> - //
> - Status = DTbtForcePower (PeiTbtConfig);
> - //
> - // VGA Enable and VGA 16-bit decode registers of Bridge control register
> of Root port where
> - // Host router resides should be cleaned
> - //
> - Status = DTbtClearVgaRegisters (PeiTbtConfig);
> - //
> - // Upon wake, if BIOS saved pre-Sx Host Router state as active (system
> went to sleep with
> - // attached devices), BIOS should:
> - // 1. Execute "Sx_Exit_TBT_Connected" mailbox command.
> - // 2. If procedure above returns true, BIOS should perform "wait for fast
> link bring-up" loop
> - // 3. Continue regular wake flow.
> - //
> - Status = DTbtSxExitFlow (PeiTbtConfig);
> - return EFI_SUCCESS;
> -}
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtDxe.c
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtDxe.c
> deleted file mode 100644
> index 5e8f80fa59..0000000000
> --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtDxe.c
> +++ /dev/null
> @@ -1,228 +0,0 @@
> -/** @file
> - Thunderbolt initialization in DXE.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -#include <Uefi.h>
> -#include <Library/BaseMemoryLib.h>
> -#include <Library/TbtCommonLib.h>
> -#include <Library/DxeTbtPolicyLib.h>
> -#include <TbtBoardInfo.h>
> -#include <Protocol/DxeTbtPolicy.h>
> -#include <Protocol/TbtNvsArea.h>
> -#include <Library/DebugLib.h>
> -#include <Library/HobLib.h>
> -#include <Library/UefiBootServicesTableLib.h>
> -#include <Library/UefiRuntimeServicesTableLib.h>
> -#include <Library/UefiLib.h>
> -#include <Uefi/UefiSpec.h>
> -#include <Library/PcdLib.h>
> -#include <Library/AslUpdateLib.h>
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED TBT_NVS_AREA_PROTOCOL
> mTbtNvsAreaProtocol;
> -GLOBAL_REMOVE_IF_UNREFERENCED TBT_INFO_HOB
> *gTbtInfoHob = NULL;
> -
> -/**
> - TBT NVS Area Initialize
> -
> -**/
> -
> -VOID
> -TbtNvsAreaInit (
> - IN VOID **mTbtNvsAreaPtr
> - )
> -{
> - UINTN Pages;
> - EFI_PHYSICAL_ADDRESS Address;
> - EFI_STATUS Status;
> - TBT_NVS_AREA_PROTOCOL *TbtNvsAreaProtocol;
> - DXE_TBT_POLICY_PROTOCOL *DxeTbtConfig;
> -
> - DEBUG ((DEBUG_INFO, "TbtNvsAreaInit Start\n"));
> - Status = gBS->LocateProtocol (
> - &gDxeTbtPolicyProtocolGuid,
> - NULL,
> - (VOID **) &DxeTbtConfig
> - );
> - ASSERT_EFI_ERROR (Status);
> -
> - Pages = EFI_SIZE_TO_PAGES (sizeof (TBT_NVS_AREA));
> - Address = 0xffffffff; // allocate address below 4G.
> -
> - Status = gBS->AllocatePages (
> - AllocateMaxAddress,
> - EfiACPIMemoryNVS,
> - Pages,
> - &Address
> - );
> - ASSERT_EFI_ERROR (Status);
> -
> - *mTbtNvsAreaPtr = (VOID *) (UINTN) Address;
> - SetMem (*mTbtNvsAreaPtr, sizeof (TBT_NVS_AREA), 0);
> -
> - //
> - // TBTNvsAreaProtocol default value init here
> - //
> - TbtNvsAreaProtocol = (TBT_NVS_AREA_PROTOCOL *) &Address;
> -
> - //
> - // Initialize default values
> - //
> - TbtNvsAreaProtocol->Area->WAKFinished = 0;
> - TbtNvsAreaProtocol->Area->DiscreteTbtSupport = ((gTbtInfoHob->
> DTbtControllerConfig.DTbtControllerEn == 1 ) ? TRUE : FALSE);
> - TbtNvsAreaProtocol->Area->TbtAcpiRemovalSupport = 0;
> - TbtNvsAreaProtocol->Area->TbtGpioFilter = (UINT8)
> DxeTbtConfig->TbtCommonConfig.Gpio5Filter;
> -// TbtNvsAreaProtocol->Area->TrOsup = (UINT8)
> DxeTbtConfig->TbtCommonConfig.TrA0OsupWa;
> - TbtNvsAreaProtocol->Area->TbtFrcPwrEn =
> gTbtInfoHob->DTbtCommonConfig.Gpio3ForcePwr;
> - TbtNvsAreaProtocol->Area->TbtAspm = (UINT8)
> DxeTbtConfig->TbtCommonConfig.TbtAspm;
> -// TbtNvsAreaProtocol->Area->TbtL1SubStates = (UINT8)
> DxeTbtConfig->TbtCommonConfig.TbtL1SubStates;
> - TbtNvsAreaProtocol->Area->TbtSetClkReq = (UINT8)
> DxeTbtConfig->TbtCommonConfig.TbtSetClkReq;
> - TbtNvsAreaProtocol->Area->TbtLtr = (UINT8)
> DxeTbtConfig->TbtCommonConfig.TbtLtr;
> -// TbtNvsAreaProtocol->Area->TbtPtm = (UINT8)
> DxeTbtConfig->TbtCommonConfig.TbtPtm;
> - TbtNvsAreaProtocol->Area->TbtWakeupSupport = (UINT8)
> DxeTbtConfig->TbtCommonConfig.TbtWakeupSupport;
> - TbtNvsAreaProtocol->Area->TbtAcDcSwitch = (UINT8)
> DxeTbtConfig->TbtCommonConfig.TbtAcDcSwitch;
> - TbtNvsAreaProtocol->Area->Rtd3TbtSupport = (UINT8)
> DxeTbtConfig->TbtCommonConfig.Rtd3Tbt; // TBT RTD3
> Enable.
> - TbtNvsAreaProtocol->Area->Rtd3TbtOffDelay = (UINT16)
> DxeTbtConfig->TbtCommonConfig.Rtd3TbtOffDelay; // TBT RTD3 Off
> delay in ms.
> - TbtNvsAreaProtocol->Area->Rtd3TbtClkReq = (UINT8)
> DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReq; // TBT RTD3
> ClkReq Mask Enable.
> - TbtNvsAreaProtocol->Area->Rtd3TbtClkReqDelay = (UINT16)
> DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReqDelay; // TBT RTD3 ClkReq
> mask delay in ms.
> - TbtNvsAreaProtocol->Area->TbtWin10Support = (UINT8)
> DxeTbtConfig->TbtCommonConfig.Win10Support; // TBT FW Execution Mode
> -
> - //
> - // DTBT Controller 1
> - //
> - TbtNvsAreaProtocol->Area->DTbtControllerEn0 = gTbtInfoHob->
> DTbtControllerConfig.DTbtControllerEn;
> - TbtNvsAreaProtocol->Area->RootportSelected0 = gTbtInfoHob->
> DTbtControllerConfig.PcieRpNumber;
> - TbtNvsAreaProtocol->Area->RootportSelected0Type = gTbtInfoHob->
> DTbtControllerConfig.Type;
> - TbtNvsAreaProtocol->Area->RootportEnabled0 = gTbtInfoHob->
> DTbtControllerConfig.DTbtControllerEn;
> - TbtNvsAreaProtocol->Area->TbtFrcPwrGpioNo0 = gTbtInfoHob->
> DTbtControllerConfig.ForcePwrGpio.GpioPad;
> - TbtNvsAreaProtocol->Area->TbtFrcPwrGpioLevel0 = gTbtInfoHob->
> DTbtControllerConfig.ForcePwrGpio.GpioLevel;
> - TbtNvsAreaProtocol->Area->TbtCioPlugEventGpioNo0 = gTbtInfoHob->
> DTbtControllerConfig.CioPlugEventGpio.GpioPad;
> - TbtNvsAreaProtocol->Area->TbtPcieRstGpioNo0 = gTbtInfoHob->
> DTbtControllerConfig.PcieRstGpio.GpioPad;
> - TbtNvsAreaProtocol->Area->TbtPcieRstGpioLevel0 = gTbtInfoHob->
> DTbtControllerConfig.PcieRstGpio.GpioLevel;
> -
> - TbtNvsAreaProtocol->Area->TBtCommonGpioSupport =
> gTbtInfoHob->DTbtCommonConfig.DTbtSharedGpioConfiguration;
> -
> - DEBUG ((DEBUG_INFO, "TbtNvsAreaInit End\n"));
> -}
> -
> -/**
> - This function gets registered as a callback to patch TBT ASL code
> -
> - @param[in] Event - A pointer to the Event that triggered the
> callback.
> - @param[in] Context - A pointer to private data registered with the
> callback function.
> - can we put this also in read me
> -**/
> -VOID
> -EFIAPI
> -TbtAcpiEndOfDxeCallback (
> - IN EFI_EVENT Event,
> - IN VOID *Context
> - )
> -{
> - EFI_STATUS Status;
> - UINT32 Address;
> - UINT16 Length;
> - UINT32 Signature;
> -
> - Status = InitializeAslUpdateLib ();
> - ASSERT_EFI_ERROR (Status);
> -
> - Address = (UINT32) (UINTN) mTbtNvsAreaProtocol.Area;
> - Length = (UINT16) sizeof (TBT_NVS_AREA);
> - DEBUG ((DEBUG_INFO, "Patch TBT NvsAreaAddress: TBT NVS Address %x
> Length %x\n", Address, Length));
> - Status = UpdateNameAslCode (SIGNATURE_32 ('T','N','V','B'), &Address,
> sizeof (Address));
> - ASSERT_EFI_ERROR (Status);
> - Status = UpdateNameAslCode (SIGNATURE_32 ('T','N','V','L'), &Length,
> sizeof (Length));
> - ASSERT_EFI_ERROR (Status);
> -
> - if (gTbtInfoHob != NULL) {
> - if (gTbtInfoHob-> DTbtControllerConfig.DTbtControllerEn == 1) {
> - if (gTbtInfoHob->
> DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignaturePorting == TRUE) {
> - DEBUG ((DEBUG_INFO, "Patch ATBT Method Name\n"));
> - Signature = gTbtInfoHob->
> DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature;
> - Status = UpdateNameAslCode (SIGNATURE_32 ('A','T','B','T'),
> &Signature, sizeof (Signature));
> - ASSERT_EFI_ERROR (Status);
> - }
> - }
> - }
> -
> - return;
> -}
> -
> -/**
> - Initialize Thunderbolt(TM) SSDT ACPI tables
> -
> - @retval EFI_SUCCESS ACPI tables are initialized successfully
> - @retval EFI_NOT_FOUND ACPI tables not found
> -**/
> -
> -EFI_STATUS
> -EFIAPI
> -TbtDxeEntryPoint (
> - IN EFI_HANDLE ImageHandle,
> - IN EFI_SYSTEM_TABLE *SystemTable
> - )
> -{
> - EFI_STATUS Status;
> - EFI_HANDLE Handle;
> - // EFI_EVENT EndOfDxeEvent;
> -
> - DEBUG ((DEBUG_INFO, "TbtDxeEntryPoint \n"));
> -
> - //
> - // Get TBT INFO HOB
> - //
> - gTbtInfoHob = (TBT_INFO_HOB *) GetFirstGuidHob (&gTbtInfoHobGuid);
> - if (gTbtInfoHob == NULL) {
> - return EFI_NOT_FOUND;
> - }
> - InstallTbtPolicy (ImageHandle);
> - //
> - // Update DXE TBT Policy
> - //
> - UpdateTbtPolicyCallback ();
> -
> - //
> - // Print DXE TBT Policy
> - //
> - TbtPrintDxePolicyConfig ();
> -
> - //
> - // Initialize Tbt Nvs Area
> - //
> - TbtNvsAreaInit ((VOID **) &mTbtNvsAreaProtocol.Area);
> -
> -
> - //
> - // [ACPI] Thunderbolt ACPI table
> - //
> -
> -
> - Handle = NULL;
> -
> - Status = gBS->InstallMultipleProtocolInterfaces (
> - &Handle,
> - &gTbtNvsAreaProtocolGuid,
> - &mTbtNvsAreaProtocol,
> - NULL
> - );
> - ASSERT_EFI_ERROR (Status);
> -
> - //
> - // Register an end of DXE event for TBT ACPI to do some patch can be put
> as description
> - //
> - /**
> - Status = gBS->CreateEventEx (
> - EVT_NOTIFY_SIGNAL,
> - TPL_CALLBACK,
> - TbtAcpiEndOfDxeCallback,
> - NULL,
> - &gEfiEndOfDxeEventGroupGuid,
> - &EndOfDxeEvent
> - );
> - ASSERT_EFI_ERROR (Status);
> -**/
> - return EFI_SUCCESS;
> -}
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiTbtInit.c
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiTbtInit.c
> deleted file mode 100644
> index a824886697..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiTbtInit.c
> +++ /dev/null
> @@ -1,193 +0,0 @@
> -/** @file
> - Thunderbolt initialization in PEI.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <Library/IoLib.h>
> -#include <Library/HobLib.h>
> -#include <Library/DebugLib.h>
> -#include <Library/BaseMemoryLib.h>
> -#include <Library/PeiServicesLib.h>
> -#include <Library/PciSegmentLib.h>
> -#include <Library/PeiTbtPolicyLib.h>
> -#include <Ppi/SiPolicy.h>
> -#include <Ppi/PeiTbtPolicy.h>
> -#include <Ppi/EndOfPeiPhase.h>
> -#include <TbtBoardInfo.h>
> -#include <Private/Library/PeiDTbtInitLib.h>
> -
> -/**
> - This function pass PEI TBT Policy to Hob at the end of PEI
> -
> - @param[in] PeiServices Pointer to PEI Services Table.
> - @param[in] NotifyDesc Pointer to the descriptor for the Notification
> event that
> - caused this function to execute.
> - @param[in] Ppi Pointer to the PPI data associated with this
> function.
> -
> - @retval EFI_SUCCESS The function completes successfully
> - @retval others
> -**/
> -EFI_STATUS
> -EFIAPI
> -PassTbtPolicyToHob (
> -VOID
> - )
> -{
> - EFI_STATUS Status;
> - EFI_BOOT_MODE BootMode;
> - TBT_INFO_HOB *TbtInfoHob;
> - PEI_TBT_POLICY *PeiTbtConfig;
> -
> - DEBUG ((DEBUG_INFO, "PassTbtPolicyToHob\n"));
> -
> - Status = PeiServicesGetBootMode (&BootMode);
> - ASSERT_EFI_ERROR (Status);
> - if (BootMode == BOOT_ON_S3_RESUME ) {
> - return EFI_SUCCESS;
> - }
> -
> - Status = PeiServicesLocatePpi (
> - &gPeiTbtPolicyPpiGuid,
> - 0,
> - NULL,
> - (VOID **) &PeiTbtConfig
> - );
> - if (EFI_ERROR(Status)) {
> - DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n"));
> - }
> - ASSERT_EFI_ERROR (Status);
> -
> - //
> - // Create HOB for TBT Data
> - //
> - Status = PeiServicesCreateHob (
> - EFI_HOB_TYPE_GUID_EXTENSION,
> - sizeof (TBT_INFO_HOB),
> - (VOID **) &TbtInfoHob
> - );
> - DEBUG ((DEBUG_INFO, "TbtInfoHob Created \n"));
> - ASSERT_EFI_ERROR (Status);
> -
> - //
> - // Initialize the TBT INFO HOB data.
> - //
> - TbtInfoHob->EfiHobGuidType.Name = gTbtInfoHobGuid;
> -
> - //
> - // Update DTBT Policy
> - //
> - TbtInfoHob-> DTbtControllerConfig.DTbtControllerEn = PeiTbtConfig->
> DTbtControllerConfig.DTbtControllerEn;
> - TbtInfoHob-> DTbtControllerConfig.Type = PeiTbtConfig->
> DTbtControllerConfig.Type;
> - TbtInfoHob-> DTbtControllerConfig.PcieRpNumber = PeiTbtConfig->
> DTbtControllerConfig.PcieRpNumber;
> - TbtInfoHob-> DTbtControllerConfig.ForcePwrGpio.GpioPad =
> PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioPad;
> - TbtInfoHob-> DTbtControllerConfig.ForcePwrGpio.GpioLevel =
> PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioLevel;
> - TbtInfoHob-> DTbtControllerConfig.CioPlugEventGpio.GpioPad =
> PeiTbtConfig-> DTbtControllerConfig.CioPlugEventGpio.GpioPad;
> - TbtInfoHob-> DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature =
> PeiTbtConfig-> DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature;
> - TbtInfoHob->
> DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignaturePorting =
> PeiTbtConfig->
> DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignaturePorting;
> - TbtInfoHob-> DTbtControllerConfig.PcieRstGpio.GpioPad = PeiTbtConfig->
> DTbtControllerConfig.PcieRstGpio.GpioPad;
> - TbtInfoHob-> DTbtControllerConfig.PcieRstGpio.GpioLevel =
> PeiTbtConfig-> DTbtControllerConfig.PcieRstGpio.GpioLevel;
> -
> - TbtInfoHob->DTbtCommonConfig.TbtBootOn =
> PeiTbtConfig->DTbtCommonConfig.TbtBootOn;
> - TbtInfoHob->DTbtCommonConfig.TbtUsbOn =
> PeiTbtConfig->DTbtCommonConfig.TbtUsbOn;
> - TbtInfoHob->DTbtCommonConfig.Gpio3ForcePwr =
> PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr;
> - TbtInfoHob->DTbtCommonConfig.Gpio3ForcePwrDly =
> PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly;
> - TbtInfoHob->DTbtCommonConfig.DTbtSharedGpioConfiguration =
> PeiTbtConfig->DTbtCommonConfig.DTbtSharedGpioConfiguration;
> - TbtInfoHob->DTbtCommonConfig.PcieRstSupport =
> PeiTbtConfig->DTbtCommonConfig.PcieRstSupport;
> -
> - return EFI_SUCCESS;
> -}
> -
> -/**
> - This function handles TbtInit task at the end of PEI
> -
> - @param[in] PeiServices Pointer to PEI Services Table.
> - @param[in] NotifyDesc Pointer to the descriptor for the Notification
> event that
> - caused this function to execute.
> - @param[in] Ppi Pointer to the PPI data associated with this
> function.
> -
> - @retval EFI_SUCCESS The function completes successfully
> - @retval others
> -**/
> -EFI_STATUS
> -EFIAPI
> -TbtInitEndOfPei (
> - VOID
> - )
> -{
> - EFI_STATUS Status;
> - BOOLEAN DTbtExisted;
> - PEI_TBT_POLICY *PeiTbtConfig;
> -
> - DEBUG ((DEBUG_INFO, "TbtInitEndOfPei Entry\n"));
> -
> - Status = EFI_SUCCESS;
> - PeiTbtConfig = NULL;
> - DTbtExisted = FALSE;
> -
> - Status = PeiServicesLocatePpi (
> - &gPeiTbtPolicyPpiGuid,
> - 0,
> - NULL,
> - (VOID **) &PeiTbtConfig
> - );
> - if (EFI_ERROR(Status)) {
> - DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n"));
> - }
> - ASSERT_EFI_ERROR (Status);
> -
> - if (PeiTbtConfig-> DTbtControllerConfig.DTbtControllerEn == 1) {
> - DTbtExisted = TRUE;
> - }
> -
> - if (DTbtExisted == TRUE) {
> - //
> - // Call Init function
> - //
> - Status = TbtInit ();
> - }
> -
> - return EFI_SUCCESS;
> -}
> -
> -/**
> - TBT Init PEI module entry point
> -
> - @param[in] FileHandle Not used.
> - @param[in] PeiServices General purpose services available
> to every PEIM.
> -
> - @retval EFI_SUCCESS The function completes
> successfully
> - @retval EFI_OUT_OF_RESOURCES Insufficient resources to create
> database
> -**/
> -EFI_STATUS
> -EFIAPI
> -TbtInitEntryPoint (
> - IN EFI_PEI_FILE_HANDLE FileHandle,
> - IN CONST EFI_PEI_SERVICES **PeiServices
> - )
> -{
> - EFI_STATUS Status;
> -
> - DEBUG ((DEBUG_INFO, "TBT PEI EntryPoint\n"));
> -
> - //
> - // Install PEI TBT Policy
> - //
> - Status = InstallPeiTbtPolicy ();
> - ASSERT_EFI_ERROR (Status);
> -
> -
> - UpdatePeiTbtPolicy ();
> -
> - TbtPrintPeiPolicyConfig ();
> - //
> - // Performing PassTbtPolicyToHob and TbtInitEndOfPei
> - //
> - Status = PassTbtPolicyToHob ();
> -
> - Status = TbtInitEndOfPei ();
> -
> - return Status;
> -}
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmiHan
> dler.c
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmiHan
> dler.c
> deleted file mode 100644
> index 216a7b155c..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmiHan
> dler.c
> +++ /dev/null
> @@ -1,1610 +0,0 @@
> -/**@file
> - Thunderbolt SMI handler.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include "TbtSmiHandler.h"
> -#include <Library/IoLib.h>
> -#include <Library/BaseLib.h>
> -#include <Library/DebugLib.h>
> -#include <Protocol/SmmVariable.h>
> -#include <Library/BaseMemoryLib.h>
> -#include <Library/SmmServicesTableLib.h>
> -#include <Library/PciSegmentLib.h>
> -#define MEM_PER_SLOT (DEF_RES_MEM_PER_DEV << 4)
> -#define PMEM_PER_SLOT (DEF_RES_PMEM_PER_DEV << 4)
> -#define IO_PER_SLOT (DEF_RES_IO_PER_DEV << 2)
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED UINTN
> gDeviceBaseAddress;
> -//
> -//US(X:0:0), DS(X+1:3:0),DS(X+1:4:0),DS(X+1:5:0),DS(X+1:6:0)
> -//
> -GLOBAL_REMOVE_IF_UNREFERENCED BRDG_CONFIG
> HrConfigs[MAX_CFG_PORTS];
> -
> -extern UINT8 gCurrentDiscreteTbtRootPort;
> -extern UINT8 gCurrentDiscreteTbtRootPortType;
> -
> -BOOLEAN isLegacyDevice = FALSE;
> -STATIC UINT8 TbtSegment = 0;
> -
> -STATIC
> -VOID
> -PortInfoInit (
> - IN OUT PORT_INFO *PortInfo
> - )
> -{
> - PortInfo->BusNumLimit = 4;
> -}
> -
> -STATIC
> -VOID
> -UnsetVesc (
> - IN UINT8 Bus,
> - IN UINT8 Dev,
> - IN UINT8 Fun
> - )
> -{
> - UINT8 Dbus;
> - UINT32 Data32;
> - gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev,
> Fun, 0);
> -
> - //
> - // Check for abcence of DS bridge
> - //
> - if(0xFFFF == PciSegmentRead16(gDeviceBaseAddress +
> PCI_DEVICE_ID_OFFSET)) {
> - return;
> - }
> -
> - //
> - // Unset vesc_reg2[23] bit (to have an option to access below DS)
> - //
> - Data32 = PciSegmentRead32 (gDeviceBaseAddress + PCI_TBT_VESC_REG2);
> - Data32 &= 0xFF7FFFFF;
> - PciSegmentWrite32(gDeviceBaseAddress + PCI_TBT_VESC_REG2, Data32);
> - //
> - // Go to Device behind DS
> - //
> - Dbus = PciSegmentRead8 (gDeviceBaseAddress +
> PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
> - DEBUG((DEBUG_INFO, "Dbus = %d\n",Dbus));
> - //
> - // Check if there is something behind this Downstream Port (Up or Ep)
> - // If there nothing behind Downstream Port Set vesc_reg2[23] bit -> this
> will flush all future MemWr
> - //
> - gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Dbus,
> 0x00, 0x00, 0);
> - if(0xFFFF == PciSegmentRead16(gDeviceBaseAddress +
> PCI_DEVICE_ID_OFFSET))
> - {
> - gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev,
> Fun, 0);
> - Data32 = PciSegmentRead32 (gDeviceBaseAddress + PCI_TBT_VESC_REG2);
> - Data32 |= 0x00800000;
> - PciSegmentWrite32 (gDeviceBaseAddress + PCI_TBT_VESC_REG2, Data32);
> - }
> -}// Unset_VESC_REG2
> -
> -STATIC
> -UINT16
> -MemPerSlot (
> - IN UINT16 CurrentUsage
> - )
> -{
> - if (CurrentUsage == 0) {
> - return 0;
> - }
> -
> - if (CurrentUsage <= 16) {
> - return 16;
> - }
> -
> - if (CurrentUsage <= 64) {
> - return 64;
> - }
> -
> - if (CurrentUsage <= 128) {
> - return 128;
> - }
> -
> - if (CurrentUsage <= 256) {
> - return 256;
> - }
> -
> - if (CurrentUsage <= 512) {
> - return 512;
> - }
> -
> - if (CurrentUsage <= 1024) {
> - return 1024;
> - }
> -
> - return CurrentUsage;
> -} // MemPerSlot
> -
> -STATIC
> -UINT64
> -PMemPerSlot (
> - IN UINT64 CurrentUsage
> - )
> -{
> - if (CurrentUsage == 0) {
> - return 0;
> - }
> -
> - if (CurrentUsage <= 1024ULL) {
> - return 1024ULL;
> - }
> -
> - if (CurrentUsage <= 4096ULL) {
> - return 4096ULL;
> - }
> -
> - return CurrentUsage;
> -} // PMemPerSlot
> -
> -STATIC
> -VOID
> -SetPhyPortResources (
> - IN UINT8 Bus,
> - IN UINT8 Dev,
> - IN UINT8 SubBus,
> - IN INT8 Depth,
> - IN PORT_INFO *CurrentPi,
> - IN OUT PORT_INFO *PortInfo
> - )
> -{
> - UINT8 Cmd;
> - UINT16 DeltaMem;
> - UINT64 DeltaPMem;
> -
> - Cmd = CMD_BUS_MASTER;
> - gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev,
> 0x00, 0);
> -
> - PciSegmentWrite8 (gDeviceBaseAddress +
> PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET, SubBus);
> - PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, Cmd);
> -
> - DeltaMem = PortInfo->MemBase - CurrentPi->MemBase;
> - if (isLegacyDevice) {
> - if (Depth >= 0 && (DeltaMem < MEM_PER_SLOT)) {
> - PortInfo->MemBase += MEM_PER_SLOT - DeltaMem;
> - }
> - } else {
> - if (DeltaMem < MemPerSlot (DeltaMem)) {
> - PortInfo->MemBase += MemPerSlot (DeltaMem) - DeltaMem;
> - }
> - }
> -
> - if (PortInfo->MemBase > CurrentPi->MemBase && (PortInfo->MemBase -
> 0x10) <= PortInfo->MemLimit) {
> - PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.MemoryBase), CurrentPi->MemBase);
> - PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.MemoryLimit), PortInfo->MemBase - 0x10);
> - Cmd |= CMD_BM_MEM;
> - } else {
> - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.MemoryBase), DISBL_MEM32_REG20);
> - PortInfo->MemBase = CurrentPi->MemBase;
> - }
> -
> - DeltaPMem = PortInfo->PMemBase64 - CurrentPi->PMemBase64;
> - if (isLegacyDevice) {
> - if ((Depth >= 0) && ((UINTN)DeltaPMem < (UINTN)PMEM_PER_SLOT)) {
> - PortInfo->PMemBase64 += PMEM_PER_SLOT - DeltaPMem;
> - }
> - } else {
> - if (DeltaPMem < PMemPerSlot (DeltaPMem)) {
> - PortInfo->PMemBase64 += PMemPerSlot (DeltaPMem) - DeltaPMem;
> - }
> - }
> -
> - if (PortInfo->PMemBase64 > CurrentPi->PMemBase64 &&
> (PortInfo->PMemBase64 - 0x10) <= PortInfo->PMemLimit64) {
> - PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.PrefetchableMemoryBase), (UINT16) (CurrentPi->PMemBase64 &
> 0xFFFF));
> - PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.PrefetchableMemoryLimit), (UINT16) ((PortInfo->PMemBase64 - 0x10)
> & 0xFFFF));
> - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.PrefetchableBaseUpper32), (UINT32) (CurrentPi->PMemBase64 >>
> 16));
> - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.PrefetchableLimitUpper32), (UINT32) ((PortInfo->PMemBase64 - 0x10)
> >> 16));
> - Cmd |= CMD_BM_MEM;
> - } else {
> - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.PrefetchableMemoryBase), DISBL_PMEM_REG24);
> - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.PrefetchableBaseUpper32), 0);
> - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.PrefetchableLimitUpper32), 0);
> - PortInfo->PMemBase64 = CurrentPi->PMemBase64;
> - }
> -
> - PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, Cmd);
> - PciSegmentWrite8 (gDeviceBaseAddress + PCI_CACHELINE_SIZE_OFFSET,
> DEF_CACHE_LINE_SIZE);
> -} // SetPhyPortResources
> -
> -STATIC
> -UINT32
> -SaveSetGetRestoreBar (
> - IN UINTN Bar
> - )
> -{
> - UINT32 BarReq;
> - UINT32 OrigBar;
> -
> - OrigBar = PciSegmentRead32(Bar); // Save BAR
> - PciSegmentWrite32(Bar, 0xFFFFFFFF); // Set BAR
> - BarReq = PciSegmentRead32(Bar); // Get BAR
> - PciSegmentWrite32(Bar, OrigBar); // Restore BAR
> -
> - return BarReq;
> -} // SaveSetGetRestoreBar
> -
> -STATIC
> -VOID
> -SetIoBar (
> - IN UINTN BAR,
> - IN UINT32 BarReq,
> - IN OUT UINT8 *Cmd,
> - IN OUT IO_REGS *IoReg
> - )
> -{
> - UINT16 Alignment;
> - UINT16 Size;
> - UINT16 NewBase;
> -
> - Alignment = ~(BarReq & 0xFFFC);
> - Size = Alignment + 1;
> -
> - if (IoReg->Base > IoReg->Limit || !Size) {
> - return ;
> -
> - }
> -
> - NewBase = BAR_ALIGN (IoReg->Base, Alignment);
> - if (NewBase > IoReg->Limit || NewBase + Size - 1 > IoReg->Limit) {
> - return ;
> -
> - }
> - PciSegmentWrite16(BAR, NewBase);
> - IoReg->Base = NewBase + Size; // Advance to new position
> - *Cmd |= CMD_BM_IO; // Set Io Space Enable
> -} // SetIoBar
> -
> -STATIC
> -VOID
> -SetMemBar (
> - IN UINTN BAR,
> - IN UINT32 BarReq,
> - IN OUT UINT8 *Cmd,
> - IN OUT MEM_REGS *MemReg
> - )
> -{
> - UINT32 Alignment;
> - UINT32 Size;
> - UINT32 NewBase;
> -
> - Alignment = ~(BarReq & 0xFFFFFFF0);
> - Size = Alignment + 1;
> -
> - if (MemReg->Base > MemReg->Limit || !Size) {
> - return ;
> -
> - }
> -
> - NewBase = BAR_ALIGN (MemReg->Base, Alignment);
> - if (NewBase > MemReg->Limit || NewBase + Size - 1 > MemReg->Limit) {
> - return ;
> -
> - }
> -
> - PciSegmentWrite32(BAR, NewBase);
> - MemReg->Base = NewBase + Size; // Advance to new position
> - *Cmd |= CMD_BM_MEM; // Set Memory Space Enable
> -} // SetMemBar
> -
> -STATIC
> -VOID
> -SetPMem64Bar (
> - IN UINTN BAR,
> - IN BOOLEAN IsMaxBar,
> - IN UINT32 BarReq,
> - IN OUT UINT8 *Cmd,
> - IN OUT PMEM_REGS *MemReg
> - )
> -{
> - UINT32 Alignment;
> - UINT32 Size;
> - UINT64 NewBase;
> -
> - Alignment = ~(BarReq & 0xFFFFFFF0);
> - Size = Alignment + 1;
> -
> - if (MemReg->Base64 > MemReg->Limit64 || !Size) {
> - return ;
> - }
> -
> - NewBase = BAR_ALIGN (MemReg->Base64, Alignment);
> - if (NewBase > MemReg->Limit64 || NewBase + Size - 1 >
> MemReg->Limit64) {
> - return ;
> - }
> - PciSegmentWrite32(BAR, (UINT32)(NewBase & 0xFFFFFFFF));
> - if (!IsMaxBar) {
> - BAR++;
> - PciSegmentWrite32(BAR, (UINT32)(NewBase >> 32));
> - }
> - MemReg->Base64 = NewBase + Size; // Advance to new position
> - *Cmd |= CMD_BM_MEM; // Set Memory Space Enable
> -} // SetPMem64Bar
> -
> -STATIC
> -VOID
> -SetDevResources (
> - IN UINT8 Bus,
> - IN UINT8 Dev,
> - IN UINT8 MaxFun, // PCI_MAX_FUNC for devices, 1 for
> bridge
> - IN UINT8 MaxBar, // PCI_BAR5 for devices, PCI_BAR1
> for bridge
> - IN OUT PORT_INFO *PortInfo
> - )
> -{
> - UINT8 Fun;
> - UINT8 Reg;
> - UINT32 BarReq;
> - IO_REGS Io;
> - MEM_REGS Mem;
> - PMEM_REGS PMem;
> - UINT8 Cmd;
> -
> - Io.Base = PortInfo->IoBase << 8;
> - Io.Limit = (PortInfo->IoLimit << 8) | 0xFF;
> - Mem.Base = PortInfo->MemBase << 16;
> - Mem.Limit = (PortInfo->MemLimit << 16) | 0xFFFF;
> - PMem.Base64 = PortInfo->PMemBase64 << 16;
> - PMem.Limit64 = (PortInfo->PMemLimit64 << 16) | 0xFFFF;
> -
> - for (Fun = 0; Fun < MaxFun; ++Fun) {
> - gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus,
> Dev, Fun, 0);
> - PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET,
> CMD_BUS_MASTER);
> - Cmd = PciSegmentRead8 (gDeviceBaseAddress +
> PCI_COMMAND_OFFSET);
> - if (0xFFFF == PciSegmentRead16 (gDeviceBaseAddress +
> PCI_DEVICE_ID_OFFSET)) {
> - continue;
> -
> - }
> -
> - for (Reg = PCI_BASE_ADDRESSREG_OFFSET; Reg <= MaxBar; Reg += 4) {
> - BarReq = SaveSetGetRestoreBar(gDeviceBaseAddress + Reg); //
> Perform BAR sizing
> -
> - if (BarReq & BIT0) {
> - //
> - // I/O BAR
> - //
> - SetIoBar (
> - (gDeviceBaseAddress + Reg),
> - BarReq,
> - &Cmd,
> - &Io
> - );
> - continue;
> - }
> -
> - if (BarReq & BIT3) {
> - //
> - // P-Memory BAR
> - //
> - SetPMem64Bar ((gDeviceBaseAddress + Reg), MaxBar == Reg,
> BarReq, &Cmd, &PMem);
> - } else {
> - SetMemBar ((gDeviceBaseAddress + Reg), BarReq, &Cmd, &Mem);
> - }
> -
> - if (BIT2 == (BarReq & (BIT2 | BIT1))) {
> - //
> - // Base address is 64 bits wide
> - //
> - Reg += 4;
> - if (!(BarReq & BIT3)) {
> - //
> - // 64-bit memory bar
> - //
> - PciSegmentWrite32 (gDeviceBaseAddress + Reg, 0);
> - }
> - }
> - }
> -
> - if (Cmd & BIT1) {
> - //
> - // If device uses I/O and MEM mapping use only MEM mepping
> - //
> - Cmd &= ~BIT0;
> - }
> -
> - PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET,
> Cmd);
> - PciSegmentWrite8 (gDeviceBaseAddress + PCI_CACHELINE_SIZE_OFFSET,
> DEF_CACHE_LINE_SIZE);
> - }
> - //
> - // Update PortInfo if any changes
> - //
> - if (Io.Base > ((UINT32) PortInfo->IoBase << 8)) {
> - PortInfo->IoBase = (UINT8) (BAR_ALIGN (Io.Base, 0xFFF) >> 8);
> - }
> -
> - if (Mem.Base > ((UINT32) PortInfo->MemBase << 16)) {
> - PortInfo->MemBase = (UINT16) (BAR_ALIGN (Mem.Base, 0xFFFFF) >>
> 16);
> - }
> -
> - if (PMem.Base64 > (PortInfo->PMemBase64 << 16)) {
> - PortInfo->PMemBase64 = (BAR_ALIGN (PMem.Base64, 0xFFFFF) >> 16);
> - }
> -} // SetDevResources
> -
> -STATIC
> -VOID
> -InitARHRConfigs(
> - IN HR_CONFIG *Hr_Config,
> - IN UINT8 BusNumLimit,
> - IN OUT BRDG_RES_CONFIG* HrResConf
> -)
> -{
> - UINT8 i,j;
> -
> - //
> - // DS port for USB device
> - //
> - HrConfigs[AR_DS_PORT2].DevId.Bus = HrConfigs[HR_US_PORT].DevId.Bus
> + 1;
> - HrConfigs[AR_DS_PORT2].DevId.Dev = 2;
> - HrConfigs[AR_DS_PORT2].DevId.Fun = 0;
> - HrConfigs[AR_DS_PORT2].PBus = HrConfigs[AR_DS_PORT2].DevId.Bus;
> - HrConfigs[AR_DS_PORT2].SBus = HrConfigs[AR_DS_PORT2].PBus + 1;
> - HrConfigs[AR_DS_PORT2].SubBus = HrConfigs[AR_DS_PORT2].PBus + 1;
> - //
> - // CIO port
> - //
> - HrConfigs[AR_DS_PORT1].DevId.Bus = HrConfigs[HR_US_PORT].DevId.Bus
> + 1;
> - HrConfigs[AR_DS_PORT1].DevId.Dev = 1;
> - HrConfigs[AR_DS_PORT1].DevId.Fun = 0;
> - HrConfigs[AR_DS_PORT1].PBus = HrConfigs[AR_DS_PORT1].DevId.Bus;
> - HrConfigs[AR_DS_PORT1].SBus = HrConfigs[HR_DS_PORT0].SubBus + 1;
> - HrConfigs[AR_DS_PORT1].SubBus = BusNumLimit;
> -
> - switch(Hr_Config->DeviceId)
> - {
> - //
> - // HR with 1 DS and 1 USB
> - //
> - case AR_HR_2C:
> - case AR_HR_LP:
> - case AR_HR_C0_2C:
> - case TR_HR_2C:
> - Hr_Config->MinDSNumber = HrConfigs[AR_DS_PORT1].DevId.Dev;
> - Hr_Config->MaxDSNumber = HrConfigs[AR_DS_PORT2].DevId.Dev;
> - Hr_Config->BridgeLoops = 4;
> - break;
> - //
> - // HR with 2 DS and 1 USB
> - //
> - case AR_HR_4C:
> - case TR_HR_4C:
> - case AR_HR_C0_4C:
> - Hr_Config->MinDSNumber = 1;
> - Hr_Config->MaxDSNumber = 4;
> - Hr_Config->BridgeLoops = 6;
> - for(j = 2, i = Hr_Config->MinDSNumber; j < count(HrConfigs) && i <=
> Hr_Config->MaxDSNumber; ++j, ++i)
> - {
> - HrConfigs[j].DevId.Bus = HrConfigs[HR_US_PORT].DevId.Bus + 1;
> - HrConfigs[j].DevId.Dev = i;
> - HrConfigs[j].DevId.Fun = 0;
> - HrConfigs[j].PBus = HrConfigs[j].DevId.Bus;
> - HrConfigs[j].Res.Cls = DEF_CACHE_LINE_SIZE;
> - }
> - break;
> - }
> -}//InitARHRConfigs
> -
> -
> -STATIC
> -VOID
> -InitCommonHRConfigs (
> - IN HR_CONFIG *Hr_Config,
> - IN UINT8 BusNumLimit,
> - IN OUT BRDG_RES_CONFIG *HrResConf
> - )
> -{
> - UINT8 i;
> -
> - UINT8 j;
> - for(i = 0; i < count(HrConfigs); ++i) {
> - HrConfigs[i].IsDSBridge = TRUE;
> - }
> - //
> - // US(HRBus:0:0)
> - //
> - HrConfigs[HR_US_PORT].DevId.Bus = Hr_Config->HRBus;
> - HrConfigs[HR_US_PORT].DevId.Dev = 0;
> - HrConfigs[HR_US_PORT].DevId.Fun = 0;
> - HrConfigs[HR_US_PORT].Res = *HrResConf;
> - HrConfigs[HR_US_PORT].Res.IoBase = 0xF1;
> - HrConfigs[HR_US_PORT].Res.IoLimit = 0x01;
> - HrConfigs[HR_US_PORT].PBus =
> HrConfigs[HR_US_PORT].DevId.Bus;
> - HrConfigs[HR_US_PORT].SBus = HrConfigs[HR_US_PORT].PBus +
> 1;
> - HrConfigs[HR_US_PORT].SubBus = BusNumLimit;
> - HrConfigs[HR_US_PORT].IsDSBridge = FALSE;
> -
> - //
> - // HIA resides here
> - //
> - HrConfigs[HR_DS_PORT0].DevId.Bus =
> HrConfigs[HR_US_PORT].DevId.Bus + 1;
> - HrConfigs[HR_DS_PORT0].DevId.Dev = 0;
> - HrConfigs[HR_DS_PORT0].DevId.Fun = 0;
> - HrConfigs[HR_DS_PORT0].Res = NOT_IN_USE_BRIDGE;
> - HrConfigs[HR_DS_PORT0].Res.MemBase = HrResConf->MemLimit;
> - HrConfigs[HR_DS_PORT0].Res.MemLimit = HrResConf->MemLimit;
> - HrResConf->MemLimit -= 0x10; //This 1 MB chunk will
> be used by HIA
> - HrConfigs[HR_DS_PORT0].Res.Cmd = CMD_BM_MEM;
> - HrConfigs[HR_DS_PORT0].Res.Cls = DEF_CACHE_LINE_SIZE;
> - HrConfigs[HR_DS_PORT0].PBus =
> HrConfigs[HR_DS_PORT0].DevId.Bus;
> - HrConfigs[HR_DS_PORT0].SBus = HrConfigs[HR_DS_PORT0].PBus
> + 1;
> - HrConfigs[HR_DS_PORT0].SubBus = HrConfigs[HR_DS_PORT0].PBus
> + 1;
> -
> - switch (Hr_Config->DeviceId) {
> - //
> - // Alpine Ridge
> - //
> - case AR_HR_2C:
> - case AR_HR_C0_2C:
> - case AR_HR_LP:
> - case AR_HR_4C:
> - case AR_HR_C0_4C:
> - //
> - // Titan Ridge
> - //
> - case TR_HR_2C:
> - case TR_HR_4C:
> - InitARHRConfigs(Hr_Config, BusNumLimit, HrResConf);
> - break;
> -
> - default:
> - //
> - // DS(HRBus+2:3-6:0)
> - //
> - Hr_Config->MinDSNumber = 3;
> - Hr_Config->MaxDSNumber = 6;
> - Hr_Config->BridgeLoops = count (HrConfigs);
> -
> - for (j = 2, i = Hr_Config->MinDSNumber; j < count (HrConfigs) && i <=
> Hr_Config->MaxDSNumber; ++j, ++i) {
> - HrConfigs[j].DevId.Bus = HrConfigs[HR_US_PORT].DevId.Bus + 1;
> - HrConfigs[j].DevId.Dev = i;
> - HrConfigs[j].DevId.Fun = 0;
> - HrConfigs[j].PBus = HrConfigs[j].DevId.Bus;
> - HrConfigs[j].Res.Cls = DEF_CACHE_LINE_SIZE;
> - }
> - }
> -} // InitCommonHRConfigs
> -
> -STATIC
> -VOID
> -InitHRDSPort_Disable (
> - IN UINT8 id,
> - IN OUT BRDG_CONFIG *BrdgConf
> - )
> -{
> - HrConfigs[id].Res = NOT_IN_USE_BRIDGE;
> - HrConfigs[id].SBus = BrdgConf->SBus;
> - HrConfigs[id].SubBus = BrdgConf->SBus;
> -
> - BrdgConf->SBus++;
> -} // InitHRDSPort_Disable
> -
> -//AR only
> -
> -STATIC
> -VOID
> -InitARDSPort_1Port(
> - IN OUT BRDG_CONFIG* BrdgConf
> -)
> -{
> - UINT16 MemBase = BrdgConf->Res.MemBase & 0xFFF0;
> - UINT64 PMemBase64 = BrdgConf->Res.PMemBase64 & ~0xFULL;
> - UINT8 BusRange = BrdgConf->SubBus - BrdgConf->PBus - 2;
> -
> - HrConfigs[AR_DS_PORT1].Res = NOT_IN_USE_BRIDGE;
> - HrConfigs[AR_DS_PORT1].Res.Cls = DEF_CACHE_LINE_SIZE;
> - HrConfigs[AR_DS_PORT1].Res.Cmd = CMD_BM_MEM;
> - HrConfigs[AR_DS_PORT1].Res.MemBase = MemBase;
> - HrConfigs[AR_DS_PORT1].Res.MemLimit = BrdgConf->Res.MemLimit - 1;
> - HrConfigs[AR_DS_PORT1].Res.PMemBase64 = PMemBase64;
> - HrConfigs[AR_DS_PORT1].Res.PMemLimit64 =
> BrdgConf->Res.PMemLimit64;
> - HrConfigs[AR_DS_PORT1].SBus = BrdgConf->SBus;
> - HrConfigs[AR_DS_PORT1].SubBus = BrdgConf->SBus + BusRange;
> -
> - BrdgConf->SBus = HrConfigs[AR_DS_PORT1].SubBus + 1;
> -
> - HrConfigs[AR_DS_PORT2].Res = NOT_IN_USE_BRIDGE;
> - HrConfigs[AR_DS_PORT2].Res.Cls = DEF_CACHE_LINE_SIZE;
> - HrConfigs[AR_DS_PORT2].Res.Cmd = CMD_BM_MEM;
> - HrConfigs[AR_DS_PORT2].Res.MemBase = BrdgConf->Res.MemLimit;
> - HrConfigs[AR_DS_PORT2].Res.MemLimit = BrdgConf->Res.MemLimit;
> - HrConfigs[AR_DS_PORT2].SBus = BrdgConf->SBus;
> - HrConfigs[AR_DS_PORT2].SubBus = BrdgConf->SBus;
> -
> - BrdgConf->SBus = HrConfigs[AR_DS_PORT2].SubBus + 1;
> -}//InitARDSPort_1Port
> -
> -STATIC
> -VOID
> -InitARDSPort_2Port(
> - IN OUT BRDG_CONFIG* BrdgConf
> -)
> -{
> - UINT16 MemBase = BrdgConf->Res.MemBase & 0xFFF0;
> - UINT64 PMemBase64 = BrdgConf->Res.PMemBase64 & ~0xFULL;
> - UINT8 BusRange = BrdgConf->SubBus - BrdgConf->PBus - 3;
> -
> - // Busses are split between ports 1 and 4
> - BusRange /= 2;
> -
> - HrConfigs[AR_DS_PORT1].Res = NOT_IN_USE_BRIDGE;
> - HrConfigs[AR_DS_PORT1].Res.Cls = DEF_CACHE_LINE_SIZE;
> - HrConfigs[AR_DS_PORT1].Res.Cmd = CMD_BM_MEM;
> - HrConfigs[AR_DS_PORT1].Res.MemBase = MemBase;
> - HrConfigs[AR_DS_PORT1].Res.MemLimit = MemBase + 0x17F0 - 1;
> - HrConfigs[AR_DS_PORT1].Res.PMemBase64 = PMemBase64;
> - HrConfigs[AR_DS_PORT1].Res.PMemLimit64 = PMemBase64 + 0x2000 - 1;
> - HrConfigs[AR_DS_PORT1].SBus = BrdgConf->SBus;
> - HrConfigs[AR_DS_PORT1].SubBus = BrdgConf->SBus + BusRange;
> -
> - BrdgConf->SBus = HrConfigs[AR_DS_PORT1].SubBus + 1;
> -
> - HrConfigs[AR_DS_PORT2].Res = NOT_IN_USE_BRIDGE;
> - HrConfigs[AR_DS_PORT2].Res.Cls = DEF_CACHE_LINE_SIZE;
> - HrConfigs[AR_DS_PORT2].Res.Cmd = CMD_BM_MEM;
> - HrConfigs[AR_DS_PORT2].Res.MemBase = MemBase + 0x17F0;
> - HrConfigs[AR_DS_PORT2].Res.MemLimit = MemBase + 0x1800 - 1;
> - HrConfigs[AR_DS_PORT2].SBus = BrdgConf->SBus;
> - HrConfigs[AR_DS_PORT2].SubBus = BrdgConf->SBus;
> -
> - BrdgConf->SBus = HrConfigs[AR_DS_PORT2].SubBus + 1;
> -
> -
> - HrConfigs[AR_DS_PORT4].Res = NOT_IN_USE_BRIDGE;
> - HrConfigs[AR_DS_PORT4].Res.Cls = DEF_CACHE_LINE_SIZE;
> - HrConfigs[AR_DS_PORT4].Res.Cmd = CMD_BM_MEM;
> - HrConfigs[AR_DS_PORT4].Res.MemBase = MemBase + 0x1800;
> - HrConfigs[AR_DS_PORT4].Res.MemLimit = BrdgConf->Res.MemLimit;
> - HrConfigs[AR_DS_PORT4].Res.PMemBase64 = PMemBase64 + 0x2000;
> - HrConfigs[AR_DS_PORT4].Res.PMemLimit64 =
> BrdgConf->Res.PMemLimit64;
> - HrConfigs[AR_DS_PORT4].SBus = BrdgConf->SBus;
> - HrConfigs[AR_DS_PORT4].SubBus = BrdgConf->SubBus;
> -
> - BrdgConf->SBus = HrConfigs[AR_DS_PORT4].SubBus + 1;
> -}//InitARDSPort_2Port
> -
> -
> -STATIC
> -BOOLEAN
> -CheckLimits (
> - IN BOOLEAN Is2PortDev,
> - IN BRDG_RES_CONFIG *HrResConf,
> - IN UINT8 BusRange
> - )
> -{
> - UINT16 MemBase;
> - UINT16 MemLimit;
> - UINT64 PMemBase64;
> - UINT64 PMemLimit64;
> -
> - MemBase = HrResConf->MemBase & 0xFFF0;
> - MemLimit = HrResConf->MemLimit & 0xFFF0;
> - PMemBase64 = HrResConf->PMemBase64 & 0xFFF0;
> - PMemLimit64 = HrResConf->PMemLimit64 & 0xFFF0;
> - //
> - // Check memoty alignment
> - //
> - if (MemBase & 0x3FF) {
> - DEBUG((DEBUG_INFO, "M alig\n"));
> - return FALSE;
> - }
> -
> - if (PMemBase64 & 0xFFF) {
> - DEBUG((DEBUG_INFO, "PM alig\n"));
> - return FALSE;
> - }
> -
> - if (Is2PortDev) {
> - //
> - // Check mem size
> - //
> - if (MemLimit + 0x10 - MemBase < 0x2E00) {
> - DEBUG((DEBUG_INFO, "M size\n"));
> - return FALSE;
> - }
> - //
> - // Check P-mem size
> - //
> - if (PMemLimit64 + 0x10 - PMemBase64 < 0x4A00) {
> - DEBUG((DEBUG_INFO, "PM size\n"));
> - return FALSE;
> - }
> - //
> - // Check bus range
> - //
> - if (BusRange < 106) {
> - DEBUG((DEBUG_INFO, "Bus range\n"));
> - return FALSE;
> - }
> - } else {
> - //
> - // Check mem size
> - //
> - if (MemLimit + 0x10 - MemBase < 0x1600) {
> - DEBUG((DEBUG_INFO, "M size\n"));
> - return FALSE;
> - }
> - //
> - // Check P-mem size
> - //
> - if (PMemLimit64 + 0x10 - PMemBase64 < 0x2200) {
> - DEBUG((DEBUG_INFO, "PM size\n"));
> - return FALSE;
> - }
> - //
> - // Check bus range
> - //
> - if (BusRange < 56) {
> - DEBUG((DEBUG_INFO, "Bus range\n"));
> - return FALSE;
> - }
> - }
> -
> - return TRUE;
> -} // CheckLimits
> -
> -STATIC
> -BOOLEAN
> -InitHRResConfigs (
> - IN OUT HR_CONFIG *Hr_Config,
> - IN UINT8 BusNumLimit,
> - IN OUT BRDG_RES_CONFIG*HrResConf
> - )
> -{
> - BRDG_CONFIG BrdgConf = { { 0 } };
> -
> - InitCommonHRConfigs (Hr_Config, BusNumLimit, HrResConf);
> - BrdgConf.PBus = Hr_Config->HRBus + 2;// Take into account busses
> - BrdgConf.SBus = Hr_Config->HRBus + 3;// for US and DS of HIA
> - BrdgConf.SubBus = BusNumLimit;
> - BrdgConf.Res = *HrResConf;
> - while (TRUE) {
> - switch (Hr_Config->DeviceId) {
> - case AR_HR_4C:
> - case TR_HR_4C:
> - case AR_HR_C0_4C:
> - //
> - // 2 Port host
> - //
> - if (CheckLimits (TRUE, HrResConf, BusNumLimit - Hr_Config->HRBus))
> {
> -
> -
> - InitARDSPort_2Port(&BrdgConf);
> - DEBUG((DEBUG_INFO, "AR2\n"));
> -
> - return TRUE;
> - } else {
> - return FALSE;
> - }
> - // AR only
> - case AR_HR_2C: // 1 port host
> - case AR_HR_C0_2C:
> - case AR_HR_LP:
> - case TR_HR_2C:
> - DEBUG((DEBUG_INFO, "AR1\n"));
> - InitARDSPort_1Port(&BrdgConf);
> - return TRUE;
> -
> - default:
> - InitHRDSPort_Disable (HR_DS_PORT3, &BrdgConf);
> - InitHRDSPort_Disable (HR_DS_PORT4, &BrdgConf);
> - InitHRDSPort_Disable (HR_DS_PORT5, &BrdgConf);
> - InitHRDSPort_Disable (HR_DS_PORT6, &BrdgConf);
> - return FALSE;
> - }
> - }
> -} // InitHRResConfigs
> -
> -STATIC
> -BOOLEAN
> -InitializeHostRouter (
> - OUT HR_CONFIG *Hr_Config,
> - IN UINTN RpSegment,
> - IN UINTN RpBus,
> - IN UINTN RpDevice,
> - IN UINTN RpFunction
> - )
> -{
> - UINT8 BusNumLimit;
> - BRDG_RES_CONFIG HrResConf = { 0 };
> - UINT8 i;
> - BOOLEAN Ret;
> -
> - Ret = TRUE;
> -
> - gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (RpSegment,
> RpBus, RpDevice, RpFunction, 0);
> - Hr_Config->HRBus = PciSegmentRead8 (gDeviceBaseAddress +
> PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
> - gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (RpSegment,
> Hr_Config->HRBus, 0x00, 0x00, 0);
> - Hr_Config->DeviceId = PciSegmentRead16 (gDeviceBaseAddress +
> PCI_DEVICE_ID_OFFSET);
> - if (!(IsTbtHostRouter (Hr_Config->DeviceId))) {
> - return FALSE;
> - }
> - TbtSegment = (UINT8)RpSegment;
> -
> - HrResConf.Cmd = CMD_BM_MEM;
> - HrResConf.Cls = DEF_CACHE_LINE_SIZE;
> - gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (RpSegment,
> RpBus, RpDevice, RpFunction, 0);
> - HrResConf.IoBase = PciSegmentRead8 (gDeviceBaseAddress +
> OFFSET_OF (PCI_TYPE01, Bridge.IoBase));
> - HrResConf.IoLimit = PciSegmentRead8 (gDeviceBaseAddress +
> OFFSET_OF (PCI_TYPE01, Bridge.IoLimit));
> - HrResConf.MemBase = PciSegmentRead16 (gDeviceBaseAddress +
> OFFSET_OF (PCI_TYPE01, Bridge.MemoryBase));
> - HrResConf.MemLimit = PciSegmentRead16 (gDeviceBaseAddress +
> OFFSET_OF (PCI_TYPE01, Bridge.MemoryLimit));
> - HrResConf.PMemBase64 = PciSegmentRead16 (gDeviceBaseAddress +
> OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableMemoryBase));
> - HrResConf.PMemLimit64 = PciSegmentRead16 (gDeviceBaseAddress +
> OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableMemoryLimit));
> - HrResConf.PMemBase64 |= (UINT64)(PciSegmentRead32
> (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.PrefetchableBaseUpper32))) << 16;
> - HrResConf.PMemLimit64 |= (UINT64)(PciSegmentRead32
> (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.PrefetchableLimitUpper32))) << 16;
> - BusNumLimit = PciSegmentRead8 (gDeviceBaseAddress +
> PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);
> -
> - Ret = InitHRResConfigs (Hr_Config, BusNumLimit, &HrResConf);
> -
> - for (i = 0; i < Hr_Config->BridgeLoops; ++i) {
> - UINT8 Bus;
> - UINT8 Dev;
> - UINT8 Fun;
> - Bus = HrConfigs[i].DevId.Bus;
> - Dev = HrConfigs[i].DevId.Dev;
> - Fun = HrConfigs[i].DevId.Fun;
> - gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus,
> Dev, Fun, 0);
> -
> - PciSegmentWrite8 (gDeviceBaseAddress + PCI_CACHELINE_SIZE_OFFSET,
> HrConfigs[i].Res.Cls);
> - PciSegmentWrite8 (gDeviceBaseAddress +
> PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET, HrConfigs[i].PBus);
> - PciSegmentWrite8 (gDeviceBaseAddress +
> PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET, HrConfigs[i].SBus);
> - PciSegmentWrite8 (gDeviceBaseAddress +
> PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET, HrConfigs[i].SubBus);
> - PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.MemoryBase), HrConfigs[i].Res.MemBase);
> - PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.MemoryLimit), HrConfigs[i].Res.MemLimit);
> - PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.PrefetchableMemoryBase), (UINT16) (HrConfigs[i].Res.PMemBase64 &
> 0xFFFF));
> - PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.PrefetchableMemoryLimit), (UINT16) (HrConfigs[i].Res.PMemLimit64 &
> 0xFFFF));
> - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.PrefetchableBaseUpper32), (UINT32) (HrConfigs[i].Res.PMemBase64
> >> 16));
> - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.PrefetchableLimitUpper32), (UINT32) (HrConfigs[i].Res.PMemLimit64
> >> 16));
> - PciSegmentWrite8 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.IoBase), HrConfigs[i].Res.IoBase);
> - PciSegmentWrite8 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.IoLimit), HrConfigs[i].Res.IoLimit);
> - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.IoBaseUpper16), 0x00000000);
> - PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET,
> HrConfigs[i].Res.Cmd);
> - }
> - if (Hr_Config->DeviceId == AR_HR_2C || Hr_Config->DeviceId ==
> AR_HR_4C || Hr_Config->DeviceId == AR_HR_LP) {
> - for (i = 0; i < Hr_Config->BridgeLoops; ++i) {
> - if(HrConfigs[i].IsDSBridge) {
> - UnsetVesc(HrConfigs[i].DevId.Bus, HrConfigs[i].DevId.Dev,
> HrConfigs[i].DevId.Fun);
> - }
> - }
> - }
> -
> - gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS
> (TbtSegment,(Hr_Config->HRBus + 2), 0x00, 0x00, 0);
> - PciSegmentWrite32 (gDeviceBaseAddress +
> PCI_BASE_ADDRESSREG_OFFSET + (PCI_BAR_IDX0 * 4),
> HrConfigs[HR_DS_PORT0].Res.MemLimit << 16);
> - PciSegmentWrite32 (gDeviceBaseAddress +
> PCI_BASE_ADDRESSREG_OFFSET + (PCI_BAR_IDX1 * 4),
> (HrConfigs[HR_DS_PORT0].Res.MemLimit + 0x4) << 16);
> - PciSegmentWrite8 (gDeviceBaseAddress + PCI_CACHELINE_SIZE_OFFSET,
> DEF_CACHE_LINE_SIZE);
> - PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET,
> CMD_BM_MEM);
> - return Ret;
> -} // InitializeHostRouter
> -STATIC
> -UINT8
> -ConfigureSlot (
> - IN UINT8 Bus,
> - IN UINT8 MAX_DEVICE,
> - IN INT8 Depth,
> - IN BOOLEAN ArPcie,
> - IN OUT PORT_INFO *PortInfo
> - )
> -{
> - UINT8 Device;
> - UINT8 SBus;
> - UINT8 UsedBusNumbers;
> - UINT8 RetBusNum;
> - PORT_INFO CurrentSlot;
> -
> - RetBusNum = 0;
> -
> - for (Device = 0; Device < MAX_DEVICE; Device++) {
> - //
> - // Continue if device is absent
> - //
> - gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus,
> Device, 0x00, 0);
> - if (0xFFFF == PciSegmentRead16 (gDeviceBaseAddress +
> PCI_DEVICE_ID_OFFSET)) {
> - continue;
> -
> - }
> -
> - if (P2P_BRIDGE != PciSegmentRead16 (gDeviceBaseAddress +
> (PCI_CLASSCODE_OFFSET + 1))) {
> - SetDevResources (
> - Bus,
> - Device,
> - PCI_MAX_FUNC,
> - PCI_BASE_ADDRESSREG_OFFSET + (PCI_BAR_IDX5 * 4),
> - PortInfo
> - );
> - continue;
> - }
> - //
> - // Else Bridge
> - //
> - CopyMem (&CurrentSlot, PortInfo, sizeof (PORT_INFO));
> -
> - ++RetBusNum; // UP Bridge
> - SBus = Bus + RetBusNum; // DS Bridge
> -
> - if (SBus + 1 >= PortInfo->BusNumLimit) {
> - continue;
> -
> - }
> -
> - SetDevResources (Bus, Device, 1, PCI_BASE_ADDRESSREG_OFFSET +
> (PCI_BAR_IDX1 * 4), PortInfo);
> -
> - //
> - // Init UP Bridge to reach DS Bridge
> - //
> - PciSegmentWrite8 (gDeviceBaseAddress +
> PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET, Bus);
> - PciSegmentWrite8 (gDeviceBaseAddress +
> PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET, SBus);
> - PciSegmentWrite8 (gDeviceBaseAddress +
> PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET, PortInfo->BusNumLimit);
> - PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET,
> CMD_BM_MEM);
> -
> - if(ArPcie) {
> - UnsetVesc(Bus, Device, 0x00);
> - }
> -
> - UsedBusNumbers = ConfigureSlot(SBus, PCI_MAX_DEVICE + 1, -1, FALSE,
> PortInfo);
> - RetBusNum += UsedBusNumbers;
> -
> - SetPhyPortResources (
> - Bus,
> - Device,
> - SBus + UsedBusNumbers,
> - Depth,
> - &CurrentSlot,
> - PortInfo
> - );
> - }
> - //
> - // for (Device = 0; Device <= PCI_MAX_DEVICE; Device++)
> - //
> - return RetBusNum;
> -} // ConfigureSlot
> -
> -STATIC
> -VOID
> -SetCioPortResources (
> - IN UINT8 Bus,
> - IN UINT8 Dev,
> - IN UINT8 SBus,
> - IN UINT8 SubBus,
> - IN PORT_INFO *portInfoBeforeChange,
> - IN OUT PORT_INFO *PortInfo
> - )
> -{
> - UINT8 Cmd;
> - Cmd = CMD_BUS_MASTER;
> -
> - gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Dev,
> 0x00, 0);
> - PciSegmentWrite8 (gDeviceBaseAddress +
> PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET, Bus);
> - PciSegmentWrite8 (gDeviceBaseAddress +
> PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET, SBus);
> - PciSegmentWrite8 (gDeviceBaseAddress +
> PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET, SubBus);
> - PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, Cmd);
> -
> - if (PortInfo->IoBase <= PortInfo->IoLimit) {
> - PciSegmentWrite8 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.IoBase), PortInfo->IoBase);
> - PciSegmentWrite8 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.IoLimit), PortInfo->IoLimit);
> - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.IoBaseUpper16), 0x00000000);
> - Cmd |= CMD_BM_IO;
> - } else {
> - PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.IoBase), DISBL_IO_REG1C);
> - }
> -
> - if (PortInfo->MemBase <= PortInfo->MemLimit) {
> - PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.MemoryBase), PortInfo->MemBase);
> - PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.MemoryLimit), PortInfo->MemLimit);
> - Cmd |= CMD_BM_MEM;
> - } else {
> - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.MemoryBase), DISBL_MEM32_REG20);
> - }
> -
> - if (PortInfo->PMemBase64 <= PortInfo->PMemLimit64) {
> - PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.PrefetchableMemoryBase), (UINT16) (PortInfo->PMemBase64 &
> 0xFFFF));
> - PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.PrefetchableMemoryLimit), (UINT16) (PortInfo->PMemLimit64 &
> 0xFFFF));
> - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.PrefetchableBaseUpper32), (UINT32) (PortInfo->PMemBase64 >> 16));
> - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.PrefetchableLimitUpper32), (UINT32) (PortInfo->PMemLimit64 >> 16));
> - Cmd |= CMD_BM_MEM;
> - } else {
> - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.PrefetchableMemoryBase), DISBL_PMEM_REG24);
> - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.PrefetchableBaseUpper32), 0);
> - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.PrefetchableLimitUpper32), 0);
> - }
> -
> - PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, Cmd);
> - PciSegmentWrite8 (gDeviceBaseAddress + PCI_CACHELINE_SIZE_OFFSET,
> DEF_CACHE_LINE_SIZE);
> -} // SetCioPortResources
> -
> -STATIC
> -VOID
> -SetSlotsAsUnused (
> - IN UINT8 Bus,
> - IN UINT8 MaxSlotNum,
> - IN UINT8 CioSlot,
> - IN OUT PORT_INFO *PortInfo
> - )
> -{
> - UINT8 Slot;
> - for (Slot = MaxSlotNum; Slot > CioSlot; --Slot) {
> - gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus,
> Slot, 0x00, 0);
> - if (0xFFFF == PciSegmentRead16 (gDeviceBaseAddress +
> PCI_DEVICE_ID_OFFSET)) {
> - continue;
> - }
> -
> - PciSegmentWrite8 (gDeviceBaseAddress + PCI_CACHELINE_SIZE_OFFSET,
> DEF_CACHE_LINE_SIZE);
> - PciSegmentWrite8 (gDeviceBaseAddress +
> PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET, Bus);
> - PciSegmentWrite8 (gDeviceBaseAddress +
> PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET, PortInfo->BusNumLimit);
> - PciSegmentWrite8 (gDeviceBaseAddress +
> PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET, PortInfo->BusNumLimit);
> - PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.IoBase), DISBL_IO_REG1C);
> - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.MemoryBase), DISBL_MEM32_REG20);
> - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.PrefetchableMemoryBase), DISBL_PMEM_REG24);
> - PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET,
> CMD_BUS_MASTER);
> - PortInfo->BusNumLimit--;
> - }
> -} // SetSlotsAsUnused
> -
> -STATIC
> -UINT16
> -FindVendorSpecificHeader(
> - IN UINT8 Bus
> -)
> -{
> - PCI_EXP_EXT_HDR *ExtHdr;
> - UINT32 ExtHdrValue;
> - UINT16 ExtendedRegister;
> -
> - ExtHdr = (PCI_EXP_EXT_HDR*) &ExtHdrValue;
> - ExtendedRegister = 0x100;
> - gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus,
> 0x00, 0x00, 0);
> - while (ExtendedRegister) {
> - ExtHdrValue = PciSegmentRead32 (gDeviceBaseAddress +
> ExtendedRegister);
> - if (ExtHdr->CapabilityId == 0xFFFF) {
> - return 0x0000; // No Vendor-Specific Extended Capability header
> - }
> -
> - if (PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID ==
> ExtHdr->CapabilityId) {
> - return ExtendedRegister;
> - }
> -
> - ExtendedRegister = (UINT16) ExtHdr->NextCapabilityOffset;
> - }
> - return 0x0000; // No Vendor-Specific Extended Capability header
> -}
> -
> -STATIC
> -UINT8
> -FindSsid_SsvidHeader (
> - IN UINT8 Bus
> - )
> -{
> - UINT8 CapHeaderId;
> - UINT8 CapHeaderOffset;
> - gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus,
> 0x00, 0x00, 0);
> - CapHeaderOffset = PciSegmentRead8 (gDeviceBaseAddress +
> PCI_CAPBILITY_POINTER_OFFSET);
> -
> - while (CapHeaderOffset != 0) {
> - CapHeaderId = PciSegmentRead8 (gDeviceBaseAddress +
> CapHeaderOffset);
> -
> - if (CapHeaderId == PCIE_CAP_ID_SSID_SSVID) {
> - return CapHeaderOffset;
> - }
> -
> - CapHeaderOffset = PciSegmentRead8 (gDeviceBaseAddress +
> CapHeaderOffset + 1);
> - }
> -
> - DEBUG((DEBUG_INFO, "SID0\n"));
> - return 0;
> -} // FindSsid_SsvidHeader
> -
> -STATIC
> -BOOLEAN
> -GetCioSlotByDevId (
> - IN UINT8 Bus,
> - OUT UINT8 *CioSlot,
> - OUT UINT8 *MaxSlotNum,
> - OUT BOOLEAN *ArPcie
> - )
> -{
> - UINT16 VSECRegister;
> - BRDG_CIO_MAP_REG BridgMap;
> - UINT32 BitScanRes;
> - UINT16 DevId;
> - gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus,
> 0x00, 0x00, 0);
> - DevId = PciSegmentRead16 (gDeviceBaseAddress +
> PCI_DEVICE_ID_OFFSET);
> -
> - //
> - // Init out params in case device is not recognised
> - //
> - *CioSlot = 4;
> - *MaxSlotNum = 7;
> - *ArPcie = FALSE;
> -
> - switch (DevId) {
> - //
> - // For known device IDs
> - //
> - case 0x1578:
> - *ArPcie = TRUE;
> - }
> -
> - switch (DevId) {
> - //
> - // For known device IDs
> - //
> - case 0x1513:
> - case 0x151A:
> - case 0x151B:
> - case 0x1547:
> - case 0x1548:
> - return TRUE; // Just return
> - case 0x1549:
> - return FALSE; // Just return
> - }
> -
> - VSECRegister = FindVendorSpecificHeader(Bus);
> - if (!VSECRegister) {
> - return TRUE; // Just return
> - }
> - //
> - // Go to Bridge/CIO map register
> - //
> - VSECRegister += 0x18;
> - BridgMap.AB_REG = PciSegmentRead32(gDeviceBaseAddress +
> VSECRegister);
> - //
> - // Check for range
> - //
> - if (BridgMap.Bits.NumOfDSPorts < 1 || BridgMap.Bits.NumOfDSPorts > 27)
> {
> - return TRUE;
> - //
> - // Not a valid register
> - //
> - }
> - //
> - // Set OUT params
> - //
> - *MaxSlotNum = (UINT8) BridgMap.Bits.NumOfDSPorts;
> -
> -#ifdef _MSC_VER
> - if(!_BitScanForward(&BitScanRes, BridgMap.Bits.CioPortMap)) { // No DS
> bridge which is CIO port
> - return FALSE;
> - }
> -#else
> -#ifdef __GNUC__
> - if (BridgMap.Bits.CioPortMap == 0) {
> - return FALSE;
> - }
> - BitScanRes = __builtin_ctz (BridgMap.Bits.CioPortMap);
> -#else
> -#error Unsupported Compiler
> -#endif
> -#endif
> -
> - *CioSlot = (UINT8)BitScanRes;
> - return TRUE;
> -} // GetCioSlotByDevId
> -
> -#define TBT_LEGACY_SUB_SYS_ID 0x11112222
> -
> -STATIC
> -BOOLEAN
> -IsLegacyDevice (
> - IN UINT8 Bus
> - )
> -{
> - UINT32 Sid;
> - UINT8 SidRegister;
> - UINT16 DevId;
> -
> - gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus,
> 0x00, 0x00, 0);
> - DevId = PciSegmentRead16 (gDeviceBaseAddress +
> PCI_DEVICE_ID_OFFSET);
> - switch (DevId) {
> - //
> - // For known device IDs
> - //
> - case 0x1513:
> - case 0x151A:
> - case 0x151B:
> - DEBUG((DEBUG_INFO, "Legacy "));
> - DEBUG((DEBUG_INFO, "DevId = %d\n",DevId));
> - return TRUE;
> - //
> - // Legacy device by Device Id
> - //
> - }
> -
> - SidRegister = FindSsid_SsvidHeader(Bus);
> -
> - if (!SidRegister) {
> - return TRUE; // May be absent for legacy devices
> - }
> - //
> - // Go to register
> - //
> - SidRegister += 0x4;
> - Sid = PciSegmentRead32(gDeviceBaseAddress + SidRegister);
> - DEBUG((DEBUG_INFO, "SID"));
> - DEBUG((DEBUG_INFO, " = %d\n", Sid));
> -
> -return TBT_LEGACY_SUB_SYS_ID == Sid || 0 == Sid;
> -} // IsLegacyDevice
> -
> -STATIC
> -VOID
> -UnsetVescEp(
> - IN UINT8 Bus,
> - IN UINT8 MaxSlotNum
> - )
> -{
> - UINT8 i;
> -
> - for (i = 0; i <= MaxSlotNum; ++i)
> - {
> - UnsetVesc(Bus, i, 0);
> - }
> -}// Unset_VESC_REG2_EP
> -
> -STATIC
> -BOOLEAN
> -ConfigureEP (
> - IN INT8 Depth,
> - IN OUT UINT8 *Bus,
> - IN OUT PORT_INFO *PortInfo
> - )
> -{
> - UINT8 SBus;
> - UINT8 CioSlot;
> - UINT8 MaxSlotNum;
> - BOOLEAN ArPcie;
> - UINT8 MaxPHYSlots;
> - UINT8 UsedBusNumbers;
> - UINT8 cmd;
> - BOOLEAN CioSlotPresent;
> - BOOLEAN Continue;
> - PORT_INFO PortInfoOrg;
> - UINT8 CioBus;
> -
> - CioSlot = 4;
> - MaxSlotNum = 7;
> - CopyMem (&PortInfoOrg, PortInfo, sizeof (PORT_INFO));
> -
> - gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, *Bus,
> 0x00, 0x00, 0);
> - cmd = PciSegmentRead8 (gDeviceBaseAddress +
> PCI_COMMAND_OFFSET);
> - // AR ONLY
> - // Endpoint on CIO slot, but not a bridge device
> - if (P2P_BRIDGE != PciSegmentRead16 (gDeviceBaseAddress +
> (PCI_CLASSCODE_OFFSET + 1))) {
> - DEBUG((DEBUG_INFO, "UEP\n"));
> - // Check whether EP already configured by examining CMD register
> - if(cmd & CMD_BUS_MASTER) // Yes, no need to touch this EP
> - {
> - DEBUG((DEBUG_INFO, "BMF\n"));
> - return FALSE;
> - }
> - // Configure it as regular PCIe device
> - ConfigureSlot(*Bus, PCI_MAX_DEVICE + 1, -1, FALSE, PortInfo);
> -
> - return FALSE;
> - }
> -
> - //
> - // Based on Device ID assign Cio slot and max number of PHY slots to
> scan
> - //
> - CioSlotPresent = GetCioSlotByDevId(*Bus, &CioSlot, &MaxSlotNum,
> &ArPcie);
> - MaxPHYSlots = MaxSlotNum;
> - //
> - // Check whether EP already configured by examining CMD register
> - //
> -
> - if (cmd & CMD_BUS_MASTER) {
> - //
> - // Yes no need to touch this EP, just move to next one in chain
> - //
> - CioBus = *Bus + 1;
> - if(ArPcie){
> - UnsetVescEp(CioBus, MaxSlotNum);
> - }
> - if (!CioSlotPresent) {
> - //
> - // Cio slot is not present in EP, just return FALSE
> - //
> - DEBUG((DEBUG_INFO, "BMF\n"));
> - return FALSE;
> - }
> - //
> - // Take all resources from Cio slot and return
> - //
> - gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS
> (TbtSegment,CioBus, CioSlot, 0x00, 0);
> - PortInfo->BusNumLimit = PciSegmentRead8 (gDeviceBaseAddress +
> PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);
> - PortInfo->IoBase = PciSegmentRead8 (gDeviceBaseAddress +
> OFFSET_OF (PCI_TYPE01, Bridge.IoBase));
> - PortInfo->IoLimit = PciSegmentRead8 (gDeviceBaseAddress +
> OFFSET_OF (PCI_TYPE01, Bridge.IoLimit));
> - PortInfo->MemBase = PciSegmentRead16 (gDeviceBaseAddress
> + OFFSET_OF (PCI_TYPE01, Bridge.MemoryBase));
> - PortInfo->MemLimit = PciSegmentRead16 (gDeviceBaseAddress +
> OFFSET_OF (PCI_TYPE01, Bridge.MemoryLimit));
> - PortInfo->PMemBase64 = PciSegmentRead16 (gDeviceBaseAddress
> + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableMemoryBase)) & 0xFFF0;
> - PortInfo->PMemLimit64 = PciSegmentRead16 (gDeviceBaseAddress +
> OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableMemoryLimit)) & 0xFFF0;
> - PortInfo->PMemBase64 |= (UINT64)(PciSegmentRead32
> (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.PrefetchableBaseUpper32))) << 16;
> - PortInfo->PMemLimit64 |= (UINT64)(PciSegmentRead32
> (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.PrefetchableLimitUpper32))) << 16;
> - PortInfo->PMemLimit64 |= 0xF;
> - //
> - // Jump to next EP
> - //
> - *Bus = PciSegmentRead8 (gDeviceBaseAddress +
> PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
> - //
> - // Should we continue?
> - //
> - gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,*Bus,
> 0x00, 0x00, 0);
> - Continue = 0xFFFF != PciSegmentRead16
> (gDeviceBaseAddress + PCI_DEVICE_ID_OFFSET);
> - return Continue;
> - }
> - //
> - // Set is legacy dvice
> - //
> - isLegacyDevice = IsLegacyDevice (*Bus);
> -
> - SetCioPortResources (
> - *Bus,
> - 0, // Assign all available resources to US port of EP
> - *Bus + 1,
> - PortInfo->BusNumLimit,
> - 0,
> - PortInfo
> - );
> -
> - SBus = *Bus + 1;// Jump to DS port
> -
> - if (CioSlotPresent) {
> - MaxPHYSlots = CioSlot;
> - }
> -
> - UsedBusNumbers = ConfigureSlot(SBus, MaxPHYSlots, Depth, ArPcie,
> PortInfo);
> - if (!CioSlotPresent) {
> - return FALSE;
> - //
> - // Stop resource assignment on this chain
> - //
> - }
> - //
> - // Set rest of slots us unused
> - //
> - SetSlotsAsUnused (SBus, MaxSlotNum, CioSlot, PortInfo);
> -
> - SetCioPortResources (
> - SBus,
> - CioSlot,
> - SBus + UsedBusNumbers + 1,
> - PortInfo->BusNumLimit,
> - &PortInfoOrg,
> - PortInfo
> - );
> - *Bus = SBus + UsedBusNumbers + 1;// Go to next EP
> - if(ArPcie) {
> - UnsetVesc(SBus, CioSlot, 0x00);
> - }
> - if (*Bus > PortInfo->BusNumLimit - 2) {
> - //
> - // In case of bus numbers are exhausted stop enumeration
> - //
> - return FALSE;
> - }
> - //
> - // Check whether we should continue on this chain
> - //
> - gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,*Bus,
> 0x00, 0x00, 0);
> - Continue = 0xFFFF != PciSegmentRead16 (gDeviceBaseAddress
> + PCI_DEVICE_ID_OFFSET);
> - return Continue;
> -} // ConfigureEP
> -
> -STATIC
> -VOID
> -GetPortResources (
> - IN UINT8 Bus,
> - IN UINT8 Dev,
> - IN UINT8 Fun,
> - IN OUT PORT_INFO *PortInfo
> - )
> -{
> - gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Dev,
> Fun, 0);
> - PortInfo->BusNumLimit = PciSegmentRead8 (gDeviceBaseAddress +
> PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);
> - PortInfo->IoBase = PciSegmentRead8 (gDeviceBaseAddress +
> OFFSET_OF (PCI_TYPE01, Bridge.IoBase)) & 0xF0;
> - PortInfo->IoLimit = PciSegmentRead8 (gDeviceBaseAddress +
> OFFSET_OF (PCI_TYPE01, Bridge.IoLimit)) & 0xF0;
> - PortInfo->MemBase = PciSegmentRead16 (gDeviceBaseAddress +
> OFFSET_OF (PCI_TYPE01, Bridge.MemoryBase)) & 0xFFF0;
> - PortInfo->MemLimit = PciSegmentRead16 (gDeviceBaseAddress +
> OFFSET_OF (PCI_TYPE01, Bridge.MemoryLimit)) & 0xFFF0;
> - PortInfo->PMemBase64 = PciSegmentRead16 (gDeviceBaseAddress +
> OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableMemoryBase)) & 0xFFF0;
> - PortInfo->PMemLimit64 = PciSegmentRead16 (gDeviceBaseAddress +
> OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableMemoryLimit)) & 0xFFF0;
> - PortInfo->PMemBase64 |= (UINT64)(PciSegmentRead32
> (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.PrefetchableBaseUpper32))) << 16;
> - PortInfo->PMemLimit64 |= (UINT64)(PciSegmentRead32
> (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01,
> Bridge.PrefetchableLimitUpper32))) << 16;
> - PortInfo->IoLimit |= 0xF;
> - PortInfo->MemLimit |= 0xF;
> - PortInfo->PMemLimit64 |= 0xF;
> -} // GetPortResources
> -
> -STATIC
> -VOID
> -ConfigurePort (
> - IN UINT8 Bus,
> - IN UINT8 Dev,
> - IN UINT8 Fun,
> - IN OUT PORT_INFO *PortInfo
> - )
> -{
> - INT8 i;
> - UINT8 USBusNum;
> - gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Dev,
> Fun, 0);
> - USBusNum = PciSegmentRead8 (gDeviceBaseAddress +
> PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
> - gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,
> USBusNum, 0x00, 0x00, 0);
> - if (0xFFFF == PciSegmentRead16 (gDeviceBaseAddress +
> PCI_DEVICE_ID_OFFSET)) {
> - //
> - // Nothing to do if TBT device is not connected
> - //
> - return ;
> - }
> -
> - GetPortResources(Bus, Dev, Fun, PortInfo);// Take reserved resources
> from DS port
> - //
> - // Assign resources to EPs
> - //
> - for (i = 0; i < MAX_TBT_DEPTH; ++i) {
> - PortInfo->ConfedEP++;
> - if (!ConfigureEP (i, &USBusNum, PortInfo)) {
> - return ;
> - }
> - }
> -} // ConfigurePort
> -
> -VOID
> -ThunderboltCallback (
> - IN UINT8 Type
> - )
> -{
> - PORT_INFO PortInfoOrg = { 0 };
> - HR_CONFIG HrConfig = { 0 };
> - UINT8 i;
> - UINTN Segment = 0;
> - UINTN Bus = 0;
> - UINTN Device;
> - UINTN Function;
> -
> - DEBUG((DEBUG_INFO, "ThunderboltCallback.Entry\n"));
> -
> - DEBUG((DEBUG_INFO, "PortInfo Initialization\n"));
> - PortInfoInit (&PortInfoOrg);
> - if(Type == DTBT_CONTROLLER) {
> - if (gCurrentDiscreteTbtRootPort == 0) {
> - DEBUG((DEBUG_ERROR, "Invalid RP Input\n"));
> - return;
> - }
> - GetDTbtRpDevFun(gCurrentDiscreteTbtRootPortType,
> gCurrentDiscreteTbtRootPort - 1, &Device, &Function);
> - DEBUG((DEBUG_INFO, "InitializeHostRouter. \n"));
> - if (!InitializeHostRouter (&HrConfig, Segment, Bus, Device, Function)) {
> - return ;
> - }
> - //
> - // Configure DS ports
> - //
> - for (i = HrConfig.MinDSNumber; i <= HrConfig.MaxDSNumber; ++i) {
> - DEBUG((DEBUG_INFO, "ConfigurePort. \n"));
> - ConfigurePort (HrConfig.HRBus + 1, i,0, &PortInfoOrg);
> - }
> -
> - DEBUG((DEBUG_INFO, "EndOfThunderboltCallback.\n"));
> - EndOfThunderboltCallback (Segment, Bus, Device, Function);
> -
> - }
> - DEBUG((DEBUG_INFO, "ThunderboltCallback.Exit\n"));
> -} // ThunderboltCallback
> -
> -VOID
> -DisablePCIDevicesAndBridges (
> - IN UINT8 MinBus,
> - IN UINT8 MaxBus
> - )
> -{
> - UINT8 Bus;
> - UINT8 Dev;
> - UINT8 Fun;
> - UINT8 RegVal;
> - //
> - // Disable PCI device First, and then Disable PCI Bridge
> - //
> - for (Bus = MaxBus; Bus > MinBus; --Bus) {
> - for (Dev = 0; Dev <= PCI_MAX_DEVICE; ++Dev) {
> - for (Fun = 0; Fun <= PCI_MAX_FUNC; ++Fun) {
> - gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS
> (TbtSegment,Bus, Dev, Fun, 0);
> - if (INVALID_PCI_DEVICE == PciSegmentRead32
> (gDeviceBaseAddress + PCI_VENDOR_ID_OFFSET)) {
> - if (Fun == 0) {
> - break;
> -
> - }
> -
> - continue;
> - }
> -
> - RegVal = PciSegmentRead8 (gDeviceBaseAddress +
> PCI_HEADER_TYPE_OFFSET);
> - if (HEADER_TYPE_DEVICE == (RegVal & 1)) {
> - //
> - // ******** Disable PCI Device ********
> - // BIT0 I/O Space Enabled BIT1 Memory Space Enabled
> - // BIT2 Bus Master Enabled BIT4 Memory Write and
> Invalidation Enable
> - //
> - PciSegmentAnd8 (gDeviceBaseAddress +
> PCI_COMMAND_OFFSET, (UINT8)~(BIT0 | BIT1 | BIT2 | BIT4));
> - PciSegmentWrite32 (gDeviceBaseAddress +
> PCI_BASE_ADDRESSREG_OFFSET + (PCI_BAR_IDX0 * 4), 0);
> - PciSegmentWrite32 (gDeviceBaseAddress +
> PCI_BASE_ADDRESSREG_OFFSET + (PCI_BAR_IDX1 * 4), 0);
> - PciSegmentWrite32 (gDeviceBaseAddress +
> PCI_BASE_ADDRESSREG_OFFSET + (PCI_BAR_IDX2 * 4), 0);
> - PciSegmentWrite32 (gDeviceBaseAddress +
> PCI_BASE_ADDRESSREG_OFFSET + (PCI_BAR_IDX3 * 4), 0);
> - PciSegmentWrite32 (gDeviceBaseAddress +
> PCI_BASE_ADDRESSREG_OFFSET + (PCI_BAR_IDX4 * 4), 0);
> - PciSegmentWrite32 (gDeviceBaseAddress +
> PCI_BASE_ADDRESSREG_OFFSET + (PCI_BAR_IDX5 * 4), 0);
> - }
> - }
> - }
> - }
> - //
> - // now no more PCI dev on another side of PCI Bridge can safty disable
> PCI Bridge
> - //
> - for (Bus = MaxBus; Bus > MinBus; --Bus) {
> - for (Dev = 0; Dev <= PCI_MAX_DEVICE; ++Dev) {
> - for (Fun = 0; Fun <= PCI_MAX_FUNC; ++Fun) {
> - gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS
> (TbtSegment,Bus, Dev, Fun, 0);
> - if (INVALID_PCI_DEVICE == PciSegmentRead32
> (gDeviceBaseAddress + PCI_VENDOR_ID_OFFSET)) {
> - if (Fun == 0) {
> - break;
> - }
> -
> - continue;
> - }
> -
> - RegVal = PciSegmentRead8 (gDeviceBaseAddress +
> PCI_HEADER_TYPE_OFFSET);
> - if (HEADER_TYPE_PCI_TO_PCI_BRIDGE == (RegVal & BIT0)) {
> - PciSegmentAnd8 (gDeviceBaseAddress +
> PCI_COMMAND_OFFSET, (UINT8)~(BIT0 | BIT1 | BIT2 | BIT4));
> - PciSegmentWrite8 (gDeviceBaseAddress +
> PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET, 0);
> - PciSegmentWrite8 (gDeviceBaseAddress +
> PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET, 0);
> - PciSegmentWrite8 (gDeviceBaseAddress +
> PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET, 0);
> - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF
> (PCI_TYPE01, Bridge.PrefetchableBaseUpper32), 0);
> - }
> - } // for ( Fun .. )
> - } // for ( Dev ... )
> - } // for ( Bus ... )
> -} // DisablePCIDevicesAndBridges
> -
> -VOID
> -TbtDisablePCIDevicesAndBridges (
> - IN UINT8 Type
> - )
> -{
> - UINTN Segment = 0;
> - UINTN Bus = 0;
> - UINTN Device;
> - UINTN Function;
> - UINT8 MinBus;
> - UINT8 MaxBus;
> - UINT16 DeviceId;
> -
> - MinBus = 1;
> - if(Type == DTBT_CONTROLLER) {
> - //
> - // for(Dev = 0; Dev < 8; ++Dev)
> - // {
> - // PciOr8(PCI_LIB_ADDRESS(2, Dev, 0,
> PCI_BRIDGE_CONTROL_REGISTER_OFFSET), 0x40);
> - // gBS->Stall(2000); // 2msec
> - // PciAnd8(PCI_LIB_ADDRESS(2, Dev, 0,
> PCI_BRIDGE_CONTROL_REGISTER_OFFSET), 0xBF);
> - // }
> - // gBS->Stall(200 * 1000); // 200 msec
> - //
> - if (gCurrentDiscreteTbtRootPort == 0) {
> - DEBUG((DEBUG_ERROR, "Invalid RP Input\n"));
> - return;
> - }
> - GetDTbtRpDevFun(gCurrentDiscreteTbtRootPortType,
> gCurrentDiscreteTbtRootPort - 1, &Device, &Function);
> - gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (Segment, Bus,
> Device, Function, 0);
> - MinBus = PciSegmentRead8 (gDeviceBaseAddress +
> PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
> - MaxBus = PciSegmentRead8 (gDeviceBaseAddress +
> PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);
> - gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (Segment, MinBus,
> 0x00, 0x00, 0);
> - DeviceId = PciSegmentRead16 (gDeviceBaseAddress +
> PCI_DEVICE_ID_OFFSET);
> - if (!(IsTbtHostRouter (DeviceId))) {
> - return;
> - }
> - TbtSegment = (UINT8)Segment;
> - MinBus++;
> - //
> - // @todo : Move this out when we dont have Loop for ITBT
> - //
> - DisablePCIDevicesAndBridges(MinBus, MaxBus);
> -
> - }
> -} // DisablePCIDevicesAndBridges
> -
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.c
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.c
> deleted file mode 100644
> index 5810447792..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.c
> +++ /dev/null
> @@ -1,1764 +0,0 @@
> -/** @file
> - Thunderbolt initialization in SMM.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -//
> -// Module specific Includes
> -//
> -#include <Library/BaseMemoryLib.h>
> -#include <Library/BaseLib.h>
> -#include <Library/GpioLib.h>
> -#include <TbtBoardInfo.h>
> -#include <Protocol/TbtNvsArea.h>
> -#include <PchAccess.h>
> -#include <Library/BaseLib.h>
> -#include <Library/PciSegmentLib.h>
> -#include <Library/PchInfoLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/SmmServicesTableLib.h>
> -#include <Protocol/SmmSxDispatch2.h>
> -#include <Protocol/SmmSwDispatch2.h>
> -#include <Uefi/UefiSpec.h>
> -#include <Library/UefiLib.h>
> -#include <Library/UefiRuntimeServicesTableLib.h>
> -#include <Library/UefiBootServicesTableLib.h>
> -#include <Library/DebugLib.h>
> -#include <Library/HobLib.h>
> -#include <Guid/HobList.h>
> -#include "TbtSmiHandler.h"
> -#include <PcieRegs.h>
> -#include <Protocol/SaPolicy.h>
> -#include <Protocol/DxeTbtPolicy.h>
> -#include <Library/PchPmcLib.h>
> -#define P2P_BRIDGE (((PCI_CLASS_BRIDGE) << 8) |
> (PCI_CLASS_BRIDGE_P2P))
> -
> -#define CMD_BM_MEM_IO (CMD_BUS_MASTER | BIT1 |
> BIT0)
> -
> -#define DISBL_IO_REG1C 0x01F1
> -#define DISBL_MEM32_REG20 0x0000FFF0
> -#define DISBL_PMEM_REG24 0x0001FFF1
> -
> -#define DOCK_BUSSES 8
> -
> -#define PCI_CAPABILITY_ID_PCIEXP 0x10
> -#define PCI_CAPBILITY_POINTER_OFFSET 0x34
> -
> -#define LTR_MAX_SNOOP_LATENCY_VALUE 0x0846 ///<
> Intel recommended maximum value for Snoop Latency can we put like
> this ?
> -#define LTR_MAX_NON_SNOOP_LATENCY_VALUE 0x0846 ///<
> Intel recommended maximum value for Non-Snoop Latency can we put like
> this ?
> -
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED TBT_NVS_AREA
> *mTbtNvsAreaPtr;
> -GLOBAL_REMOVE_IF_UNREFERENCED UINT8
> gCurrentDiscreteTbtRootPort;
> -GLOBAL_REMOVE_IF_UNREFERENCED UINT8
> gCurrentDiscreteTbtRootPortType;
> -GLOBAL_REMOVE_IF_UNREFERENCED UINT16
> TbtLtrMaxSnoopLatency;
> -GLOBAL_REMOVE_IF_UNREFERENCED UINT16
> TbtLtrMaxNoSnoopLatency;
> -GLOBAL_REMOVE_IF_UNREFERENCED UINT8
> gDTbtPcieRstSupport;
> -GLOBAL_REMOVE_IF_UNREFERENCED TBT_INFO_HOB
> *gTbtInfoHob = NULL;
> -STATIC UINTN
> mPciExpressBaseAddress;
> -STATIC UINT8 TbtSegment = 0;
> -VOID
> -GpioWrite (
> - IN UINT32 GpioNumber,
> - IN BOOLEAN Value
> - )
> -{
> - GpioSetOutputValue (GpioNumber, (UINT32)Value);
> -}
> -
> -/**
> - Search and return the offset of desired Pci Express Capability ID
> - CAPID list:
> - 0x0001 = Advanced Error Reporting Capability
> - 0x0002 = Virtual Channel Capability
> - 0x0003 = Device Serial Number Capability
> - 0x0004 = Power Budgeting Capability
> -
> - @param[in] Bus Pci Bus Number
> - @param[in] Device Pci Device Number
> - @param[in] Function Pci Function Number
> - @param[in] CapId Extended CAPID to search for
> -
> - @retval 0 CAPID not found
> - @retval Other CAPID found, Offset of desired
> CAPID
> -**/
> -UINT16
> -PcieFindExtendedCapId (
> - IN UINT8 Bus,
> - IN UINT8 Device,
> - IN UINT8 Function,
> - IN UINT16 CapId
> - )
> -{
> - UINT16 CapHeaderOffset;
> - UINT16 CapHeaderId;
> - UINT64 DeviceBase;
> -
> - DeviceBase = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Device,
> Function, 0);
> -
> - ///
> - /// Start to search at Offset 0x100
> - /// Get Capability Header, A pointer value of 00h is used to indicate the
> last capability in the list.
> - ///
> - CapHeaderId = 0;
> - CapHeaderOffset = 0x100;
> - while (CapHeaderOffset != 0 && CapHeaderId != 0xFFFF) {
> - CapHeaderId = PciSegmentRead16 (DeviceBase + CapHeaderOffset);
> - if (CapHeaderId == CapId) {
> - return CapHeaderOffset;
> - }
> - ///
> - /// Each capability must be DWORD aligned.
> - /// The bottom two bits of all pointers are reserved and must be
> implemented as 00b
> - /// although software must mask them to allow for future uses of
> these bits.
> - ///
> - CapHeaderOffset = (PciSegmentRead16 (DeviceBase + CapHeaderOffset
> + 2) >> 4) & ((UINT16) ~(BIT0 | BIT1));
> - }
> -
> - return 0;
> -}
> -
> -/**
> - Find the Offset to a given Capabilities ID
> - CAPID list:
> - 0x01 = PCI Power Management Interface
> - 0x04 = Slot Identification
> - 0x05 = MSI Capability
> - 0x10 = PCI Express Capability
> -
> - @param[in] Bus Pci Bus Number
> - @param[in] Device Pci Device Number
> - @param[in] Function Pci Function Number
> - @param[in] CapId CAPID to search for
> -
> - @retval 0 CAPID not found
> - @retval Other CAPID found, Offset of desired
> CAPID
> -**/
> -UINT8
> -PcieFindCapId (
> - IN UINT8 Segment,
> - IN UINT8 Bus,
> - IN UINT8 Device,
> - IN UINT8 Function,
> - IN UINT8 CapId
> - )
> -{
> - UINT8 CapHeaderOffset;
> - UINT8 CapHeaderId;
> - UINT64 DeviceBase;
> -
> - DeviceBase = PCI_SEGMENT_LIB_ADDRESS (Segment, Bus, Device,
> Function, 0);
> -
> - if ((PciSegmentRead8 (DeviceBase + PCI_PRIMARY_STATUS_OFFSET) &
> EFI_PCI_STATUS_CAPABILITY) == 0x00) {
> - ///
> - /// Function has no capability pointer
> - ///
> - return 0;
> - }
> -
> - ///
> - /// Check the header layout to determine the Offset of Capabilities
> Pointer Register
> - ///
> - if ((PciSegmentRead8 (DeviceBase + PCI_HEADER_TYPE_OFFSET) &
> HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE)) {
> - ///
> - /// If CardBus bridge, start at Offset 0x14
> - ///
> - CapHeaderOffset = 0x14;
> - } else {
> - ///
> - /// Otherwise, start at Offset 0x34
> - ///
> - CapHeaderOffset = 0x34;
> - }
> - ///
> - /// Get Capability Header, A pointer value of 00h is used to indicate the
> last capability in the list.
> - ///
> - CapHeaderId = 0;
> - CapHeaderOffset = PciSegmentRead8 (DeviceBase + CapHeaderOffset) &
> ((UINT8) ~(BIT0 | BIT1));
> - while (CapHeaderOffset != 0 && CapHeaderId != 0xFF) {
> - CapHeaderId = PciSegmentRead8 (DeviceBase + CapHeaderOffset);
> - if (CapHeaderId == CapId) {
> - return CapHeaderOffset;
> - }
> - ///
> - /// Each capability must be DWORD aligned.
> - /// The bottom two bits of all pointers (including the initial pointer at
> 34h) are reserved
> - /// and must be implemented as 00b although software must mask
> them to allow for future uses of these bits.
> - ///
> - CapHeaderOffset = PciSegmentRead8 (DeviceBase + CapHeaderOffset +
> 1) & ((UINT8) ~(BIT0 | BIT1));
> - }
> -
> - return 0;
> -}
> -/**
> - This function configures the L1 Substates.
> - It can be used for Rootport and endpoint devices.
> -
> - @param[in] DownstreamPort Indicates if the device
> about to be programmed is a downstream port
> - @param[in] DeviceBase Device PCI configuration
> base address
> - @param[in] L1SubstateExtCapOffset Pointer to L1 Substate
> Capability Structure
> - @param[in] PortL1SubstateCapSupport L1 Substate capability setting
> - @param[in] PortCommonModeRestoreTime Common Mode Restore
> Time
> - @param[in] PortTpowerOnValue Tpower_on Power On Wait
> Time
> - @param[in] PortTpowerOnScale Tpower-on Scale
> -
> - @retval none
> -**/
> -VOID
> -ConfigureL1s (
> - IN UINTN DeviceBase,
> - IN UINT16 L1SubstateExtCapOffset,
> - IN UINT32 PortL1SubstateCapSupport,
> - IN UINT32
> PortCommonModeRestoreTime,
> - IN UINT32 PortTpowerOnValue,
> - IN UINT32 PortTpowerOnScale,
> - IN UINT16 MaxLevel
> - )
> -{
> -
> - PciSegmentAndThenOr32 (
> - DeviceBase + L1SubstateExtCapOffset + R_PCIE_EX_L1SCTL1_OFFSET,
> - (UINT32) ~(0xFF00),
> - (UINT32) PortCommonModeRestoreTime << 8
> - );
> -
> - PciSegmentAnd32(DeviceBase + L1SubstateExtCapOffset +
> R_PCIE_EX_L1SCTL2_OFFSET, 0xFFFFFF04);
> -
> - PciSegmentOr32(DeviceBase + L1SubstateExtCapOffset +
> R_PCIE_EX_L1SCTL2_OFFSET,(UINT32) ((PortTpowerOnValue <<
> N_PCIE_EX_L1SCTL2_POWT) | PortTpowerOnScale));
> -
> - PciSegmentAndThenOr32 (
> - DeviceBase + L1SubstateExtCapOffset + R_PCIE_EX_L1SCTL1_OFFSET,
> - (UINT32) ~(0xE3FF0000),
> - (UINT32) (BIT30 | BIT23 | BIT21)
> - );
> -
> -}
> -
> -VOID
> -RootportL1sSupport (
> - IN UINT8 Bus,
> - IN UINT8 Dev,
> - IN UINT8 Fun,
> - IN UINT16 RootL1SubstateExtCapOffset,
> - IN UINT16 MaxL1Level
> - )
> -{
> - UINTN ComponentABaseAddress;
> - UINTN ComponentBBaseAddress;
> - UINT8 SecBus;
> - UINT32 PortL1SubstateCapSupport;
> - UINT32 PortCommonModeRestoreTime;
> - UINT32 PortTpowerOnValue;
> - UINT32 PortTpowerOnScale;
> - UINT16 ComponentBL1SubstateExtCapOffset;
> - UINT32 ComponentBL1Substates;
> - UINT32 ComponentBCommonModeRestoreTime;
> - UINT32 ComponentBTpowerOnValue;
> - UINT32 ComponentBTpowerOnScale;
> - UINT32 Data32;
> -
> - PortL1SubstateCapSupport = 0;
> - PortCommonModeRestoreTime = 0;
> - PortTpowerOnValue = 0;
> - PortTpowerOnScale = 0;
> - Data32 = 0;
> -
> - ComponentABaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,
> Bus, Dev, Fun, 0);
> - if (RootL1SubstateExtCapOffset != 0) {
> - Data32 = PciSegmentRead32 (ComponentABaseAddress +
> RootL1SubstateExtCapOffset + R_PCIE_EX_L1SCAP_OFFSET);
> - PortL1SubstateCapSupport = (Data32) & 0x0F;
> - PortCommonModeRestoreTime = (Data32 >> 8) & 0xFF;
> - PortTpowerOnScale = (Data32 >> 16) & 0x3;
> - PortTpowerOnValue = (Data32 >> 19) & 0x1F;
> - } else {
> - MaxL1Level = 0; // If L1 Substates from Root Port side
> is disable, then Disable from Device side also.
> - }
> -
> - SecBus = PciSegmentRead8 (ComponentABaseAddress
> + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
> - ComponentBBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,
> SecBus, 0, 0, 0);
> -
> - if (PciSegmentRead16 (ComponentBBaseAddress +
> PCI_DEVICE_ID_OFFSET) == 0xFFFF) {
> - ComponentBL1SubstateExtCapOffset = PcieFindExtendedCapId (
> - SecBus,
> - 0,
> - 0,
> - V_PCIE_EX_L1S_CID
> - );
> - if (ComponentBL1SubstateExtCapOffset != 0) {
> - ComponentBL1Substates = PciSegmentRead32
> (ComponentBBaseAddress + ComponentBL1SubstateExtCapOffset +
> R_PCIE_EX_L1SCAP_OFFSET);
> - ComponentBCommonModeRestoreTime = (ComponentBL1Substates
> >> 8) & 0xFF;
> - ComponentBTpowerOnScale = (ComponentBL1Substates >>
> 16) & 0x3;
> - ComponentBTpowerOnValue = (ComponentBL1Substates
> >> 19) & 0x1F;
> -
> - if (MaxL1Level == 3) {
> - if (Data32 >= ComponentBL1Substates) {
> - if (~(Data32 | BIT2)) {
> - MaxL1Level = 1;
> - }
> - }
> - else {
> - if (~(ComponentBL1Substates | BIT2)) {
> - MaxL1Level = 1;
> - }
> - }
> - }
> -
> - if (MaxL1Level == 3) {
> - ConfigureL1s (
> - ComponentABaseAddress,
> - RootL1SubstateExtCapOffset,
> - PortL1SubstateCapSupport,
> - ComponentBCommonModeRestoreTime,
> - ComponentBTpowerOnValue,
> - ComponentBTpowerOnScale,
> - MaxL1Level
> - );
> -
> - ConfigureL1s (
> - ComponentBBaseAddress,
> - ComponentBL1SubstateExtCapOffset,
> - ComponentBL1Substates,
> - PortCommonModeRestoreTime,
> - PortTpowerOnValue,
> - PortTpowerOnScale,
> - MaxL1Level
> - );
> - }
> -
> - if (MaxL1Level == 1) {
> - PciSegmentOr32 (
> - ComponentABaseAddress + RootL1SubstateExtCapOffset +
> R_PCIE_EX_L1SCTL1_OFFSET,
> - (UINT32) (BIT3 | BIT1)
> - );
> -
> - PciSegmentOr32 (
> - ComponentBBaseAddress +
> ComponentBL1SubstateExtCapOffset + R_PCIE_EX_L1SCTL1_OFFSET,
> - (UINT32) (BIT3 | BIT1)
> - );
> - }
> - else {
> - if (RootL1SubstateExtCapOffset != 0) {
> - PciSegmentOr32 (
> - ComponentABaseAddress + RootL1SubstateExtCapOffset +
> R_PCIE_EX_L1SCTL1_OFFSET,
> - (UINT32) (BIT3 | BIT1)
> - );
> -
> - PciSegmentOr32 (
> - ComponentABaseAddress + RootL1SubstateExtCapOffset +
> R_PCIE_EX_L1SCTL1_OFFSET,
> - (UINT32) (BIT2 | BIT0)
> - );
> - }
> - if (ComponentBL1SubstateExtCapOffset != 0) {
> - PciSegmentOr32 (
> - ComponentBBaseAddress +
> ComponentBL1SubstateExtCapOffset + R_PCIE_EX_L1SCTL1_OFFSET,
> - (UINT32) (BIT3 | BIT1)
> - );
> -
> - PciSegmentOr32 (
> - ComponentBBaseAddress +
> ComponentBL1SubstateExtCapOffset + R_PCIE_EX_L1SCTL1_OFFSET,
> - (UINT32) (BIT2 | BIT0)
> - );
> - }
> - }
> - }
> - }
> -}
> -
> -VOID
> -MultiFunctionDeviceAspm (
> - IN UINT8 Bus,
> - IN UINT8 Dev
> - )
> -{
> - UINT16 LowerAspm;
> - UINT16 AspmVal;
> - UINT8 Fun;
> - UINT64 DeviceBaseAddress;
> - UINT8 CapHeaderOffset;
> -
> - LowerAspm = 3; // L0s and L1 Supported
> - for (Fun = 0; Fun <= PCI_MAX_FUNC; ++Fun) {
> - //
> - // Check for Device availability
> - //
> - DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus,
> Dev, Fun, 0);
> - if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) ==
> 0xFFFF) {
> - // Device not present
> - continue;
> - }
> -
> - CapHeaderOffset = PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0x10);
> -
> - AspmVal = (PciSegmentRead16 (DeviceBaseAddress + CapHeaderOffset
> + 0x00C) >> 10) & 3;
> - if (LowerAspm > AspmVal) {
> - LowerAspm = AspmVal;
> - }
> - } //Fun
> -
> - for (Fun = 0; Fun <= PCI_MAX_FUNC; ++Fun) {
> - //
> - // Check for Device availability
> - //
> - DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus,
> Dev, Fun, 0);
> - if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) ==
> 0xFFFF) {
> - //
> - // Device not present
> - //
> - continue;
> - }
> -
> - CapHeaderOffset = PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0x10);
> -
> - PciSegmentAndThenOr16 (DeviceBaseAddress + CapHeaderOffset +
> 0x10, 0xFFFC, LowerAspm);
> - } //Fun
> -}
> -
> -UINT16
> -LimitAspmLevel (
> - IN UINT16 SelectedAspm,
> - IN UINT16 MaxAspmLevel
> - )
> -{
> - SelectedAspm = SelectedAspm & MaxAspmLevel;
> -
> - return SelectedAspm;
> -}
> -
> -UINT16
> -FindOptimalAspm (
> - IN UINT16 ComponentAaspm,
> - IN UINT16 ComponentBaspm
> - )
> -{
> - UINT16 SelectedAspm;
> -
> - SelectedAspm = ComponentAaspm & ComponentBaspm;
> -
> - return SelectedAspm;
> -}
> -
> -UINT16
> -FindComponentBaspm (
> - IN UINT8 Bus,
> - IN UINT8 MaxBus
> - )
> -{
> - UINT8 BusNo;
> - UINT8 DevNo;
> - UINT8 FunNo;
> - UINT64 DevBaseAddress;
> - UINT8 RegVal;
> - UINT8 SecBusNo;
> - UINT16 SelectedAspm; // No ASPM Support
> - UINT8 CapHeaderOffset_B;
> - BOOLEAN AspmFound;
> -
> - SelectedAspm = 0;
> - AspmFound = FALSE;
> -
> - for (BusNo = MaxBus; (BusNo != 0xFF) && (!AspmFound); --BusNo) {
> - for (DevNo = 0; (DevNo <= PCI_MAX_DEVICE) && (!AspmFound);
> ++DevNo) {
> - for (FunNo = 0; (FunNo <= PCI_MAX_FUNC) && (!AspmFound);
> ++FunNo) {
> - //
> - // Check for Device availability
> - //
> - DevBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,
> BusNo, DevNo, FunNo, 0);
> - if (PciSegmentRead16 (DevBaseAddress + PCI_DEVICE_ID_OFFSET)
> == 0xFFFF) {
> - //
> - // Device not present
> - //
> - continue;
> - }
> -
> - RegVal = PciSegmentRead8 (DevBaseAddress +
> PCI_HEADER_TYPE_OFFSET);
> - if ((RegVal & (BIT0 + BIT1 + BIT2 + BIT3 + BIT4 + BIT5 + BIT6)) !=
> 0x01) {
> - //
> - // Not a PCI-to-PCI bridges device
> - //
> - continue;
> - }
> -
> - SecBusNo = PciSegmentRead8 (DevBaseAddress +
> PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
> -
> - if (SecBusNo == Bus) {
> - //
> - // This is the Rootbridge for the given 'Bus' device
> - //
> - CapHeaderOffset_B = PcieFindCapId (TbtSegment, BusNo,
> DevNo, FunNo, 0x10);
> - SelectedAspm = (PciSegmentRead16 (DevBaseAddress +
> CapHeaderOffset_B + 0x00C) >> 10) & 3;
> - AspmFound = TRUE;
> - }
> - } //FunNo
> - } //DevNo
> - } //BusNo
> -
> - return (SelectedAspm);
> -}
> -
> -VOID
> -NoAspmSupport (
> - IN UINT8 Bus,
> - IN UINT8 Dev,
> - IN UINT8 Fun,
> - IN UINT8 CapHeaderOffset
> - )
> -{
> - UINT64 DeviceBaseAddress;
> -
> - DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev,
> Fun, 0);
> - PciSegmentAndThenOr16 (DeviceBaseAddress + CapHeaderOffset + 0x10,
> 0xFFFC, 0x00);
> -}
> -
> -VOID
> -EndpointAspmSupport (
> - IN UINT8 Bus,
> - IN UINT8 Dev,
> - IN UINT8 Fun,
> - IN UINT8 CapHeaderOffset,
> - IN UINT8 MaxBus,
> - IN UINT16 MaxAspmLevel
> - )
> -{
> - UINT64 DeviceBaseAddress;
> - UINT16 ComponentAaspm;
> - UINT16 ComponentBaspm;
> - UINT16 SelectedAspm;
> -
> - DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev,
> Fun, 0);
> - ComponentAaspm = (PciSegmentRead16 (DeviceBaseAddress +
> CapHeaderOffset + 0x00C) >> 10) & 3;
> - ComponentBaspm = FindComponentBaspm (Bus, MaxBus);
> - SelectedAspm = FindOptimalAspm (ComponentAaspm,
> ComponentBaspm);
> - SelectedAspm = LimitAspmLevel (SelectedAspm, MaxAspmLevel);
> - PciSegmentAndThenOr16 (DeviceBaseAddress + CapHeaderOffset + 0x10,
> 0xFFFC, SelectedAspm);
> -}
> -
> -VOID
> -UpstreamAspmSupport (
> - IN UINT8 Bus,
> - IN UINT8 Dev,
> - IN UINT8 Fun,
> - IN UINT8 CapHeaderOffset,
> - IN UINT8 MaxBus,
> - IN UINT16 MaxAspmLevel
> - )
> -{
> - UINT64 DeviceBaseAddress;
> - UINT16 ComponentAaspm;
> - UINT16 ComponentBaspm;
> - UINT16 SelectedAspm;
> -
> - DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev,
> Fun, 0);
> - ComponentAaspm = (PciSegmentRead16 (DeviceBaseAddress +
> CapHeaderOffset + 0x00C) >> 10) & 3;
> - ComponentBaspm = FindComponentBaspm (Bus, MaxBus);
> - SelectedAspm = FindOptimalAspm (ComponentAaspm,
> ComponentBaspm);
> - SelectedAspm = LimitAspmLevel (SelectedAspm, MaxAspmLevel);
> - PciSegmentAndThenOr16 (DeviceBaseAddress + CapHeaderOffset + 0x10,
> 0xFFFC, SelectedAspm);
> -}
> -
> -VOID
> -DownstreamAspmSupport (
> - IN UINT8 Bus,
> - IN UINT8 Dev,
> - IN UINT8 Fun,
> - IN UINT8 CapHeaderOffset,
> - IN UINT16 MaxAspmLevel
> - )
> -{
> - UINT64 ComponentABaseAddress;
> - UINT64 ComponentBBaseAddress;
> - UINT16 ComponentAaspm;
> - UINT16 ComponentBaspm;
> - UINT16 SelectedAspm;
> - UINT8 SecBus;
> - UINT8 CapHeaderOffset_B;
> -
> - ComponentABaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,
> Bus, Dev, Fun, 0);
> - ComponentAaspm = (PciSegmentRead16
> (ComponentABaseAddress + CapHeaderOffset + 0x00C) >> 10) & 3;
> -
> - SecBus = PciSegmentRead8 (ComponentABaseAddress
> + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
> - ComponentBBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,
> SecBus, 0, 0, 0);
> - ComponentBaspm = 0; // No ASPM Support
> - if (PciSegmentRead16 (ComponentBBaseAddress +
> PCI_DEVICE_ID_OFFSET) != 0xFFFF) {
> - CapHeaderOffset_B = PcieFindCapId (TbtSegment, SecBus, 0, 0, 0x10);
> - ComponentBaspm = (PciSegmentRead16
> (ComponentBBaseAddress + CapHeaderOffset_B + 0x00C) >> 10) & 3;
> - }
> -
> - SelectedAspm = FindOptimalAspm (ComponentAaspm,
> ComponentBaspm);
> - SelectedAspm = LimitAspmLevel (SelectedAspm, MaxAspmLevel);
> - PciSegmentAndThenOr16 (ComponentABaseAddress + CapHeaderOffset +
> 0x10, 0xFFFC, SelectedAspm);
> -}
> -
> -VOID
> -RootportAspmSupport (
> - IN UINT8 Bus,
> - IN UINT8 Dev,
> - IN UINT8 Fun,
> - IN UINT8 CapHeaderOffset,
> - IN UINT16 MaxAspmLevel
> - )
> -{
> - UINT64 ComponentABaseAddress;
> - UINT64 ComponentBBaseAddress;
> - UINT16 ComponentAaspm;
> - UINT16 ComponentBaspm;
> - UINT16 SelectedAspm;
> - UINT8 SecBus;
> - UINT8 CapHeaderOffset_B;
> -
> - ComponentABaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,
> Bus, Dev, Fun, 0);
> - ComponentAaspm = (PciSegmentRead16
> (ComponentABaseAddress + CapHeaderOffset + 0x00C) >> 10) & 3;
> -
> - SecBus = PciSegmentRead8 (ComponentABaseAddress
> + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
> - ComponentBBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,
> SecBus, 0, 0, 0);
> - ComponentBaspm = 0; // No ASPM Support
> - if (PciSegmentRead16 (ComponentBBaseAddress +
> PCI_DEVICE_ID_OFFSET) != 0xFFFF) {
> - CapHeaderOffset_B = PcieFindCapId (TbtSegment, SecBus, 0, 0, 0x10);
> - ComponentBaspm = (PciSegmentRead16
> (ComponentBBaseAddress + CapHeaderOffset_B + 0x00C) >> 10) & 3;
> - }
> -
> - SelectedAspm = FindOptimalAspm (ComponentAaspm,
> ComponentBaspm);
> - SelectedAspm = LimitAspmLevel (SelectedAspm, MaxAspmLevel);
> - PciSegmentAndThenOr16 (ComponentABaseAddress + CapHeaderOffset +
> 0x10, 0xFFFC, SelectedAspm);
> -}
> -
> -VOID
> -ThunderboltEnableAspmWithoutLtr (
> - IN UINT16 MaxAspmLevel,
> - IN UINTN RpSegment,
> - IN UINTN RpBus,
> - IN UINTN RpDevice,
> - IN UINTN RpFunction
> - )
> -{
> - UINT8 Bus;
> - UINT8 Dev;
> - UINT8 Fun;
> - UINT8 RootBus;
> - UINT8 RootDev;
> - UINT8 RootFun;
> - UINT8 MinBus;
> - UINT8 MaxBus;
> - UINT16 DeviceId;
> - UINT64 DeviceBaseAddress;
> - UINT8 RegVal;
> - UINT8 CapHeaderOffset;
> - UINT16 DevicePortType;
> -
> - MinBus = 0;
> - MaxBus = 0;
> -
> - MinBus = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS
> (RpSegment, RpBus, RpDevice, RpFunction,
> PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET));
> - MaxBus = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS
> (RpSegment, RpBus, RpDevice, RpFunction,
> PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET));
> - DeviceId = PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (RpSegment,
> MinBus, 0x00, 0x00, PCI_DEVICE_ID_OFFSET));
> - if (!(IsTbtHostRouter (DeviceId))) {
> - return;
> - }
> -
> - TbtSegment = (UINT8)RpSegment;
> -
> - RootBus = (UINT8)RpBus;
> - RootDev = (UINT8)RpDevice;
> - RootFun = (UINT8)RpFunction;
> -
> - //
> - // Enumerate all the bridges and devices which are available on TBT
> host controller
> - //
> - for (Bus = MinBus; Bus <= MaxBus; ++Bus) {
> - for (Dev = 0; Dev <= PCI_MAX_DEVICE; ++Dev) {
> - //
> - // Check for Device availability
> - //
> - DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus,
> Dev, 0, 0);
> - if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET)
> == 0xFFFF) {
> - //
> - // Device not present
> - //
> - continue;
> - }
> -
> - RegVal = PciSegmentRead8 (DeviceBaseAddress +
> PCI_HEADER_TYPE_OFFSET);
> - if ((RegVal & BIT7) == 0) {
> - //
> - // Not a multi-function device
> - //
> - continue;
> - }
> -
> - MultiFunctionDeviceAspm(Bus, Dev);
> - } //Dev
> - } //Bus
> -
> -
> - for (Bus = MinBus; Bus <= MaxBus; ++Bus) {
> - for (Dev = 0; Dev <= PCI_MAX_DEVICE; ++Dev) {
> - for (Fun = 0; Fun <= PCI_MAX_FUNC; ++Fun) {
> - //
> - // Check for Device availability
> - //
> - DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,
> Bus, Dev, Fun, 0);
> - if (PciSegmentRead16 (DeviceBaseAddress +
> PCI_DEVICE_ID_OFFSET) == 0xFFFF) {
> - //
> - // Device not present
> - //
> - continue;
> - }
> -
> - CapHeaderOffset = PcieFindCapId (TbtSegment, Bus, Dev, Fun,
> 0x10);
> - DevicePortType = (PciSegmentRead16 (DeviceBaseAddress +
> CapHeaderOffset + 0x002) >> 4) & 0xF;
> - if(PciSegmentRead8 (DeviceBaseAddress + PCI_CLASSCODE_OFFSET)
> == PCI_CLASS_SERIAL) {
> - MaxAspmLevel = (UINT16) 0x1;
> - }
> -
> - switch (DevicePortType) {
> - case 0:
> - //
> - // PCI Express Endpoint
> - //
> - EndpointAspmSupport (Bus, Dev, Fun, CapHeaderOffset,
> MaxBus, MaxAspmLevel);
> - break;
> -
> - case 1:
> - //
> - // Legacy PCI Express Endpoint
> - //
> - EndpointAspmSupport (Bus, Dev, Fun, CapHeaderOffset,
> MaxBus, MaxAspmLevel);
> - break;
> -
> - case 4:
> - //
> - // Root Port of PCI Express Root Complex
> - //
> - RootportAspmSupport (Bus, Dev, Fun, CapHeaderOffset,
> MaxAspmLevel);
> - break;
> -
> - case 5:
> - //
> - // Upstream Port of PCI Express Switch
> - //
> - UpstreamAspmSupport (Bus, Dev, Fun, CapHeaderOffset,
> MaxBus, MaxAspmLevel);
> - break;
> -
> - case 6:
> - //
> - // Downstream Port of PCI Express Switch
> - //
> - DownstreamAspmSupport (Bus, Dev, Fun, CapHeaderOffset,
> MaxAspmLevel);
> - break;
> -
> - case 7:
> - //
> - // PCI Express to PCI/PCI-X Bridge
> - //
> - NoAspmSupport (Bus, Dev, Fun, CapHeaderOffset);
> - break;
> -
> - case 8:
> - //
> - // PCI/PCI-X to PCI Express Bridge
> - //
> - NoAspmSupport (Bus, Dev, Fun, CapHeaderOffset);
> - break;
> -
> - case 9:
> - //
> - // Root Complex Integrated Endpoint
> - //
> - EndpointAspmSupport (Bus, Dev, Fun, CapHeaderOffset,
> MaxBus, MaxAspmLevel);
> - break;
> -
> - case 10:
> - //
> - // Root Complex Event Collector
> - //
> - EndpointAspmSupport (Bus, Dev, Fun, CapHeaderOffset,
> MaxBus, MaxAspmLevel);
> - break;
> -
> - default:
> - break;
> - }
> - //
> - // switch(DevicePortType)
> - //
> - }
> - //
> - // Fun
> - //
> - }
> - //
> - // Dev
> - //
> - }
> - //
> - // Bus
> - //
> - CapHeaderOffset = PcieFindCapId (TbtSegment, RootBus, RootDev,
> RootFun, 0x10);
> - RootportAspmSupport (RootBus, RootDev, RootFun, CapHeaderOffset,
> MaxAspmLevel);
> -}
> -
> -VOID
> -ThunderboltEnableL1Sub (
> - IN UINT16 MaxL1Level,
> - IN UINTN RpSegment,
> - IN UINTN RpBus,
> - IN UINTN RpDevice,
> - IN UINTN RpFunction
> - )
> -{
> - UINT16 CapHeaderOffsetExtd;
> -
> - RpBus = 0;
> -
> - CapHeaderOffsetExtd = PcieFindExtendedCapId ((UINT8) RpBus, (UINT8)
> RpDevice, (UINT8) RpFunction, V_PCIE_EX_L1S_CID);
> - RootportL1sSupport ((UINT8) RpBus, (UINT8) RpDevice, (UINT8)
> RpFunction, CapHeaderOffsetExtd, MaxL1Level);
> -}
> -
> -VOID
> -ThunderboltDisableAspmWithoutLtr (
> - IN UINTN RpSegment,
> - IN UINTN RpBus,
> - IN UINTN RpDevice,
> - IN UINTN RpFunction
> - )
> -{
> - UINT8 Bus;
> - UINT8 Dev;
> - UINT8 Fun;
> - UINT8 RootBus;
> - UINT8 RootDev;
> - UINT8 RootFun;
> - UINT8 MinBus;
> - UINT8 MaxBus;
> - UINT16 DeviceId;
> - UINT64 DeviceBaseAddress;
> - UINT8 CapHeaderOffset;
> -
> - MinBus = 0;
> - MaxBus = 0;
> -
> - MinBus = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS
> (RpSegment, RpBus, RpDevice, RpFunction,
> PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET));
> - MaxBus = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS
> (RpSegment, RpBus, RpDevice, RpFunction,
> PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET));
> - DeviceId = PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (RpSegment,
> MinBus, 0x00, 0x00, PCI_DEVICE_ID_OFFSET));
> - if (!(IsTbtHostRouter (DeviceId))) {
> - return;
> - }
> -
> - TbtSegment = (UINT8)RpSegment;
> - RootBus = (UINT8)RpBus;
> - RootDev = (UINT8)RpDevice;
> - RootFun = (UINT8)RpFunction;
> -
> - //
> - // Enumerate all the bridges and devices which are available on TBT
> host controller
> - //
> - for (Bus = MinBus; Bus <= MaxBus; ++Bus) {
> - for (Dev = 0; Dev <= PCI_MAX_DEVICE; ++Dev) {
> - for (Fun = 0; Fun <= PCI_MAX_FUNC; ++Fun) {
> - //
> - // Check for Device availability
> - //
> - DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,
> Bus, Dev, Fun, 0);
> - if (PciSegmentRead16 (DeviceBaseAddress +
> PCI_DEVICE_ID_OFFSET) == 0xFFFF) {
> - //
> - // Device not present
> - //
> - continue;
> - }
> -
> - CapHeaderOffset = PcieFindCapId (TbtSegment, Bus, Dev, Fun,
> 0x10);
> - PciSegmentAndThenOr16 (DeviceBaseAddress + CapHeaderOffset
> + 0x10, 0xFFFC, 0x00);
> - } //Fun
> - } //Dev
> - } //Bus
> -
> - CapHeaderOffset = PcieFindCapId (TbtSegment, RootBus, RootDev,
> RootFun, 0x10);
> - NoAspmSupport(RootBus, RootDev, RootFun, CapHeaderOffset);
> -}
> -
> -VOID
> -TbtProgramClkReq (
> - IN UINT8 Bus,
> - IN UINT8 Device,
> - IN UINT8 Function,
> - IN UINT8 ClkReqSetup
> - )
> -{
> - UINT64 DeviceBaseAddress;
> - UINT8 CapHeaderOffset;
> - UINT16 Data16;
> -
> - DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus,
> Device, Function, 0);
> - CapHeaderOffset = PcieFindCapId (TbtSegment, Bus, Device, Function,
> 0x10);
> -
> - //
> - // Check if CLKREQ# is supported
> - //
> - if ((PciSegmentRead32 (DeviceBaseAddress + CapHeaderOffset + 0x0C) &
> BIT18) != 0) {
> - Data16 = PciSegmentRead16 (DeviceBaseAddress + CapHeaderOffset +
> 0x010);
> -
> - if (ClkReqSetup) {
> - Data16 = Data16 | BIT8; // Enable Clock Power Management
> - } else {
> - Data16 = Data16 & (UINT16)(~BIT8); // Disable Clock Power
> Management
> - }
> -
> - PciSegmentWrite16 (DeviceBaseAddress + CapHeaderOffset + 0x010,
> Data16);
> - }
> -}
> -VOID
> -TbtProgramPtm(
> - IN UINT8 Bus,
> - IN UINT8 Device,
> - IN UINT8 Function,
> - IN UINT8 PtmSetup,
> - IN BOOLEAN IsRoot
> -)
> -{
> - UINT64 DeviceBaseAddress;
> - UINT16 CapHeaderOffset;
> - UINT16 PtmControlRegister;
> - UINT16 PtmCapabilityRegister;
> -
> - DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS(TbtSegment, Bus,
> Device, Function, 0);
> - CapHeaderOffset = PcieFindExtendedCapId(Bus, Device, Function,
> 0x001F /*V_PCIE_EX_PTM_CID*/);
> - if(CapHeaderOffset != 0) {
> - PtmCapabilityRegister = PciSegmentRead16(DeviceBaseAddress +
> CapHeaderOffset + 0x04);
> - //
> - // Check if PTM Requester/ Responder capability for the EP/Down
> stream etc
> - //
> - if ((PtmCapabilityRegister & (BIT1 | BIT0)) != 0) {
> - PtmControlRegister = PciSegmentRead16(DeviceBaseAddress +
> CapHeaderOffset + 0x08);
> -
> - if (PtmSetup) {
> - PtmControlRegister = PtmControlRegister | BIT0; // Enable
> PTM
> - if(IsRoot) {
> - PtmControlRegister = PtmControlRegister | BIT1; // Enable
> PTM
> - }
> - PtmControlRegister = PtmControlRegister |
> (PtmCapabilityRegister & 0xFF00); // Programm Local Clock Granularity
> - } else {
> - PtmControlRegister = PtmControlRegister & (UINT16)(~(BIT0 |
> BIT1)); // Disable Clock Power Management
> - }
> -
> - PciSegmentWrite16(DeviceBaseAddress + CapHeaderOffset + 0x08,
> PtmControlRegister);
> - }
> - }
> -}
> -
> -VOID
> -ConfigureTbtPm (
> - IN UINTN RpSegment,
> - IN UINTN RpBus,
> - IN UINTN RpDevice,
> - IN UINTN RpFunction,
> - IN UINT8 Configuration // 1- Clk Request , 2- PTM ,
> - )
> -{
> - UINT8 Bus;
> - UINT8 Dev;
> - UINT8 Fun;
> - UINT8 MinBus;
> - UINT8 MaxBus;
> - UINT16 DeviceId;
> - UINT64 DeviceBaseAddress;
> -
> - MinBus = 0;
> - MaxBus = 0;
> -
> - if ((Configuration != 1) && (Configuration != 2)) {
> - return;
> - }
> - MinBus = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS
> (RpSegment, RpBus, RpDevice, RpFunction,
> PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET));
> - MaxBus = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS
> (RpSegment, RpBus, RpDevice, RpFunction,
> PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET));
> - DeviceId = PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (RpSegment,
> MinBus, 0x00, 0x00, PCI_DEVICE_ID_OFFSET));
> - if (!(IsTbtHostRouter (DeviceId))) {
> - return;
> - }
> -
> - TbtSegment = (UINT8)RpSegment;
> - //
> - // Enumerate all the bridges and devices which are available on TBT
> host controller
> - //
> - for (Bus = MaxBus; Bus >= MinBus; --Bus) {
> - for (Dev = 0; Dev <= PCI_MAX_DEVICE; ++Dev) {
> - for (Fun = 0; Fun <= PCI_MAX_FUNC; ++Fun) {
> - //
> - // Check for Device availability
> - //
> - DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,
> Bus, Dev, Fun, 0);
> - if (PciSegmentRead16 (DeviceBaseAddress +
> PCI_DEVICE_ID_OFFSET) == 0xFFFF) {
> - if (Fun == 0) {
> - //
> - // IF Fun is zero, stop enumerating other functions of the
> particular bridge
> - //
> - break;
> - }
> - //
> - // otherwise, just skip checking for CLKREQ support
> - //
> - continue;
> - }
> - switch (Configuration) {
> - case 1:
> - TbtProgramClkReq (Bus, Dev, Fun, (UINT8)
> mTbtNvsAreaPtr->TbtSetClkReq);
> - break;
> - case 2:
> - TbtProgramPtm (Bus, Dev, Fun, (UINT8)
> mTbtNvsAreaPtr->TbtPtm, FALSE);
> - TbtProgramPtm((UINT8) RpBus, (UINT8) RpDevice, (UINT8)
> RpFunction, (UINT8) mTbtNvsAreaPtr->TbtPtm, TRUE);
> - break;
> - default:
> - break;
> - }
> - } //Fun
> - } // Dev
> - } // Bus
> -}
> -
> -/**
> - 1) Check LTR support in device capabilities 2 register (bit 11).
> - 2) If supported enable LTR in device control 2 register (bit 10).
> -
> -**/
> -VOID
> -TbtProgramLtr (
> - IN UINT8 Bus,
> - IN UINT8 Device,
> - IN UINT8 Function,
> - IN UINT8 LtrSetup
> - )
> -{
> - UINT64 DeviceBaseAddress;
> - UINT8 CapHeaderOffset;
> - UINT16 Data16;
> -
> - DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus,
> Device, Function, 0);
> - CapHeaderOffset = PcieFindCapId (TbtSegment, Bus, Device, Function,
> 0x10);
> -
> - //
> - // Check if LTR# is supported
> - //
> - if ((PciSegmentRead32 (DeviceBaseAddress + CapHeaderOffset + 0x24) &
> BIT11) != 0) {
> - Data16 = PciSegmentRead16 (DeviceBaseAddress + CapHeaderOffset +
> 0x028);
> -
> - if (LtrSetup) {
> - Data16 = Data16 | BIT10; // LTR Mechanism Enable
> - } else {
> - Data16 = Data16 & (UINT16)(~BIT10); // LTR Mechanism Disable
> - }
> -
> - PciSegmentWrite16 (DeviceBaseAddress + CapHeaderOffset + 0x028,
> Data16);
> - }
> -}
> -
> -VOID
> -ConfigureLtr (
> - IN UINTN RpSegment,
> - IN UINTN RpBus,
> - IN UINTN RpDevice,
> - IN UINTN RpFunction
> - )
> -{
> - UINT8 Bus;
> - UINT8 Dev;
> - UINT8 Fun;
> - UINT8 MinBus;
> - UINT8 MaxBus;
> - UINT16 DeviceId;
> - UINT64 DeviceBaseAddress;
> -
> - MinBus = 0;
> - MaxBus = 0;
> -
> - MinBus = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS
> (RpSegment, RpBus, RpDevice, RpFunction,
> PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET));
> - MaxBus = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS
> (RpSegment, RpBus, RpDevice, RpFunction,
> PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET));
> - DeviceId = PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (RpSegment,
> MinBus, 0x00, 0x00, PCI_DEVICE_ID_OFFSET));
> - if (!(IsTbtHostRouter (DeviceId))) {
> - return;
> - }
> -
> - TbtSegment = (UINT8)RpSegment;
> - //
> - // Enumerate all the bridges and devices which are available on TBT
> host controller
> - //
> - for (Bus = MinBus; Bus <= MaxBus; ++Bus) {
> - for (Dev = 0; Dev <= PCI_MAX_DEVICE; ++Dev) {
> - for (Fun = 0; Fun <= PCI_MAX_FUNC; ++Fun) {
> - //
> - // Check for Device availability
> - //
> - DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,
> Bus, Dev, Fun, 0);
> - if (PciSegmentRead16 (DeviceBaseAddress +
> PCI_DEVICE_ID_OFFSET) == 0xFFFF) {
> - if (Fun == 0) {
> - //
> - // IF Fun is zero, stop enumerating other functions of the
> particular bridge
> - //
> - break;
> - }
> - //
> - // otherwise, just skip checking for LTR support
> - //
> - continue;
> - }
> -
> - TbtProgramLtr (Bus, Dev, Fun, (UINT8) mTbtNvsAreaPtr->TbtLtr);
> -
> - } //Fun
> - } // Dev
> - } // Bus
> - TbtProgramLtr ((UINT8) RpBus, (UINT8) RpDevice, (UINT8) RpFunction,
> (UINT8) mTbtNvsAreaPtr->TbtLtr);
> -}
> -
> -/*
> - US ports and endpoints which declare support must also have the LTR
> capability structure (cap ID 18h).
> - In this structure you need to enter the max snoop latency and max
> non-snoop latency in accordance with the format specified in the PCIe spec.
> - The latency value itself is platform specific so you'll need to get it from
> the platform architect or whatever.
> -*/
> -VOID
> -ThunderboltGetLatencyLtr (
> - VOID
> - )
> -{
> - PCH_SERIES PchSeries;
> -
> - PchSeries = GetPchSeries ();
> -
> - if(gCurrentDiscreteTbtRootPortType == DTBT_TYPE_PEG) {
> - // PEG selector
> - TbtLtrMaxSnoopLatency = LTR_MAX_SNOOP_LATENCY_VALUE;
> - TbtLtrMaxNoSnoopLatency = LTR_MAX_NON_SNOOP_LATENCY_VALUE;
> - } else if (gCurrentDiscreteTbtRootPortType == DTBT_TYPE_PCH) {
> - // PCH selector
> -
> - if (PchSeries == PchLp) {
> - TbtLtrMaxSnoopLatency = 0x1003;
> - TbtLtrMaxNoSnoopLatency = 0x1003;
> - }
> - if (PchSeries == PchH) {
> - TbtLtrMaxSnoopLatency = 0x0846;
> - TbtLtrMaxNoSnoopLatency = 0x0846;
> - }
> - }
> -}
> -
> -VOID
> -SetLatencyLtr (
> - IN UINT8 Bus,
> - IN UINT8 Dev,
> - IN UINT8 Fun,
> - IN UINT16 CapHeaderOffsetExtd,
> - IN UINT16 LtrMaxSnoopLatency,
> - IN UINT16 LtrMaxNoSnoopLatency
> - )
> -{
> - UINT64 DeviceBaseAddress;
> - if(CapHeaderOffsetExtd == 0) {
> - return;
> - }
> - DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev,
> Fun, 0);
> - PciSegmentWrite16 (DeviceBaseAddress + CapHeaderOffsetExtd + 0x004,
> LtrMaxSnoopLatency);
> - PciSegmentWrite16 (DeviceBaseAddress + CapHeaderOffsetExtd + 0x006,
> LtrMaxNoSnoopLatency);
> -}
> -
> -VOID
> -ThunderboltSetLatencyLtr (
> - IN UINTN RpSegment,
> - IN UINTN RpBus,
> - IN UINTN RpDevice,
> - IN UINTN RpFunction
> - )
> -{
> - UINT8 Bus;
> - UINT8 Dev;
> - UINT8 Fun;
> - UINT8 MinBus;
> - UINT8 MaxBus;
> - UINT16 DeviceId;
> - UINT64 DeviceBaseAddress;
> - UINT8 CapHeaderOffsetStd;
> - UINT16 CapHeaderOffsetExtd;
> - UINT16 DevicePortType;
> -
> - MinBus = 0;
> - MaxBus = 0;
> -
> - MinBus = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS
> (RpSegment, RpBus, RpDevice, RpFunction,
> PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET));
> - MaxBus = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS
> (RpSegment, RpBus, RpDevice, RpFunction,
> PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET));
> - DeviceId = PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (RpSegment,
> MinBus, 0x00, 0x00, PCI_DEVICE_ID_OFFSET));
> - if (!(IsTbtHostRouter (DeviceId))) {
> - return;
> - }
> -
> - TbtSegment = (UINT8)RpSegment;
> -
> - for (Bus = MinBus; Bus <= MaxBus; ++Bus) {
> - for (Dev = 0; Dev <= PCI_MAX_DEVICE; ++Dev) {
> - for (Fun = 0; Fun <= PCI_MAX_FUNC; ++Fun) {
> - //
> - // Check for Device availability
> - //
> - DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,
> Bus, Dev, Fun, 0);
> - if (PciSegmentRead16 (DeviceBaseAddress +
> PCI_DEVICE_ID_OFFSET) == 0xFFFF) {
> - //
> - // Device not present
> - //
> - continue;
> - }
> -
> - CapHeaderOffsetStd = PcieFindCapId (TbtSegment, Bus, Dev, Fun,
> 0x10);
> - DevicePortType = (PciSegmentRead16 (DeviceBaseAddress +
> CapHeaderOffsetStd + 0x002) >> 4) & 0xF;
> -
> - CapHeaderOffsetExtd = PcieFindExtendedCapId (Bus, Dev, Fun,
> 0x0018);
> -
> - switch (DevicePortType) {
> - case 0:
> - //
> - // PCI Express Endpoint
> - //
> - SetLatencyLtr (Bus, Dev, Fun, CapHeaderOffsetExtd,
> TbtLtrMaxSnoopLatency, TbtLtrMaxNoSnoopLatency);
> - break;
> -
> - case 1:
> - //
> - // Legacy PCI Express Endpoint
> - //
> - SetLatencyLtr (Bus, Dev, Fun, CapHeaderOffsetExtd,
> TbtLtrMaxSnoopLatency, TbtLtrMaxNoSnoopLatency);
> - break;
> -
> - case 4:
> - //
> - // Root Port of PCI Express Root Complex
> - //
> - // Do-nothing
> - break;
> -
> - case 5:
> - //
> - // Upstream Port of PCI Express Switch
> - //
> - SetLatencyLtr (Bus, Dev, Fun, CapHeaderOffsetExtd,
> TbtLtrMaxSnoopLatency, TbtLtrMaxNoSnoopLatency);
> - break;
> -
> - case 6:
> - //
> - // Downstream Port of PCI Express Switch
> - //
> - // Do-nothing
> - break;
> -
> - case 7:
> - //
> - // PCI Express to PCI/PCI-X Bridge
> - //
> - // Do-nothing
> - break;
> -
> - case 8:
> - //
> - // PCI/PCI-X to PCI Express Bridge
> - //
> - // Do-nothing
> - break;
> -
> - case 9:
> - //
> - // Root Complex Integrated Endpoint
> - //
> - // Do-nothing
> - break;
> -
> - case 10:
> - //
> - // Root Complex Event Collector
> - //
> - // Do-nothing
> - break;
> -
> - default:
> - break;
> - }
> - //
> - // switch(DevicePortType)
> - //
> - }
> - //
> - // Fun
> - //
> - }
> - //
> - // Dev
> - //
> - }
> - //
> - // Bus
> - //
> -}
> -
> -static
> -VOID
> -Stall (
> - UINTN Usec
> - )
> -{
> - UINTN Index;
> - UINT32 Data32;
> - UINT32 PrevData;
> - UINTN Counter;
> -
> - Counter = (UINTN) ((Usec * 10) / 3);
> - //
> - // Call WaitForTick for Counter + 1 ticks to try to guarantee Counter tick
> - // periods, thus attempting to ensure Microseconds of stall time.
> - //
> - if (Counter != 0) {
> -
> - PrevData = IoRead32 (PcdGet16 (PcdAcpiBaseAddress) +
> R_PCH_ACPI_PM1_TMR);
> - for (Index = 0; Index < Counter;) {
> - Data32 = IoRead32 (PcdGet16 (PcdAcpiBaseAddress) +
> R_PCH_ACPI_PM1_TMR);
> - if (Data32 < PrevData) {
> - //
> - // Reset if there is a overlap
> - //
> - PrevData = Data32;
> - continue;
> - }
> -
> - Index += (Data32 - PrevData);
> - PrevData = Data32;
> - }
> - }
> -
> - return ;
> -}
> -/**
> - Called during Sx entry, initates TbtSetPcie2TbtCommand HandShake to set
> GO2SX_NO_WAKE
> - for Tbt devices if WakeupSupport is not present.
> -
> - @param[in] DispatchHandle - The unique handle assigned to
> this handler by SmiHandlerRegister().
> - @param[in] DispatchContext - Points to an optional handler
> context which was specified when the
> - handler was registered.
> - @param[in, out] CommBuffer - A pointer to a collection of data
> in memory that will
> - be conveyed from a non-SMM
> environment into an SMM environment.
> - @param[in, out] CommBufferSize - The size of the CommBuffer.
> -
> - @retval EFI_SUCCESS - The interrupt was handled
> successfully.
> -**/
> -EFI_STATUS
> -EFIAPI
> -SxDTbtEntryCallback (
> - IN EFI_HANDLE DispatchHandle,
> - IN CONST VOID *DispatchContext,
> - IN OUT VOID *CommBuffer OPTIONAL,
> - IN UINTN *CommBufferSize OPTIONAL
> - )
> -{
> - UINT16 DeviceId;
> - UINT8 CableConnected;
> - UINT8 RootportSelected;
> - UINT8 HoustRouteBus;
> - volatile UINT32 *PowerState;
> - UINT32 PowerStatePrev;
> - BOOLEAN SecSubBusAssigned;
> - UINT64 DeviceBaseAddress;
> - UINT8 CapHeaderOffset;
> - UINTN RpDev;
> - UINTN RpFunc;
> - EFI_STATUS Status;
> - UINT32 Timeout;
> - UINT32 RegisterValue;
> - UINT64 Tbt2Pcie;
> - UINTN Index;
> - UINT32 TbtCioPlugEventGpioNo;
> - UINT32 TbtFrcPwrGpioNo;
> - UINT8 TbtFrcPwrGpioLevel;
> - UINT32 TbtPcieRstGpioNo;
> - UINT8 TbtPcieRstGpioLevel;
> - EFI_SMM_SX_REGISTER_CONTEXT *EntryDispatchContext;
> -
> - CableConnected = 0;
> - HoustRouteBus = 3;
> - SecSubBusAssigned = FALSE;
> - Timeout = 600;
> - RootportSelected = 0;
> - TbtCioPlugEventGpioNo = 0;
> - TbtFrcPwrGpioNo = 0;
> - TbtFrcPwrGpioLevel = 0;
> - TbtPcieRstGpioNo = 0;
> - TbtPcieRstGpioLevel = 0;
> - Index = 0;
> -
> - EntryDispatchContext = (EFI_SMM_SX_REGISTER_CONTEXT*)
> DispatchContext;
> -
> -// CableConnected = GetTbtHostRouterStatus ();
> - //SaveTbtHostRouterStatus (CableConnected & 0xF0);
> - //
> - // Get the Power State and Save
> - //
> - if (((mTbtNvsAreaPtr->DTbtControllerEn0 == 0) && (Index == 0))) {
> -
> - RootportSelected = mTbtNvsAreaPtr->RootportSelected0;
> - TbtCioPlugEventGpioNo = mTbtNvsAreaPtr->TbtCioPlugEventGpioNo0;
> - TbtFrcPwrGpioNo = mTbtNvsAreaPtr->TbtFrcPwrGpioNo0;
> - TbtFrcPwrGpioLevel = mTbtNvsAreaPtr->TbtFrcPwrGpioLevel0;
> - TbtPcieRstGpioNo = mTbtNvsAreaPtr->TbtPcieRstGpioNo0;
> - TbtPcieRstGpioLevel = mTbtNvsAreaPtr->TbtPcieRstGpioLevel0;
> - }
> -
> - Status = GetDTbtRpDevFun (gCurrentDiscreteTbtRootPortType,
> RootportSelected - 1, &RpDev, &RpFunc);
> - ASSERT_EFI_ERROR (Status);
> - CapHeaderOffset = PcieFindCapId (TbtSegment, 0x00, (UINT8)RpDev,
> (UINT8)RpFunc, 0x01);
> - DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, 0x00,
> (UINT32)RpDev, (UINT32)RpFunc, 0);
> - PowerState = &*((volatile UINT32 *) (mPciExpressBaseAddress +
> DeviceBaseAddress + CapHeaderOffset + 4)); //PMCSR
> - PowerStatePrev = *PowerState;
> - *PowerState &= 0xFFFFFFFC;
> -
> - HoustRouteBus = PciSegmentRead8 (DeviceBaseAddress +
> PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
> - //
> - // Check the Subordinate bus .If it is Zero ,assign temporary bus to
> - // find the device presence .
> - //
> - if (HoustRouteBus == 0) {
> - PciSegmentWrite8 (DeviceBaseAddress +
> PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET, 0xF0);
> - PciSegmentWrite8 (DeviceBaseAddress +
> PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET, 0xF0);
> - HoustRouteBus = 0xF0;
> - SecSubBusAssigned = TRUE;
> - }
> - //
> - // Clear Interrupt capability of TBT CIO Plug Event Pin to make sure no SCI
> is getting generated,
> - // This GPIO will be reprogrammed while resuming as part of Platform
> GPIO Programming.
> - //
> - GpioSetPadInterruptConfig (TbtCioPlugEventGpioNo, GpioIntDis);
> - //
> - // Read the TBT Host router DeviceID
> - //
> - DeviceId = PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (TbtSegment,
> HoustRouteBus, 0, 0, PCI_DEVICE_ID_OFFSET));
> -
> - //
> - // Check For HostRouter Presence
> - //
> - if (IsTbtHostRouter (DeviceId)) {
> - // CableConnected = GetTbtHostRouterStatus ();
> - if (!((CableConnected & (DTBT_SAVE_STATE_OFFSET << Index)) ==
> (DTBT_SAVE_STATE_OFFSET << Index))) {
> - CableConnected = CableConnected | (DTBT_SAVE_STATE_OFFSET <<
> Index);
> - // SaveTbtHostRouterStatus (CableConnected);
> - }
> - }
> -
> - //
> - // Check value of Tbt2Pcie reg, if Tbt is not present, bios needs to apply
> force power prior to sending mailbox command
> - //
> - GET_TBT2PCIE_REGISTER_ADDRESS(TbtSegment, HoustRouteBus, 0x00,
> 0x00, Tbt2Pcie)
> - RegisterValue = PciSegmentRead32 (Tbt2Pcie);
> - if (0xFFFFFFFF == RegisterValue) {
> -
> - GpioWrite (TbtFrcPwrGpioNo,TbtFrcPwrGpioLevel);
> -
> - while (Timeout -- > 0) {
> - RegisterValue = PciSegmentRead32 (Tbt2Pcie);
> - if (0xFFFFFFFF != RegisterValue) {
> - break;
> - }
> - Stall(1* (UINTN)1000);
> - }
> - //
> - // Before entering Sx state BIOS should execute GO2SX/NO_WAKE
> mailbox command for AIC.
> - // However BIOS shall not execute go2sx mailbox command on
> S5/reboot cycle.
> - //
> -
> - if( (EntryDispatchContext->Type == SxS3) ||
> (EntryDispatchContext->Type == SxS4))
> - {
> - if(!mTbtNvsAreaPtr->TbtWakeupSupport) {
> - //Wake Disabled, GO2SX_NO_WAKE Command
> - TbtSetPcie2TbtCommand (PCIE2TBT_GO2SX_NO_WAKE,
> HoustRouteBus, 0, 0, TBT_5S_TIMEOUT);
> - } else {
> - //Wake Enabled, GO2SX Command
> - TbtSetPcie2TbtCommand (PCIE2TBT_GO2SX, HoustRouteBus, 0, 0,
> TBT_5S_TIMEOUT);
> - }
> - }
> - if (mTbtNvsAreaPtr->TbtFrcPwrEn == 0) {
> - GpioWrite (TbtFrcPwrGpioNo,!(TbtFrcPwrGpioLevel));
> - }
> - } else {
> - //
> - // Before entering Sx state BIOS should execute GO2SX/NO_WAKE
> mailbox command for AIC.
> - // However BIOS shall not execute go2sx mailbox command on
> S5/reboot cycle.
> - //
> - if( (EntryDispatchContext->Type == SxS3) ||
> (EntryDispatchContext->Type == SxS4))
> - {
> - if(!mTbtNvsAreaPtr->TbtWakeupSupport) {
> - //Wake Disabled, GO2SX_NO_WAKE Command
> - TbtSetPcie2TbtCommand (PCIE2TBT_GO2SX_NO_WAKE,
> HoustRouteBus, 0, 0, TBT_5S_TIMEOUT);
> - } else {
> - //Wake Enabled, GO2SX Command
> - TbtSetPcie2TbtCommand (PCIE2TBT_GO2SX, HoustRouteBus, 0, 0,
> TBT_5S_TIMEOUT);
> - }
> - }
> - }
> - *PowerState = PowerStatePrev;
> - //
> - // Restore the bus number in case we assigned temporarily
> - //
> - if (SecSubBusAssigned) {
> - PciSegmentWrite8 (DeviceBaseAddress +
> PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET, 0x00);
> - PciSegmentWrite8 (DeviceBaseAddress +
> PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET, 0x00);
> - }
> - if (gDTbtPcieRstSupport) {
> - GpioWrite (TbtPcieRstGpioNo,TbtPcieRstGpioLevel);
> - }
> - return EFI_SUCCESS;
> -}
> -
> -VOID
> -ThunderboltSwSmiCallback (
> - IN UINT8 Type
> - )
> -{
> - UINT8 ThunderboltSmiFunction;
> -
> - DEBUG ((DEBUG_INFO, "ThunderboltSwSmiCallback Entry\n"));
> - ThunderboltSmiFunction = mTbtNvsAreaPtr->ThunderboltSmiFunction;
> - DEBUG ((DEBUG_INFO, "ThunderboltSwSmiCallback.
> ThunderboltSmiFunction=%d\n", ThunderboltSmiFunction));
> - if (Type == DTBT_CONTROLLER) {
> - gCurrentDiscreteTbtRootPort =
> mTbtNvsAreaPtr->CurrentDiscreteTbtRootPort;
> - gCurrentDiscreteTbtRootPortType =
> mTbtNvsAreaPtr->CurrentDiscreteTbtRootPortType;
> - }
> -
> - switch (ThunderboltSmiFunction) {
> - case 21:
> - ThunderboltCallback (Type);
> - break;
> -
> - case 22:
> - TbtDisablePCIDevicesAndBridges (Type);
> - break;
> -
> - case 23:
> - ConfigureTbtAspm (Type, (UINT16) 0x02);
> - break;
> -
> - case 24:
> - ConfigureTbtAspm (Type, (UINT16) 0x01);
> - break;
> -
> - default:
> - break;
> - }
> - DEBUG ((DEBUG_INFO, "ThunderboltSwSmiCallback Exit.\n"));
> -}
> -STATIC
> -EFI_STATUS
> -EFIAPI
> -DiscreteThunderboltSwSmiCallback (
> - IN EFI_HANDLE DispatchHandle,
> - IN CONST VOID *DispatchContext,
> - IN OUT VOID *CommBuffer OPTIONAL,
> - IN UINTN *CommBufferSize OPTIONAL
> - )
> -{
> - ThunderboltSwSmiCallback(DTBT_CONTROLLER);
> - return EFI_SUCCESS;
> -}
> -EFI_STATUS
> -TbtRegisterHandlers (
> - IN BOOLEAN Type
> - )
> -{
> - EFI_STATUS Status;
> - UINTN SmiInputValue;
> - EFI_SMM_HANDLER_ENTRY_POINT2 SxHandler;
> - EFI_SMM_HANDLER_ENTRY_POINT2 SwHandler;
> - EFI_SMM_SX_DISPATCH2_PROTOCOL *SxDispatchProtocol;
> - EFI_SMM_SW_DISPATCH2_PROTOCOL *SwDispatch;
> - EFI_SMM_SX_REGISTER_CONTEXT EntryDispatchContext;
> - EFI_SMM_SW_REGISTER_CONTEXT SwContext;
> - EFI_HANDLE SwDispatchHandle;
> - EFI_HANDLE S3DispatchHandle;
> - EFI_HANDLE S4DispatchHandle;
> - EFI_HANDLE S5DispatchHandle;
> -
> - Status = EFI_UNSUPPORTED;
> -
> - if(Type == DTBT_CONTROLLER) {
> - SxHandler = SxDTbtEntryCallback;
> - SwHandler = DiscreteThunderboltSwSmiCallback;
> - SmiInputValue = PcdGet8 (PcdSwSmiDTbtEnumerate);
> - gDTbtPcieRstSupport =
> gTbtInfoHob->DTbtCommonConfig.PcieRstSupport;
> - Status = EFI_SUCCESS;
> - }
> - if (EFI_ERROR (Status)) {
> - return Status;
> - }
> -
> - SwDispatchHandle = NULL;
> - S3DispatchHandle = NULL;
> - S4DispatchHandle = NULL;
> - S5DispatchHandle = NULL;
> -
> - Status = gSmst->SmmLocateProtocol (
> - &gEfiSmmSxDispatch2ProtocolGuid,
> - NULL,
> - (VOID **) &SxDispatchProtocol
> - );
> - ASSERT_EFI_ERROR (Status);
> - //
> - // Register S3 entry phase call back function
> - //
> - EntryDispatchContext.Type = SxS3;
> - EntryDispatchContext.Phase = SxEntry;
> - Status = SxDispatchProtocol->Register (
> - SxDispatchProtocol,
> - SxHandler,
> - &EntryDispatchContext,
> - &S3DispatchHandle
> - );
> - ASSERT_EFI_ERROR (Status);
> - //
> - // Register S4 entry phase call back function
> - //
> - EntryDispatchContext.Type = SxS4;
> - EntryDispatchContext.Phase = SxEntry;
> - Status = SxDispatchProtocol->Register (
> - SxDispatchProtocol,
> - SxHandler,
> - &EntryDispatchContext,
> - &S4DispatchHandle
> - );
> - ASSERT_EFI_ERROR (Status);
> - //
> - // Register S5 entry phase call back function
> - //
> - EntryDispatchContext.Type = SxS5;
> - EntryDispatchContext.Phase = SxEntry;
> - Status = SxDispatchProtocol->Register (
> - SxDispatchProtocol,
> - SxHandler,
> - &EntryDispatchContext,
> - &S5DispatchHandle
> - );
> - ASSERT_EFI_ERROR (Status);
> - //
> - // Locate the SMM SW dispatch protocol
> - //
> - Status = gSmst->SmmLocateProtocol (
> - &gEfiSmmSwDispatch2ProtocolGuid,
> - NULL,
> - (VOID **) &SwDispatch
> - );
> -
> - ASSERT_EFI_ERROR (Status);
> - //
> - // Register SWSMI handler
> - //
> - SwContext.SwSmiInputValue = SmiInputValue;
> - Status = SwDispatch->Register (
> - SwDispatch,
> - SwHandler,
> - &SwContext,
> - &SwDispatchHandle
> - );
> - ASSERT_EFI_ERROR (Status);
> -
> - return Status;
> -}
> -EFI_STATUS
> -InSmmFunction (
> - IN EFI_HANDLE ImageHandle,
> - IN EFI_SYSTEM_TABLE *SystemTable
> - )
> -{
> - EFI_STATUS Status;
> -
> - Status = EFI_SUCCESS;
> -
> - Status = TbtRegisterHandlers(DTBT_CONTROLLER);
> - return Status;
> -}
> -
> -EFI_STATUS
> -EFIAPI
> -TbtSmmEntryPoint (
> - IN EFI_HANDLE ImageHandle,
> - IN EFI_SYSTEM_TABLE *SystemTable
> - )
> -{
> - TBT_NVS_AREA_PROTOCOL *TbtNvsAreaProtocol;
> - EFI_STATUS Status;
> -
> - DEBUG ((DEBUG_INFO, "TbtSmmEntryPoint\n"));
> -
> - mPciExpressBaseAddress = PcdGet64 (PcdPciExpressBaseAddress);
> - //
> - // Locate Tbt shared data area
> - //
> - Status = gBS->LocateProtocol (&gTbtNvsAreaProtocolGuid, NULL, (VOID **)
> &TbtNvsAreaProtocol);
> - ASSERT_EFI_ERROR (Status);
> - mTbtNvsAreaPtr = TbtNvsAreaProtocol->Area;
> -
> - //
> - // Get TBT INFO HOB
> - //
> - gTbtInfoHob = (TBT_INFO_HOB *) GetFirstGuidHob (&gTbtInfoHobGuid);
> - if (gTbtInfoHob == NULL) {
> - return EFI_NOT_FOUND;
> - }
> -
> - return InSmmFunction (ImageHandle, SystemTable);
> -}
> -
> -VOID
> -EndOfThunderboltCallback (
> - IN UINTN RpSegment,
> - IN UINTN RpBus,
> - IN UINTN RpDevice,
> - IN UINTN RpFunction
> - )
> -{
> - if(mTbtNvsAreaPtr->TbtL1SubStates != 0) {
> - ThunderboltEnableL1Sub (mTbtNvsAreaPtr->TbtL1SubStates,
> RpSegment, RpBus, RpDevice, RpFunction);
> - }
> - ConfigureTbtPm(RpSegment, RpBus, RpDevice, RpFunction, 1);
> - if (!mTbtNvsAreaPtr->TbtAspm) { //Aspm disable case
> - ThunderboltDisableAspmWithoutLtr (RpSegment, RpBus, RpDevice,
> RpFunction);
> - } else { //Aspm enable case
> - ThunderboltEnableAspmWithoutLtr
> ((UINT16)mTbtNvsAreaPtr->TbtAspm, RpSegment, RpBus, RpDevice,
> RpFunction);
> - }
> -
> - if (mTbtNvsAreaPtr->TbtLtr) {
> - ThunderboltGetLatencyLtr ();
> - ThunderboltSetLatencyLtr (RpSegment, RpBus, RpDevice, RpFunction);
> - }
> - ConfigureLtr (RpSegment, RpBus, RpDevice, RpFunction);
> - ConfigureTbtPm(RpSegment, RpBus, RpDevice, RpFunction, 2);
> -} // EndOfThunderboltCallback
> -
> -VOID
> -ConfigureTbtAspm (
> - IN UINT8 Type,
> - IN UINT16 Aspm
> - )
> -{
> - UINTN RpSegment = 0;
> - UINTN RpBus = 0;
> - UINTN RpDevice;
> - UINTN RpFunction;
> -
> - if(Type == DTBT_CONTROLLER) {
> - if (gCurrentDiscreteTbtRootPort == 0) {
> - return;
> - }
> - GetDTbtRpDevFun(DTBT_CONTROLLER, gCurrentDiscreteTbtRootPort - 1,
> &RpDevice, &RpFunction);
> -
> - ConfigureTbtPm (RpSegment, RpBus, RpDevice, RpFunction, 1);
> - if (!mTbtNvsAreaPtr->TbtAspm) { //Aspm disable case
> - ThunderboltDisableAspmWithoutLtr (RpSegment, RpBus, RpDevice,
> RpFunction);
> - } else { //Aspm enable case
> - ThunderboltEnableAspmWithoutLtr ((UINT16) Aspm, RpSegment,
> RpBus, RpDevice, RpFunction);
> - }
> -
> - if (mTbtNvsAreaPtr->TbtLtr) {
> - ThunderboltGetLatencyLtr ();
> - ThunderboltSetLatencyLtr (RpSegment, RpBus, RpDevice,
> RpFunction);
> - }
> - ConfigureLtr (RpSegment, RpBus, RpDevice, RpFunction);
> - } // EndOfThunderboltCallback
> -}
> \ No newline at end of file
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGp
> ioExpanderLib.c
> b/Platform/Intel/ClevoOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGp
> ioExpanderLib.c
> deleted file mode 100644
> index cc70f15c24..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGp
> ioExpanderLib.c
> +++ /dev/null
> @@ -1,306 +0,0 @@
> -/** @file
> - Support for IO expander TCA6424.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <Library/GpioExpanderLib.h>
> -#include <Library/I2cAccessLib.h>
> -
> -//
> -// Addresses of registers inside expander
> -//
> -GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mInputRegister[3] =
> {0x0,0x1,0x2};
> -GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mOutputRegister[3] =
> {0x4,0x5,0x6};
> -GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mConfigRegister[3] =
> {0xC,0xD,0xE};
> -GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mPolarityRegister[3] =
> {0x8,0x9,0xA};
> -
> -#define PCH_SERIAL_IO_I2C4 4
> -#define TCA6424_I2C_ADDRESS 0x22
> -#define PINS_PER_REGISTER 8
> -#define GPIO_EXP_PIN_DIRECTION_OUT 1
> -#define GPIO_EXP_PIN_DIRECTION_IN 0
> -#define GPIO_EXP_PIN_POLARITY_NORMAL 0
> -#define GPIO_EXP_PIN_POLARITY_INVERTED 1
> -#define GPIO_EXP_SET_OUTPUT 0
> -#define GPIO_EXP_SET_DIR 1
> -#define GPIO_EXP_GET_INPUT 2
> -#define GPIO_EXP_SET_POLARITY 3
> -#define AUTO_INCREMENT 0x80
> -
> -/**
> - Returns the Controller on which GPIO expander is present.
> -
> - This function returns the Controller value
> -
> - @param[out] Controller Pointer to a Controller value on
> - which I2C expander is
> configured.
> -
> - @retval EFI_SUCCESS non.
> -**/
> -EFI_STATUS
> -GpioExpGetController (
> - OUT UINT8 *Controller
> - )
> -{
> - *Controller = PCH_SERIAL_IO_I2C4;
> - return EFI_SUCCESS;
> -}
> -
> -/**
> - Returns the data from register value giving in the input.
> -
> - This function is to get the data from the Expander
> - Registers by following the I2C Protocol communication
> -
> -
> - @param[in] Bar0 Bar address of the SerialIo Controller
> - @param[in] Address Expander Value with in the Contoller
> - @param[in] Register Address of Input/Output/Configure/Polarity
> - registers with in the Expander
> -
> - @retval UINT8 Value returned from the register
> -**/
> -UINT8
> -GpioExpGetRegister (
> - IN UINTN Bar0,
> - IN UINT8 Address,
> - IN UINT8 Register
> - )
> -{
> - UINT8 WriBuf[1];
> - UINT8 ReBuf[1] = {0};
> -
> - WriBuf[0] = Register;
> - I2cWriteRead (Bar0, TCA6424_I2C_ADDRESS + Address, 1, WriBuf, 1, ReBuf,
> WAIT_1_SECOND);
> -
> - return ReBuf[0];
> -}
> -/**
> - Set the input register to a give value mentioned in the function.
> -
> - This function is to Programm the data value to the Expander
> - Register by following the I2C Protocol communication.
> -
> - @param[in] Bar0 Bar address of the SerialIo Controller
> - @param[in] Address Expander Value with in the Contoller
> - @param[in] Register Address of Input/Output/Configure/Polarity
> - registers with in the Expander
> - @param[in] Value Value to set in the mentioned the register
> -**/
> -VOID
> -GpioExpSetRegister (
> - IN UINTN Bar0,
> - IN UINT8 Address,
> - IN UINT8 Register,
> - IN UINT8 Value
> - )
> -{
> - UINT8 WriBuf[2];
> -
> - WriBuf[0] = Register;
> - WriBuf[1] = Value;
> - I2cWriteRead (Bar0, TCA6424_I2C_ADDRESS + Address, 2, WriBuf, 0, NULL,
> WAIT_1_SECOND);
> -}
> -/**
> - Set the input register to a give value mentioned in the function.
> -
> - This function is to update the status of the Gpio Expander
> - pin based on the input Operation value of the caller.This
> - function calculates the exact address of the register with
> - the help of the Register Bank
> -
> - @param[in] Controller SerialIo Controller value
> - @param[in] Expander Expander Value with in the Contoller
> - @param[in] Pin Pin with in the Expnader Value
> - @param[in] Value none
> - @param[in] Operation Type of operation (Setoutput/Setdirection
> - /Getinput/Setpolarity)
> - @retval UINT8 Final Value returned from the register
> -**/
> -UINT8
> -GpioExpDecodeRegAccess (
> - IN UINT8 Controller,
> - IN UINT8 Expander,
> - IN UINT8 Pin,
> - IN UINT8 Value,
> - IN UINT8 Operation
> - )
> -{
> - UINT8* RegisterBank;
> - UINT8 OldValue;
> - UINT8 NewValue;
> - UINT8 RegisterAddress;
> - UINT8 PinNumber;
> - UINT8 ReturnValue = 0;
> -
> - DEBUG ((DEBUG_INFO, "GpioExpDecodeRegAccess() %x:%x:%x:%x:%x\n",
> Controller, Expander, Pin, Value, Operation));
> - ASSERT(Controller<6);
> - ASSERT(Expander<2);
> - ASSERT(Pin<24);
> - ASSERT(Value<2);
> - ASSERT(Operation<4);
> - //
> - // Find the register Address value based on the OPeration
> - //
> - switch(Operation) {
> - case GPIO_EXP_SET_OUTPUT:
> - RegisterBank = mOutputRegister;
> - break;
> - case GPIO_EXP_SET_DIR:
> - RegisterBank = mConfigRegister;
> - break;
> - case GPIO_EXP_GET_INPUT:
> - RegisterBank = mInputRegister;
> - break;
> - case GPIO_EXP_SET_POLARITY:
> - RegisterBank = mPolarityRegister;
> - break;
> - default:
> - ASSERT(FALSE);
> - return 0;
> - }
> - //
> - // Each bit of register represents each Pin
> - // calaulate the register address and Pinnumber(offset with in register)
> - //
> - if (Pin >= 24) {
> - //
> - // Avoid out-of-bound usage of RegisterBank
> - //
> - return 0;
> - }
> -
> - RegisterAddress = RegisterBank[(Pin/PINS_PER_REGISTER)];
> - PinNumber = Pin%PINS_PER_REGISTER;
> -
> - OldValue = GpioExpGetRegister(FindSerialIoBar(Controller, 0), Expander,
> RegisterAddress);
> - //
> - // If it to get the data ,just returned otherwise mark the input value and
> write the register
> - //
> - if (Operation == GPIO_EXP_GET_INPUT) {
> - ReturnValue = 0x1 & (OldValue>>PinNumber);
> - } else {
> - NewValue = OldValue;
> - NewValue &= ~(BIT0<<PinNumber);
> - NewValue |= (Value<<PinNumber);
> - if(NewValue!=OldValue) {
> - GpioExpSetRegister(FindSerialIoBar(Controller, 0), Expander,
> RegisterAddress, NewValue);
> - }
> - }
> - return ReturnValue;
> -}
> -/**
> - Set the Output value for the given Expander Gpio pin.
> -
> - This function is to Set the Output value for the GPIO
> - Pin within the giving Expander.
> -
> - @param[in] Expander Expander Value with in the Contoller
> - @param[in] Pin Pin with in the Expnader Value
> - @param[in] Value none
> -
> -**/
> -VOID
> -GpioExpSetOutput (
> - IN UINT8 Expander,
> - IN UINT8 Pin,
> - IN UINT8 Value
> - )
> -{
> - UINT8 Controller;
> - if(!EFI_ERROR(GpioExpGetController(&Controller))) {
> -
> GpioExpDecodeRegAccess(Controller,Expander,Pin,Value,GPIO_EXP_SET_OUT
> PUT);
> - }
> -}
> -/**
> - Set the Direction value for the given Expander Gpio pin.
> -
> - This function is to Set the direction value for the GPIO
> - Pin within the giving Expander.
> -
> - @param[in] Expander Expander Value with in the Contoller
> - @param[in] Pin Pin with in the Expnader Value
> - @param[in] Value none
> -**/
> -VOID
> -GpioExpSetDirection (
> - IN UINT8 Expander,
> - IN UINT8 Pin,
> - IN UINT8 Value
> - )
> -{
> -
> - UINT8 Controller;
> - if(!EFI_ERROR(GpioExpGetController(&Controller))) {
> -
> GpioExpDecodeRegAccess(Controller,Expander,Pin,Value,GPIO_EXP_SET_DIR);
> - }
> -}
> -
> -
> -/**
> - Get the input value for the given Expander Gpio pin.
> -
> - This function is to get the input value for the GPIO
> - Pin within the giving Expander.
> -
> - @param[in] Expander Expander Value with in the Contoller
> - @param[in] Pin Pin with in the Expnader Value
> -
> - @retval UINT8 Final Value returned from the register
> -**/
> -UINT8
> -GpioExpGetInput (
> - IN UINT8 Expander,
> - IN UINT8 Pin
> - )
> -{
> - UINT8 Controller;
> - if(!EFI_ERROR(GpioExpGetController(&Controller))) {
> - return
> GpioExpDecodeRegAccess(Controller,Expander,Pin,0,GPIO_EXP_GET_INPUT);
> - }
> - return 0;
> -}
> -
> -/**
> - Configures all registers of a single IO Expander in one go.
> -
> - @param[in] Expander Expander number (0/1)
> - @param[in] Direction Bit-encoded direction values. BIT0 is for pin0,
> etc. 0=output, 1=input
> - @param[in] Polarity Bit-encoded input inversion values. BIT0 is for
> pin0, etc. 0=normal, 1=inversion
> - @param[in] Output Bit-encoded output state, ignores polarity,
> only applicable if direction=INPUT. BIT0 is for pin0, etc. 0=low, 1=high
> -
> -**/
> -VOID
> -GpioExpBulkConfig (
> - IN UINT8 Expander,
> - IN UINT32 Direction,
> - IN UINT32 Polarity,
> - IN UINT32 Output
> - )
> -{
> - UINT8 WriteBuf[4];
> - UINT8 Controller;
> -
> - GpioExpGetController(&Controller);
> -
> - WriteBuf[0] = mOutputRegister[0] + AUTO_INCREMENT;
> - WriteBuf[1] = Output & 0xFF;
> - WriteBuf[2] = (Output>>8) & 0xFF;
> - WriteBuf[3] = (Output>>16) & 0xFF;
> - I2cWriteRead( FindSerialIoBar(Controller,0),
> TCA6424_I2C_ADDRESS+Expander, 4, WriteBuf, 0, NULL, WAIT_1_SECOND);
> - WriteBuf[0] = mPolarityRegister[0] + AUTO_INCREMENT;
> - WriteBuf[1] = Polarity & 0xFF;
> - WriteBuf[2] = (Polarity>>8) & 0xFF;
> - WriteBuf[3] = (Polarity>>16) & 0xFF;
> - I2cWriteRead( FindSerialIoBar(Controller,0),
> TCA6424_I2C_ADDRESS+Expander, 4, WriteBuf, 0, NULL, WAIT_1_SECOND);
> - WriteBuf[0] = mConfigRegister[0] + AUTO_INCREMENT;
> - WriteBuf[1] = Direction & 0xFF;
> - WriteBuf[2] = (Direction>>8) & 0xFF;
> - WriteBuf[3] = (Direction>>16) & 0xFF;
> - I2cWriteRead( FindSerialIoBar(Controller,0),
> TCA6424_I2C_ADDRESS+Expander, 4, WriteBuf, 0, NULL, WAIT_1_SECOND);
> -
> -}
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cAccessLi
> b.c
> b/Platform/Intel/ClevoOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cAccessLi
> b.c
> deleted file mode 100644
> index d66571bdc4..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cAccessLi
> b.c
> +++ /dev/null
> @@ -1,115 +0,0 @@
> -/** @file
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <Library/I2cAccessLib.h>
> -
> -EFI_STATUS
> -I2cWriteRead (
> - IN UINTN MmioBase,
> - IN UINT8 SlaveAddress,
> - IN UINT8 WriteLength,
> - IN UINT8 *WriteBuffer,
> - IN UINT8 ReadLength,
> - IN UINT8 *ReadBuffer,
> - IN UINT64 TimeBudget
> - //TODO: add Speed parameter
> - )
> -{
> - UINT8 ReadsNeeded = ReadLength;
> - UINT64 CutOffTime;
> -
> - if ((WriteLength == 0 && ReadLength == 0) ||
> - (WriteLength != 0 && WriteBuffer == NULL) ||
> - (ReadLength != 0 && ReadBuffer == NULL) ) {
> - DEBUG ((DEBUG_ERROR, "I2cWR Invalid Parameters\n"));
> - return EFI_INVALID_PARAMETER;
> - }
> -
> - //
> - // Sanity checks to verify the I2C controller is alive
> - // Conveniently, ICON register's values of 0 or FFFFFFFF indicate
> - // I2c controller is out-of-order: either disabled, in D3 or in reset.
> - //
> - if (MmioRead32(MmioBase+R_IC_CON) == 0xFFFFFFFF ||
> MmioRead32(MmioBase+R_IC_CON) == 0x0) {
> - DEBUG ((DEBUG_ERROR, "I2cWR Device Error\n"));
> - return EFI_DEVICE_ERROR;
> - }
> -
> - MmioWrite32(MmioBase+R_IC_ENABLE, 0x0);
> - MmioRead32(MmioBase+0x40);
> - MmioRead32(MmioBase+R_IC_CLR_TX_ABRT);
> - MmioWrite32(MmioBase+R_IC_SDA_HOLD, 0x001C001C);
> - //
> - // Set I2C Bus Speed at 400 kHz for GPIO Expander
> - //
> - MmioWrite32(MmioBase + R_IC_FS_SCL_HCNT, 128);
> - MmioWrite32(MmioBase + R_IC_FS_SCL_LCNT, 160);
> - MmioWrite32(MmioBase + R_IC_TAR, SlaveAddress);
> - MmioWrite32(MmioBase + R_IC_CON, B_IC_MASTER_MODE |
> V_IC_SPEED_FAST | B_IC_RESTART_EN | B_IC_SLAVE_DISABLE );
> - MmioWrite32(MmioBase+R_IC_ENABLE, 0x1);
> - CutOffTime = AsmReadTsc() + TimeBudget;
> -
> - while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)==0 ) {
> - if (AsmReadTsc() > CutOffTime) {
> - DEBUG ((DEBUG_ERROR, "I2cWR timeout\n"));
> - return EFI_TIMEOUT;
> - }
> - }
> -
> - while(1) {
> - if(MmioRead32(MmioBase+R_IC_INTR_STAT) & B_IC_INTR_TX_ABRT) {
> - DEBUG ((DEBUG_ERROR, "I2cWR Transfer aborted, reason =
> 0x%08x\n",MmioRead32(MmioBase+R_IC_TX_ABRT_SOURCE)));
> - MmioRead32(MmioBase+R_IC_CLR_TX_ABRT);
> - MmioAnd32(MmioBase+R_IC_ENABLE, 0xFFFFFFFE);
> - while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)==1 ) {}
> - return EFI_DEVICE_ERROR;
> - }
> - if (MmioRead32(MmioBase+R_IC_STATUS) & B_IC_STATUS_TFNF) {
> - if (WriteLength > 1) {
> - MmioWrite32(MmioBase+R_IC_DATA_CMD, *WriteBuffer);
> - WriteBuffer++;
> - WriteLength--;
> - } else if (WriteLength==1 && ReadLength != 0) {
> - MmioWrite32(MmioBase+R_IC_DATA_CMD, *WriteBuffer);
> - WriteBuffer++;
> - WriteLength--;
> - } else if (WriteLength==1 && ReadLength == 0) {
> - MmioWrite32(MmioBase+R_IC_DATA_CMD, *WriteBuffer |
> B_IC_CMD_STOP);
> - WriteBuffer++;
> - WriteLength--;
> - } else if (ReadLength > 1) {
> - MmioWrite32(MmioBase+R_IC_DATA_CMD, B_IC_CMD_READ);
> - ReadLength--;
> - } else if (ReadLength == 1) {
> - MmioWrite32(MmioBase+R_IC_DATA_CMD,
> B_IC_CMD_READ|B_IC_CMD_STOP);
> - ReadLength--;
> - }
> - }
> -
> - if (ReadsNeeded) {
> - if (MmioRead32(MmioBase+R_IC_STATUS) & B_IC_STATUS_RFNE) {
> - *ReadBuffer = (UINT8)MmioRead32(MmioBase+R_IC_DATA_CMD);
> - ReadBuffer++;
> - ReadsNeeded--;
> - }
> - }
> - if (WriteLength==0 && ReadsNeeded==0
> && !(MmioRead32(MmioBase+R_IC_STATUS)&B_IC_STATUS_ACTIVITY)) {
> - MmioAnd32(MmioBase+R_IC_ENABLE, 0xFFFFFFFE);
> - while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)==1 ) {}
> - DEBUG ((DEBUG_INFO, "I2cWR success\n"));
> - return EFI_SUCCESS;
> - }
> - if (AsmReadTsc() > CutOffTime) {
> - MmioAnd32(MmioBase+R_IC_ENABLE, 0xFFFFFFFE);
> - while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)==1 ) {}
> - DEBUG ((DEBUG_ERROR, "I2cWR wrong ENST value\n"));
> - return EFI_TIMEOUT;
> - }
> -
> - }
> -}
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSer
> ialPortLibSpiFlash.c
> b/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSe
> rialPortLibSpiFlash.c
> deleted file mode 100644
> index 0230149a38..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSer
> ialPortLibSpiFlash.c
> +++ /dev/null
> @@ -1,320 +0,0 @@
> -/** @file
> - Serial I/O Port library implementation for output to SPI flash
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <Base.h>
> -#include <Ppi/Spi.h>
> -#include <Library/BaseLib.h>
> -#include <Library/BaseMemoryLib.h>
> -#include <Library/HobLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/PeiServicesLib.h>
> -#include <Library/SerialPortLib.h>
> -#include <Library/SpiLib.h>
> -
> -typedef struct {
> - PCH_SPI_PPI *PchSpiPpi;
> - UINT32 CurrentWriteOffset;
> -} SPI_FLASH_DEBUG_CONTEXT;
> -
> -/**
> - Update reference to the most recent PCH SPI PPI installed
> -
> - @param PeiServices An indirect pointer to the EFI_PEI_SERVICES
> table published by the PEI Foundation
> - @param NotifyDescriptor Address of the notification descriptor data
> structure.
> - @param Ppi Address of the PPI that was installed.
> -
> - @retval EFI_SUCCESS Successfully update the PCH SPI PPI reference
> - @retval EFI_NOT_FOUND An error occurred locating a required
> interface
> - @retval EFI_NOT_SUPPORTED
> -
> -**/
> -EFI_STATUS
> -EFIAPI
> -SpiPpiNotifyCallback (
> - IN EFI_PEI_SERVICES **PeiServices,
> - IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
> - IN VOID *Ppi
> - )
> -{
> - EFI_STATUS Status;
> - EFI_HOB_GUID_TYPE *GuidHob;
> - PCH_SPI_PPI *PchSpiPpi;
> - SPI_FLASH_DEBUG_CONTEXT *Context;
> -
> - GuidHob = GetFirstGuidHob (&gSpiFlashDebugHobGuid);
> - if (GuidHob == NULL) {
> - return EFI_NOT_FOUND;
> - }
> - Context = GET_GUID_HOB_DATA (GuidHob);
> -
> - Status = PeiServicesLocatePpi (
> - &gPchSpiPpiGuid,
> - 0,
> - NULL,
> - (VOID **) &PchSpiPpi
> - );
> - if (EFI_ERROR (Status)) {
> - return EFI_NOT_FOUND;
> - }
> -
> - Context->PchSpiPpi = PchSpiPpi;
> -
> - return EFI_SUCCESS;
> -}
> -
> -EFI_PEI_NOTIFY_DESCRIPTOR mSpiPpiNotifyList[] = {
> - {
> - (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
> - &gPchSpiPpiGuid,
> - SpiPpiNotifyCallback
> - }
> -};
> -
> -/**
> - Common function to write trace data to a chosen debug interface like
> - UART Serial device, USB Serial device or Trace Hub device
> -
> - @param Buffer Point of data buffer which need to be
> writed.
> - @param NumberOfBytes Number of output bytes which are cached
> in Buffer.
> -
> -**/
> -UINTN
> -EFIAPI
> -SerialPortWrite (
> - IN UINT8 *Buffer,
> - IN UINTN NumberOfBytes
> - )
> -{
> - EFI_STATUS Status;
> - EFI_HOB_GUID_TYPE *GuidHob;
> - SPI_FLASH_DEBUG_CONTEXT *Context;
> - UINT32 BytesWritten;
> - UINT32 SourceBufferOffset;
> - UINT32 NvMessageAreaSize;
> - UINT32 LinearOffset;
> -
> - BytesWritten = NumberOfBytes;
> - SourceBufferOffset = 0;
> -
> - NvMessageAreaSize = (UINT32) FixedPcdGet32
> (PcdFlashNvDebugMessageSize);
> -
> - if (NumberOfBytes == 0 || NvMessageAreaSize == 0) {
> - return 0;
> - }
> - GuidHob = GetFirstGuidHob (&gSpiFlashDebugHobGuid);
> - if (GuidHob == NULL) {
> - return 0;
> - }
> - Context = GET_GUID_HOB_DATA (GuidHob);
> - if (Context == NULL || Context->PchSpiPpi == NULL ||
> Context->CurrentWriteOffset >= NvMessageAreaSize) {
> - return 0;
> - }
> -
> - if ((Context->CurrentWriteOffset + NumberOfBytes) / NvMessageAreaSize
> > 0) {
> - LinearOffset = (UINT32) (FixedPcdGet32
> (PcdFlashNvDebugMessageBase) - FixedPcdGet32
> (PcdFlashAreaBaseAddress));
> - Status = Context->PchSpiPpi->FlashErase (
> - Context->PchSpiPpi,
> - FlashRegionBios,
> - LinearOffset,
> - NvMessageAreaSize
> - );
> - if (!EFI_ERROR (Status)) {
> - Context->CurrentWriteOffset = 0;
> - } else {
> - return 0;
> - }
> - }
> -
> - if (NumberOfBytes > NvMessageAreaSize) {
> - BytesWritten = NvMessageAreaSize;
> - SourceBufferOffset = NumberOfBytes - NvMessageAreaSize;
> - }
> -
> - LinearOffset = (FixedPcdGet32 (PcdFlashNvDebugMessageBase) +
> Context->CurrentWriteOffset) - FixedPcdGet32 (PcdFlashAreaBaseAddress);
> -
> - Status = Context->PchSpiPpi->FlashWrite (
> - Context->PchSpiPpi,
> - FlashRegionBios,
> - LinearOffset,
> - BytesWritten,
> - (UINT8 *)
> &Buffer[SourceBufferOffset]
> - );
> - if (!EFI_ERROR (Status)) {
> - Context->CurrentWriteOffset += BytesWritten;
> - return BytesWritten;
> - }
> -
> - return 0;
> -}
> -
> -/**
> - Common function to Read data from UART serial device, USB serial
> device and save the datas in buffer.
> -
> - @param Buffer Point of data buffer which need to be
> writed.
> - @param NumberOfBytes Number of output bytes which are cached
> in Buffer.
> -
> - @retval 0 Read data failed, no data is to be read.
> - @retval >0 Actual number of bytes read from debug
> device.
> -
> -**/
> -UINTN
> -EFIAPI
> -SerialPortRead (
> - OUT UINT8 *Buffer,
> - IN UINTN NumberOfBytes
> -)
> -{
> - return 0;
> -}
> -
> -/**
> - Polls a serial device to see if there is any data waiting to be read.
> -
> - Polls a serial device to see if there is any data waiting to be read.
> - If there is data waiting to be read from the serial device, then TRUE is
> returned.
> - If there is no data waiting to be read from the serial device, then FALSE is
> returned.
> -
> - @retval TRUE Data is waiting to be read from the serial
> device.
> - @retval FALSE There is no data waiting to be read from the
> serial device.
> -
> -**/
> -BOOLEAN
> -EFIAPI
> -SerialPortPoll (
> - VOID
> - )
> -{
> - return FALSE;
> -}
> -
> -/**
> - Sets the control bits on a serial device.
> -
> - @param Control Sets the bits of Control that are
> settable.
> -
> - @retval RETURN_SUCCESS The new control bits were set on the
> serial device.
> - @retval RETURN_UNSUPPORTED The serial device does not support
> this operation.
> - @retval RETURN_DEVICE_ERROR The serial device is not functioning
> correctly.
> -
> -**/
> -RETURN_STATUS
> -EFIAPI
> -SerialPortSetControl (
> - IN UINT32 Control
> - )
> -{
> - return EFI_UNSUPPORTED;
> -}
> -
> -/**
> - Retrieve the status of the control bits on a serial device.
> -
> - @param Control A pointer to return the current
> control signals from the serial device.
> -
> - @retval RETURN_SUCCESS The control bits were read from the
> serial device.
> - @retval RETURN_UNSUPPORTED The serial device does not support
> this operation.
> - @retval RETURN_DEVICE_ERROR The serial device is not functioning
> correctly.
> -
> -**/
> -RETURN_STATUS
> -EFIAPI
> -SerialPortGetControl (
> - OUT UINT32 *Control
> - )
> -{
> - return EFI_UNSUPPORTED;
> -}
> -
> -/**
> - Sets the baud rate, receive FIFO depth, transmit/receice time out, parity,
> - data bits, and stop bits on a serial device.
> -
> - @param BaudRate The requested baud rate. A BaudRate
> value of 0 will use the
> - device's default interface speed.
> - On output, the value actually set.
> - @param ReveiveFifoDepth The requested depth of the FIFO on the
> receive side of the
> - serial interface. A ReceiveFifoDepth value
> of 0 will use
> - the device's default FIFO depth.
> - On output, the value actually set.
> - @param Timeout The requested time out for a single
> character in microseconds.
> - This timeout applies to both the transmit
> and receive side of the
> - interface. A Timeout value of 0 will use
> the device's default time
> - out value.
> - On output, the value actually set.
> - @param Parity The type of parity to use on this serial
> device. A Parity value of
> - DefaultParity will use the device's default
> parity value.
> - On output, the value actually set.
> - @param DataBits The number of data bits to use on the
> serial device. A DataBits
> - vaule of 0 will use the device's default
> data bit setting.
> - On output, the value actually set.
> - @param StopBits The number of stop bits to use on this
> serial device. A StopBits
> - value of DefaultStopBits will use the
> device's default number of
> - stop bits.
> - On output, the value actually set.
> -
> - @retval RETURN_SUCCESS The new attributes were set on
> the serial device.
> - @retval RETURN_UNSUPPORTED The serial device does not
> support this operation.
> - @retval RETURN_INVALID_PARAMETER One or more of the attributes
> has an unsupported value.
> - @retval RETURN_DEVICE_ERROR The serial device is not
> functioning correctly.
> -
> -**/
> -RETURN_STATUS
> -EFIAPI
> -SerialPortSetAttributes (
> - IN OUT UINT64 *BaudRate,
> - IN OUT UINT32 *ReceiveFifoDepth,
> - IN OUT UINT32 *Timeout,
> - IN OUT EFI_PARITY_TYPE *Parity,
> - IN OUT UINT8 *DataBits,
> - IN OUT EFI_STOP_BITS_TYPE *StopBits
> - )
> -{
> - return EFI_UNSUPPORTED;
> -}
> -
> -/**
> - Initialize the serial device hardware.
> -
> - If no initialization is required, then return RETURN_SUCCESS.
> - If the serial device was successfully initialized, then return
> RETURN_SUCCESS.
> - If the serial device could not be initialized, then return
> RETURN_DEVICE_ERROR.
> -
> - @retval RETURN_SUCCESS The serial device was initialized.
> - @retval RETURN_DEVICE_ERROR The serial device could not be
> initialized.
> -
> -**/
> -RETURN_STATUS
> -EFIAPI
> -SerialPortInitialize (
> - VOID
> - )
> -{
> - EFI_STATUS Status;
> - SPI_FLASH_DEBUG_CONTEXT *Context;
> -
> - Context = (SPI_FLASH_DEBUG_CONTEXT *) BuildGuidHob
> (&gSpiFlashDebugHobGuid, sizeof (SPI_FLASH_DEBUG_CONTEXT));
> - if (Context == NULL) {
> - return EFI_DEVICE_ERROR;
> - }
> - ZeroMem ((VOID *) Context, sizeof (SPI_FLASH_DEBUG_CONTEXT));
> -
> - Status = PeiServicesNotifyPpi (&mSpiPpiNotifyList[0]);
> - if (EFI_ERROR (Status)) {
> - return EFI_DEVICE_ERROR;
> - }
> -
> - //
> - // Perform silicon specific initialization required to enable write to SPI
> flash.
> - //
> - Status = SpiServiceInit ();
> - if (EFI_ERROR (Status)) {
> - Status = EFI_DEVICE_ERROR;
> - }
> -
> - return Status;
> -}
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilico
> nPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.c
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilic
> onPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.c
> deleted file mode 100644
> index 0fedd81cd0..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilico
> nPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.c
> +++ /dev/null
> @@ -1,103 +0,0 @@
> -/** @file
> - This library implements constructor function to register notify call back
> - when policy PPI installed.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -#include <PiPei.h>
> -#include <Library/DebugLib.h>
> -#include <Library/MemoryAllocationLib.h>
> -#include <Library/PeiServicesLib.h>
> -#include <Library/SiPolicyLib.h>
> -
> -/**
> - Callback function to update policy when policy PPI installed.
> -
> - @param[in] PeiServices General purpose services available to
> every PEIM.
> - @param[in] NotifyDescriptor The notification structure this PEIM
> registered on install.
> - @param[in] Ppi The memory discovered PPI. Not
> used.
> -
> - @retval EFI_SUCCESS Succeeds.
> - @retval Others Error code returned by
> sub-functions.
> -**/
> -EFI_STATUS
> -EFIAPI
> -SiPreMemPolicyPpiNotify (
> - IN EFI_PEI_SERVICES **PeiServices,
> - IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
> - IN VOID *Ppi
> - )
> -{
> - EFI_STATUS Status;
> - SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
> - SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;
> -
> - DEBUG ((DEBUG_INFO, "SiPreMemPolicyPpiNotify() Start\n"));
> -
> - Status = PeiServicesLocatePpi (
> - &gSiPreMemPolicyPpiGuid,
> - 0,
> - NULL,
> - (VOID **)&SiPreMemPolicyPpi
> - );
> - ASSERT_EFI_ERROR (Status);
> - if (SiPreMemPolicyPpi != NULL) {
> - //
> - // Get requisite IP Config Blocks which needs to be used here
> - //
> - Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi,
> &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig);
> - ASSERT_EFI_ERROR (Status);
> -
> - //
> - // Update SpdAddressTable policy when it is installed.
> - //
> - if (MiscPeiPreMemConfig != NULL) {
> - MiscPeiPreMemConfig->SpdAddressTable[0] = PcdGet8
> (PcdMrcSpdAddressTable0);
> - DEBUG ((DEBUG_INFO, "MiscPeiPreMemConfig->SpdAddressTable[0]
> 0x%x\n", MiscPeiPreMemConfig->SpdAddressTable[0]));
> - MiscPeiPreMemConfig->SpdAddressTable[1] = PcdGet8
> (PcdMrcSpdAddressTable1);
> - DEBUG ((DEBUG_INFO, "MiscPeiPreMemConfig->SpdAddressTable[1]
> 0x%x\n", MiscPeiPreMemConfig->SpdAddressTable[1]));
> - MiscPeiPreMemConfig->SpdAddressTable[2] = PcdGet8
> (PcdMrcSpdAddressTable2);
> - DEBUG ((DEBUG_INFO, "MiscPeiPreMemConfig->SpdAddressTable[2]
> 0x%x\n", MiscPeiPreMemConfig->SpdAddressTable[2]));
> - MiscPeiPreMemConfig->SpdAddressTable[3] = PcdGet8
> (PcdMrcSpdAddressTable3);
> - DEBUG ((DEBUG_INFO, "MiscPeiPreMemConfig->SpdAddressTable[3]
> 0x%x\n", MiscPeiPreMemConfig->SpdAddressTable[3]));
> - }
> - }
> - return Status;
> -}
> -
> -static EFI_PEI_NOTIFY_DESCRIPTOR mSiPreMemPolicyPpiNotifyList[] = {
> - {
> - EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
> - &gSiPreMemPolicyPpiGuid,
> - SiPreMemPolicyPpiNotify
> - }
> -};
> -
> -/**
> - The library constructuor.
> - The function register a policy install notify callback.
> -
> - @param[in] ImageHandle The firmware allocated handle for the
> UEFI image.
> - @param[in] SystemTable A pointer to the EFI system table.
> -
> - @retval EFI_SUCCESS The function always return
> EFI_SUCCESS for now.
> - It will ASSERT on error for debug
> version.
> -**/
> -EFI_STATUS
> -EFIAPI
> -PeiPreMemSiliconPolicyNotifyLibConstructor (
> - IN EFI_PEI_FILE_HANDLE FileHandle,
> - IN CONST EFI_PEI_SERVICES **PeiServices
> - )
> -{
> - EFI_STATUS Status;
> - //
> - // Register call back after PPI produced
> - //
> - Status = PeiServicesNotifyPpi (mSiPreMemPolicyPpiNotifyList);
> - ASSERT_EFI_ERROR (Status);
> -
> - return EFI_SUCCESS;
> -}
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilico
> nPolicyUpdateLibFsp/PcieDeviceTable.c
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilic
> onPolicyUpdateLibFsp/PcieDeviceTable.c
> deleted file mode 100644
> index 7898dc3592..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilico
> nPolicyUpdateLibFsp/PcieDeviceTable.c
> +++ /dev/null
> @@ -1,115 +0,0 @@
> -/** @file
> - Intel PCH PEI Policy initialization.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include "PeiPchPolicyUpdate.h"
> -#include <Library/BaseMemoryLib.h>
> -#include <Library/MemoryAllocationLib.h>
> -#include <Library/HobLib.h>
> -#include <Guid/GlobalVariable.h>
> -#include <Library/PchGbeLib.h>
> -#include <Library/PchInfoLib.h>
> -#include <Library/PchPcrLib.h>
> -#include <Library/PchHsioLib.h>
> -#include <Library/PchSerialIoLib.h>
> -#include <Library/PchPcieRpLib.h>
> -#include <GpioConfig.h>
> -#include <GpioPinsSklH.h>
> -#include <Library/DebugLib.h>
> -#include <Library/PchGbeLib.h>
> -
> -#define PCI_CLASS_NETWORK 0x02
> -#define PCI_CLASS_NETWORK_ETHERNET 0x00
> -#define PCI_CLASS_NETWORK_OTHER 0x80
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE
> mPcieDeviceTable[] = {
> - //
> - // Intel PRO/Wireless
> - //
> - { 0x8086, 0x422b, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0,
> 0, 0, 0, 0, 0, 0 },
> - { 0x8086, 0x422c, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0,
> 0, 0, 0, 0, 0 },
> - { 0x8086, 0x4238, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0,
> 0, 0, 0, 0, 0, 0 },
> - { 0x8086, 0x4239, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0,
> 0, 0, 0, 0, 0, 0 },
> - //
> - // Intel WiMAX/WiFi Link
> - //
> - { 0x8086, 0x0082, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0,
> 0, 0, 0, 0, 0, 0 },
> - { 0x8086, 0x0085, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0,
> 0, 0, 0, 0, 0, 0 },
> - { 0x8086, 0x0083, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0,
> 0, 0, 0, 0, 0, 0 },
> - { 0x8086, 0x0084, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0,
> 0, 0, 0, 0, 0, 0 },
> - { 0x8086, 0x0086, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0,
> 0, 0, 0, 0, 0, 0 },
> - { 0x8086, 0x0087, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0,
> 0, 0, 0, 0, 0, 0 },
> - { 0x8086, 0x0088, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0,
> 0, 0, 0, 0, 0, 0 },
> - { 0x8086, 0x0089, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0,
> 0, 0, 0, 0, 0, 0 },
> - { 0x8086, 0x008F, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0,
> 0, 0, 0, 0, 0 },
> - { 0x8086, 0x0090, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0,
> 0, 0, 0, 0, 0, 0 },
> - //
> - // Intel Crane Peak WLAN NIC
> - //
> - { 0x8086, 0x08AE, 0xff, PCI_CLASS_NETWORK,
> PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0,
> 0, 0, 0, 0 },
> - { 0x8086, 0x08AF, 0xff, PCI_CLASS_NETWORK,
> PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0,
> 0, 0, 0, 0 },
> - //
> - // Intel Crane Peak w/BT WLAN NIC
> - //
> - { 0x8086, 0x0896, 0xff, PCI_CLASS_NETWORK,
> PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0,
> 0, 0, 0, 0 },
> - { 0x8086, 0x0897, 0xff, PCI_CLASS_NETWORK,
> PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0,
> 0, 0, 0, 0 },
> - //
> - // Intel Kelsey Peak WiFi, WiMax
> - //
> - { 0x8086, 0x0885, 0xff, PCI_CLASS_NETWORK,
> PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0,
> 0, 0, 0, 0 },
> - { 0x8086, 0x0886, 0xff, PCI_CLASS_NETWORK,
> PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0,
> 0, 0, 0, 0 },
> - //
> - // Intel Centrino Wireless-N 105
> - //
> - { 0x8086, 0x0894, 0xff, PCI_CLASS_NETWORK,
> PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0,
> 0, 0, 0, 0 },
> - { 0x8086, 0x0895, 0xff, PCI_CLASS_NETWORK,
> PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0,
> 0, 0, 0, 0 },
> - //
> - // Intel Centrino Wireless-N 135
> - //
> - { 0x8086, 0x0892, 0xff, PCI_CLASS_NETWORK,
> PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0,
> 0, 0, 0, 0 },
> - { 0x8086, 0x0893, 0xff, PCI_CLASS_NETWORK,
> PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0,
> 0, 0, 0, 0 },
> - //
> - // Intel Centrino Wireless-N 2200
> - //
> - { 0x8086, 0x0890, 0xff, PCI_CLASS_NETWORK,
> PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0,
> 0, 0, 0, 0 },
> - { 0x8086, 0x0891, 0xff, PCI_CLASS_NETWORK,
> PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0,
> 0, 0, 0, 0 },
> - //
> - // Intel Centrino Wireless-N 2230
> - //
> - { 0x8086, 0x0887, 0xff, PCI_CLASS_NETWORK,
> PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0,
> 0, 0, 0, 0 },
> - { 0x8086, 0x0888, 0xff, PCI_CLASS_NETWORK,
> PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0,
> 0, 0, 0, 0 },
> - //
> - // Intel Centrino Wireless-N 6235
> - //
> - { 0x8086, 0x088E, 0xff, PCI_CLASS_NETWORK,
> PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0,
> 0, 0, 0, 0 },
> - { 0x8086, 0x088F, 0xff, PCI_CLASS_NETWORK,
> PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0,
> 0, 0, 0, 0 },
> - //
> - // Intel CampPeak 2 Wifi
> - //
> - { 0x8086, 0x08B5, 0xff, PCI_CLASS_NETWORK,
> PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0,
> 0, 0, 0, 0 },
> - { 0x8086, 0x08B6, 0xff, PCI_CLASS_NETWORK,
> PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0,
> 0, 0, 0, 0 },
> - //
> - // Intel WilkinsPeak 1 Wifi
> - //
> - { 0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK,
> PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1,
> PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 },
> - { 0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK,
> PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1,
> PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 },
> - //
> - // Intel Wilkins Peak 2 Wifi
> - //
> - { 0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK,
> PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1,
> PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 },
> - { 0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK,
> PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1,
> PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 },
> - //
> - // Intel Wilkins Peak PF Wifi
> - //
> - { 0x8086, 0x08B0, 0xff, PCI_CLASS_NETWORK,
> PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0,
> 0, 0, 0, 0 },
> -
> - //
> - // End of Table
> - //
> - { 0 }
> -};
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilico
> nPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilic
> onPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
> deleted file mode 100644
> index 9d6c0176f6..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilico
> nPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
> +++ /dev/null
> @@ -1,87 +0,0 @@
> -/** @file
> - Implementation of Fsp Misc UPD Initialization.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <PiPei.h>
> -
> -#include <Library/DebugLib.h>
> -#include <Library/PeiLib.h>
> -#include <Library/ConfigBlockLib.h>
> -
> -#include <FspEas.h>
> -#include <FspmUpd.h>
> -#include <FspsUpd.h>
> -
> -#include <Library/MemoryAllocationLib.h>
> -#include <Library/DebugLib.h>
> -#include <Library/DebugPrintErrorLevelLib.h>
> -#include <Library/PciLib.h>
> -#include <Guid/MemoryOverwriteControl.h>
> -#include <PchAccess.h>
> -
> -/**
> - Performs FSP Misc UPD initialization.
> -
> - @param[in][out] FspmUpd Pointer to FSPM_UPD Data.
> -
> - @retval EFI_SUCCESS FSP UPD Data is updated.
> -**/
> -EFI_STATUS
> -EFIAPI
> -PeiFspMiscUpdUpdatePreMem (
> - IN OUT FSPM_UPD *FspmUpd
> - )
> -{
> - EFI_STATUS Status;
> - UINTN VariableSize;
> - VOID *MemorySavedData;
> - UINT8 MorControl;
> - VOID *MorControlPtr;
> -
> - //
> - // Initialize S3 Data variable (S3DataPtr). It may be used for warm and fast
> boot paths.
> - //
> - VariableSize = 0;
> - MemorySavedData = NULL;
> - Status = PeiGetVariable (
> - L"MemoryConfig",
> - &gFspNonVolatileStorageHobGuid,
> - &MemorySavedData,
> - &VariableSize
> - );
> - DEBUG ((DEBUG_INFO, "Get L\"MemoryConfig\"
> gFspNonVolatileStorageHobGuid - %r\n", Status));
> - DEBUG ((DEBUG_INFO, "MemoryConfig Size - 0x%x\n", VariableSize));
> - FspmUpd->FspmArchUpd.NvsBufferPtr = MemorySavedData;
> -
> - if (FspmUpd->FspmArchUpd.NvsBufferPtr != NULL) {
> - //
> - // Set the DISB bit in PCH (DRAM Initialization Scratchpad Bit -
> GEN_PMCON_A[23]),
> - // after memory Data is saved to NVRAM.
> - //
> - PciOr32 ((UINTN)PCI_LIB_ADDRESS (0, PCI_DEVICE_NUMBER_PCH_PMC,
> PCI_FUNCTION_NUMBER_PCH_PMC, R_PCH_PMC_GEN_PMCON_A),
> B_PCH_PMC_GEN_PMCON_A_DISB);
> - }
> -
> - //
> - // MOR
> - //
> - MorControl = 0;
> - MorControlPtr = &MorControl;
> - VariableSize = sizeof (MorControl);
> - Status = PeiGetVariable (
> - MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME,
> - &gEfiMemoryOverwriteControlDataGuid,
> - &MorControlPtr,
> - &VariableSize
> - );
> - DEBUG ((DEBUG_INFO, "MorControl - 0x%x (%r)\n", MorControl, Status));
> - if (MOR_CLEAR_MEMORY_VALUE (MorControl)) {
> - FspmUpd->FspmConfig.CleanMemory = (BOOLEAN)(MorControl &
> MOR_CLEAR_MEMORY_BIT_MASK);
> - }
> -
> - return EFI_SUCCESS;
> -}
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilico
> nPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilic
> onPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c
> deleted file mode 100644
> index c665f7888d..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilico
> nPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c
> +++ /dev/null
> @@ -1,186 +0,0 @@
> -/** @file
> - Provides FSP policy update functionality.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <PiPei.h>
> -#include <Library/PcdLib.h>
> -#include <Library/DebugLib.h>
> -#include <Library/BaseMemoryLib.h>
> -#include <Library/MemoryAllocationLib.h>
> -#include <Library/FspWrapperApiLib.h>
> -#include <Library/SiliconPolicyUpdateLib.h>
> -
> -#include <FspEas.h>
> -#include <FspmUpd.h>
> -#include <FspsUpd.h>
> -
> -/**
> - Performs FSP Misc UPD initialization.
> -
> - @param[in][out] FspmUpd Pointer to FSPM_UPD Data.
> -
> - @retval EFI_SUCCESS FSP UPD Data is updated.
> -**/
> -EFI_STATUS
> -EFIAPI
> -PeiFspMiscUpdUpdatePreMem (
> - IN OUT FSPM_UPD *FspmUpd
> - );
> -
> -/**
> - Performs FSP PCH PEI Policy pre mem initialization.
> -
> - @param[in][out] FspmUpd Pointer to FSP UPD Data.
> -
> - @retval EFI_SUCCESS FSP UPD Data is updated.
> - @retval EFI_NOT_FOUND Fail to locate required PPI.
> - @retval Other FSP UPD Data update process
> fail.
> -**/
> -EFI_STATUS
> -EFIAPI
> -PeiFspPchPolicyUpdatePreMem (
> - IN OUT FSPM_UPD *FspmUpd
> - );
> -
> -/**
> - Performs FSP PCH PEI Policy initialization.
> -
> - @param[in][out] FspsUpd Pointer to FSP UPD Data.
> -
> - @retval EFI_SUCCESS FSP UPD Data is updated.
> - @retval EFI_NOT_FOUND Fail to locate required PPI.
> - @retval Other FSP UPD Data update process
> fail.
> -**/
> -EFI_STATUS
> -EFIAPI
> -PeiFspPchPolicyUpdate (
> - IN OUT FSPS_UPD *FspsUpd
> - );
> -
> -/**
> - Performs FSP SA PEI Policy initialization in pre-memory.
> -
> - @param[in][out] FspmUpd Pointer to FSP UPD Data.
> -
> - @retval EFI_SUCCESS FSP UPD Data is updated.
> - @retval EFI_NOT_FOUND Fail to locate required PPI.
> - @retval Other FSP UPD Data update process
> fail.
> -**/
> -EFI_STATUS
> -EFIAPI
> -PeiFspSaPolicyUpdatePreMem (
> - IN OUT FSPM_UPD *FspmUpd
> - );
> -
> -/**
> - Performs FSP SA PEI Policy initialization.
> -
> - @param[in][out] FspsUpd Pointer to FSP UPD Data.
> -
> - @retval EFI_SUCCESS FSP UPD Data is updated.
> - @retval EFI_NOT_FOUND Fail to locate required PPI.
> - @retval Other FSP UPD Data update process
> fail.
> -**/
> -EFI_STATUS
> -EFIAPI
> -PeiFspSaPolicyUpdate (
> - IN OUT FSPS_UPD *FspsUpd
> - );
> -
> -VOID
> -InternalPrintVariableData (
> - IN UINT8 *Data8,
> - IN UINTN DataSize
> - )
> -{
> - UINTN Index;
> -
> - for (Index = 0; Index < DataSize; Index++) {
> - if (Index % 0x10 == 0) {
> - DEBUG ((DEBUG_INFO, "\n%08X:", Index));
> - }
> - DEBUG ((DEBUG_INFO, " %02X", *Data8++));
> - }
> - DEBUG ((DEBUG_INFO, "\n"));
> -}
> -
> -/**
> - Performs silicon pre-mem policy update.
> -
> - The meaning of Policy is defined by silicon code.
> - It could be the raw data, a handle, a PPI, etc.
> -
> - The input Policy must be returned by SiliconPolicyDonePreMem().
> -
> - 1) In FSP path, the input Policy should be FspmUpd.
> - A platform may use this API to update the FSPM UPD policy initialized
> - by the silicon module or the default UPD data.
> - The output of FSPM UPD data from this API is the final UPD data.
> -
> - 2) In non-FSP path, the board may use additional way to get
> - the silicon policy data field based upon the input Policy.
> -
> - @param[in, out] Policy Pointer to policy.
> -
> - @return the updated policy.
> -**/
> -VOID *
> -EFIAPI
> -SiliconPolicyUpdatePreMem (
> - IN OUT VOID *FspmUpd
> - )
> -{
> - FSPM_UPD *FspmUpdDataPtr;
> -
> - FspmUpdDataPtr = FspmUpd;
> - PeiFspSaPolicyUpdatePreMem (FspmUpdDataPtr);
> - PeiFspPchPolicyUpdatePreMem (FspmUpdDataPtr);
> - PeiFspMiscUpdUpdatePreMem (FspmUpdDataPtr);
> -
> - InternalPrintVariableData ((VOID *)FspmUpdDataPtr, sizeof(FSPM_UPD));
> -
> - return FspmUpd;
> -}
> -
> -/**
> - Performs silicon post-mem policy update.
> -
> - The meaning of Policy is defined by silicon code.
> - It could be the raw data, a handle, a PPI, etc.
> -
> - The input Policy must be returned by SiliconPolicyDonePostMem().
> -
> - 1) In FSP path, the input Policy should be FspsUpd.
> - A platform may use this API to update the FSPS UPD policy initialized
> - by the silicon module or the default UPD data.
> - The output of FSPS UPD data from this API is the final UPD data.
> -
> - 2) In non-FSP path, the board may use additional way to get
> - the silicon policy data field based upon the input Policy.
> -
> - @param[in, out] Policy Pointer to policy.
> -
> - @return the updated policy.
> -**/
> -VOID *
> -EFIAPI
> -SiliconPolicyUpdatePostMem (
> - IN OUT VOID *FspsUpd
> - )
> -{
> - FSPS_UPD *FspsUpdDataPtr;
> -
> - FspsUpdDataPtr = FspsUpd;
> - PeiFspSaPolicyUpdate (FspsUpdDataPtr);
> - PeiFspPchPolicyUpdate (FspsUpdDataPtr);
> -
> - InternalPrintVariableData ((VOID *)FspsUpdDataPtr, sizeof(FSPS_UPD));
> -
> - return FspsUpd;
> -}
> -
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilico
> nPolicyUpdateLibFsp/PeiPchPolicyUpdate.c
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilic
> onPolicyUpdateLibFsp/PeiPchPolicyUpdate.c
> deleted file mode 100644
> index 0bdd51d288..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilico
> nPolicyUpdateLibFsp/PeiPchPolicyUpdate.c
> +++ /dev/null
> @@ -1,153 +0,0 @@
> -/** @file
> - Intel PCH PEI Policy initialization.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include "PeiPchPolicyUpdate.h"
> -#include <Library/BaseMemoryLib.h>
> -#include <Library/MemoryAllocationLib.h>
> -#include <Library/HobLib.h>
> -#include <Guid/GlobalVariable.h>
> -#include <Library/PchGbeLib.h>
> -#include <Library/PchInfoLib.h>
> -#include <Library/PchPcrLib.h>
> -#include <Library/PchHsioLib.h>
> -#include <Library/PchSerialIoLib.h>
> -#include <Library/PchPcieRpLib.h>
> -#include <GpioConfig.h>
> -#include <GpioPinsSklH.h>
> -#include <Library/DebugLib.h>
> -#include <Library/PchGbeLib.h>
> -
> -extern PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[];
> -
> -/**
> - Add verb table helper function.
> - This function calculates verbtable number and shows verb table
> information.
> -
> - @param[in,out] VerbTableEntryNum Input current VerbTable
> number and output the number after adding new table
> - @param[in,out] VerbTableArray Pointer to array of VerbTable
> - @param[in] VerbTable VerbTable which is going to
> add into array
> -**/
> -STATIC
> -VOID
> -InternalAddVerbTable (
> - IN OUT UINT8 *VerbTableEntryNum,
> - IN OUT UINT32 *VerbTableArray,
> - IN HDAUDIO_VERB_TABLE *VerbTable
> - )
> -{
> - if (VerbTable == NULL) {
> - DEBUG ((DEBUG_ERROR, "InternalAddVerbTable wrong input:
> VerbTable == NULL\n"));
> - return;
> - }
> -
> - VerbTableArray[*VerbTableEntryNum] = (UINT32) VerbTable;
> - *VerbTableEntryNum += 1;
> -
> - DEBUG ((DEBUG_INFO,
> - "Add verb table for vendor = 0x%04X devId = 0x%04X (size = %d
> DWords)\n",
> - VerbTable->Header.VendorId,
> - VerbTable->Header.DeviceId,
> - VerbTable->Header.DataDwords)
> - );
> -}
> -
> -enum HDAUDIO_CODEC_SELECT {
> - PchHdaCodecPlatformOnboard = 0,
> - PchHdaCodecExternalKit = 1
> -};
> -
> -/**
> - Add verb table function.
> - This function update the verb table number and verb table ptr of policy.
> -
> - @param[in] HdAudioConfig HDAudie config block
> - @param[in] CodecType Platform codec type indicator
> - @param[in] AudioConnectorType Platform audio connector type
> -**/
> -STATIC
> -VOID
> -InternalAddPlatformVerbTables (
> - IN OUT FSPS_UPD *FspsUpd,
> - IN UINT8 CodecType,
> - IN UINT8 AudioConnectorType
> - )
> -{
> - UINT8 VerbTableEntryNum;
> - UINT32 VerbTableArray[32];
> - UINT32 *VerbTablePtr;
> -
> - VerbTableEntryNum = 0;
> -
> - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *)
> (UINTN) PcdGet32 (PcdDisplayAudioHdaVerbTable));
> -
> - if (CodecType == PchHdaCodecPlatformOnboard) {
> - DEBUG ((DEBUG_INFO, "HDA Policy: Onboard codec selected\n"));
> - if ((VOID *) (UINTN) PcdGet32 (PcdExtHdaVerbTable) != NULL) {
> - if (AudioConnectorType == 0) { //Type-C Audio connector selected in
> Bios Setup menu
> - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray,
> (VOID *) (UINTN) PcdGet32 (PcdExtHdaVerbTable));
> - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray,
> NULL);
> - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray,
> NULL);
> - DEBUG ((DEBUG_INFO, "HDA: Type-C Audio connector
> selected!\n"));
> - } else { //Stacked Jack Audio connector selected in Bios Setup menu
> - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray,
> (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable));
> - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray,
> (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable2));
> - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray,
> NULL);
> - DEBUG ((DEBUG_INFO, "HDA: Stacked-Jack Audio connector
> selected!\n"));
> - }
> - } else {
> - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID
> *) (UINTN) PcdGet32 (PcdHdaVerbTable));
> - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID
> *) (UINTN) PcdGet32 (PcdHdaVerbTable2));
> - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL);
> - }
> - } else {
> - DEBUG ((DEBUG_INFO, "HDA Policy: External codec kit selected\n"));
> - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *)
> (UINTN) PcdGet32 (PcdCommonHdaVerbTable1));
> - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *)
> (UINTN) PcdGet32 (PcdCommonHdaVerbTable2));
> - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *)
> (UINTN) PcdGet32 (PcdCommonHdaVerbTable3));
> - }
> -
> - FspsUpd->FspsConfig.PchHdaVerbTableEntryNum = VerbTableEntryNum;
> -
> - VerbTablePtr = (UINT32 *) AllocateZeroPool (sizeof (UINT32) *
> VerbTableEntryNum);
> - CopyMem (VerbTablePtr, VerbTableArray, sizeof (UINT32) *
> VerbTableEntryNum);
> - FspsUpd->FspsConfig.PchHdaVerbTablePtr = (UINT32) VerbTablePtr;
> -}
> -
> -/**
> - Performs FSP PCH PEI Policy initialization.
> -
> - @param[in][out] FspsUpd Pointer to FSP UPD Data.
> -
> - @retval EFI_SUCCESS FSP UPD Data is updated.
> - @retval EFI_NOT_FOUND Fail to locate required PPI.
> - @retval Other FSP UPD Data update process
> fail.
> -**/
> -EFI_STATUS
> -EFIAPI
> -PeiFspPchPolicyUpdate (
> - IN OUT FSPS_UPD *FspsUpd
> - )
> -{
> -
> - FspsUpd->FspsConfig.PchSubSystemVendorId = V_PCH_INTEL_VENDOR_ID;
> - FspsUpd->FspsConfig.PchSubSystemId = V_PCH_DEFAULT_SID;
> -
> - FspsUpd->FspsConfig.PchPcieDeviceOverrideTablePtr = (UINT32)
> mPcieDeviceTable;
> -
> - InternalAddPlatformVerbTables (FspsUpd, PchHdaCodecPlatformOnboard,
> PcdGet8 (PcdAudioConnector));
> -
> -DEBUG_CODE_BEGIN();
> -if ((PcdGet8 (PcdSerialIoUartDebugEnable) == 1) &&
> - FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 +
> PcdGet8 (PcdSerialIoUartNumber)] == PchSerialIoDisabled ) {
> - FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 +
> PcdGet8 (PcdSerialIoUartNumber)] = PchSerialIoLegacyUart;
> - }
> -DEBUG_CODE_END();
> -
> - return EFI_SUCCESS;
> -}
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilico
> nPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilic
> onPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c
> deleted file mode 100644
> index 5a62f9bb72..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilico
> nPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c
> +++ /dev/null
> @@ -1,248 +0,0 @@
> -/** @file
> - Intel PCH PEI Policy initialization.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include "PeiPchPolicyUpdate.h"
> -#include <Library/BaseMemoryLib.h>
> -#include <Library/MemoryAllocationLib.h>
> -#include <Library/HobLib.h>
> -#include <Guid/GlobalVariable.h>
> -#include <Library/PchInfoLib.h>
> -#include <Library/PchPcrLib.h>
> -#include <Library/PchHsioLib.h>
> -#include <Library/PchPcieRpLib.h>
> -#include <PchHsioPtssTables.h>
> -#include <Library/DebugLib.h>
> -
> -VOID
> -InstallPlatformHsioPtssTable (
> - IN OUT FSPM_UPD *FspmUpd
> - )
> -{
> - HSIO_PTSS_TABLES *UnknowPtssTables;
> - HSIO_PTSS_TABLES *SpecificPtssTables;
> - HSIO_PTSS_TABLES *PtssTables;
> - UINT8 PtssTableIndex;
> - UINT32 UnknowTableSize;
> - UINT32 SpecificTableSize;
> - UINT32 TableSize;
> - UINT32 Entry;
> - UINT8 LaneNum;
> - UINT8 Index;
> - UINT8 MaxSataPorts;
> - UINT8 MaxPciePorts;
> - UINT8
> PcieTopologyReal[PCH_MAX_PCIE_ROOT_PORTS];
> - UINT8 PciePort;
> - UINTN RpBase;
> - UINTN RpDevice;
> - UINTN RpFunction;
> - UINT32 StrapFuseCfg;
> - UINT8 PcieControllerCfg;
> - EFI_STATUS Status;
> -
> - UnknowPtssTables = NULL;
> - UnknowTableSize = 0;
> - SpecificPtssTables = NULL;
> - SpecificTableSize = 0;
> -
> - if (GetPchGeneration () == SklPch) {
> - switch (PchStepping ()) {
> - case PchLpB0:
> - case PchLpB1:
> - UnknowPtssTables = (VOID *) (UINTN) PcdGet32
> (PcdUnknowLpHsioPtssTable1);
> - UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable1Size);
> - SpecificPtssTables = (VOID *) (UINTN) PcdGet32
> (PcdSpecificLpHsioPtssTable1);
> - SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable1Size);
> - break;
> - case PchLpC0:
> - case PchLpC1:
> - UnknowPtssTables = (VOID *) (UINTN) PcdGet32
> (PcdUnknowLpHsioPtssTable2);
> - UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable2Size);
> - SpecificPtssTables = (VOID *) (UINTN) PcdGet32
> (PcdSpecificLpHsioPtssTable2);
> - SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable2Size);
> - break;
> - case PchHB0:
> - case PchHC0:
> - UnknowPtssTables = (VOID *) (UINTN) PcdGet32
> (PcdUnknowHHsioPtssTable1);
> - UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable1Size);
> - SpecificPtssTables = (VOID *) (UINTN) PcdGet32
> (PcdSpecificHHsioPtssTable1);
> - SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable1Size);
> - break;
> - case PchHD0:
> - case PchHD1:
> - UnknowPtssTables = (VOID *) (UINTN) PcdGet32
> (PcdUnknowHHsioPtssTable2);
> - UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size);
> - SpecificPtssTables = (VOID *) (UINTN) PcdGet32
> (PcdSpecificHHsioPtssTable2);
> - SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size);
> - break;
> - default:
> - UnknowPtssTables = NULL;
> - UnknowTableSize = 0;
> - SpecificPtssTables = NULL;
> - SpecificTableSize = 0;
> - DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n"));
> - }
> - } else {
> - switch (PchStepping ()) {
> - case KblPchHA0:
> - UnknowPtssTables = (VOID *) (UINTN) PcdGet32
> (PcdUnknowHHsioPtssTable2);
> - UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size);
> - SpecificPtssTables = (VOID *) (UINTN) PcdGet32
> (PcdSpecificHHsioPtssTable2);
> - SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size);
> - break;
> - default:
> - UnknowPtssTables = NULL;
> - UnknowTableSize = 0;
> - SpecificPtssTables = NULL;
> - SpecificTableSize = 0;
> - DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n"));
> - }
> - }
> -
> - PtssTableIndex = 0;
> - MaxSataPorts = GetPchMaxSataPortNum ();
> - MaxPciePorts = GetPchMaxPciePortNum ();
> - ZeroMem (PcieTopologyReal, sizeof (PcieTopologyReal));
> -
> - //Populate PCIe topology based on lane configuration
> - for (PciePort = 0; PciePort < MaxPciePorts; PciePort += 4) {
> - Status = GetPchPcieRpDevFun (PciePort, &RpDevice, &RpFunction);
> - ASSERT_EFI_ERROR (Status);
> -
> - RpBase = MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH, (UINT32)
> RpDevice, (UINT32) RpFunction);
> - StrapFuseCfg = MmioRead32 (RpBase + R_PCH_PCIE_STRPFUSECFG);
> - PcieControllerCfg = (UINT8) ((StrapFuseCfg &
> B_PCH_PCIE_STRPFUSECFG_RPC) >> N_PCH_PCIE_STRPFUSECFG_RPC);
> - DEBUG ((DEBUG_INFO, "PCIE Port %d StrapFuseCfg Value = %d\n",
> PciePort, PcieControllerCfg));
> - }
> - for (Index = 0; Index < MaxPciePorts; Index++) {
> - DEBUG ((DEBUG_INFO, "PCIE PTSS Assigned RP %d Topology = %d\n",
> Index, PcieTopologyReal[Index]));
> - }
> -
> - //Case 1: BoardId is known, Topology is known/unknown
> - //Case 1a: SATA
> - PtssTables = SpecificPtssTables;
> - TableSize = SpecificTableSize;
> - for (Index = 0; Index < MaxSataPorts; Index++) {
> - if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
> - for (Entry = 0; Entry < TableSize; Entry++) {
> - if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
> - (PtssTables[Entry].PtssTable.PhyMode ==
> V_PCH_PCR_FIA_LANE_OWN_SATA)
> - )
> - {
> - PtssTableIndex++;
> - if ((PtssTables[Entry].PtssTable.Offset == (UINT32)
> R_PCH_HSIO_RX_DWORD20) &&
> - (((UINT32) ~PtssTables[Entry].PtssTable.BitMask &
> B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32)
> B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) {
> -
> FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] =
> TRUE;
> - FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index]
> = (PtssTables[Entry].PtssTable.Value & (UINT32)
> ~PtssTables[Entry].PtssTable.BitMask) >>
> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0;
> - } else if ((PtssTables[Entry].PtssTable.Offset == (UINT32)
> R_PCH_HSIO_TX_DWORD8)) {
> - if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32)
> B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32)
> B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) {
> -
> FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Index] =
> TRUE;
> -
> FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] =
> (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32)
> B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >>
> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0);
> - }
> - if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32)
> B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32)
> B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) {
> -
> FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Index] =
> TRUE;
> -
> FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] =
> (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32)
> B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >>
> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0);
> - }
> - } else {
> - ASSERT (FALSE);
> - }
> - }
> - }
> - }
> - }
> - //Case 1b: PCIe
> - for (Index = 0; Index < MaxPciePorts; Index++) {
> - if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
> - for (Entry = 0; Entry < TableSize; Entry++) {
> - if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
> - (PtssTables[Entry].PtssTable.PhyMode ==
> V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) &&
> - (PcieTopologyReal[Index] == PtssTables[Entry].Topology)) {
> - PtssTableIndex++;
> - if ((PtssTables[Entry].PtssTable.Offset == (UINT32)
> R_PCH_HSIO_RX_DWORD25) &&
> - (((UINT32) ~PtssTables[Entry].PtssTable.BitMask &
> B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32)
> B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) {
> - FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] =
> TRUE;
> - FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] =
> (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32)
> ~PtssTables[Entry].PtssTable.BitMask) >>
> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0);
> - } else {
> - ASSERT (FALSE);
> - }
> - }
> - }
> - }
> - }
> - //Case 2: BoardId is unknown, Topology is known/unknown
> - if (PtssTableIndex == 0) {
> - DEBUG ((DEBUG_INFO, "PTSS Settings for unknown board will be
> applied\n"));
> -
> - PtssTables = UnknowPtssTables;
> - TableSize = UnknowTableSize;
> -
> - for (Index = 0; Index < MaxSataPorts; Index++) {
> - if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
> - for (Entry = 0; Entry < TableSize; Entry++) {
> - if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
> - (PtssTables[Entry].PtssTable.PhyMode ==
> V_PCH_PCR_FIA_LANE_OWN_SATA)
> - )
> - {
> - if ((PtssTables[Entry].PtssTable.Offset == (UINT32)
> R_PCH_HSIO_RX_DWORD20) &&
> - (((UINT32) ~PtssTables[Entry].PtssTable.BitMask &
> B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32)
> B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) {
> -
> FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] =
> TRUE;
> -
> FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] =
> (PtssTables[Entry].PtssTable.Value & (UINT32)
> ~PtssTables[Entry].PtssTable.BitMask) >>
> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0;
> - } else if (PtssTables[Entry].PtssTable.Offset == (UINT32)
> R_PCH_HSIO_TX_DWORD8) {
> - if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask &
> (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32)
> B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) {
> -
> FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Index] =
> TRUE;
> -
> FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] =
> (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32)
> B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >>
> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0);
> - }
> - if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask &
> (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32)
> B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) {
> -
> FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Index] =
> TRUE;
> -
> FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] =
> (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32)
> B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >>
> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0);
> - }
> - } else {
> - ASSERT (FALSE);
> - }
> - }
> - }
> - }
> - }
> - for (Index = 0; Index < MaxPciePorts; Index++) {
> - if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
> - for (Entry = 0; Entry < TableSize; Entry++) {
> - if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
> - (PtssTables[Entry].PtssTable.PhyMode ==
> V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) &&
> - (PcieTopologyReal[Index] == PtssTables[Entry].Topology)) {
> - if ((PtssTables[Entry].PtssTable.Offset == (UINT32)
> R_PCH_HSIO_RX_DWORD25) &&
> - (((UINT32) ~PtssTables[Entry].PtssTable.BitMask &
> B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32)
> B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) {
> - FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index]
> = TRUE;
> - FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] =
> (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32)
> ~PtssTables[Entry].PtssTable.BitMask) >>
> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0);
> - } else {
> - ASSERT (FALSE);
> - }
> - }
> - }
> - }
> - }
> - }
> -}
> -
> -/**
> - Performs FSP PCH PEI Policy pre mem initialization.
> -
> - @param[in][out] FspmUpd Pointer to FSP UPD Data.
> -
> - @retval EFI_SUCCESS FSP UPD Data is updated.
> - @retval EFI_NOT_FOUND Fail to locate required PPI.
> - @retval Other FSP UPD Data update process
> fail.
> -**/
> -EFI_STATUS
> -EFIAPI
> -PeiFspPchPolicyUpdatePreMem (
> - IN OUT FSPM_UPD *FspmUpd
> - )
> -{
> - InstallPlatformHsioPtssTable (FspmUpd);
> - return EFI_SUCCESS;
> -}
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilico
> nPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilic
> onPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
> deleted file mode 100644
> index 133b8c963f..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilico
> nPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
> +++ /dev/null
> @@ -1,84 +0,0 @@
> -/** @file
> - Intel System Agent policy initialization.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include "PeiSaPolicyUpdate.h"
> -#include <Guid/MemoryTypeInformation.h>
> -#include <Library/HobLib.h>
> -#include <PchAccess.h>
> -#include <SaAccess.h>
> -#include <Pi/PiFirmwareFile.h>
> -#include <Pi/PiPeiCis.h>
> -#include <Library/BaseMemoryLib.h>
> -#include <Library/MemoryAllocationLib.h>
> -#include <Library/PeiSaPolicyLib.h>
> -#include <Library/PeiLib.h>
> -
> -/**
> - Performs FSP SA PEI Policy initialization.
> -
> - @param[in][out] FspsUpd Pointer to FSP UPD Data.
> -
> - @retval EFI_SUCCESS FSP UPD Data is updated.
> - @retval EFI_NOT_FOUND Fail to locate required PPI.
> - @retval Other FSP UPD Data update process
> fail.
> -**/
> -EFI_STATUS
> -EFIAPI
> -PeiFspSaPolicyUpdate (
> - IN OUT FSPS_UPD *FspsUpd
> - )
> -{
> - VOID *Buffer;
> - VOID *MemBuffer;
> - UINT32 Size;
> -
> - DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n"));
> -
> - FspsUpd->FspsConfig.PeiGraphicsPeimInit = 1;
> -
> - Size = 0;
> - Buffer = NULL;
> - PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid),
> EFI_SECTION_RAW, 0, &Buffer, &Size);
> - if (Buffer == NULL) {
> - DEBUG((DEBUG_WARN, "Could not locate VBT\n"));
> - } else {
> - MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES
> ((UINTN)Size));
> - if ((MemBuffer != NULL) && (Buffer != NULL)) {
> - CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
> - FspsUpd->FspsConfig.GraphicsConfigPtr =
> (UINT32)(UINTN)MemBuffer;
> - } else {
> - DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n"));
> - FspsUpd->FspsConfig.GraphicsConfigPtr = 0;
> - }
> - }
> - DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is
> 0x%x\n", FspsUpd->FspsConfig.GraphicsConfigPtr));
> - DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n",
> Size));
> -
> - Size = 0;
> - Buffer = NULL;
> - PeiGetSectionFromAnyFv (&gTianoLogoGuid, EFI_SECTION_RAW, 0,
> &Buffer, &Size);
> - if (Buffer == NULL) {
> - DEBUG((DEBUG_WARN, "Could not locate Logo\n"));
> - } else {
> - MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES
> ((UINTN)Size));
> - if ((MemBuffer != NULL) && (Buffer != NULL)) {
> - CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
> - FspsUpd->FspsConfig.LogoPtr = (UINT32)(UINTN)MemBuffer;
> - FspsUpd->FspsConfig.LogoSize = Size;
> - } else {
> - DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n"));
> - FspsUpd->FspsConfig.LogoPtr = 0;
> - FspsUpd->FspsConfig.LogoSize = 0;
> - }
> - }
> - DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n",
> FspsUpd->FspsConfig.LogoPtr));
> - DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n",
> FspsUpd->FspsConfig.LogoSize));
> -
> - return EFI_SUCCESS;
> -}
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilico
> nPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilic
> onPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c
> deleted file mode 100644
> index 93d79c2313..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilico
> nPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c
> +++ /dev/null
> @@ -1,75 +0,0 @@
> -/** @file
> - Intel System Agent policy initialization.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include "PeiSaPolicyUpdate.h"
> -#include <CpuRegs.h>
> -#include <Library/CpuPlatformLib.h>
> -#include <Guid/MemoryTypeInformation.h>
> -#include <Guid/MemoryOverwriteControl.h>
> -#include <Library/HobLib.h>
> -#include <PchAccess.h>
> -#include <SaAccess.h>
> -#include <Library/CpuMailboxLib.h>
> -#include <Library/BaseMemoryLib.h>
> -#include <Library/MemoryAllocationLib.h>
> -#include <Library/PeiSaPolicyLib.h>
> -#include <Library/GpioLib.h>
> -#include <GpioPinsSklH.h>
> -
> -
> -/**
> - Performs FSP SA PEI Policy initialization in pre-memory.
> -
> - @param[in][out] FspmUpd Pointer to FSP UPD Data.
> -
> - @retval EFI_SUCCESS FSP UPD Data is updated.
> - @retval EFI_NOT_FOUND Fail to locate required PPI.
> - @retval Other FSP UPD Data update process
> fail.
> -**/
> -EFI_STATUS
> -EFIAPI
> -PeiFspSaPolicyUpdatePreMem (
> - IN OUT FSPM_UPD *FspmUpd
> - )
> -{
> - VOID *Buffer;
> -
> -//
> -// Update UPD:DqPinsInterleaved
> -//
> - FspmUpd->FspmConfig.DqPinsInterleaved =
> (UINT8)PcdGetBool(PcdMrcDqPinsInterleaved);
> -
> - //
> - // Update UPD:DqPinsInterleaved
> - //
> - FspmUpd->FspmConfig.CaVrefConfig = PcdGet8(PcdMrcCaVrefConfig);
> -
> - DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling
> Settings...\n"));
> - Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap);
> - if (Buffer) {
> - CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh0, Buffer, 12);
> - CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh1, (UINT8*)
> Buffer + 12, 12);
> - }
> - Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram);
> - if (Buffer) {
> - CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh0,
> Buffer, 8);
> - CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh1,
> (UINT8*) Buffer + 8, 8);
> - }
> -
> - DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor &
> Rcomp Target Settings...\n"));
> - Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor);
> - if (Buffer) {
> - CopyMem ((VOID *)FspmUpd->FspmConfig.RcompResistor, Buffer, 6);
> - }
> - Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget);
> - if (Buffer) {
> - CopyMem ((VOID *)FspmUpd->FspmConfig.RcompTarget, Buffer, 10);
> - }
> - return EFI_SUCCESS;
> -}
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BasePlatformHookLib
> /BasePlatformHookLib.c
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BasePlatformHookLi
> b/BasePlatformHookLib.c
> deleted file mode 100644
> index 5c5d6a25b4..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BasePlatformHookLib
> /BasePlatformHookLib.c
> +++ /dev/null
> @@ -1,662 +0,0 @@
> -/** @file
> - Platform Hook Library
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <Base.h>
> -#include <Uefi/UefiBaseType.h>
> -#include <Library/PlatformHookLib.h>
> -#include <Library/BaseLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/PciLib.h>
> -#include <Library/PcdLib.h>
> -#include <SystemAgent/Include/SaAccess.h>
> -#include <SioRegs.h>
> -#include <Library/MmPciLib.h>
> -#include <Library/PchCycleDecodingLib.h>
> -#include <Register/PchRegsLpc.h>
> -#include <PchAccess.h>
> -
> -#define COM1_BASE 0x3f8
> -#define COM2_BASE 0x2f8
> -
> -#define SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS 0x0690
> -
> -#define LPC_SIO_INDEX_DEFAULT_PORT_2 0x2E
> -#define LPC_SIO_DATA_DEFAULT_PORT_2 0x2F
> -#define LPC_SIO_GPIO_REGISTER_ADDRESS_2 0x0A20
> -
> -#define LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT 0x2E
> -#define LEGACY_DAUGHTER_CARD_SIO_DATA_PORT 0x2F
> -#define LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT 0x4E
> -#define LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT 0x4F
> -
> -typedef struct {
> - UINT8 Register;
> - UINT8 Value;
> -} EFI_SIO_TABLE;
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTable[] = {
> - {0x002, 0x88}, // Power On UARTs
> - {0x024, COM1_BASE >> 2},
> - {0x025, COM2_BASE >> 2},
> - {0x028, 0x043}, // IRQ of UARTs, UART2 IRQ=3,UART1 IRQ=4,
> - {0x029, 0x080}, // SIRQ_CLKRUN_EN
> - {0x02A, 0x000},
> - {0x02B, 0x0DE},
> - {0x00A, 0x040},
> - {0x00C, 0x00E},
> - {0x02c, 0x002},
> - {0x030, FixedPcdGet16 (PcdSioBaseAddress) >> 4},
> - {0x03b, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS >> 8},
> - {0x03c, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS & 0xff},
> - {0x03a, 0x00A}, // LPC Docking Enabling
> - {0x031, 0x01f},
> - {0x032, 0x000},
> - {0x033, 0x004},
> - {0x038, 0x0FB},
> - {0x035, 0x0FE},
> - {0x036, 0x000},
> - {0x037, 0x0FF},
> - {0x039, 0x000},
> - {0x034, 0x001},
> - {0x012, FixedPcdGet16 (PcdLpcSioConfigDefaultPort) & 0xFF},
> // Relocate configuration ports base address
> - {0x013, (FixedPcdGet16 (PcdLpcSioConfigDefaultPort) >> 8) & 0xFF}
> // to ensure SIO config address can be accessed in OS
> -};
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableSmsc1000[]
> = {
> - {0x002, 0x88}, // Power On UARTs
> - {0x007, 0x00},
> - {0x024, COM1_BASE >> 2},
> - {0x025, COM2_BASE >> 2},
> - {0x028, 0x043}, // IRQ of UARTs, UART2 IRQ=3,UART1 IRQ=4,
> - {0x029, 0x080}, // SIRQ_CLKRUN_EN
> - {0x02A, 0x000},
> - {0x02B, 0x0DE},
> - {0x00A, 0x040},
> - {0x00C, 0x00E},
> - {0x030, FixedPcdGet16 (PcdSioBaseAddress) >> 4},
> - {0x03b, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS >> 8},
> - {0x03c, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS & 0xff},
> - {0x03a, 0x00A}, // LPC Docking Enabling
> - {0x031, 0x01f},
> - {0x032, 0x000},
> - {0x033, 0x004},
> - {0x038, 0x0FB},
> - {0x035, 0x0FE},
> - {0x036, 0x000},
> - {0x037, 0x0FE},
> - {0x039, 0x000},
> - {0x034, 0x001}
> -};
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableWpcn381u[]
> = {
> - {0x29, 0x0A0}, // Enable super I/O clock and set to
> 48MHz
> - {0x22, 0x003}, //
> - {0x07, 0x003}, // Select UART0 device
> - {0x60, (COM1_BASE >> 8)}, // Set Base Address MSB
> - {0x61, (COM1_BASE & 0x00FF)}, // Set Base Address LSB
> - {0x70, 0x004}, // Set to IRQ4
> - {0x30, 0x001}, // Enable it with Activation bit
> - {0x07, 0x002}, // Select UART1 device
> - {0x60, (COM2_BASE >> 8)}, // Set Base Address MSB
> - {0x61, (COM2_BASE & 0x00FF)}, // Set Base Address LSB
> - {0x70, 0x003}, // Set to IRQ3
> - {0x30, 0x001}, // Enable it with Activation bit
> - {0x07, 0x007}, // Select GPIO device
> - {0x60, (LPC_SIO_GPIO_REGISTER_ADDRESS_2 >> 8)}, // Set Base
> Address MSB
> - {0x61, (LPC_SIO_GPIO_REGISTER_ADDRESS_2 & 0x00FF)}, // Set Base
> Address LSB
> - {0x30, 0x001}, // Enable it with Activation bit
> - {0x21, 0x001}, // Global Device Enable
> - {0x26, 0x000} // Fast Enable UART 0 & 1 as their
> enable & activation bit
> -};
> -
> -//
> -// National PC8374L
> -//
> -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mDesktopSioTable[] = {
> - {0x007, 0x03}, // Select Com1
> - {0x061, 0xF8}, // 0x3F8
> - {0x060, 0x03}, // 0x3F8
> - {0x070, 0x04}, // IRQ4
> - {0x030, 0x01} // Active
> -};
> -
> -//
> -// IT8628
> -//
> -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE
> mSioIt8628TableSerialPort[] = {
> - {0x023, 0x09}, // Clock Selection register
> - {0x007, 0x01}, // Com1 Logical Device Number select
> - {0x061, 0xF8}, // Serial Port 1 Base Address MSB Register
> - {0x060, 0x03}, // Serial Port 1 Base Address LSB Register
> - {0x070, 0x04}, // Serial Port 1 Interrupt Level Select
> - {0x030, 0x01}, // Serial Port 1 Activate
> - {0x007, 0x02}, // Com1 Logical Device Number select
> - {0x061, 0xF8}, // Serial Port 2 Base Address MSB Register
> - {0x060, 0x02}, // Serial Port 2 Base Address MSB Register
> - {0x070, 0x03}, // Serial Port 2 Interrupt Level Select
> - {0x030, 0x01} // Serial Port 2 Activate
> -};
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE
> mSioIt8628TableParallelPort[] = {
> - {0x007, 0x03}, // Parallel Port Logical Device Number select
> - {0x030, 0x00}, // Parallel port Activate
> - {0x061, 0x78}, // Parallel Port Base Address 1 MSB Register
> - {0x060, 0x03}, // Parallel Port Base Address 1 LSB Register
> - {0x063, 0x78}, // Parallel Port Base Address 2 MSB Register
> - {0x062, 0x07}, // Parallel Port Base Address 1 LSB Register
> - {0x0F0, 0x03} // Special Configuration register
> -};
> -
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE
> mSioTableWinbondX374[] = {
> - {0x07, 0x03}, // Select UART0 device
> - {0x60, (COM1_BASE >> 8)}, // Set Base Address MSB
> - {0x61, (COM1_BASE & 0x00FF)}, // Set Base Address LSB
> - {0x70, 0x04}, // Set to IRQ4
> - {0x30, 0x01} // Enable it with Activation bit
> -};
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTablePilot3[] = {
> - {0x07, 0x02}, // Set logical device SP Serial port Com0
> - {0x61, 0xF8}, // Write Base Address LSB register 0x3F8
> - {0x60, 0x03}, // Write Base Address MSB register 0x3F8
> - {0x70, 0x04}, // Write IRQ1 value (IRQ 1) keyboard
> - {0x30, 0x01} // Enable serial port with Activation bit
> -};
> -
> -/**
> - Detect if a National 393 SIO is docked. If yes, enable the docked SIO
> - and its serial port, and disable the onboard serial port.
> -
> - @retval EFI_SUCCESS Operations performed successfully.
> -**/
> -STATIC
> -VOID
> -CheckNationalSio (
> - VOID
> - )
> -{
> - UINT8 Data8;
> -
> - //
> - // Pc87393 access is through either (0x2e, 0x2f) or (0x4e, 0x4f).
> - // We use (0x2e, 0x2f) which is determined by BADD default strapping
> - //
> -
> - //
> - // Read the Pc87393 signature
> - //
> - IoWrite8 (0x2e, 0x20);
> - Data8 = IoRead8 (0x2f);
> -
> - if (Data8 == 0xea) {
> - //
> - // Signature matches - National PC87393 SIO is docked
> - //
> -
> - //
> - // Enlarge the LPC decode scope to accommodate the Docking LPC
> Switch
> - // Register (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS is
> allocated at
> - // SIO_BASE_ADDRESS + 0x10)
> - //
> - PchLpcGenIoRangeSet ((FixedPcdGet16 (PcdSioBaseAddress) &
> (UINT16)~0x7F), 0x20);
> -
> - //
> - // Enable port switch
> - //
> - IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x06);
> -
> - //
> - // Turn on docking power
> - //
> - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x8c);
> -
> - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x9c);
> -
> - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0xBc);
> -
> - //
> - // Enable port switch
> - //
> - IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x7);
> -
> - //
> - // GPIO setting
> - //
> - IoWrite8 (0x2e, 0x24);
> - IoWrite8 (0x2f, 0x29);
> -
> - //
> - // Enable chip clock
> - //
> - IoWrite8 (0x2e, 0x29);
> - IoWrite8 (0x2f, 0x1e);
> -
> -
> - //
> - // Enable serial port
> - //
> -
> - //
> - // Select com1
> - //
> - IoWrite8 (0x2e, 0x7);
> - IoWrite8 (0x2f, 0x3);
> -
> - //
> - // Base address: 0x3f8
> - //
> - IoWrite8 (0x2e, 0x60);
> - IoWrite8 (0x2f, 0x03);
> - IoWrite8 (0x2e, 0x61);
> - IoWrite8 (0x2f, 0xf8);
> -
> - //
> - // Interrupt: 4
> - //
> - IoWrite8 (0x2e, 0x70);
> - IoWrite8 (0x2f, 0x04);
> -
> - //
> - // Enable bank selection
> - //
> - IoWrite8 (0x2e, 0xf0);
> - IoWrite8 (0x2f, 0x82);
> -
> - //
> - // Activate
> - //
> - IoWrite8 (0x2e, 0x30);
> - IoWrite8 (0x2f, 0x01);
> -
> - //
> - // Disable onboard serial port
> - //
> - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0x55);
> -
> - //
> - // Power Down UARTs
> - //
> - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x2);
> - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x00);
> -
> - //
> - // Dissable COM1 decode
> - //
> - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x24);
> - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0);
> -
> - //
> - // Disable COM2 decode
> - //
> - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x25);
> - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0);
> -
> - //
> - // Disable interrupt
> - //
> - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x28);
> - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x0);
> -
> - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA);
> -
> - //
> - // Enable floppy
> - //
> -
> - //
> - // Select floppy
> - //
> - IoWrite8 (0x2e, 0x7);
> - IoWrite8 (0x2f, 0x0);
> -
> - //
> - // Base address: 0x3f0
> - //
> - IoWrite8 (0x2e, 0x60);
> - IoWrite8 (0x2f, 0x03);
> - IoWrite8 (0x2e, 0x61);
> - IoWrite8 (0x2f, 0xf0);
> -
> - //
> - // Interrupt: 6
> - //
> - IoWrite8 (0x2e, 0x70);
> - IoWrite8 (0x2f, 0x06);
> -
> - //
> - // DMA 2
> - //
> - IoWrite8 (0x2e, 0x74);
> - IoWrite8 (0x2f, 0x02);
> -
> - //
> - // Activate
> - //
> - IoWrite8 (0x2e, 0x30);
> - IoWrite8 (0x2f, 0x01);
> -
> - } else {
> -
> - //
> - // No National pc87393 SIO is docked, turn off dock power and
> - // disable port switch
> - //
> - // IoWrite8 (SIO_BASE_ADDRESS + 0x0E, 0xbf);
> - // IoWrite8 (0x690, 0);
> -
> - //
> - // If no National pc87393, just return
> - //
> - return;
> - }
> -}
> -
> -
> -/**
> -Check whether the IT8628 SIO present on LPC. If yes, enable its serial
> -ports, parallel port, and port 80.
> -
> - at retval EFI_SUCCESS Operations performed successfully.
> -**/
> -STATIC
> -VOID
> -It8628SioSerialPortInit (
> - VOID
> - )
> -{
> - UINT8 ChipId0 = 0;
> - UINT8 ChipId1 = 0;
> - UINT16 LpcIoDecondeRangeSet = 0;
> - UINT16 LpcIoDecoodeSet = 0;
> - UINT8 Index;
> - UINTN LpcBaseAddr;
> -
> -
> - //
> - // Enable I/O decoding for COM1 (3F8h-3FFh), COM2(2F8h-2FFh), I/O port
> 2Eh/2Fh.
> - //
> - LpcBaseAddr = MmPciBase (
> - DEFAULT_PCI_BUS_NUMBER_PCH,
> - PCI_DEVICE_NUMBER_PCH_LPC,
> - PCI_FUNCTION_NUMBER_PCH_LPC
> - );
> -
> - LpcIoDecondeRangeSet = (UINT16) MmioRead16 (LpcBaseAddr +
> R_PCH_LPC_IOD);
> - LpcIoDecoodeSet = (UINT16) MmioRead16 (LpcBaseAddr +
> R_PCH_LPC_IOE);
> - MmioWrite16 ((LpcBaseAddr + R_PCH_LPC_IOD), (LpcIoDecondeRangeSet
> | ((V_PCH_LPC_IOD_COMB_2F8 << 4) | V_PCH_LPC_IOD_COMA_3F8)));
> - MmioWrite16 ((LpcBaseAddr + R_PCH_LPC_IOE), (LpcIoDecoodeSet |
> (B_PCH_LPC_IOE_SE | B_PCH_LPC_IOE_CBE | B_PCH_LPC_IOE_CAE)));
> -
> - //
> - // Enter MB PnP Mode
> - //
> - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x87);
> - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x01);
> - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x55);
> - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x55);
> -
> - //
> - // Read Chip Id of SIO IT8628 (registers 0x20 and 0x21)
> - //
> - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x20);
> - ChipId0 = IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2);
> -
> - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x21);
> - ChipId1 = IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2);
> -
> - //
> - // Enable Serial Port 1, Port 2
> - //
> - if ((ChipId0 == 0x86) && (ChipId1 == 0x28)) {
> - for (Index = 0; Index < sizeof (mSioIt8628TableSerialPort) / sizeof
> (EFI_SIO_TABLE); Index++) {
> - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2,
> mSioIt8628TableSerialPort[Index].Register);
> - IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2,
> mSioIt8628TableSerialPort[Index].Value);
> - }
> - }
> -
> - //
> - // Exit MB PnP Mode
> - //
> - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x02);
> - IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, 0x02);
> -
> - return;
> -}
> -
> -
> -/**
> - Performs platform specific initialization required for the CPU to access
> - the hardware associated with a SerialPortLib instance. This function
> does
> - not initialize the serial port hardware itself. Instead, it initializes
> - hardware devices that are required for the CPU to access the serial port
> - hardware. This function may be called more than once.
> -
> - @retval RETURN_SUCCESS The platform specific initialization
> succeeded.
> - @retval RETURN_DEVICE_ERROR The platform specific initialization
> could not be completed.
> -
> -**/
> -RETURN_STATUS
> -EFIAPI
> -PlatformHookSerialPortInitialize (
> - VOID
> - )
> -{
> - UINT16 ConfigPort;
> - UINT16 IndexPort;
> - UINT16 DataPort;
> - UINT16 DeviceId;
> - UINT8 Index;
> - UINT16 AcpiBase;
> -
> - //
> - // Set the ICH ACPI Base Address (Reg#40h) and ACPI Enable bit
> - // in ACPI Controll (Reg#44h bit7) for PrePpiStall function use.
> - //
> - IndexPort = 0;
> - DataPort = 0;
> - Index = 0;
> - AcpiBase = 0;
> - PchAcpiBaseGet (&AcpiBase);
> - if (AcpiBase == 0) {
> - PchAcpiBaseSet (PcdGet16 (PcdAcpiBaseAddress));
> - }
> -
> - //
> - // Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port
> 2Eh/2Fh, 4Eh/4Fh, 60h/64Fh and 62h/66h.
> - //
> - PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange));
> - PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding));
> -
> - // Configure Sio IT8628
> - It8628SioSerialPortInit ();
> -
> - DeviceId = MmioRead16 (MmPciBase (SA_MC_BUS, 0, 0) +
> R_SA_MC_DEVICE_ID);
> - if (IS_SA_DEVICE_ID_MOBILE (DeviceId)) {
> - //
> - // if no EC, it is SV Bidwell Bar board
> - //
> - if ((IoRead8 (0x66) != 0xFF) && (IoRead8 (0x62) != 0xFF)) {
> - //
> - // Super I/O initialization for SMSC SI1007
> - //
> - ConfigPort = FixedPcdGet16 (PcdLpcSioConfigDefaultPort);
> - DataPort = PcdGet16 (PcdLpcSioDataDefaultPort);
> - IndexPort = PcdGet16 (PcdLpcSioIndexDefaultPort);
> -
> - //
> - // 128 Byte Boundary and SIO Runtime Register Range is 0x0 to 0xF;
> - //
> - PchLpcGenIoRangeSet (FixedPcdGet16 (PcdSioBaseAddress) &
> (~0x7F), 0x10);
> -
> - //
> - // Program and Enable Default Super IO Configuration Port
> Addresses and range
> - //
> - PchLpcGenIoRangeSet (FixedPcdGet16 (PcdLpcSioConfigDefaultPort)
> & (~0xF), 0x10);
> -
> - //
> - // Enter Config Mode
> - //
> - IoWrite8 (ConfigPort, 0x55);
> -
> - //
> - // Check for SMSC SIO1007
> - //
> - IoWrite8 (IndexPort, 0x0D); // SMSC SIO1007 Device ID register is
> 0x0D
> - if (IoRead8 (DataPort) == 0x20) { // SMSC SIO1007 Device ID is
> 0x20
> - //
> - // Configure SIO
> - //
> - for (Index = 0; Index < sizeof (mSioTable) / sizeof (EFI_SIO_TABLE);
> Index++) {
> - IoWrite8 (IndexPort, mSioTable[Index].Register);
> - IoWrite8 (DataPort, mSioTable[Index].Value);
> - }
> -
> - //
> - // Exit Config Mode
> - //
> - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA);
> -
> - //
> - // GPIO 15-17:IN 10-14:OUT Enable RS232 ref: Page42 of
> CRB_SCH
> - //
> - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0c, 0x1f);
> - }
> -
> - //
> - // Check if a National Pc87393 SIO is docked
> - //
> - CheckNationalSio ();
> -
> - //
> - // Super I/O initialization for SMSC SIO1000
> - //
> - ConfigPort = PcdGet16 (PcdLpcSioIndexPort);
> - IndexPort = PcdGet16 (PcdLpcSioIndexPort);
> - DataPort = PcdGet16 (PcdLpcSioDataPort);
> -
> - //
> - // Enter Config Mode
> - //
> - IoWrite8 (ConfigPort, 0x55);
> -
> - //
> - // Check for SMSC SIO1000
> - //
> - if (IoRead8 (ConfigPort) != 0xFF) {
> - //
> - // Configure SIO
> - //
> - for (Index = 0; Index < sizeof (mSioTableSmsc1000) / sizeof
> (EFI_SIO_TABLE); Index++) {
> - IoWrite8 (IndexPort, mSioTableSmsc1000[Index].Register);
> - IoWrite8 (DataPort, mSioTableSmsc1000[Index].Value);
> - }
> -
> - //
> - // Exit Config Mode
> - //
> - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA);
> - }
> -
> - //
> - // Super I/O initialization for Winbond WPCN381U
> - //
> - IndexPort = LPC_SIO_INDEX_DEFAULT_PORT_2;
> - DataPort = LPC_SIO_DATA_DEFAULT_PORT_2;
> -
> - //
> - // Check for Winbond WPCN381U
> - //
> - IoWrite8 (IndexPort, 0x20); // Winbond WPCN381U Device
> ID register is 0x20
> - if (IoRead8 (DataPort) == 0xF4) { // Winbond WPCN381U Device ID
> is 0xF4
> - //
> - // Configure SIO
> - //
> - for (Index = 0; Index < sizeof (mSioTableWpcn381u) / sizeof
> (EFI_SIO_TABLE); Index++) {
> - IoWrite8 (IndexPort, mSioTableWpcn381u[Index].Register);
> - IoWrite8 (DataPort, mSioTableWpcn381u[Index].Value);
> - }
> - }
> - } //EC is not exist, skip mobile board detection for SV board
> -
> - //
> - //add for SV Bidwell Bar board
> - //
> - if (IoRead8 (COM1_BASE) == 0xFF) {
> - //
> - // Super I/O initialization for Winbond WPCD374 (LDC2) and 8374
> (LDC)
> - // Looking for LDC2 card first
> - //
> - IoWrite8 (LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT, 0x55);
> - if (IoRead8 (LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT) == 0x55)
> {
> - IndexPort = LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT;
> - DataPort = LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT;
> - } else {
> - IndexPort = LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT;
> - DataPort = LEGACY_DAUGHTER_CARD_SIO_DATA_PORT;
> - }
> -
> - IoWrite8 (IndexPort, 0x20); // Winbond x374 Device ID
> register is 0x20
> - if (IoRead8 (DataPort) == 0xF1) { // Winbond x374 Device ID is
> 0xF1
> - for (Index = 0; Index < sizeof (mSioTableWinbondX374) / sizeof
> (EFI_SIO_TABLE); Index++) {
> - IoWrite8 (IndexPort, mSioTableWinbondX374[Index].Register);
> - IoWrite8 (DataPort, mSioTableWinbondX374[Index].Value);
> - }
> - }
> - }// end of Bidwell Bar SIO initialization
> - } else if (IS_SA_DEVICE_ID_DESKTOP (DeviceId) ||
> IS_SA_DEVICE_ID_SERVER (DeviceId)) {
> - //
> - // If we are in debug mode, we will allow serial status codes
> - //
> -
> - //
> - // National PC8374 SIO & Winbond WPCD374 (LDC2)
> - //
> - IndexPort = LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT;
> -
> - IoWrite8 (IndexPort, 0x55);
> - if (IoRead8 (IndexPort) == 0x55) {
> - IndexPort = LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT;
> - DataPort = LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT;
> - } else {
> - IndexPort = LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT;
> - DataPort = LEGACY_DAUGHTER_CARD_SIO_DATA_PORT;
> - }
> -
> - //
> - // Configure SIO
> - //
> - IoWrite8 (IndexPort, 0x20); // Winbond x374 Device ID
> register is 0x20
> - if (IoRead8 (DataPort) == 0xF1) { // Winbond x374 Device ID is 0xF1
> - for (Index = 0; Index < sizeof (mDesktopSioTable) / sizeof
> (EFI_SIO_TABLE); Index++) {
> - IoWrite8 (IndexPort, mDesktopSioTable[Index].Register);
> - //PrePpiStall (200);
> - IoWrite8 (DataPort, mDesktopSioTable[Index].Value);
> - //PrePpiStall (200);
> - }
> - return RETURN_SUCCESS;
> - }
> - //
> - // Configure Pilot3 SIO
> - //
> - IoWrite8 (PILOTIII_SIO_INDEX_PORT, PILOTIII_UNLOCK); //Enter config
> mode.
> - IoWrite8 (PILOTIII_SIO_INDEX_PORT, PILOTIII_CHIP_ID_REG); //
> Pilot3 SIO Device ID register is 0x20.
> - if (IoRead8 (PILOTIII_SIO_DATA_PORT) == PILOTIII_CHIP_ID) { //
> Pilot3 SIO Device ID register is 0x03.
> - //
> - // Configure SIO
> - //
> - for (Index = 0; Index < sizeof (mSioTablePilot3) / sizeof
> (EFI_SIO_TABLE); Index++) {
> - IoWrite8 (PILOTIII_SIO_INDEX_PORT,
> mSioTablePilot3[Index].Register);
> - IoWrite8 (PILOTIII_SIO_DATA_PORT, mSioTablePilot3[Index].Value);
> - }
> - }
> - IoWrite8 (PILOTIII_SIO_INDEX_PORT , PILOTIII_LOCK); //Exit config
> mode.
> - }
> -
> -
> - return RETURN_SUCCESS;
> -}
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeBo
> ardAcpiTableLib.c
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeBo
> ardAcpiTableLib.c
> deleted file mode 100644
> index c56334e82b..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeBo
> ardAcpiTableLib.c
> +++ /dev/null
> @@ -1,36 +0,0 @@
> -/** @file
> - DXE board-specific ACPI functionality.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <Base.h>
> -#include <Uefi.h>
> -#include <PiDxe.h>
> -#include <Library/BaseLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/BoardAcpiTableLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/DebugLib.h>
> -
> -EFI_STATUS
> -EFIAPI
> -N1xxWUBoardUpdateAcpiTable (
> - IN OUT EFI_ACPI_COMMON_HEADER *Table,
> - IN OUT EFI_ACPI_TABLE_VERSION *Version
> - );
> -
> -EFI_STATUS
> -EFIAPI
> -BoardUpdateAcpiTable (
> - IN OUT EFI_ACPI_COMMON_HEADER *Table,
> - IN OUT EFI_ACPI_TABLE_VERSION *Version
> - )
> -{
> - N1xxWUBoardUpdateAcpiTable (Table, Version);
> -
> - return EFI_SUCCESS;
> -}
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeMu
> ltiBoardAcpiSupportLib.c
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeMu
> ltiBoardAcpiSupportLib.c
> deleted file mode 100644
> index 4171d4ad6d..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeMu
> ltiBoardAcpiSupportLib.c
> +++ /dev/null
> @@ -1,43 +0,0 @@
> -/** @file
> - DXE multi-board ACPI table support functionality.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <Base.h>
> -#include <Uefi.h>
> -#include <PiDxe.h>
> -#include <Library/BaseLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/BoardAcpiTableLib.h>
> -#include <Library/MultiBoardAcpiSupportLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/DebugLib.h>
> -
> -#include <N1xxWUId.h>
> -
> -EFI_STATUS
> -EFIAPI
> -N1xxWUBoardUpdateAcpiTable (
> - IN OUT EFI_ACPI_COMMON_HEADER *Table,
> - IN OUT EFI_ACPI_TABLE_VERSION *Version
> - );
> -
> -BOARD_ACPI_TABLE_FUNC mN1xxWUBoardAcpiTableFunc = {
> - N1xxWUBoardUpdateAcpiTable
> -};
> -
> -EFI_STATUS
> -EFIAPI
> -DxeN1xxWUMultiBoardAcpiSupportLibConstructor (
> - VOID
> - )
> -{
> - if (LibPcdGetSku () == BoardIdN1xxWU) {
> - return RegisterBoardAcpiTableFunc (&mN1xxWUBoardAcpiTableFunc);
> - }
> - return EFI_SUCCESS;
> -}
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeN1
> xxWUAcpiTableLib.c
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeN1
> xxWUAcpiTableLib.c
> deleted file mode 100644
> index 96a3232fe5..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeN1
> xxWUAcpiTableLib.c
> +++ /dev/null
> @@ -1,74 +0,0 @@
> -/** @file
> - Clevo N1xxWU board DXE ACPI table functionality.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <Base.h>
> -#include <Uefi.h>
> -#include <PiDxe.h>
> -#include <Library/BaseLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/BoardAcpiTableLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/DebugLib.h>
> -#include <Library/UefiBootServicesTableLib.h>
> -#include <Library/AslUpdateLib.h>
> -#include <Protocol/GlobalNvsArea.h>
> -
> -#include <N1xxWUId.h>
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED EFI_GLOBAL_NVS_AREA_PROTOCOL
> mGlobalNvsArea;
> -
> -VOID
> -N1xxWUUpdateGlobalNvs (
> - VOID
> - )
> -{
> -
> - //
> - // Allocate and initialize the NVS area for SMM and ASL communication.
> - //
> - mGlobalNvsArea.Area = (VOID *)(UINTN)PcdGet64 (PcdAcpiGnvsAddress);
> -
> - //
> - // Update global NVS area for ASL and SMM init code to use
> - //
> -
> - //
> - // Enable PowerState
> - //
> - mGlobalNvsArea.Area->PowerState = 1; // AC =1; for mobile platform, will
> update this value in SmmPlatform.c
> -
> - mGlobalNvsArea.Area->NativePCIESupport = PcdGet8
> (PcdPciExpNative);
> -
> - //
> - // Enable APIC
> - //
> - mGlobalNvsArea.Area->ApicEnable = GLOBAL_NVS_DEVICE_ENABLE;
> -
> - //
> - // Low Power S0 Idle - Enabled/Disabled
> - //
> - mGlobalNvsArea.Area->LowPowerS0Idle = PcdGet8 (PcdLowPowerS0Idle);
> -
> - mGlobalNvsArea.Area->Ps2MouseEnable = FALSE;
> - mGlobalNvsArea.Area->Ps2KbMsEnable = PcdGet8
> (PcdPs2KbMsEnable);
> -}
> -
> -EFI_STATUS
> -EFIAPI
> -N1xxWUBoardUpdateAcpiTable (
> - IN OUT EFI_ACPI_COMMON_HEADER *Table,
> - IN OUT EFI_ACPI_TABLE_VERSION *Version
> - )
> -{
> - if (Table->Signature ==
> EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) {
> - N1xxWUUpdateGlobalNvs ();
> - }
> -
> - return EFI_SUCCESS;
> -}
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmB
> oardAcpiEnableLib.c
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmB
> oardAcpiEnableLib.c
> deleted file mode 100644
> index 2d9e9e98da..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmB
> oardAcpiEnableLib.c
> +++ /dev/null
> @@ -1,62 +0,0 @@
> -/** @file
> - Clevo N1xxWU board SMM ACPI table enable/disable functionality.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <Base.h>
> -#include <Uefi.h>
> -#include <PiDxe.h>
> -#include <Library/BaseLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/BoardAcpiEnableLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/DebugLib.h>
> -
> -EFI_STATUS
> -EFIAPI
> -N1xxWUBoardEnableAcpi (
> - IN BOOLEAN EnableSci
> - );
> -
> -EFI_STATUS
> -EFIAPI
> -N1xxWUBoardDisableAcpi (
> - IN BOOLEAN DisableSci
> - );
> -
> -EFI_STATUS
> -EFIAPI
> -SiliconEnableAcpi (
> - IN BOOLEAN EnableSci
> - );
> -
> -EFI_STATUS
> -EFIAPI
> -SiliconDisableAcpi (
> - IN BOOLEAN DisableSci
> - );
> -
> -EFI_STATUS
> -EFIAPI
> -BoardEnableAcpi (
> - IN BOOLEAN EnableSci
> - )
> -{
> - SiliconEnableAcpi (EnableSci);
> - return N1xxWUBoardEnableAcpi (EnableSci);
> -}
> -
> -EFI_STATUS
> -EFIAPI
> -BoardDisableAcpi (
> - IN BOOLEAN DisableSci
> - )
> -{
> - SiliconDisableAcpi (DisableSci);
> - return N1xxWUBoardDisableAcpi (DisableSci);
> -}
> -
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmM
> ultiBoardAcpiSupportLib.c
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmM
> ultiBoardAcpiSupportLib.c
> deleted file mode 100644
> index a06505a34a..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmM
> ultiBoardAcpiSupportLib.c
> +++ /dev/null
> @@ -1,81 +0,0 @@
> -/** @file
> - SMM multi-board ACPI support functionality.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <Base.h>
> -#include <Uefi.h>
> -#include <PiDxe.h>
> -#include <Library/BaseLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/BoardAcpiEnableLib.h>
> -#include <Library/MultiBoardAcpiSupportLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/DebugLib.h>
> -
> -#include <N1xxWUId.h>
> -
> -EFI_STATUS
> -EFIAPI
> -N1xxWUBoardEnableAcpi (
> - IN BOOLEAN EnableSci
> - );
> -
> -EFI_STATUS
> -EFIAPI
> -N1xxWUBoardDisableAcpi (
> - IN BOOLEAN DisableSci
> - );
> -
> -EFI_STATUS
> -EFIAPI
> -SiliconEnableAcpi (
> - IN BOOLEAN EnableSci
> - );
> -
> -EFI_STATUS
> -EFIAPI
> -SiliconDisableAcpi (
> - IN BOOLEAN DisableSci
> - );
> -
> -EFI_STATUS
> -EFIAPI
> -N1xxWUMultiBoardEnableAcpi (
> - IN BOOLEAN EnableSci
> - )
> -{
> - SiliconEnableAcpi (EnableSci);
> - return N1xxWUBoardEnableAcpi (EnableSci);
> -}
> -
> -EFI_STATUS
> -EFIAPI
> -N1xxWUMultiBoardDisableAcpi (
> - IN BOOLEAN DisableSci
> - )
> -{
> - SiliconDisableAcpi (DisableSci);
> - return N1xxWUBoardDisableAcpi (DisableSci);
> -}
> -
> -BOARD_ACPI_ENABLE_FUNC mN1xxWUBoardAcpiEnableFunc = {
> - N1xxWUMultiBoardEnableAcpi,
> - N1xxWUMultiBoardDisableAcpi,
> -};
> -
> -EFI_STATUS
> -EFIAPI
> -SmmN1xxWUMultiBoardAcpiSupportLibConstructor (
> - VOID
> - )
> -{
> - if (LibPcdGetSku () == BoardIdN1xxWU) {
> - return RegisterBoardAcpiEnableFunc
> (&mN1xxWUBoardAcpiEnableFunc);
> - }
> - return EFI_SUCCESS;
> -}
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmN
> 1xxWUAcpiEnableLib.c
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmN
> 1xxWUAcpiEnableLib.c
> deleted file mode 100644
> index 8c1caa1898..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmN
> 1xxWUAcpiEnableLib.c
> +++ /dev/null
> @@ -1,39 +0,0 @@
> -/** @file
> - Platform Hook Library instances
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <Base.h>
> -#include <Uefi.h>
> -#include <PiDxe.h>
> -#include <Library/BaseLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/BoardAcpiTableLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/DebugLib.h>
> -
> -#include <N1xxWUId.h>
> -
> -EFI_STATUS
> -EFIAPI
> -N1xxWUBoardEnableAcpi (
> - IN BOOLEAN EnableSci
> - )
> -{
> - // enable additional board register
> - return EFI_SUCCESS;
> -}
> -
> -EFI_STATUS
> -EFIAPI
> -N1xxWUBoardDisableAcpi (
> - IN BOOLEAN DisableSci
> - )
> -{
> - // enable additional board register
> - return EFI_SUCCESS;
> -}
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmSi
> liconAcpiEnableLib.c
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmSi
> liconAcpiEnableLib.c
> deleted file mode 100644
> index 1baa8daa70..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmSi
> liconAcpiEnableLib.c
> +++ /dev/null
> @@ -1,168 +0,0 @@
> -/** @file
> - SMM ACPI enable library.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <Base.h>
> -#include <Uefi.h>
> -#include <PiDxe.h>
> -#include <Library/BaseLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/BoardAcpiEnableLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/DebugLib.h>
> -#include <PchAccess.h>
> -#include <Library/MmPciLib.h>
> -#include <Library/PchCycleDecodingLib.h>
> -
> -/**
> - Clear Port 80h
> -
> - SMI handler to enable ACPI mode
> -
> - Dispatched on reads from APM port with value
> EFI_ACPI_ENABLE_SW_SMI
> -
> - Disables the SW SMI Timer.
> - ACPI events are disabled and ACPI event status is cleared.
> - SCI mode is then enabled.
> -
> - Clear SLP SMI status
> - Enable SLP SMI
> -
> - Disable SW SMI Timer
> -
> - Clear all ACPI event status and disable all ACPI events
> -
> - Disable PM sources except power button
> - Clear status bits
> -
> - Disable GPE0 sources
> - Clear status bits
> -
> - Disable GPE1 sources
> - Clear status bits
> -
> - Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
> -
> - Enable SCI
> -**/
> -EFI_STATUS
> -EFIAPI
> -SiliconEnableAcpi (
> - IN BOOLEAN EnableSci
> - )
> -{
> - UINT32 OutputValue;
> - UINT32 SmiEn;
> - UINT32 SmiSts;
> - UINT32 ULKMC;
> - UINTN LpcBaseAddress;
> - UINT16 AcpiBaseAddr;
> - UINT32 Pm1Cnt;
> -
> - LpcBaseAddress = MmPciBase (
> - DEFAULT_PCI_BUS_NUMBER_PCH,
> - PCI_DEVICE_NUMBER_PCH_LPC,
> - PCI_FUNCTION_NUMBER_PCH_LPC
> - );
> -
> - //
> - // Get the ACPI Base Address
> - //
> - PchAcpiBaseGet (&AcpiBaseAddr);
> -
> - //
> - // BIOS must also ensure that CF9GR is cleared and locked before
> handing control to the
> - // OS in order to prevent the host from issuing global resets and resetting
> ME
> - //
> - // EDK2: To match PCCG current BIOS behavior, do not lock CF9 Global
> Reset
> - // MmioWrite32 (
> - // PmcBaseAddress + R_PCH_PMC_ETR3),
> - // PmInit);
> -
> - //
> - // Clear Port 80h
> - //
> - IoWrite8 (0x80, 0);
> -
> - //
> - // Disable SW SMI Timer and clean the status
> - //
> - SmiEn = IoRead32 (AcpiBaseAddr + R_PCH_SMI_EN);
> - SmiEn &= ~(B_PCH_SMI_EN_LEGACY_USB2 |
> B_PCH_SMI_EN_SWSMI_TMR | B_PCH_SMI_EN_LEGACY_USB);
> - IoWrite32 (AcpiBaseAddr + R_PCH_SMI_EN, SmiEn);
> -
> - SmiSts = IoRead32 (AcpiBaseAddr + R_PCH_SMI_STS);
> - SmiSts |= B_PCH_SMI_EN_LEGACY_USB2 | B_PCH_SMI_EN_SWSMI_TMR |
> B_PCH_SMI_EN_LEGACY_USB;
> - IoWrite32 (AcpiBaseAddr + R_PCH_SMI_STS, SmiSts);
> -
> - //
> - // Disable port 60/64 SMI trap if they are enabled
> - //
> - ULKMC = MmioRead32 (LpcBaseAddress + R_PCH_LPC_ULKMC) &
> ~(B_PCH_LPC_ULKMC_60REN | B_PCH_LPC_ULKMC_60WEN |
> B_PCH_LPC_ULKMC_64REN | B_PCH_LPC_ULKMC_64WEN |
> B_PCH_LPC_ULKMC_A20PASSEN);
> - MmioWrite32 (LpcBaseAddress + R_PCH_LPC_ULKMC, ULKMC);
> -
> - //
> - // Disable PM sources except power button
> - //
> - IoWrite16 (AcpiBaseAddr + R_PCH_ACPI_PM1_EN,
> B_PCH_ACPI_PM1_EN_PWRBTN);
> -
> - //
> - // Clear PM status except Power Button status for RapidStart Resume
> - //
> - IoWrite16 (AcpiBaseAddr + R_PCH_ACPI_PM1_STS, 0xFEFF);
> -
> - //
> - // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
> - //
> - IoWrite8 (R_PCH_RTC_INDEX_ALT, R_PCH_RTC_REGD);
> - IoWrite8 (R_PCH_RTC_TARGET_ALT, 0x0);
> -
> - //
> - // Write ALT_GPI_SMI_EN to disable GPI1 (SMC_EXTSMI#)
> - //
> - OutputValue = IoRead32 (AcpiBaseAddr + 0x38);
> - OutputValue = OutputValue & ~(1 << (UINTN) PcdGet8
> (PcdSmcExtSmiBitPosition));
> - IoWrite32 (AcpiBaseAddr + 0x38, OutputValue);
> -
> -
> - //
> - // Enable SCI
> - //
> - if (EnableSci) {
> - Pm1Cnt = IoRead32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT);
> - Pm1Cnt |= B_PCH_ACPI_PM1_CNT_SCI_EN;
> - IoWrite32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
> - }
> -
> - return EFI_SUCCESS;
> -}
> -
> -EFI_STATUS
> -EFIAPI
> -SiliconDisableAcpi (
> - IN BOOLEAN DisableSci
> - )
> -{
> - UINT16 AcpiBaseAddr;
> - UINT32 Pm1Cnt;
> -
> - //
> - // Get the ACPI Base Address
> - //
> - PchAcpiBaseGet (&AcpiBaseAddr);
> -
> - //
> - // Disable SCI
> - //
> - if (DisableSci) {
> - Pm1Cnt = IoRead32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT);
> - Pm1Cnt &= ~B_PCH_ACPI_PM1_CNT_SCI_EN;
> - IoWrite32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
> - }
> -
> - return EFI_SUCCESS;
> -}
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxW
> UGpioTable.c
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxW
> UGpioTable.c
> deleted file mode 100644
> index 27f70df001..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxW
> UGpioTable.c
> +++ /dev/null
> @@ -1,370 +0,0 @@
> -/** @file
> - GPIO definition table for N1xxWU
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#ifndef _N1_XX_WU_GPIO_TABLE_H_
> -#define _N1_XX_WU_GPIO_TABLE_H_
> -
> -#include <PiPei.h>
> -#include <GpioPinsSklLp.h>
> -#include <Library/GpioLib.h>
> -#include <GpioConfig.h>
> -#include <IoExpander.h>
> -
> -
> -#define END_OF_GPIO_TABLE 0xFFFFFFFF
> -
> -GPIO_INIT_CONFIG mGpioTableN1xxWU[] =
> -{
> - {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //RCINB_TIME_SYNC_1
> - {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirInOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNative}}, //LAD_0_ESPI_IO_0
> - {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirInOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //LAD_1_ESPI_IO_1
> - {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirInOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNative}}, //LAD_2_ESPI_IO_2
> - {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirInOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //LAD_3_ESPI_IO_3
> - {GPIO_SKL_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //LFRAMEB_ESPI_CSB
> - {GPIO_SKL_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirInOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //SERIRQ
> - {GPIO_SKL_LP_GPP_A7, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //PIRQAB_GSPI0_CS1B
> - {GPIO_SKL_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //CLKRUNB
> - {GPIO_SKL_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermWpd20K}}, //CLKOUT_LPC_0_ESPI_CLK
> - {GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermWpd20K}}, //CLKOUT_LPC_1
> - {GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermWpu20K}}, //PMEB_GSPI1_CS1B
> - {GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //BM_BUSYB_ISH_GP_6
> - {GPIO_SKL_LP_GPP_A13, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //SUSWARNB_SUSPWRDNACK
> - {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //SUS_STATB_ESPI_RESETB
> - {GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermWpu20K}}, //SUSACKB
> - {GPIO_SKL_LP_GPP_A16, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //SD_1P8_SEL
> - {GPIO_SKL_LP_GPP_A17, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //SD_VDD1_PWR_EN_B_ISH_GP_7
> - {GPIO_SKL_LP_GPP_A18, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //ISH_GP_0
> - {GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //ISH_GP_1
> - {GPIO_SKL_LP_GPP_A20, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //ISH_GP_2
> - {GPIO_SKL_LP_GPP_A21, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioPlatformReset,
> GpioTermNone}}, //ISH_GP_3
> - {GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioResumeReset,
> GpioTermNone}}, //ISH_GP_4
> - {GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioResumeReset,
> GpioTermNone}}, //ISH_GP_5
> - {GPIO_SKL_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //CORE_VID_0
> - {GPIO_SKL_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //CORE_VID_1
> - {GPIO_SKL_LP_GPP_B2, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //VRALERTB
> - {GPIO_SKL_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //CPU_GP_2
> - {GPIO_SKL_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //CPU_GP_3
> - {GPIO_SKL_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //SRCCLKREQB_0
> - {GPIO_SKL_LP_GPP_B6, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //SRCCLKREQB_1
> - {GPIO_SKL_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //SRCCLKREQB_2
> - {GPIO_SKL_LP_GPP_B8, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //SRCCLKREQB_3
> - {GPIO_SKL_LP_GPP_B9, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutLow, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //SRCCLKREQB_4
> - {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //SRCCLKREQB_5
> - {GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //EXT_PWR_GATEB
> - {GPIO_SKL_LP_GPP_B12, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //SLP_S0B
> - {GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //PLTRSTB
> - {GPIO_SKL_LP_GPP_B14, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermWpd20K}}, //SPKR
> - {GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //GSPI0_CS0B
> - {GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //GSPI0_CLK
> - {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //GSPI0_MISO
> - {GPIO_SKL_LP_GPP_B18, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermWpu20K}}, //GSPI0_MOSI
> - {GPIO_SKL_LP_GPP_B19, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //GSPI1_CS0B
> - {GPIO_SKL_LP_GPP_B20, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //GSPI1_CLK_NFC_CLK
> - {GPIO_SKL_LP_GPP_B21, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //GSPI1_MISO_NFC_CLKREQ
> - {GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermWpd20K}}, //GSPI1_MOSI
> - {GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //SML1ALERTB_PCHHOTB
> - {GPIO_SKL_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //GPPC_G_0_SD3_CMD
> - {GPIO_SKL_LP_GPP_G1, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //GPPC_G_1_SD3_D0_SD4_RCLK_P
> - {GPIO_SKL_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //GPPC_G_2_SD3_D1_SD4_RCLK_N
> - {GPIO_SKL_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //GPPC_G_3_SD3_D2
> - {GPIO_SKL_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //GPPC_G_4_SD3_D3
> - {GPIO_SKL_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //GPPC_G_5_SD3_CDB
> - {GPIO_SKL_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //GPPC_G_6_SD3_CLK
> - {GPIO_SKL_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //GPPC_G_7_SD3_WP
> - {GPIO_SKL_LP_GPP_D0, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //SPI1_CSB_BK_0
> - {GPIO_SKL_LP_GPP_D1, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //SPI1_CLK_BK_1
> - {GPIO_SKL_LP_GPP_D2, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //SPI1_MISO_IO_1_BK_2
> - {GPIO_SKL_LP_GPP_D3, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //SPI1_MOSI_IO_0_BK_3
> - {GPIO_SKL_LP_GPP_D4, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //IMGCLKOUT_0_BK_4
> - {GPIO_SKL_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutHigh, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //ISH_I2C0_SDA
> - {GPIO_SKL_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //ISH_I2C0_SCL
> - {GPIO_SKL_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //ISH_I2C1_SDA
> - {GPIO_SKL_LP_GPP_D8, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //ISH_I2C1_SCL
> - {GPIO_SKL_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //ISH_SPI_CSB
> - {GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //ISH_SPI_CLK
> - {GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //ISH_SPI_MISO_GP_BSSB_CLK
> - {GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //ISH_SPI_MOSI_GP_BSSB_DI
> - {GPIO_SKL_LP_GPP_D13, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //ISH_UART0_RXD_SML0BDATA
> - {GPIO_SKL_LP_GPP_D14, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //ISH_UART0_TXD_SML0BCLK
> - {GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //ISH_UART0_RTSB_GSPI2_CS1B
> - {GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //ISH_UART0_CTSB_SML0BALERTB
> - {GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //DMIC_CLK_1_SNDW3_CLK
> - {GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //DMIC_DATA_1_SNDW3_DATA
> - {GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //DMIC_CLK_0_SNDW4_CLK
> - {GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //DMIC_DATA_0_SNDW4_DATA
> - {GPIO_SKL_LP_GPP_D21, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //SPI1_IO_2
> - {GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //SPI1_IO_3
> - {GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //SSP_MCLK
> - {GPIO_SKL_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //CNV_GNSS_PA_BLANKING
> - {GPIO_SKL_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //CNV_GNSS_FTA
> - {GPIO_SKL_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //CNV_GNSS_SYSCK
> - {GPIO_SKL_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //
> - {GPIO_SKL_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //CNV_BRI_DT_UART0_RTSB
> - {GPIO_SKL_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //CNV_BRI_RSP_UART0_RXD
> - {GPIO_SKL_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //CNV_RGI_DT_UART0_TXD
> - {GPIO_SKL_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //CNV_RGI_RSP_UART0_CTSB
> - {GPIO_SKL_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //CNV_MFUART2_RXD
> - {GPIO_SKL_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutHigh, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //CNV_MFUART2_TXD
> - {GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnDefault,
> GpioDirDefault, GpioOutHigh, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //
> - {GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //EMMC_CMD
> - {GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //EMMC_DATA0
> - {GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //EMMC_DATA1
> - {GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //EMMC_DATA2
> - {GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //EMMC_DATA3
> - {GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //EMMC_DATA4
> - {GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //EMMC_DATA5
> - {GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //EMMC_DATA6
> - {GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //EMMC_DATA7
> - {GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //EMMC_RCLK
> - {GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //EMMC_CLK
> - {GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //EMMC_RESETB
> - {GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnAcpi,
> GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic,
> GpioHostDeepReset, GpioTermNone}}, //A4WP_PRESENT
> - {GPIO_SKL_LP_GPD0, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioResetDefault,
> GpioTermNone}}, //BATLOWB
> - {GPIO_SKL_LP_GPD1, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioResetDefault,
> GpioTermNative}}, //ACPRESENT
> - {GPIO_SKL_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi,
> GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci,
> GpioResetDefault, GpioTermNone}}, //LAN_WAKEB
> - {GPIO_SKL_LP_GPD3, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioResetDefault,
> GpioTermWpu20K}}, //PWRBTNB
> - {GPIO_SKL_LP_GPD4, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDefault,
> GpioTermNone}}, //SLP_S3B
> - {GPIO_SKL_LP_GPD5, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDefault,
> GpioTermNone}}, //SLP_S4B
> - {GPIO_SKL_LP_GPD6, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDefault,
> GpioTermNone}}, //SLP_AB
> - {GPIO_SKL_LP_GPD7, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDefault,
> GpioTermNone}}, //
> - {GPIO_SKL_LP_GPD8, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioResetDefault,
> GpioTermNone}}, //SUSCLK
> - {GPIO_SKL_LP_GPD9, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDefault,
> GpioTermNone}}, //SLP_WLANB
> - {GPIO_SKL_LP_GPD10, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDefault,
> GpioTermNone}}, //SLP_S5B
> - {GPIO_SKL_LP_GPD11, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDefault,
> GpioTermNone}}, //LANPHYPC
> - {GPIO_SKL_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //SMBCLK
> - {GPIO_SKL_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //SMBDATA
> - {GPIO_SKL_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset,
> GpioTermWpd20K}}, //SMBALERTB
> - {GPIO_SKL_LP_GPP_C3, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //SML0CLK
> - {GPIO_SKL_LP_GPP_C4, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //SML0DATA
> - {GPIO_SKL_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //SML0ALERTB
> - {GPIO_SKL_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //SML1CLK
> - {GPIO_SKL_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //SML1DATA
> - {GPIO_SKL_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //UART0_RXD
> - {GPIO_SKL_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //UART0_TXD
> - {GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //UART0_RTSB
> - {GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //UART0_CTSB
> - {GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //UART1_RXD_ISH_UART1_RXD
> - {GPIO_SKL_LP_GPP_C13, {GpioPadModeGpio, GpioHostOwnAcpi,
> GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci,
> GpioPlatformReset, GpioTermNone}}, //UART1_TXD_ISH_UART1_TXD
> - {GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //UART1_RTSB_ISH_UART1_RTSB
> - {GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutHigh, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //UART1_CTSB_ISH_UART1_CTSB
> - {GPIO_SKL_LP_GPP_C16, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //I2C0_SDA
> - {GPIO_SKL_LP_GPP_C17, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //I2C0_SCL
> - {GPIO_SKL_LP_GPP_C18, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //I2C1_SDA
> - {GPIO_SKL_LP_GPP_C19, {GpioPadModeGpio, GpioHostOwnAcpi,
> GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci,
> GpioHostDeepReset, GpioTermNone}}, //I2C1_SCL
> - {GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutLow, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //UART2_RXD
> - {GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //UART2_TXD
> - {GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //UART2_RTSB
> - {GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //UART2_CTSB
> - {GPIO_SKL_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirIn, GpioOutDefault, GpioIntEdge | GpioIntApic,
> GpioHostDeepReset, GpioTermWpd20K}}, //SATAXPCIE_0_SATAGP_0
> - {GPIO_SKL_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //SATAXPCIE_1_SATAGP_1
> - {GPIO_SKL_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirIn, GpioOutLow, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //SATAXPCIE_2_SATAGP_2
> - {GPIO_SKL_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirInOut, GpioOutLow, GpioIntLevel | GpioIntDis,
> GpioHostDeepReset, GpioTermNone}}, //CPU_GP_0
> - {GPIO_SKL_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioResumeReset,
> GpioTermNone}}, //SATA_DEVSLP_0
> - {GPIO_SKL_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioResumeReset,
> GpioTermNone}}, //SATA_DEVSLP_1
> - {GPIO_SKL_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //SATA_DEVSLP_2
> - {GPIO_SKL_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //CPU_GP_1
> - {GPIO_SKL_LP_GPP_E8, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //SATA_LEDB
> - {GPIO_SKL_LP_GPP_E9, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //USB2_OCB_0_GP_BSSB_CLk
> - {GPIO_SKL_LP_GPP_E10, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //USB2_OCB_1_GP_BSSB_DI
> - {GPIO_SKL_LP_GPP_E11, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //USB2_OCB_2
> - {GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //USB2_OCB_3
> - {GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //DDSP_HPD_0_DISP_MISC_0
> - {GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //DDSP_HPD_1_DISP_MISC_1
> - {GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi,
> GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSmi,
> GpioHostDeepReset, GpioTermNone}}, //DDSP_HPD_2_DISP_MISC_2
> - {GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi,
> GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci,
> GpioPlatformReset, GpioTermNone}}, //DDSP_HPD_3_DISP_MISC_3
> - {GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //EDP_HPD_DISP_MISC_4
> - {GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //DDPB_CTRLCLK
> - {GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //DDPB_CTRLDATA
> - {GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //DDPC_CTRLCLK
> - {GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //DDPC_CTRLDATA
> - {GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirInOut, GpioOutDefault, GpioIntLevel | GpioIntApic,
> GpioHostDeepReset, GpioTermNone}}, //DDPD_CTRLCLK
> - {GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}}, //DDPD_CTRLDATA
> - {END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset,
> GpioTermNone}},//Marking End of Table
> -};
> -
> -UINT16 mGpioTableN1xxWUSize = sizeof (mGpioTableN1xxWU) / sizeof
> (GPIO_INIT_CONFIG) - 1;
> -
> -GPIO_INIT_CONFIG mGpioTableN1xxWUUcmcDevice[] =
> -{
> - { GPIO_SKL_LP_GPP_B0, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset,
> GpioTermNone } }, //GPP_B0
> - { GPIO_SKL_LP_GPP_B1, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset,
> GpioTermNone } }, //GPP_B1
> -};
> -
> -UINT16 mGpioTableN1xxWUUcmcDeviceSize = sizeof
> (mGpioTableN1xxWUUcmcDevice) / sizeof (GPIO_INIT_CONFIG);
> -
> -GPIO_INIT_CONFIG mGpioTableN1xxWUTouchpanel =
> - {GPIO_SKL_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic,
> GpioPlatformReset, GpioTermNone}};
> -
> -GPIO_INIT_CONFIG mGpioTableN1xxWUSdhcSidebandCardDetect =
> - {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirIn, GpioOutDefault, GpioIntBothEdge, GpioHostDeepReset,
> GpioTermNone}}; //SD_CDB D3
> -
> -//IO Expander Table for SKL RVP7, RVP13 and RVP15
> -IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpander[] =
> -{
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_3.3_PWREN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//SNSR_HUB_DFU_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//SATA_PWR_EN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_RST_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_WLAN_WAKE_CTRL_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//GFX_CRB_DET_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//MFG_MODE_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//FLIP_TO_TABLET_MODE_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//PCH_SLOT1_RST_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//USB3_CAM_PWREN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//RSVD_TESTMODE_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//BIOS_REC_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//EINK_PWREN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//TBT_FORCE_PWR_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_WIFI_RST_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_INPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//DGPU_PRSNT_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//IMAGING_DFU_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_INPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//SW_GFX_PWERGD_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_WAKE_CTRL_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_RST_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P26
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P27
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_PWREN_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_DISABLE_IOEXP_N
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//USB32_WP4_PWREN_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//USB32_OTG_WP1_PWREN_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//USB32_WP2_WP3_WP5_PWREN_R_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//PCH_AUDIO_PWREN_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_GNSS_DISABLE_IOEXP_N
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED}//M.2_WIGIG_PWREN_IOEXP
> -};
> -
> -UINT16 mGpioTableIoExpanderSize = sizeof (mGpioTableIoExpander) /
> sizeof (IO_EXPANDER_GPIO_CONFIG);
> -
> -//IO Expander Table for KBL -Refresh
> -IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpanderKabylakeRDdr4[] =
> -{
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_3.3_PWREN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//SNSR_HUB_DFU_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//SATA_PWR_EN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_RST_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_WLAN_WAKE_CTRL_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//GFX_CRB_DET_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//MFG_MODE_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//FLIP_TO_TABLET_MODE_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//PCH_SLOT1_RST_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//USB3_CAM_PWREN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//RSVD_TESTMODE_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//BIOS_REC_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_INPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//Unused pin
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//TBT_FORCE_PWR_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_WIFI_RST_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//RTD3_USB_PD1_PWR_EN
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//IMAGING_DFU_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//HRESET_PD1_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_WAKE_CTRL_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_RST_IOEXP_N
> - //{IO_EXPANDER_0, IO_EXPANDER_GPIO_22,
> IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,
> IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_RST_CNTRL_R
> - // We want the initial state to be high.
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_RST_CNTRL_R
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_WAKE_CTRL_R_N
> - // Turn off WWAN power and will turn it on later.
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_PWREN_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_DISABLE_IOEXP_N
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_INPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//RSVD
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_INPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//RSVD
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//USB32_WP2_WP3_WP5_PWREN_R_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//PCH_AUDIO_PWREN_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_GNSS_DISABLE_IOEXP_N
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_PWREN_IOEXP
> -};
> -UINT16 mGpioTableIoExpanderSizeKabylakeRDdr4 = sizeof
> (mGpioTableIoExpanderKabylakeRDdr4) / sizeof
> (IO_EXPANDER_GPIO_CONFIG);
> -
> -//IO Expander Table for KBL -kc
> -IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpanderKabylakeKcDdr3[] =
> -{
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_3.3_PWREN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//SNSR_HUB_DFU_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//SATA_PWR_EN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_RST_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_WLAN_WAKE_CTRL_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//GFX_CRB_DET_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//MFG_MODE_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//FLIP_TO_TABLET_MODE_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//PCH_SLOT1_RST_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//USB3_CAM_PWREN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//RSVD_TESTMODE_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//BIOS_REC_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//EINK_PWREN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//TBT_FORCE_PWR_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_WIFI_RST_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_INPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//RSVD
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//IMAGING_DFU_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_INPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//RSVD
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_WAKE_CTRL_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_RST_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P26
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P27
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_PWREN_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_DISABLE_IOEXP_N
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//USB32_WP4_PWREN_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//USB32_OTG_WP1_PWREN_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//USB32_WP2_WP3_WP5_PWREN_R_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//PCH_AUDIO_PWREN_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_GNSS_DISABLE_IOEXP_N
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_PWREN_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//FPS_LOCK_N
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//USB32_FLEX_PWREN
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//USB_UART_SEL
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//USB32_DOCK_PWREN_IOEXP_R
> -};
> -UINT16 mGpioTableIoExpanderSizeKabylakeKcDdr3 = sizeof
> (mGpioTableIoExpanderKabylakeKcDdr3) / sizeof
> (IO_EXPANDER_GPIO_CONFIG);
> -//IO Expander Table Full table for N 1XX WU
> -IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpanderN1xxWU[] =
> -{
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_3.3_PWREN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//SNSR_HUB_DFU_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//SATA_PWR_EN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_RST_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_WLAN_WAKE_CTRL_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//GFX_CRB_DET_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//MFG_MODE_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//FLIP_TO_TABLET_MODE_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//PCH_SLOT1_RST_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//USB3_CAM_PWREN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//RSVD_TESTMODE_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//BIOS_REC_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//EINK_PWREN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//TBT_FORCE_PWR_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_WIFI_RST_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_INPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//DGPU_PRSNT_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED },//SW_GFX_DGPU_SEL (KBL_RVP3_BOARD)
> -//{IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN_IOEXP
> (SKL_RVP3_BOARD)
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//IMAGING_DFU_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_INPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//SW_GFX_PWERGD_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_WAKE_CTRL_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_RST_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P26
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P27
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_PWREN_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_DISABLE_IOEXP_N
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//USB32_WP4_PWREN_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_INPUT,
> IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED },//Not Connected (KBK_RVP3_BOARD)
> -//{IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//USB32_OTG_WP1_PWREN_IOEXP
> (SKL_RVP3_BOARD)
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//USB32_WP2_WP3_WP5_PWREN_R_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//PCH_AUDIO_PWREN_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_GNSS_DISABLE_IOEXP_N
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_PWREN_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN (KBL_RVP3_BOARD)
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT,
> IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED,
> IO_EXPANDER_GPIO_RESERVED},//FPS_LOCK_N (KBL_RVP3_BOARD)
> -};
> -
> -UINT16 mGpioTableIoExpanderN1xxWUSize = sizeof
> (mGpioTableIoExpanderN1xxWU) / sizeof (IO_EXPANDER_GPIO_CONFIG);
> -
> -#endif // _N1_XX_WU_GPIO_TABLE_H_
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxW
> UHdaVerbTables.c
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxW
> UHdaVerbTables.c
> deleted file mode 100644
> index 26d7401c6c..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxW
> UHdaVerbTables.c
> +++ /dev/null
> @@ -1,232 +0,0 @@
> -/** @file
> - HDA Verb table for N1xxWU
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#ifndef _N1_XX_WU_HDA_VERB_TABLES_H_
> -#define _N1_XX_WU_HDA_VERB_TABLES_H_
> -
> -#include <Ppi/SiPolicy.h>
> -
> -HDAUDIO_VERB_TABLE HdaVerbTableAlc286Rvp3 =
> HDAUDIO_VERB_TABLE_INIT (
> - //
> - // VerbTable: (Realtek ALC286) for RVP3
> - // Revision ID = 0xff
> - // Codec Verb Table for SKL PCH boards
> - // Codec Address: CAd value (0/1/2)
> - // Codec Vendor: 0x10EC0286
> - //
> - 0x10EC, 0x0286,
> - 0xFF, 0xFF,
> -
> //==============================================================
> =====================================
> - //
> - // Realtek Semiconductor Corp.
> - //
> -
> //==============================================================
> =====================================
> -
> - //Realtek High Definition Audio Configuration - Version : 5.0.2.9
> - //Realtek HD Audio Codec : ALC286
> - //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086
> - //HDA Codec PnP ID :
> HDAUDIO\FUNC_01&VEN_10EC&DEV_0286&SUBSYS_10EC108E
> - //The number of verb command block : 16
> -
> - // NID 0x12 : 0x411111F0
> - // NID 0x13 : 0x40000000
> - // NID 0x14 : 0x9017011F
> - // NID 0x17 : 0x90170110
> - // NID 0x18 : 0x03A11040
> - // NID 0x19 : 0x411111F0
> - // NID 0x1A : 0x411111F0
> - // NID 0x1D : 0x4066A22D
> - // NID 0x1E : 0x411111F0
> - // NID 0x21 : 0x03211020
> -
> -
> - //===== HDA Codec Subsystem ID Verb-table =====
> - //HDA Codec Subsystem ID : 0x10EC108E
> - 0x0017208E,
> - 0x00172110,
> - 0x001722EC,
> - 0x00172310,
> -
> - //===== Pin Widget Verb-table =====
> - //Widget node 0x01 :
> - 0x0017FF00,
> - 0x0017FF00,
> - 0x0017FF00,
> - 0x0017FF00,
> - //Pin widget 0x12 - DMIC
> - 0x01271CF0,
> - 0x01271D11,
> - 0x01271E11,
> - 0x01271F41,
> - //Pin widget 0x13 - DMIC
> - 0x01371C00,
> - 0x01371D00,
> - 0x01371E00,
> - 0x01371F40,
> - //Pin widget 0x14 - SPEAKER-OUT (Port-D)
> - 0x01771C1F,
> - 0x01771D01,
> - 0x01771E17,
> - 0x01771F90,
> - //Pin widget 0x17 - I2S-OUT
> - 0x01771C10,
> - 0x01771D01,
> - 0x01771E17,
> - 0x01771F90,
> - //Pin widget 0x18 - MIC1 (Port-B)
> - 0x01871C40,
> - 0x01871D10,
> - 0x01871EA1,
> - 0x01871F03,
> - //Pin widget 0x19 - I2S-IN
> - 0x01971CF0,
> - 0x01971D11,
> - 0x01971E11,
> - 0x01971F41,
> - //Pin widget 0x1A - LINE1 (Port-C)
> - 0x01A71CF0,
> - 0x01A71D11,
> - 0x01A71E11,
> - 0x01A71F41,
> - //Pin widget 0x1D - PC-BEEP
> - 0x01D71C2D,
> - 0x01D71DA2,
> - 0x01D71E66,
> - 0x01D71F40,
> - //Pin widget 0x1E - S/PDIF-OUT
> - 0x01E71CF0,
> - 0x01E71D11,
> - 0x01E71E11,
> - 0x01E71F41,
> - //Pin widget 0x21 - HP-OUT (Port-A)
> - 0x02171C20,
> - 0x02171D10,
> - 0x02171E21,
> - 0x02171F03,
> - //Widget node 0x20 :
> - 0x02050071,
> - 0x02040014,
> - 0x02050010,
> - 0x02040C22,
> - //Widget node 0x20 - 1 :
> - 0x0205004F,
> - 0x02045029,
> - 0x0205004F,
> - 0x02045029,
> - //Widget node 0x20 - 2 :
> - 0x0205002B,
> - 0x02040DD0,
> - 0x0205002D,
> - 0x02047020,
> - //Widget node 0x20 - 3 :
> - 0x0205000E,
> - 0x02046C80,
> - 0x01771F90,
> - 0x01771F90,
> - //TI AMP settings :
> - 0x02050022,
> - 0x0204004C,
> - 0x02050023,
> - 0x02040000,
> - 0x02050025,
> - 0x02040000,
> - 0x02050026,
> - 0x0204B010,
> -
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> -
> - 0x02050022,
> - 0x0204004C,
> - 0x02050023,
> - 0x02040002,
> - 0x02050025,
> - 0x02040011,
> - 0x02050026,
> - 0x0204B010,
> -
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> -
> - 0x02050022,
> - 0x0204004C,
> - 0x02050023,
> - 0x0204000D,
> - 0x02050025,
> - 0x02040010,
> - 0x02050026,
> - 0x0204B010,
> -
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> -
> - 0x02050022,
> - 0x0204004C,
> - 0x02050023,
> - 0x02040025,
> - 0x02050025,
> - 0x02040008,
> - 0x02050026,
> - 0x0204B010,
> -
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> -
> - 0x02050022,
> - 0x0204004C,
> - 0x02050023,
> - 0x02040002,
> - 0x02050025,
> - 0x02040000,
> - 0x02050026,
> - 0x0204B010,
> -
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> -
> - 0x02050022,
> - 0x0204004C,
> - 0x02050023,
> - 0x02040003,
> - 0x02050025,
> - 0x02040000,
> - 0x02050026,
> - 0x0204B010
> -);
> -
> -#endif // _N1_XX_WU_HDA_VERB_TABLES_H_
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxW
> UHsioPtssTables.c
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxW
> UHsioPtssTables.c
> deleted file mode 100644
> index 9e52dd2671..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxW
> UHsioPtssTables.c
> +++ /dev/null
> @@ -1,105 +0,0 @@
> -/** @file
> - N1xxWU HSIO PTSS H File
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#ifndef N1_XX_WU_HSIO_PTSS_H_
> -#define N1_XX_WU_HSIO_PTSS_H_
> -
> -#include <PchHsioPtssTables.h>
> -
> -#ifndef HSIO_PTSS_TABLE_SIZE
> -#define HSIO_PTSS_TABLE_SIZE(A) A##_Size = sizeof (A) / sizeof
> (HSIO_PTSS_TABLES)
> -#endif
> -
> -//BoardId N1xxWU
> -HSIO_PTSS_TABLES PchLpHsioPtss_Cx_N1xxWU[] = {
> - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32)
> ~0x3F000000}, PchSataTopoUnknown},
> - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32)
> ~0x3F000000}, PchSataTopoM2},
> - {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32)
> ~0x1F0000}, PchPcieTopoM2},
> - {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32)
> ~0x1F0000}, PchPcieTopoUnknown},
> - {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32)
> ~0x1F0000}, PchPcieTopox4},
> - {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32)
> ~0x1F0000}, PchPcieTopoUnknown},
> - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32)
> ~0x3F000000}, PchSataTopoUnknown},
> - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x04000000, (UINT32)
> ~0x3F000000}, PchSataTopoDirectConnect},
> - {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32)
> ~0x1F0000}, PchPcieTopoM2},
> - {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32)
> ~0x1F0000}, PchPcieTopoUnknown},
> - {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32)
> ~0x1F0000}, PchPcieTopox4},
> - {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32)
> ~0x1F0000}, PchPcieTopoUnknown},
> - {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32)
> ~0x1F0000}, PchPcieTopox4},
> - {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32)
> ~0x1F0000}, PchPcieTopoUnknown},
> - {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32)
> ~0x3F000000}, PchSataTopoUnknown},
> - {{12, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32)
> ~0x1F0000}, PchPcieTopoUnknown},
> - {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32)
> ~0x3F000000}, PchSataTopoUnknown},
> - {{13, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32)
> ~0x1F0000}, PchPcieTopoUnknown},
> - {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32)
> ~0x3F000000}, PchSataTopoUnknown},
> - {{14, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32)
> ~0x1F0000}, PchPcieTopoUnknown},
> - {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32)
> ~0x3F000000}, PchSataTopoUnknown},
> - {{15, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32)
> ~0x1F0000}, PchPcieTopoUnknown},
> - {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32)
> ~0x1F0000}, PchPcieTopox4},
> - {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32)
> ~0x1F0000}, PchPcieTopoUnknown},
> - {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32)
> ~0x1F0000}, PchPcieTopoM2},
> - {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32)
> ~0x1F0000}, PchPcieTopox1},
> - {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32)
> ~0x1F0000}, PchPcieTopoUnknown},
> - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32)
> ~0x3F3F00}, PchSataTopoUnknown},
> - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00322900, (UINT32)
> ~0x3F3F00}, PchSataTopoM2},
> - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32)
> ~0x3F3F00}, PchSataTopoUnknown},
> - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00382C00, (UINT32)
> ~0x3F3F00}, PchSataTopoDirectConnect},
> - {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32)
> ~0x3F3F00}, PchSataTopoUnknown},
> - {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32)
> ~0x1F0000}, PchPcieTopoM2},
> - {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32)
> ~0x1F0000}, PchPcieTopox1},
> - {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32)
> ~0x1F0000}, PchPcieTopoUnknown},
> - {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32)
> ~0x3F3F00}, PchSataTopoUnknown},
> - {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32)
> ~0x3F3F00}, PchSataTopoUnknown},
> - {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32)
> ~0x3F3F00}, PchSataTopoUnknown}
> -};
> -
> -UINT16 PchLpHsioPtss_Cx_N1xxWU_Size =
> sizeof(PchLpHsioPtss_Cx_N1xxWU) / sizeof(HSIO_PTSS_TABLES);
> -
> -HSIO_PTSS_TABLES PchLpHsioPtss_Bx_N1xxWU[] = {
> - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32)
> ~0x3F000000}, PchSataTopoUnknown},
> - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32)
> ~0x3F000000}, PchPcieTopoUnknown},
> - {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32)
> ~0x1F0000}, PchPcieTopoUnknown},
> - {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32)
> ~0x1F0000}, PchPcieTopoUnknown},
> - {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32)
> ~0x1F0000}, PchPcieTopox4},
> - {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32)
> ~0x1F0000}, PchPcieTopoUnknown},
> - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32)
> ~0x3F000000}, PchSataTopoUnknown},
> - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x04000000, (UINT32)
> ~0x3F000000}, PchSataTopoDirectConnect},
> - {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32)
> ~0x1F0000}, PchPcieTopoUnknown},
> - {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32)
> ~0x1F0000}, PchPcieTopoUnknown},
> - {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32)
> ~0x1F0000}, PchPcieTopox4},
> - {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32)
> ~0x1F0000}, PchPcieTopoUnknown},
> - {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32)
> ~0x1F0000}, PchPcieTopox4},
> - {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32)
> ~0x1F0000}, PchPcieTopoUnknown},
> - {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32)
> ~0x3F000000}, PchSataTopoUnknown},
> - {{12, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32)
> ~0x1F0000}, PchPcieTopoUnknown},
> - {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32)
> ~0x3F000000}, PchSataTopoUnknown},
> - {{13, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32)
> ~0x1F0000}, PchPcieTopoUnknown},
> - {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32)
> ~0x3F000000}, PchSataTopoUnknown},
> - {{14, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32)
> ~0x1F0000}, PchPcieTopoUnknown},
> - {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32)
> ~0x3F000000}, PchSataTopoUnknown},
> - {{15, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32)
> ~0x1F0000}, PchPcieTopoUnknown},
> - {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32)
> ~0x1F0000}, PchPcieTopox4},
> - {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32)
> ~0x1F0000}, PchPcieTopoUnknown},
> - {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32)
> ~0x1F0000}, PchPcieTopoUnknown},
> - {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32)
> ~0x1F0000}, PchPcieTopox1},
> - {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32)
> ~0x1F0000}, PchPcieTopoUnknown},
> - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32)
> ~0x3F3F00}, PchSataTopoUnknown},
> - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00322900, (UINT32)
> ~0x3F3F00}, PchPcieTopoUnknown},
> - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32)
> ~0x3F3F00}, PchSataTopoUnknown},
> - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00382C00, (UINT32)
> ~0x3F3F00}, PchSataTopoDirectConnect},
> - {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32)
> ~0x3F3F00}, PchSataTopoUnknown},
> - {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32)
> ~0x1F0000}, PchPcieTopoUnknown},
> - {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32)
> ~0x1F0000}, PchPcieTopox1},
> - {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32)
> ~0x1F0000}, PchPcieTopoUnknown},
> - {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32)
> ~0x3F3F00}, PchSataTopoUnknown},
> - {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32)
> ~0x3F3F00}, PchSataTopoUnknown},
> - {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32)
> ~0x3F3F00}, PchSataTopoUnknown},
> -};
> -
> -UINT16 PchLpHsioPtss_Bx_N1xxWU_Size =
> sizeof(PchLpHsioPtss_Bx_N1xxWU) / sizeof(HSIO_PTSS_TABLES);
> -
> -#endif // N1_XX_WU_HSIO_PTSS_H_
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxW
> USpdTable.c
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxW
> USpdTable.c
> deleted file mode 100644
> index 18a04eba17..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxW
> USpdTable.c
> +++ /dev/null
> @@ -1,426 +0,0 @@
> -/** @file
> - GPIO definition table for N1xxWU
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#ifndef _N1_XX_WU_SPD_TABLE_H_
> -#define _N1_XX_WU_SPD_TABLE_H_
> -
> -//
> -// DQByteMap[0] - ClkDQByteMap:
> -// If clock is per rank, program to [0xFF, 0xFF]
> -// If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF]
> -// If clock is shared by 2 ranks but does not go to all bytes,
> -// Entry[i] defines which DQ bytes Group i services
> -// DQByteMap[1] - CmdNDQByteMap: Entry[0] is CmdN/CAA and Entry[1] is
> CmdN/CAB
> -// DQByteMap[2] - CmdSDQByteMap: Entry[0] is CmdS/CAA and Entry[1] is
> CmdS/CAB
> -// DQByteMap[3] - CkeDQByteMap : Entry[0] is CKE /CAA and Entry[1] is CKE
> /CAB
> -// For DDR, DQByteMap[3:1] = [0xFF, 0]
> -// DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0] since we
> have 1 CTL / rank
> -// Variable only exists to make the
> code easier to use
> -// DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0] since we
> have 1 CA Vref
> -// Variable only exists to make the
> code easier to use
> -//
> -//
> -// DQ byte mapping to CMD/CTL/CLK, from the CPU side - for SKL RVP3, SKL
> SDS - used by SKL/KBL MRC
> -//
> -GLOBAL_REMOVE_IF_UNREFERENCED const UINT8
> mDqByteMapSklRvp3[2][6][2] = {
> - // Channel 0:
> - {
> - { 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to
> package 1 - Bytes[7:4]
> - { 0x00, 0xF0 }, // CmdN does not have CAA, CAB goes to Bytes[7:4]
> - { 0x0F, 0xF0 }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to
> Byte[7:4]
> - { 0x0F, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB
> - { 0xFF, 0x00 }, // CTL (CS) goes to all bytes
> - { 0xFF, 0x00 } // CA Vref is one for all bytes
> - },
> - // Channel 1:
> - {
> - { 0x33, 0xCC }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to
> package 1 - Bytes[7:4]
> - { 0x00, 0xCC }, // CmdN does not have CAA, CAB goes to Bytes[7:4]
> - { 0x33, 0xCC }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to
> Byte[7:4]
> - { 0x33, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB
> - { 0xFF, 0x00 }, // CTL (CS) goes to all bytes
> - { 0xFF, 0x00 } // CA Vref is one for all bytes
> - }
> -};
> -
> -//
> -// DQS byte swizzling between CPU and DRAM - for SKL DOE RVP
> -//
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED const UINT8
> mDqsMapCpu2DramSklRvp3[2][8] = {
> - { 0, 1, 3, 2, 4, 5, 6, 7 }, // Channel 0
> - { 1, 0, 4, 5, 2, 3, 6, 7 } // Channel 1
> -};
> -
> -// Samsung K4E6E304ED-EGCF 178b QDP LPDDR3, 4Gb die (256Mx16), x16
> -// or Hynix H9CCNNNBLTALAR-NUD
> -// or similar
> -// 1867, 14-17-17-40
> -// 2 ranks per channel, 2 SDRAMs per rank, 8x4Gb = 4GB total per channel
> -GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSkylakeRvp16Spd[] = {
> - 0x24, ///< 0 Number of Serial
> PD Bytes Written / SPD Device Size
> - 0x20, ///< 1 SPD Revision
> - 0x0F, ///< 2 DRAM Device Type
> - 0x0E, ///< 3 Module Type
> - 0x14, ///< 4 SDRAM Density
> and Banks: 8 Banks, 4 Gb SDRAM density
> - 0x12, ///< 5 SDRAM Addressing:
> 14 Rows, 11 Columns
> - 0xB5, ///< 6 SDRAM Package
> Type: QDP, 1 Channel per die, Signal Loading Matrix 1
> - 0x00, ///< 7 SDRAM Optional
> Features
> - 0x00, ///< 8 SDRAM Thermal
> and Refresh Options
> - 0x00, ///< 9 Other SDRAM
> Optional Features
> - 0x00, ///< 10 Reserved - must be
> coded as 0x00
> - 0x03, ///< 11 Module Nominal
> Voltage, VDD
> - 0x0A, ///< 12 Module
> Organization, SDRAM width: 16 bits, 2 Ranks
> - 0x23, ///< 13 Module Memory
> Bus Width: 2 channels, 64 bit channel bus width
> - 0x00, ///< 14 Module Thermal
> Sensor
> - 0x00, ///< 15 Extended Module
> Type
> - 0x00, ///< 16 Reserved - must be
> coded as 0x00
> - 0x00, ///< 17 Timebases
> - 0x09, ///< 18 SDRAM Minimum
> Cycle Time (tCKmin): tCKmin = 1.071ns (LPDDR3-1867)
> - 0xFF, ///< 19 SDRAM Minimum
> Cycle Time (tCKmax)
> - 0xD4, ///< 20 CAS Latencies
> Supported, First Byte (tCK): 14, 12, 10, 8
> - 0x00, ///< 21 CAS Latencies
> Supported, Second Byte
> - 0x00, ///< 22 CAS Latencies
> Supported, Third Byte
> - 0x00, ///< 23 CAS Latencies
> Supported, Fourth Byte
> - 0x78, ///< 24 Minimum CAS
> Latency Time (tAAmin) = 14.994 ns
> - 0x00, ///< 25 Read and Write
> Latency Set Options
> - 0x90, ///< 26 Minimum RAS# to
> CAS# Delay Time (tRCDmin)
> - 0xA8, ///< 27 Minimum Row
> Precharge Delay Time for all banks (tRPab)
> - 0x90, ///< 28 Minimum Row
> Precharge Delay Time per bank (tRPpb)
> - 0x10, ///< 29 Minimum Refresh
> Recovery Delay Time for all banks (tRFCab), Least Significant Byte
> - 0x04, ///< 30 Minimum Refresh
> Recovery Delay Time for all banks (tRFCab), Most Significant Byte
> - 0xE0, ///< 31 Minimum Refresh
> Recovery Delay Time for per bank (tRFCpb), Least Significant Byte
> - 0x01, ///< 32 Minimum Refresh
> Recovery Delay Time for per bank (tRFCpb), Most Significant Byte
> - 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 Connector to SDRAM Bit
> Mapping
> - 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 77 Connector to SDRAM Bit
> Mapping
> - 0, 0, ///< 78 - 79
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
> - 0x00, ///< 120 Fine Offset for
> Minimum Row Precharge Delay Time per bank (tRPpb)
> - 0x00, ///< 121 Fine Offset for
> Minimum Row Precharge Delay Time for all banks (tRPab)
> - 0x00, ///< 122 Fine Offset for
> Minimum RAS# to CAS# Delay Time (tRCDmin)
> - 0xFA, ///< 123 Fine Offset for
> Minimum CAS Latency Time (tAAmin): 14.994 ns (LPDDR3-1867)
> - 0x7F, ///< 124 Fine Offset for
> SDRAM Minimum Cycle Time (tCKmax): 32.002 ns
> - 0xCA, ///< 125 Fine Offset for
> SDRAM Minimum Cycle Time (tCKmin): 1.071 ns (LPDDR-1867)
> - 0x00, ///< 126 CRC A
> - 0x00, ///< 127 CRC B
> - 0, 0, ///< 128 - 129
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
> - 0x00, ///< 320 Module
> Manufacturer ID Code, Least Significant Byte
> - 0x00, ///< 321 Module
> Manufacturer ID Code, Most Significant Byte
> - 0x00, ///< 322 Module
> Manufacturing Location
> - 0x00, ///< 323 Module
> Manufacturing Date Year
> - 0x00, ///< 324 Module
> Manufacturing Date Week
> - 0x55, ///< 325 Module Serial
> Number A
> - 0x00, ///< 326 Module Serial
> Number B
> - 0x00, ///< 327 Module Serial
> Number C
> - 0x00, ///< 328 Module Serial
> Number D
> - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part
> Number: Unused bytes coded as ASCII Blanks (0x20)
> - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part
> Number
> - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part
> Number
> - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part
> Number
> - 0x00, ///< 349 Module Revision
> Code
> - 0x00, ///< 350 DRAM
> Manufacturer ID Code, Least Significant Byte
> - 0x00, ///< 351 DRAM
> Manufacturer ID Code, Most Significant Byte
> - 0x00, ///< 352 DRAM Stepping
> - 0, 0, 0, 0, 0, 0, 0, ///< 353 - 359
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 440 - 449
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509
> - 0, 0 ///< 510 - 511
> -};
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSkylakeRvp16SpdSize
> = sizeof (mSkylakeRvp16Spd);
> -
> -//Hynix H9CCNNNBJTMLAR-NUD, DDP, LPDDR3, 8Gb die
> -//1867
> -GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSkylakeRvp3Spd110[] =
> {
> - 0x91, ///< 0 Number of Serial
> PD Bytes Written / SPD Device Size / CRC Coverage 1, 2
> - 0x20, ///< 1 SPD Revision
> - 0xF1, ///< 2 DRAM Device
> Type
> - 0x03, ///< 3 Module Type
> - 0x05, ///< 4 SDRAM Density
> and Banks, 8Gb
> - 0x19, ///< 5 SDRAM
> Addressing: 15 Rows, 10 Columns
> - 0x05, ///< 6 Module Nominal
> Voltage
> - 0x0B, ///< 7 Module
> Organization: 32 bits, 2 Ranks
> - 0x03, ///< 8 Module Memory
> Bus Width
> - 0x11, ///< 9 Fine Timebase
> (FTB) Dividend / Divisor
> - 0x01, ///< 10 Medium
> Timebase (MTB) Dividend
> - 0x08, ///< 11 Medium
> Timebase (MTB) Divisor
> - 0x09, ///< 12 SDRAM
> Minimum Cycle Time (tCKmin): tCKmin = 1.071 ns (LPDDR3-1867)
> - 0x00, ///< 13 Reserved0
> - 0x50, ///< 14 CAS Latencies
> supported (tCK): 14, 12, 10, 8 (LSB)
> - 0x05, ///< 15 CAS Latencies
> supported (tCK): 14, 12, 10, 8 (LSB)
> - 0x78, ///< 16 Minimum CAS
> Latency (tAAmin) = 14.994 ns
> - 0x78, ///< 17 Minimum Write
> Recovery Time (tWRmin)
> - 0x90, ///< 18 Minimum RAS#
> to CAS# Delay Time (tRCDmin)
> - 0x50, ///< 19 Minimum Row
> Active to Row Active Delay Time (tRRDmin)
> - 0x90, ///< 20 Minimum Row
> Precharge Delay Time (tRPmin)
> - 0x11, ///< 21 Upper Nibbles
> for tRAS and tRC
> - 0x50, ///< 22 Minimum Active
> to Precharge Delay Time (tRASmin), Least Significant Byte
> - 0xE0, ///< 23 Minimum Active
> to Active/Refresh Delay Time (tRCmin), Least Significant Byte
> - 0x90, ///< 24 Minimum
> Refresh Recovery Delay Time (tRFCmin), Least Significant Byte
> - 0x06, ///< 25 Minimum
> Refresh Recovery Delay Time (tRFCmin), Most Significant Byte
> - 0x3C, ///< 26 Minimum
> Internal Write to Read Command Delay Time (tWTRmin)
> - 0x3C, ///< 27 Minimum
> Internal Read to Precharge Command Delay Time (tRTPmin)
> - 0x01, ///< 28 Upper Nibble for
> tFAW
> - 0x90, ///< 29 Minimum Four
> Activate Window Delay Time (tFAWmin)
> - 0x00, ///< 30 SDRAM Optional
> Features
> - 0x00, ///< 31
> SDRAMThermalAndRefreshOptions
> - 0x00, ///< 32
> ModuleThermalSensor
> - 0x00, ///< 33 SDRAM Device
> Type
> - 0xCA, ///< 34 Fine Offset for
> SDRAM Minimum Cycle Time (tCKmin): 1.071 ns (LPDDR3-1867)
> - 0xFA, ///< 35 Fine Offset for
> Minimum CAS Latency Time (tAAmin): 14.994 ns (LPDDR3-1867)
> - 0x00, ///< 36 Fine Offset for
> Minimum RAS# to CAS# Delay Time (tRCDmin)
> - 0x00, ///< 37 Fine Offset for
> Minimum Row Precharge Delay Time (tRPmin)
> - 0x00, ///< 38 Fine Offset for
> Minimum Active to Active/Refresh Delay Time (tRCmin)
> - 0xA8, ///< 39 Row precharge
> time for all banks (tRPab)
> - 0x00, ///< 40 FTB for Row
> precharge time for all banks (tRPab)
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 41 - 49
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
> - 0, 0, ///< 60 - 61
> - 0x00, ///< 62 Reference Raw
> Card Used
> - 0x00, ///< 63 Address
> Mapping from Edge Connector to DRAM
> - 0x00, ///< 64
> ThermalHeatSpreaderSolution
> - 0, 0, 0, 0, 0, ///< 65 - 69
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
> - 0, 0, 0, 0, 0, 0, 0, ///< 110 - 116
> - 0x00, ///< 117 Module
> Manufacturer ID Code, Least Significant Byte
> - 0x00, ///< 118 Module
> Manufacturer ID Code, Most Significant Byte
> - 0x00, ///< 119 Module
> Manufacturing Location
> - 0x00, ///< 120 Module
> Manufacturing Date Year
> - 0x00, ///< 121 Module
> Manufacturing Date creation work week
> - 0x55, ///< 122 Module Serial
> Number A
> - 0x00, ///< 123 Module Serial
> Number B
> - 0x00, ///< 124 Module Serial
> Number C
> - 0x00, ///< 125 Module Serial
> Number D
> - 0x00, ///< 126 CRC A
> - 0x00 ///< 127 CRC B
> -};
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED const UINT16
> mSkylakeRvp3Spd110Size = sizeof (mSkylakeRvp3Spd110);
> -
> -//
> -// Micron MT52L512M32D2PF 78b DDP LPDDR3, 8Gb die (256Mx32), x32
> -//
> -GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mKblRSpdLpddr32133[] =
> {
> - 0x91, ///< 0 128 SPD bytes
> used, 256 total, CRC covers 0..116
> - 0x20, ///< 1 SPD Revision 2.0
> - 0xF1, ///< 2 DRAM Type:
> LPDDR3 SDRAM
> - 0x03, ///< 3 Module Type:
> SO-DIMM
> - 0x05, ///< 4 8 Banks, 8 Gb
> SDRAM density
> - 0x19, ///< 5 SDRAM
> Addressing: 15 Rows, 10 Columns
> - 0x05, ///< 6 Module Nominal
> Voltage VDD: 1.2v
> - 0x0B, ///< 7 SDRAM width:
> 32 bits, 2 Ranks
> - 0x03, ///< 8 SDRAM bus
> width: 64 bits, no ECC
> - 0x11, ///< 9 Fine Timebase
> (FTB) granularity: 1 ps
> - 0x01, ///< 10 Medium
> Timebase (MTB) : 0.125 ns
> - 0x08, ///< 11 Medium
> Timebase Divisor
> - 0x08, ///< 12 tCKmin = 0.938
> ns (LPDDR3-2133)
> - 0x00, ///< 13 Reserved
> - 0x50, ///< 14 CAS Latencies
> supported (tCK): 16, 14, 12, 10, 8 (LSB)
> - 0x15, ///< 15 CAS Latencies
> supported (tCK): 16, 14, 12, 10, 8 (MSB)
> - 0x78, ///< 16 Minimum CAS
> Latency (tAAmin) = 15.008 ns
> - 0x78, ///< 17 tWR = 15 ns
> - 0x90, ///< 18 Minimum
> RAS-to-CAS delay (tRCDmin) = 18 ns
> - 0x50, ///< 19 tRRD = 10 ns
> - 0x90, ///< 20 Minimum row
> precharge time (tRPmin) = 18 ns
> - 0x11, ///< 21 Upper nibbles
> for tRAS and tRC
> - 0x50, ///< 22 tRASmin = 42 ns
> - 0xE0, ///< 23 tRCmin =
> (tRASmin + tRPmin) = 60 ns
> - 0x90, ///< 24 tRFCmin =
> (tRFCab) = 210 ns (8Gb)
> - 0x06, ///< 25 tRFCmin MSB
> - 0x3C, ///< 26 tWTRmin = 7.5
> ns
> - 0x3C, ///< 27 tRTPmin = 7.5 ns
> - 0x01, ///< 28 tFAWmin upper
> nibble
> - 0x90, ///< 29 tFAWmin = 50 ns
> - 0x00, ///< 30 SDRAM Optional
> Features - none
> - 0x00, ///< 31 SDRAM Thermal
> / Refresh options - none
> - 0x00, ///< 32
> ModuleThermalSensor
> - 0x00, ///< 33 SDRAM Device
> Type
> - 0xC2, ///< 34 FTB for tCKmin =
> 0.938 ns (LPDDR3-2133)
> - 0x08, ///< 35 FTB for tAAmin =
> 15.008 ns (LPDDR3-2133)
> - 0x00, ///< 36 Fine Offset for
> Minimum RAS# to CAS# Delay Time (tRCDmin)
> - 0x00, ///< 37 Fine Offset for
> Minimum Row Precharge Delay Time (tRPmin)
> - 0x00, ///< 38 Fine Offset for
> Minimum Active to Active/Refresh Delay Time (tRCmin)
> - 0xA8, ///< 39 Row precharge
> time for all banks (tRPab)= 21 ns
> - 0x00, ///< 40 FTB for Row
> precharge time for all banks (tRPab) = 0
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 41 - 49
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
> - 0, 0, ///< 60 - 61
> - 0x00, ///< 62 Reference Raw
> Card Used
> - 0x00, ///< 63 Rank1 Mapping:
> Standard
> - 0x00, ///< 64
> ThermalHeatSpreaderSolution
> - 0, 0, 0, 0, 0, ///< 65 - 69
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
> - 0, 0, 0, 0, 0, 0, 0, ///< 110 - 116
> - 0x00, ///< 117 Module
> Manufacturer ID Code, Least Significant Byte
> - 0x00, ///< 118 Module
> Manufacturer ID Code, Most Significant Byte
> - 0x00, ///< 119 Module
> Manufacturing Location
> - 0x00, ///< 120 Module
> Manufacturing Date Year
> - 0x00, ///< 121 Module
> Manufacturing Date creation work week
> - 0x55, ///< 122 Module ID:
> Module Serial Number
> - 0x00, ///< 123 Module Serial
> Number B
> - 0x00, ///< 124 Module Serial
> Number C
> - 0x00, ///< 125 Module Serial
> Number D
> - 0x00, ///< 126 CRC A
> - 0x00 ///< 127 CRC B
> -};
> -GLOBAL_REMOVE_IF_UNREFERENCED const UINT16
> mKblRSpdLpddr32133Size = sizeof (mKblRSpdLpddr32133);
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSpdLpddr32133[] = {
> - 0x24, ///< 0 Number of Serial
> PD Bytes Written / SPD Device Size
> - 0x01, ///< 1 SPD Revision
> - 0x0F, ///< 2 DRAM Device Type
> - 0x0E, ///< 3 Module Type
> - 0x15, ///< 4 SDRAM Density
> and Banks: 8 Banks, 8 Gb SDRAM density
> - 0x19, ///< 5 SDRAM Addressing:
> 15 Rows, 10 Columns
> - 0x90, ///< 6 SDRAM Package
> Type: QDP, 1 Channel per die, Signal Loading Matrix 1
> - 0x00, ///< 7 SDRAM Optional
> Features
> - 0x00, ///< 8 SDRAM Thermal
> and Refresh Options
> - 0x00, ///< 9 Other SDRAM
> Optional Features
> - 0x00, ///< 10 Reserved - must be
> coded as 0x00
> - 0x0B, ///< 11 Module Nominal
> Voltage, VDD
> - 0x0B, ///< 12 Module
> Organization, SDRAM width: 32 bits, 2 Ranks
> - 0x03, ///< 13 Module Memory
> Bus Width: 2 channels, 64 bit channel bus width
> - 0x00, ///< 14 Module Thermal
> Sensor
> - 0x00, ///< 15 Extended Module
> Type
> - 0x00, ///< 16 Reserved - must be
> coded as 0x00
> - 0x00, ///< 17 Timebases
> - 0x08, ///< 18 SDRAM Minimum
> Cycle Time (tCKmin)
> - 0xFF, ///< 19 SDRAM Minimum
> Cycle Time (tCKmax)
> - 0xD4, ///< 20 CAS Latencies
> Supported, First Byte
> - 0x01, ///< 21 CAS Latencies
> Supported, Second Byte
> - 0x00, ///< 22 CAS Latencies
> Supported, Third Byte
> - 0x00, ///< 23 CAS Latencies
> Supported, Fourth Byte
> - 0x78, ///< 24 Minimum CAS
> Latency Time (tAAmin)
> - 0x00, ///< 25 Read and Write
> Latency Set Options
> - 0x90, ///< 26 Minimum RAS# to
> CAS# Delay Time (tRCDmin)
> - 0xA8, ///< 27 Minimum Row
> Precharge Delay Time for all banks (tRPab)
> - 0x90, ///< 28 Minimum Row
> Precharge Delay Time per bank (tRPpb)
> - 0x90, ///< 29 Minimum Refresh
> Recovery Delay Time for all banks (tRFCab), Least Significant Byte
> - 0x06, ///< 30 Minimum Refresh
> Recovery Delay Time for all banks (tRFCab), Most Significant Byte
> - 0xD0, ///< 31 Minimum Refresh
> Recovery Delay Time for per bank (tRFCpb), Least Significant Byte
> - 0x02, ///< 32 Minimum Refresh
> Recovery Delay Time for per bank (tRFCpb), Most Significant Byte
> - 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 Connector to SDRAM Bit
> Mapping
> - 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 77 Connector to SDRAM Bit
> Mapping
> - 0, 0, ///< 78 - 79
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
> - 0x00, ///< 120 Fine Offset for
> Minimum Row Precharge Delay Time per bank (tRPpb)
> - 0x00, ///< 121 Fine Offset for
> Minimum Row Precharge Delay Time for all banks (tRPab)
> - 0x00, ///< 122 Fine Offset for
> Minimum RAS# to CAS# Delay Time (tRCDmin)
> - 0x08, ///< 123 Fine Offset for
> Minimum CAS Latency Time (tAAmin)
> - 0x7F, ///< 124 Fine Offset for
> SDRAM Minimum Cycle Time (tCKmax)
> - 0xC2, ///< 125 Fine Offset for
> SDRAM Minimum Cycle Time (tCKmin)
> - 0x00, ///< 126 CRC A
> - 0x00, ///< 127 CRC B
> - 0, 0, ///< 128 - 129
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
> - 0x00, ///< 320 Module
> Manufacturer ID Code, Least Significant Byte
> - 0x00, ///< 321 Module
> Manufacturer ID Code, Most Significant Byte
> - 0x00, ///< 322 Module
> Manufacturing Location
> - 0x00, ///< 323 Module
> Manufacturing Date Year
> - 0x00, ///< 324 Module
> Manufacturing Date Week
> - 0x55, ///< 325 Module Serial
> Number A
> - 0x00, ///< 326 Module Serial
> Number B
> - 0x00, ///< 327 Module Serial
> Number C
> - 0x00, ///< 328 Module Serial
> Number D
> - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part
> Number: Unused bytes coded as ASCII Blanks (0x20)
> - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part
> Number
> - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part
> Number
> - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part
> Number
> - 0x00, ///< 349 Module Revision
> Code
> - 0x00, ///< 350 DRAM
> Manufacturer ID Code, Least Significant Byte
> - 0x00, ///< 351 DRAM
> Manufacturer ID Code, Most Significant Byte
> - 0x00, ///< 352 DRAM Stepping
> - 0, 0, 0, 0, 0, 0, 0, ///< 353 - 359
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 440 - 449
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509
> - 0, 0 ///< 510 - 511
> -};
> -GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSpdLpddr32133Size =
> sizeof (mSpdLpddr32133);
> -
> -#endif // _N1_XX_WU_SPD_TABLE_H_
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoar
> dInitPostMemLib.c
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoar
> dInitPostMemLib.c
> deleted file mode 100644
> index b7ff3062b2..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoar
> dInitPostMemLib.c
> +++ /dev/null
> @@ -1,39 +0,0 @@
> -/** @file
> - Board post-memory initialization.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <PiPei.h>
> -#include <Library/BaseLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/BoardInitLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/DebugLib.h>
> -
> -EFI_STATUS
> -EFIAPI
> -N1xxWUBoardInitBeforeSiliconInit (
> - VOID
> - );
> -
> -EFI_STATUS
> -EFIAPI
> -BoardInitBeforeSiliconInit (
> - VOID
> - )
> -{
> - N1xxWUBoardInitBeforeSiliconInit ();
> - return EFI_SUCCESS;
> -}
> -
> -EFI_STATUS
> -EFIAPI
> -BoardInitAfterSiliconInit (
> - VOID
> - )
> -{
> - return EFI_SUCCESS;
> -}
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoar
> dInitPreMemLib.c
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoar
> dInitPreMemLib.c
> deleted file mode 100644
> index c1fe2a55c0..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoar
> dInitPreMemLib.c
> +++ /dev/null
> @@ -1,105 +0,0 @@
> -/** @file
> - Board post-memory initialization.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <PiPei.h>
> -#include <Library/BaseLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/BoardInitLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/DebugLib.h>
> -
> -EFI_STATUS
> -EFIAPI
> -N1xxWUBoardDetect (
> - VOID
> - );
> -
> -EFI_BOOT_MODE
> -EFIAPI
> -N1xxWUBoardBootModeDetect (
> - VOID
> - );
> -
> -EFI_STATUS
> -EFIAPI
> -N1xxWUBoardDebugInit (
> - VOID
> - );
> -
> -EFI_STATUS
> -EFIAPI
> -N1xxWUBoardInitBeforeMemoryInit (
> - VOID
> - );
> -
> -EFI_STATUS
> -EFIAPI
> -BoardDetect (
> - VOID
> - )
> -{
> - N1xxWUBoardDetect ();
> - return EFI_SUCCESS;
> -}
> -
> -EFI_STATUS
> -EFIAPI
> -BoardDebugInit (
> - VOID
> - )
> -{
> - N1xxWUBoardDebugInit ();
> - return EFI_SUCCESS;
> -}
> -
> -EFI_BOOT_MODE
> -EFIAPI
> -BoardBootModeDetect (
> - VOID
> - )
> -{
> - return N1xxWUBoardBootModeDetect ();
> -}
> -
> -EFI_STATUS
> -EFIAPI
> -BoardInitBeforeMemoryInit (
> - VOID
> - )
> -{
> - N1xxWUBoardInitBeforeMemoryInit ();
> - return EFI_SUCCESS;
> -}
> -
> -EFI_STATUS
> -EFIAPI
> -BoardInitAfterMemoryInit (
> - VOID
> - )
> -{
> - return EFI_SUCCESS;
> -}
> -
> -EFI_STATUS
> -EFIAPI
> -BoardInitBeforeTempRamExit (
> - VOID
> - )
> -{
> - return EFI_SUCCESS;
> -}
> -
> -EFI_STATUS
> -EFIAPI
> -BoardInitAfterTempRamExit (
> - VOID
> - )
> -{
> - return EFI_SUCCESS;
> -}
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMult
> iBoardInitPostMemLib.c
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMult
> iBoardInitPostMemLib.c
> deleted file mode 100644
> index 8570039624..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMult
> iBoardInitPostMemLib.c
> +++ /dev/null
> @@ -1,40 +0,0 @@
> -/** @file
> - Multi-board post-memory initialization.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <PiPei.h>
> -#include <Library/BaseLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/BoardInitLib.h>
> -#include <Library/MultiBoardInitSupportLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/DebugLib.h>
> -
> -#include <N1xxWUId.h>
> -
> -EFI_STATUS
> -EFIAPI
> -N1xxWUBoardInitBeforeSiliconInit (
> - VOID
> - );
> -
> -BOARD_POST_MEM_INIT_FUNC mN1xxWUBoardInitFunc = {
> - N1xxWUBoardInitBeforeSiliconInit,
> - NULL, // BoardInitAfterSiliconInit
> -};
> -
> -EFI_STATUS
> -EFIAPI
> -PeiN1xxWUMultiBoardInitLibConstructor (
> - VOID
> - )
> -{
> - if (LibPcdGetSku () == BoardIdN1xxWU) {
> - return RegisterBoardPostMemInit (&mN1xxWUBoardInitFunc);
> - }
> - return EFI_SUCCESS;
> -}
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMult
> iBoardInitPreMemLib.c
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMult
> iBoardInitPreMemLib.c
> deleted file mode 100644
> index 842316e610..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMult
> iBoardInitPreMemLib.c
> +++ /dev/null
> @@ -1,82 +0,0 @@
> -/** @file
> - Board pre-memory initialization.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <PiPei.h>
> -#include <Library/BaseLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/BoardInitLib.h>
> -#include <Library/MultiBoardInitSupportLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/DebugLib.h>
> -
> -#include <N1xxWUId.h>
> -
> -EFI_STATUS
> -EFIAPI
> -N1xxWUBoardDetect (
> - VOID
> - );
> -
> -EFI_STATUS
> -EFIAPI
> -N1xxWUMultiBoardDetect (
> - VOID
> - );
> -
> -EFI_BOOT_MODE
> -EFIAPI
> -N1xxWUBoardBootModeDetect (
> - VOID
> - );
> -
> -EFI_STATUS
> -EFIAPI
> -N1xxWUBoardDebugInit (
> - VOID
> - );
> -
> -EFI_STATUS
> -EFIAPI
> -N1xxWUBoardInitBeforeMemoryInit (
> - VOID
> - );
> -
> -BOARD_DETECT_FUNC mN1xxWUBoardDetectFunc = {
> - N1xxWUMultiBoardDetect
> -};
> -
> -BOARD_PRE_MEM_INIT_FUNC mN1xxWUBoardPreMemInitFunc = {
> - N1xxWUBoardDebugInit,
> - N1xxWUBoardBootModeDetect,
> - N1xxWUBoardInitBeforeMemoryInit,
> - NULL, // BoardInitAfterMemoryInit
> - NULL, // BoardInitBeforeTempRamExit
> - NULL, // BoardInitAfterTempRamExit
> -};
> -
> -EFI_STATUS
> -EFIAPI
> -N1xxWUMultiBoardDetect (
> - VOID
> - )
> -{
> - N1xxWUBoardDetect ();
> - if (LibPcdGetSku () == BoardIdN1xxWU) {
> - RegisterBoardPreMemInit (&mN1xxWUBoardPreMemInitFunc);
> - }
> - return EFI_SUCCESS;
> -}
> -
> -EFI_STATUS
> -EFIAPI
> -PeiN1xxWUMultiBoardInitPreMemLibConstructor (
> - VOID
> - )
> -{
> - return RegisterBoardDetect (&mN1xxWUBoardDetectFunc);
> -}
> \ No newline at end of file
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xx
> WUDetect.c
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xx
> WUDetect.c
> deleted file mode 100644
> index 9e31a92926..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xx
> WUDetect.c
> +++ /dev/null
> @@ -1,66 +0,0 @@
> -/** @file
> - Clevo N1xxWU board detection.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <PiPei.h>
> -#include <SaPolicyCommon.h>
> -#include <Library/DebugLib.h>
> -#include <Library/BaseMemoryLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/HobLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/PchCycleDecodingLib.h>
> -#include <Library/PciLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/BaseMemoryLib.h>
> -
> -#include <Library/PeiSaPolicyLib.h>
> -#include <Library/BoardInitLib.h>
> -#include <PchAccess.h>
> -#include <Library/GpioNativeLib.h>
> -#include <Library/GpioLib.h>
> -#include <GpioPinsSklLp.h>
> -#include <GpioPinsSklH.h>
> -#include <Library/GpioExpanderLib.h>
> -#include <SioRegs.h>
> -#include <Library/PchPcrLib.h>
> -#include <Library/SiliconInitLib.h>
> -
> -#include "PeiN1xxWUInitLib.h"
> -
> -#include <ConfigBlock.h>
> -#include <ConfigBlock/MemoryConfig.h>
> -
> -BOOLEAN
> -IsN1xxWU (
> - VOID
> - )
> -{
> - // TBD: Do detection - BoardIdN1xxWU v.s. BoardIdN1xxWU
> - return TRUE;
> -}
> -
> -EFI_STATUS
> -EFIAPI
> -N1xxWUBoardDetect (
> - VOID
> - )
> -{
> - if (LibPcdGetSku () != 0) {
> - return EFI_SUCCESS;
> - }
> -
> - DEBUG ((EFI_D_INFO, "N1xxWUDetectionCallback\n"));
> -
> - if (IsN1xxWU ()) {
> - LibPcdSetSku (BoardIdN1xxWU);
> -
> - DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));
> - ASSERT (LibPcdGetSku() == BoardIdN1xxWU);
> - }
> - return EFI_SUCCESS;
> -}
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xx
> WUInitPostMemLib.c
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xx
> WUInitPostMemLib.c
> deleted file mode 100644
> index 832130e15e..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xx
> WUInitPostMemLib.c
> +++ /dev/null
> @@ -1,209 +0,0 @@
> -/** @file
> - Clevo N1xxWU board post-memory initialization.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <PiPei.h>
> -#include <SaPolicyCommon.h>
> -#include <Library/DebugLib.h>
> -#include <Library/BaseMemoryLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/HobLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/PchCycleDecodingLib.h>
> -#include <Library/PciLib.h>
> -#include <Library/PeiSaPolicyLib.h>
> -#include <Library/BoardInitLib.h>
> -#include <PchAccess.h>
> -#include <Library/GpioNativeLib.h>
> -#include <Library/GpioLib.h>
> -#include <GpioPinsSklLp.h>
> -#include <GpioPinsSklH.h>
> -#include <Library/GpioExpanderLib.h>
> -#include <SioRegs.h>
> -#include <Library/PchPcrLib.h>
> -#include <IoExpander.h>
> -#include <Library/PcdLib.h>
> -#include <Library/SiliconInitLib.h>
> -
> -#include "PeiN1xxWUInitLib.h"
> -
> -/**
> - N 1XX WU board configuration init function for PEI post memory phase.
> -
> - PEI_BOARD_CONFIG_PCD_INIT
> -
> - @param Content pointer to the buffer contain init information for
> board init.
> -
> - @retval EFI_SUCCESS The function completed successfully.
> - @retval EFI_INVALID_PARAMETER The parameter is NULL.
> -**/
> -EFI_STATUS
> -EFIAPI
> -N1xxWUInit (
> - VOID
> - )
> -{
> - PcdSet32S (PcdHdaVerbTable, (UINTN) &HdaVerbTableAlc286Rvp3);
> -
> - //
> - // Assign the GPIO table with pin configs to be used for UCMC
> - //
> - PcdSet32S (PcdBoardUcmcGpioTable,
> (UINTN)mGpioTableN1xxWUUcmcDevice);
> - PcdSet16S (PcdBoardUcmcGpioTableSize,
> mGpioTableN1xxWUUcmcDeviceSize);
> -
> - return EFI_SUCCESS;
> -}
> -
> -#define EXPANDERS 2
> // defines expander's quantity
> -
> -/**
> - Configures GPIO
> -
> - @param[in] GpioTable Point to Platform Gpio table
> - @param[in] GpioTableCount Number of Gpio table entries
> -
> -**/
> -VOID
> -ConfigureGpio (
> - IN GPIO_INIT_CONFIG *GpioDefinition,
> - IN UINT16 GpioTableCount
> - )
> -{
> - EFI_STATUS Status;
> -
> - DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));
> -
> - Status = GpioConfigurePads (GpioTableCount, GpioDefinition);
> -
> - DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n"));
> -}
> -
> -VOID
> -SetBit (
> - IN OUT UINT32 *Value,
> - IN UINT32 BitNumber,
> - IN BOOLEAN NewBitValue
> - )
> -{
> - if (NewBitValue) {
> - *Value |= 1 << BitNumber;
> - } else {
> - *Value &= ~(1 << BitNumber);
> - }
> -}
> -
> -/**
> - Configures IO Expander GPIO device
> -
> - @param[in] IOExpGpioDefinition Point to IO Expander Gpio table
> - @param[in] IOExpGpioTableCount Number of Gpio table entries
> -
> -**/
> -void
> -ConfigureIoExpanderGpio (
> - IN IO_EXPANDER_GPIO_CONFIG *IoExpGpioDefinition,
> - IN UINT16 IoExpGpioTableCount
> - )
> -{
> - UINT8 Index;
> - UINT32 Direction[EXPANDERS] = {0x00FFFFFF,
> 0x00FFFFFF};
> - UINT32 Level[EXPANDERS] = {0};
> - UINT32 Polarity[EXPANDERS] = {0};
> -
> - // IoExpander {TCA6424A}
> - DEBUG ((DEBUG_INFO, "IO Expander Configuration Start\n"));
> - for (Index = 0; Index < IoExpGpioTableCount; Index++) { //Program IO
> Expander as per the table defined in PeiPlatformHooklib.c
> - SetBit(&Direction[IoExpGpioDefinition[Index].IoExpanderNumber],
> IoExpGpioDefinition[Index].GpioPinNumber,
> (BOOLEAN)IoExpGpioDefinition[Index].GpioDirection);
> - SetBit(&Level[IoExpGpioDefinition[Index].IoExpanderNumber],
> IoExpGpioDefinition[Index].GpioPinNumber,
> (BOOLEAN)IoExpGpioDefinition[Index].GpioLevel);
> - SetBit(&Polarity[IoExpGpioDefinition[Index].IoExpanderNumber],
> IoExpGpioDefinition[Index].GpioPinNumber,
> (BOOLEAN)IoExpGpioDefinition[Index].GpioInversion);
> - }
> - for (Index = 0; Index < EXPANDERS; Index++) {
> - GpioExpBulkConfig(Index, Direction[Index], Polarity[Index],
> Level[Index]);
> - }
> - DEBUG ((DEBUG_INFO, "IO Expander Configuration End\n"));
> - return;
> -}
> -
> -/**
> - Configure GPIO behind IoExpander.
> -
> - @param[in] PeiServices General purpose services available to
> every PEIM.
> - @param[in] NotifyDescriptor
> - @param[in] Interface
> -
> - @retval EFI_SUCCESS Operation success.
> -**/
> -VOID
> -ExpanderGpioInit (
> - VOID
> - )
> -{
> - ConfigureIoExpanderGpio(mGpioTableIoExpander,
> mGpioTableIoExpanderSize);
> -}
> -
> -/**
> - Configure single GPIO pad for touchpanel interrupt
> -
> -**/
> -VOID
> -TouchpanelGpioInit (
> - VOID
> - )
> -{
> - GPIO_INIT_CONFIG* TouchpanelPad;
> - GPIO_PAD_OWN PadOwnVal;
> -
> - PadOwnVal = 0;
> - TouchpanelPad = &mGpioTableN1xxWUTouchpanel;
> -
> - GpioGetPadOwnership (TouchpanelPad->GpioPad, &PadOwnVal);
> - if (PadOwnVal == GpioPadOwnHost) {
> - GpioConfigurePads (1, TouchpanelPad);
> - }
> -}
> -
> -
> -/**
> - Configure GPIO
> -
> -**/
> -VOID
> -GpioInit (
> - VOID
> - )
> -{
> - ConfigureGpio (mGpioTableN1xxWU, mGpioTableN1xxWUSize);
> -
> - TouchpanelGpioInit();
> -
> - return;
> -}
> -
> -
> -/**
> - Configure GPIO and SIO
> -
> - @retval EFI_SUCCESS Operation success.
> -**/
> -EFI_STATUS
> -EFIAPI
> -N1xxWUBoardInitBeforeSiliconInit (
> - VOID
> - )
> -{
> - N1xxWUInit ();
> -
> - GpioInit ();
> - ExpanderGpioInit ();
> -
> - ///
> - /// Do Late PCH init
> - ///
> - LateSiliconInit ();
> -
> - return EFI_SUCCESS;
> -}
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xx
> WUInitPreMemLib.c
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xx
> WUInitPreMemLib.c
> deleted file mode 100644
> index b8eb0e67c6..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xx
> WUInitPreMemLib.c
> +++ /dev/null
> @@ -1,236 +0,0 @@
> -/** @file
> - Clevo N1xxWU board pre-memory initialization.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <PiPei.h>
> -#include <SaPolicyCommon.h>
> -#include <Library/DebugLib.h>
> -#include <Library/BaseMemoryLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/HobLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/PchCycleDecodingLib.h>
> -#include <Library/PciLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/BaseMemoryLib.h>
> -
> -#include <Library/PeiSaPolicyLib.h>
> -#include <Library/BoardInitLib.h>
> -#include <PchAccess.h>
> -#include <Library/GpioNativeLib.h>
> -#include <Library/GpioLib.h>
> -#include <GpioPinsSklLp.h>
> -#include <GpioPinsSklH.h>
> -#include <Library/GpioExpanderLib.h>
> -#include <SioRegs.h>
> -#include <Library/PchPcrLib.h>
> -#include <Library/SiliconInitLib.h>
> -
> -#include "PeiN1xxWUInitLib.h"
> -
> -#include <ConfigBlock.h>
> -#include <ConfigBlock/MemoryConfig.h>
> -
> -//
> -// Reference RCOMP resistors on motherboard - for SKL RVP1
> -//
> -GLOBAL_REMOVE_IF_UNREFERENCED const UINT16
> RcompResistorSklRvp1[SA_MRC_MAX_RCOMP] = { 200, 81, 162 };
> -//
> -// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for
> SKL RVP1
> -//
> -GLOBAL_REMOVE_IF_UNREFERENCED const UINT16
> RcompTargetSklRvp1[SA_MRC_MAX_RCOMP_TARGETS] = { 100, 40, 40, 23,
> 40 };
> -
> -//
> -// Reference RCOMP resistors on motherboard - for SKL RVP2
> -//
> -GLOBAL_REMOVE_IF_UNREFERENCED const UINT16
> RcompResistorSklRvp2[SA_MRC_MAX_RCOMP] = { 121, 81, 100 };
> -//
> -// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for
> SKL RVP2
> -//
> -GLOBAL_REMOVE_IF_UNREFERENCED const UINT16
> RcompTargetSklRvp2[SA_MRC_MAX_RCOMP_TARGETS] = { 100, 40, 20, 20,
> 26 };
> -
> -/**
> - N 1XX WU board configuration init function for PEI pre-memory phase.
> -
> - PEI_BOARD_CONFIG_PCD_INIT
> -
> - @param Content pointer to the buffer contain init information for
> board init.
> -
> - @retval EFI_SUCCESS The function completed successfully.
> - @retval EFI_INVALID_PARAMETER The parameter is NULL.
> -**/
> -EFI_STATUS
> -EFIAPI
> -N1xxWUInitPreMem (
> - VOID
> - )
> -{
> - PcdSet32S (PcdPcie0WakeGpioNo, 0);
> - PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);
> - PcdSet32S (PcdPcie0HoldRstGpioNo, 8);
> - PcdSetBoolS (PcdPcie0HoldRstActive, TRUE);
> - PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);
> - PcdSet32S (PcdPcie0PwrEnableGpioNo, 16);
> - PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);
> -
> - //
> - // HSIO PTSS Table
> - //
> - PcdSet32S (PcdSpecificLpHsioPtssTable1, (UINTN)
> PchLpHsioPtss_Bx_N1xxWU);
> - PcdSet16S (PcdSpecificLpHsioPtssTable1Size, (UINTN)
> PchLpHsioPtss_Bx_N1xxWU_Size);
> - PcdSet32S (PcdSpecificLpHsioPtssTable2, (UINTN)
> PchLpHsioPtss_Cx_N1xxWU);
> - PcdSet16S (PcdSpecificLpHsioPtssTable2Size, (UINTN)
> PchLpHsioPtss_Cx_N1xxWU_Size);
> -
> - //
> - // DRAM related definition
> - //
> - PcdSet8S (PcdSaMiscUserBd, 5);
> -
> - PcdSet8S (PcdMrcSpdAddressTable0, 0xA0);
> - PcdSet8S (PcdMrcSpdAddressTable1, 0xA2);
> - PcdSet8S (PcdMrcSpdAddressTable2, 0xA4);
> - PcdSet8S (PcdMrcSpdAddressTable3, 0xA6);
> -
> -
> - PcdSetBoolS(PcdMrcDqPinsInterleavedControl, TRUE);
> - PcdSetBoolS(PcdMrcDqPinsInterleaved, TRUE);
> - PcdSet32S(PcdMrcRcompResistor, (UINTN)RcompResistorSklRvp2);
> - PcdSet32S(PcdMrcRcompTarget, (UINTN)RcompTargetSklRvp2);
> - PcdSet8S(PcdMrcCaVrefConfig, 2); // DDR4 boards
> -
> - PcdSetBoolS (PcdIoExpanderPresent, TRUE);
> -
> - return EFI_SUCCESS;
> -}
> -
> -#define SIO_RUNTIME_REG_BASE_ADDRESS
> 0x0680
> -
> -/**
> - Configures GPIO
> -
> - @param[in] GpioTable Point to Platform Gpio table
> - @param[in] GpioTableCount Number of Gpio table entries
> -
> -**/
> -VOID
> -ConfigureGpio (
> - IN GPIO_INIT_CONFIG *GpioDefinition,
> - IN UINT16 GpioTableCount
> - )
> -{
> - EFI_STATUS Status;
> -
> - DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));
> -
> - Status = GpioConfigurePads (GpioTableCount, GpioDefinition);
> -
> - DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n"));
> -}
> -
> -/**
> - Configure GPIO Before Memory is not ready.
> -
> -**/
> -VOID
> -GpioInitPreMem (
> - VOID
> - )
> -{
> - // ConfigureGpio ();
> -}
> -
> -/**
> - Configure Super IO
> -
> -**/
> -VOID
> -SioInit (
> - VOID
> - )
> -{
> - //
> - // Program and Enable Default Super IO Configuration Port Addresses
> and range
> - //
> - PchLpcGenIoRangeSet (PcdGet16 (PcdLpcSioConfigDefaultPort) & (~0xF),
> 0x10);
> -
> - //
> - // 128 Byte Boundary and SIO Runtime Register Range is 0x0 to 0xF;
> - //
> - PchLpcGenIoRangeSet (SIO_RUNTIME_REG_BASE_ADDRESS & (~0x7F),
> 0x10);
> -
> - return;
> -}
> -
> -/**
> - Configues the IC2 Controller on which GPIO Expander Communicates.
> - This Function is to enable the I2CGPIOExapanderLib to programm the
> Gpios
> - Complete intilization will be done in later Stage
> -
> -**/
> -VOID
> -EFIAPI
> -I2CGpioExpanderInitPreMem(
> - VOID
> - )
> -{
> - ConfigureSerialIoController (PchSerialIoIndexI2C4,
> PchSerialIoAcpiHidden);
> - SerialIoI2cGpioInit (PchSerialIoIndexI2C4, PchSerialIoAcpiHidden,
> PchSerialIoIs33V);
> -}
> -
> -/**
> - Configure GPIO and SIO before memory ready
> -
> - @retval EFI_SUCCESS Operation success.
> -**/
> -EFI_STATUS
> -EFIAPI
> -N1xxWUBoardInitBeforeMemoryInit (
> - VOID
> - )
> -{
> - N1xxWUInitPreMem ();
> -
> - //
> - // Configures the I2CGpioExpander
> - //
> - if (PcdGetBool (PcdIoExpanderPresent)) {
> - I2CGpioExpanderInitPreMem();
> - }
> -
> - GpioInitPreMem ();
> - SioInit ();
> -
> - ///
> - /// Do basic PCH init
> - ///
> - SiliconInit ();
> -
> - return EFI_SUCCESS;
> -}
> -
> -EFI_STATUS
> -EFIAPI
> -N1xxWUBoardDebugInit (
> - VOID
> - )
> -{
> - ///
> - /// Do Early PCH init
> - ///
> - EarlySiliconInit ();
> - return EFI_SUCCESS;
> -}
> -
> -EFI_BOOT_MODE
> -EFIAPI
> -N1xxWUBoardBootModeDetect (
> - VOID
> - )
> -{
> - return BOOT_WITH_FULL_CONFIGURATION;
> -}
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platform/Intel/Min
> PlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platform/Intel/Min
> PlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c
> deleted file mode 100644
> index b784026c1b..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platform/Intel/Min
> PlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c
> +++ /dev/null
> @@ -1,640 +0,0 @@
> -/** @file
> - Source code file for Platform Init Pre-Memory PEI module
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <Base.h>
> -#include <IndustryStandard/Pci30.h>
> -#include <Library/IoLib.h>
> -#include <Library/DebugLib.h>
> -#include <Library/HobLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/TimerLib.h>
> -#include <Library/BaseMemoryLib.h>
> -#include <Library/PeiServicesLib.h>
> -#include <Library/MtrrLib.h>
> -#include <Library/ReportFvLib.h>
> -#include <Ppi/ReadOnlyVariable2.h>
> -#include <Ppi/MemoryDiscovered.h>
> -#include <Ppi/FirmwareVolumeInfo.h>
> -#include <Ppi/BootInRecoveryMode.h>
> -#include <Ppi/MasterBootMode.h>
> -#include <Guid/FirmwareFileSystem2.h>
> -#include <Library/PeiServicesTablePointerLib.h>
> -#include <Library/BoardInitLib.h>
> -#include <Library/TestPointCheckLib.h>
> -#include <Guid/MemoryTypeInformation.h>
> -#include <Ppi/PlatformMemorySize.h>
> -#include <Ppi/BaseMemoryTest.h>
> -
> -EFI_STATUS
> -EFIAPI
> -MemoryDiscoveredPpiNotifyCallback (
> - IN CONST EFI_PEI_SERVICES **PeiServices,
> - IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
> - IN VOID *Ppi
> - );
> -
> -EFI_STATUS
> -EFIAPI
> -GetPlatformMemorySize (
> - IN EFI_PEI_SERVICES **PeiServices,
> - IN PEI_PLATFORM_MEMORY_SIZE_PPI *This,
> - IN OUT UINT64 *MemorySize
> - );
> -
> -/**
> -
> - This function checks the memory range in PEI.
> -
> - @param PeiServices Pointer to PEI Services.
> - @param This Pei memory test PPI pointer.
> - @param BeginAddress Beginning of the memory address to be
> checked.
> - @param MemoryLength Bytes of memory range to be checked.
> - @param Operation Type of memory check operation to be
> performed.
> - @param ErrorAddress Return the address of the error memory
> address.
> -
> - @retval EFI_SUCCESS The operation completed successfully.
> - @retval EFI_DEVICE_ERROR Memory test failed. It's not safe to use
> this range of memory.
> -
> -**/
> -EFI_STATUS
> -EFIAPI
> -BaseMemoryTest (
> - IN EFI_PEI_SERVICES **PeiServices,
> - IN PEI_BASE_MEMORY_TEST_PPI *This,
> - IN EFI_PHYSICAL_ADDRESS BeginAddress,
> - IN UINT64 MemoryLength,
> - IN PEI_MEMORY_TEST_OP Operation,
> - OUT EFI_PHYSICAL_ADDRESS *ErrorAddress
> - );
> -
> -static EFI_PEI_NOTIFY_DESCRIPTOR mMemDiscoveredNotifyList = {
> - (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
> - &gEfiPeiMemoryDiscoveredPpiGuid,
> - (EFI_PEIM_NOTIFY_ENTRY_POINT) MemoryDiscoveredPpiNotifyCallback
> -};
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR
> mPpiListRecoveryBootMode = {
> - (EFI_PEI_PPI_DESCRIPTOR_PPI |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
> - &gEfiPeiBootInRecoveryModePpiGuid,
> - NULL
> -};
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR
> mPpiBootMode = {
> - (EFI_PEI_PPI_DESCRIPTOR_PPI |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
> - &gEfiPeiMasterBootModePpiGuid,
> - NULL
> -};
> -
> -static PEI_BASE_MEMORY_TEST_PPI mPeiBaseMemoryTestPpi =
> { BaseMemoryTest };
> -
> -static PEI_PLATFORM_MEMORY_SIZE_PPI mMemoryMemorySizePpi =
> { GetPlatformMemorySize };
> -
> -static EFI_PEI_PPI_DESCRIPTOR mMemPpiList[] = {
> - {
> - EFI_PEI_PPI_DESCRIPTOR_PPI,
> - &gPeiBaseMemoryTestPpiGuid,
> - &mPeiBaseMemoryTestPpi
> - },
> - {
> - (EFI_PEI_PPI_DESCRIPTOR_PPI |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
> - &gPeiPlatformMemorySizePpiGuid,
> - &mMemoryMemorySizePpi
> - },
> -};
> -
> -///
> -/// Memory Reserved should be between 125% to 150% of the Current
> required memory
> -/// otherwise BdsMisc.c would do a reset to make it 125% to avoid s4
> resume issues.
> -///
> -GLOBAL_REMOVE_IF_UNREFERENCED EFI_MEMORY_TYPE_INFORMATION
> mDefaultMemoryTypeInformation[] = {
> - { EfiACPIReclaimMemory, FixedPcdGet32
> (PcdPlatformEfiAcpiReclaimMemorySize) }, // ASL
> - { EfiACPIMemoryNVS, FixedPcdGet32
> (PcdPlatformEfiAcpiNvsMemorySize) }, // ACPI NVS (including S3
> related)
> - { EfiReservedMemoryType, FixedPcdGet32
> (PcdPlatformEfiReservedMemorySize) }, // BIOS Reserved (including S3
> related)
> - { EfiRuntimeServicesData, FixedPcdGet32
> (PcdPlatformEfiRtDataMemorySize) }, // Runtime Service Data
> - { EfiRuntimeServicesCode, FixedPcdGet32
> (PcdPlatformEfiRtCodeMemorySize) }, // Runtime Service Code
> - { EfiMaxMemoryType, 0 }
> -};
> -
> -VOID
> -BuildMemoryTypeInformation (
> - VOID
> - )
> -{
> - EFI_STATUS Status;
> - EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
> - UINTN DataSize;
> - EFI_MEMORY_TYPE_INFORMATION
> MemoryData[EfiMaxMemoryType + 1];
> -
> - //
> - // Locate system configuration variable
> - //
> - Status = PeiServicesLocatePpi(
> - &gEfiPeiReadOnlyVariable2PpiGuid, // GUID
> - 0, // INSTANCE
> - NULL, //
> EFI_PEI_PPI_DESCRIPTOR
> - (VOID **) &VariableServices // PPI
> - );
> - ASSERT_EFI_ERROR(Status);
> -
> - DataSize = sizeof (MemoryData);
> - Status = VariableServices->GetVariable (
> - VariableServices,
> -
> EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME,
> - &gEfiMemoryTypeInformationGuid,
> - NULL,
> - &DataSize,
> - &MemoryData
> - );
> - if (EFI_ERROR(Status)) {
> - DataSize = sizeof (mDefaultMemoryTypeInformation);
> - CopyMem(MemoryData, mDefaultMemoryTypeInformation, DataSize);
> - }
> -
> - ///
> - /// Build the GUID'd HOB for DXE
> - ///
> - BuildGuidDataHob (
> - &gEfiMemoryTypeInformationGuid,
> - MemoryData,
> - DataSize
> - );
> -}
> -
> -EFI_STATUS
> -EFIAPI
> -GetPlatformMemorySize (
> - IN EFI_PEI_SERVICES **PeiServices,
> - IN PEI_PLATFORM_MEMORY_SIZE_PPI *This,
> - IN OUT UINT64 *MemorySize
> - )
> -{
> - EFI_STATUS Status;
> - EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;
> - UINTN DataSize;
> - EFI_MEMORY_TYPE_INFORMATION
> MemoryData[EfiMaxMemoryType + 1];
> - UINTN Index;
> - EFI_BOOT_MODE BootMode;
> - UINTN IndexNumber;
> -
> -#define PEI_MIN_MEMORY_SIZE (EFI_PHYSICAL_ADDRESS)
> ((320 * 0x100000))
> -
> - *MemorySize = PEI_MIN_MEMORY_SIZE;
> - Status = PeiServicesLocatePpi (
> - &gEfiPeiReadOnlyVariable2PpiGuid,
> - 0,
> - NULL,
> - (VOID **)&Variable
> - );
> -
> - ASSERT_EFI_ERROR (Status);
> -
> - Status = PeiServicesGetBootMode (&BootMode);
> - ASSERT_EFI_ERROR (Status);
> -
> - DataSize = sizeof (MemoryData);
> -
> - Status = Variable->GetVariable (
> - Variable,
> -
> EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME,
> - &gEfiMemoryTypeInformationGuid,
> - NULL,
> - &DataSize,
> - &MemoryData
> - );
> - IndexNumber = sizeof (mDefaultMemoryTypeInformation) / sizeof
> (EFI_MEMORY_TYPE_INFORMATION);
> -
> - //
> - // Accumulate maximum amount of memory needed
> - //
> -
> - DEBUG((DEBUG_ERROR, "PEI_MIN_MEMORY_SIZE:%dKB \n",
> DivU64x32(*MemorySize,1024)));
> - DEBUG((DEBUG_ERROR, "IndexNumber:%d MemoryDataNumber%d \n",
> IndexNumber,DataSize/ sizeof (EFI_MEMORY_TYPE_INFORMATION)));
> - if (EFI_ERROR (Status)) {
> - //
> - // Start with minimum memory
> - //
> - for (Index = 0; Index < IndexNumber; Index++) {
> - DEBUG((DEBUG_ERROR, "Index[%d].Type =
> %d .NumberOfPages=0x%x\n",
> Index,mDefaultMemoryTypeInformation[Index].Type,mDefaultMemoryTypeI
> nformation[Index].NumberOfPages));
> - *MemorySize +=
> mDefaultMemoryTypeInformation[Index].NumberOfPages * EFI_PAGE_SIZE;
> - }
> - DEBUG((DEBUG_ERROR, "No memory type, Total platform
> memory:%dKB \n", DivU64x32(*MemorySize,1024)));
> - } else {
> - //
> - // Start with at least 0x200 pages of memory for the DXE Core and the
> DXE Stack
> - //
> - for (Index = 0; Index < IndexNumber; Index++) {
> - DEBUG((DEBUG_ERROR, "Index[%d].Type =
> %d .NumberOfPages=0x%x\n",
> Index,MemoryData[Index].Type,MemoryData[Index].NumberOfPages));
> - *MemorySize += MemoryData[Index].NumberOfPages *
> EFI_PAGE_SIZE;
> -
> - }
> - DEBUG((DEBUG_ERROR, "has memory type, Total platform
> memory:%dKB \n", DivU64x32(*MemorySize,1024)));
> - }
> -
> - return EFI_SUCCESS;
> -}
> -
> -/**
> -
> - This function checks the memory range in PEI.
> -
> - @param PeiServices Pointer to PEI Services.
> - @param This Pei memory test PPI pointer.
> - @param BeginAddress Beginning of the memory address to be
> checked.
> - @param MemoryLength Bytes of memory range to be checked.
> - @param Operation Type of memory check operation to be
> performed.
> - @param ErrorAddress Return the address of the error memory
> address.
> -
> - @retval EFI_SUCCESS The operation completed successfully.
> - @retval EFI_DEVICE_ERROR Memory test failed. It's not safe to use
> this range of memory.
> -
> -**/
> -EFI_STATUS
> -EFIAPI
> -BaseMemoryTest (
> - IN EFI_PEI_SERVICES **PeiServices,
> - IN PEI_BASE_MEMORY_TEST_PPI *This,
> - IN EFI_PHYSICAL_ADDRESS BeginAddress,
> - IN UINT64 MemoryLength,
> - IN PEI_MEMORY_TEST_OP Operation,
> - OUT EFI_PHYSICAL_ADDRESS *ErrorAddress
> - )
> -{
> - UINT32 TestPattern;
> - UINT32 SpanSize;
> - EFI_PHYSICAL_ADDRESS TempAddress;
> -
> -#define MEMORY_TEST_PATTERN 0x5A5A5A5A
> -#define MEMORY_TEST_COVER_SPAN 0x40000
> -
> - TestPattern = MEMORY_TEST_PATTERN;
> - SpanSize = 0;
> -
> - //
> - // Make sure we don't try and test anything above the max physical
> address range
> - //
> - ASSERT (BeginAddress + MemoryLength < MAX_ADDRESS);
> -
> - switch (Operation) {
> - case Extensive:
> - SpanSize = 0x4;
> - break;
> -
> - case Sparse:
> - case Quick:
> - SpanSize = MEMORY_TEST_COVER_SPAN;
> - break;
> -
> - case Ignore:
> - goto Done;
> - break;
> - }
> - //
> - // Write the test pattern into memory range
> - //
> - TempAddress = BeginAddress;
> - while (TempAddress < BeginAddress + MemoryLength) {
> - (*(UINT32 *) (UINTN) TempAddress) = TestPattern;
> - TempAddress += SpanSize;
> - }
> - //
> - // Read pattern from memory and compare it
> - //
> - TempAddress = BeginAddress;
> - while (TempAddress < BeginAddress + MemoryLength) {
> - if ((*(UINT32 *) (UINTN) TempAddress) != TestPattern) {
> - *ErrorAddress = TempAddress;
> - return EFI_DEVICE_ERROR;
> - }
> -
> - TempAddress += SpanSize;
> - }
> -
> -Done:
> -
> - return EFI_SUCCESS;
> -}
> -
> -/**
> - Set Cache Mtrr.
> -**/
> -VOID
> -SetCacheMtrr (
> - VOID
> - )
> -{
> - EFI_STATUS Status;
> - EFI_PEI_HOB_POINTERS Hob;
> - MTRR_SETTINGS MtrrSetting;
> - UINT64 MemoryBase;
> - UINT64 MemoryLength;
> - UINT64 LowMemoryLength;
> - UINT64 HighMemoryLength;
> - EFI_BOOT_MODE BootMode;
> - EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
> - UINT64 CacheMemoryLength;
> -
> - ///
> - /// Reset all MTRR setting.
> - ///
> - ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS));
> -
> - ///
> - /// Cache the Flash area as WP to boost performance
> - ///
> - Status = MtrrSetMemoryAttributeInMtrrSettings (
> - &MtrrSetting,
> - (UINTN) PcdGet32 (PcdFlashAreaBaseAddress),
> - (UINTN) PcdGet32 (PcdFlashAreaSize),
> - CacheWriteProtected
> - );
> - ASSERT_EFI_ERROR (Status);
> -
> - ///
> - /// Update MTRR setting from MTRR buffer for Flash Region to be WP to
> boost performance
> - ///
> - MtrrSetAllMtrrs (&MtrrSetting);
> -
> - ///
> - /// Set low to 1 MB. Since 1MB cacheability will always be set
> - /// until override by CSM.
> - /// Initialize high memory to 0.
> - ///
> - LowMemoryLength = 0x100000;
> - HighMemoryLength = 0;
> - ResourceAttribute = (
> - EFI_RESOURCE_ATTRIBUTE_PRESENT |
> - EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
> -
> EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
> -
> EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
> -
> EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
> - );
> -
> - Status = PeiServicesGetBootMode (&BootMode);
> - ASSERT_EFI_ERROR (Status);
> -
> - if (BootMode != BOOT_ON_S3_RESUME) {
> - ResourceAttribute |= EFI_RESOURCE_ATTRIBUTE_TESTED;
> - }
> -
> - Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);
> - while (!END_OF_HOB_LIST (Hob)) {
> - if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {
> - if ((Hob.ResourceDescriptor->ResourceType ==
> EFI_RESOURCE_SYSTEM_MEMORY) ||
> - ((Hob.ResourceDescriptor->ResourceType ==
> EFI_RESOURCE_MEMORY_RESERVED) &&
> - (Hob.ResourceDescriptor->ResourceAttribute ==
> ResourceAttribute))
> - ) {
> - if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000000ULL) {
> - HighMemoryLength +=
> Hob.ResourceDescriptor->ResourceLength;
> - } else if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000) {
> - LowMemoryLength +=
> Hob.ResourceDescriptor->ResourceLength;
> - }
> - }
> - }
> -
> - Hob.Raw = GET_NEXT_HOB (Hob);
> - }
> -
> - DEBUG ((DEBUG_INFO, "Memory Length (Below 4GB) = %lx.\n",
> LowMemoryLength));
> - DEBUG ((DEBUG_INFO, "Memory Length (Above 4GB) = %lx.\n",
> HighMemoryLength));
> -
> - ///
> - /// Assume size of main memory is multiple of 256MB
> - ///
> - MemoryLength = (LowMemoryLength + 0xFFFFFFF) & 0xF0000000;
> - MemoryBase = 0;
> -
> - CacheMemoryLength = MemoryLength;
> - ///
> - /// Programming MTRRs to avoid override SPI region with UC when MAX
> TOLUD Length >= 3.5GB
> - ///
> - if (MemoryLength > 0xDC000000) {
> - CacheMemoryLength = 0xC0000000;
> - Status = MtrrSetMemoryAttributeInMtrrSettings (
> - &MtrrSetting,
> - MemoryBase,
> - CacheMemoryLength,
> - CacheWriteBack
> - );
> - ASSERT_EFI_ERROR (Status);
> -
> - MemoryBase = 0xC0000000;
> - CacheMemoryLength = MemoryLength - 0xC0000000;
> - if (MemoryLength > 0xE0000000) {
> - CacheMemoryLength = 0x20000000;
> - Status = MtrrSetMemoryAttributeInMtrrSettings (
> - &MtrrSetting,
> - MemoryBase,
> - CacheMemoryLength,
> - CacheWriteBack
> - );
> - ASSERT_EFI_ERROR (Status);
> -
> - MemoryBase = 0xE0000000;
> - CacheMemoryLength = MemoryLength - 0xE0000000;
> - }
> - }
> -
> - Status = MtrrSetMemoryAttributeInMtrrSettings (
> - &MtrrSetting,
> - MemoryBase,
> - CacheMemoryLength,
> - CacheWriteBack
> - );
> - ASSERT_EFI_ERROR (Status);
> -
> - if (LowMemoryLength != MemoryLength) {
> - MemoryBase = LowMemoryLength;
> - MemoryLength -= LowMemoryLength;
> - Status = MtrrSetMemoryAttributeInMtrrSettings (
> - &MtrrSetting,
> - MemoryBase,
> - MemoryLength,
> - CacheUncacheable
> - );
> - ASSERT_EFI_ERROR (Status);
> - }
> -
> - ///
> - /// VGA-MMIO - 0xA0000 to 0xC0000 to be UC
> - ///
> - Status = MtrrSetMemoryAttributeInMtrrSettings (
> - &MtrrSetting,
> - 0xA0000,
> - 0x20000,
> - CacheUncacheable
> - );
> - ASSERT_EFI_ERROR (Status);
> -
> - ///
> - /// Update MTRR setting from MTRR buffer
> - ///
> - MtrrSetAllMtrrs (&MtrrSetting);
> -
> - return ;
> -}
> -
> -VOID
> -ReportCpuHob (
> - VOID
> - )
> -{
> - UINT8 PhysicalAddressBits;
> - UINT32 RegEax;
> -
> - AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
> - if (RegEax >= 0x80000008) {
> - AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
> - PhysicalAddressBits = (UINT8) RegEax;
> - } else {
> - PhysicalAddressBits = 36;
> - }
> -
> - ///
> - /// Create a CPU hand-off information
> - ///
> - BuildCpuHob (PhysicalAddressBits, 16);
> -}
> -
> -/**
> - Install Firmware Volume Hob's once there is main memory
> -
> - @param[in] PeiServices General purpose services available to
> every PEIM.
> - @param[in] NotifyDescriptor Notify that this module published.
> - @param[in] Ppi PPI that was installed.
> -
> - @retval EFI_SUCCESS The function completed successfully.
> -**/
> -EFI_STATUS
> -EFIAPI
> -MemoryDiscoveredPpiNotifyCallback (
> - IN CONST EFI_PEI_SERVICES **PeiServices,
> - IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
> - IN VOID *Ppi
> - )
> -{
> - EFI_STATUS Status;
> - EFI_BOOT_MODE BootMode;
> -
> - Status = BoardInitAfterMemoryInit ();
> - ASSERT_EFI_ERROR (Status);
> -
> - Status = PeiServicesGetBootMode (&BootMode);
> - ASSERT_EFI_ERROR (Status);
> -
> -
> - ReportCpuHob ();
> -
> - TestPointMemoryDiscoveredMtrrFunctional ();
> -
> - TestPointMemoryDiscoveredMemoryResourceFunctional ();
> -
> - ///
> - /// If S3 resume, then we are done
> - ///
> - if (BootMode == BOOT_ON_S3_RESUME) {
> - return EFI_SUCCESS;
> - }
> -
> - TestPointMemoryDiscoveredDmaProtectionEnabled ();
> -
> - if (PcdGetBool (PcdStopAfterMemInit)) {
> - CpuDeadLoop ();
> - }
> -
> - return Status;
> -}
> -
> -
> -/**
> - This function handles PlatformInit task after PeiReadOnlyVariable2 PPI
> produced
> -
> - @param[in] PeiServices Pointer to PEI Services Table.
> -
> - @retval EFI_SUCCESS The function completes successfully
> - @retval others
> -**/
> -EFI_STATUS
> -EFIAPI
> -PlatformInitPreMem (
> - IN CONST EFI_PEI_SERVICES **PeiServices
> - )
> -{
> - EFI_STATUS Status;
> - EFI_BOOT_MODE BootMode;
> -
> - //
> - // Start board detection
> - //
> - BoardDetect ();
> -
> - BoardDebugInit ();
> -
> - TestPointDebugInitDone ();
> -
> - if (PcdGetBool (PcdStopAfterDebugInit)) {
> - CpuDeadLoop ();
> - }
> -
> - BootMode = BoardBootModeDetect ();
> - Status = PeiServicesSetBootMode (BootMode);
> - ASSERT_EFI_ERROR (Status);
> - if (BootMode == BOOT_IN_RECOVERY_MODE) {
> - Status = PeiServicesInstallPpi (&mPpiListRecoveryBootMode);
> - }
> - ///
> - /// Signal possible dependent modules that there has been a
> - /// final boot mode determination, it is used to build BIST
> - /// Hob for Dxe use.
> - ///
> - Status = PeiServicesInstallPpi (&mPpiBootMode);
> - ASSERT_EFI_ERROR (Status);
> -
> - BuildMemoryTypeInformation ();
> -
> - if (!PcdGetBool(PcdFspWrapperBootMode)) {
> - Status = PeiServicesInstallPpi (mMemPpiList);
> - ASSERT_EFI_ERROR (Status);
> - }
> -
> - Status = BoardInitBeforeMemoryInit ();
> - ASSERT_EFI_ERROR (Status);
> -
> - return Status;
> -}
> -
> -
> -/**
> - Platform Init before memory PEI module entry point
> -
> - @param[in] FileHandle Not used.
> - @param[in] PeiServices General purpose services available
> to every PEIM.
> -
> - @retval EFI_SUCCESS The function completes
> successfully
> - @retval EFI_OUT_OF_RESOURCES Insufficient resources to create
> database
> -**/
> -EFI_STATUS
> -EFIAPI
> -PlatformInitPreMemEntryPoint (
> - IN EFI_PEI_FILE_HANDLE FileHandle,
> - IN CONST EFI_PEI_SERVICES **PeiServices
> - )
> -{
> - EFI_STATUS Status;
> -
> - Status = PlatformInitPreMem (PeiServices);
> -
> - ///
> - /// After code reorangized, memorycallback will run because the PPI is
> already
> - /// installed when code run to here, it is supposed that the
> InstallEfiMemory is
> - /// done before.
> - ///
> - Status = PeiServicesNotifyPpi (&mMemDiscoveredNotifyList);
> -
> - return Status;
> -}
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPoli
> cyUpdateLib/DxeGopPolicyInit.c
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPoli
> cyUpdateLib/DxeGopPolicyInit.c
> deleted file mode 100644
> index 99c7d42c4e..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPoli
> cyUpdateLib/DxeGopPolicyInit.c
> +++ /dev/null
> @@ -1,175 +0,0 @@
> -/** @file
> - DXE GOP policy initialization.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include "DxeGopPolicyInit.h"
> -#include <Protocol/GopPolicy.h>
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED GOP_POLICY_PROTOCOL
> mGOPPolicy;
> -GLOBAL_REMOVE_IF_UNREFERENCED UINT32
> mVbtSize = 0;
> -GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS
> mVbtAddress = 0;
> -
> -//
> -// Function implementations
> -//
> -
> -/**
> -
> - @param[out] CurrentLidStatus
> -
> - @retval EFI_SUCCESS
> - @retval EFI_UNSUPPORTED
> -**/
> -EFI_STATUS
> -EFIAPI
> -GetPlatformLidStatus (
> - OUT LID_STATUS *CurrentLidStatus
> - )
> -{
> - return EFI_UNSUPPORTED;
> -}
> -/**
> -
> - @param[out] CurrentDockStatus
> -
> - @retval EFI_SUCCESS
> - @retval EFI_UNSUPPORTED
> -**/
> -EFI_STATUS
> -EFIAPI
> -GetPlatformDockStatus (
> - OUT DOCK_STATUS CurrentDockStatus
> - )
> -{
> - return EFI_UNSUPPORTED;
> -}
> -
> -
> -/**
> -
> - @param[out] VbtAddress
> - @param[out] VbtSize
> -
> - @retval EFI_SUCCESS
> - @retval EFI_NOT_FOUND
> -**/
> -EFI_STATUS
> -EFIAPI
> -GetVbtData (
> - OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
> - OUT UINT32 *VbtSize
> - )
> -{
> - EFI_STATUS Status;
> - UINTN FvProtocolCount;
> - EFI_HANDLE *FvHandles;
> - EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;
> - UINTN Index;
> - UINT32 AuthenticationStatus;
> - UINT8 *Buffer;
> - UINTN VbtBufferSize;
> -
> -
> - Status = EFI_NOT_FOUND;
> - if ( mVbtAddress == 0) {
> - Fv = NULL;
> -
> - Buffer = 0;
> - FvHandles = NULL;
> - Status = gBS->LocateHandleBuffer (
> - ByProtocol,
> - &gEfiFirmwareVolume2ProtocolGuid,
> - NULL,
> - &FvProtocolCount,
> - &FvHandles
> - );
> - if (!EFI_ERROR (Status)) {
> - for (Index = 0; Index < FvProtocolCount; Index++) {
> - Status = gBS->HandleProtocol (
> - FvHandles[Index],
> - &gEfiFirmwareVolume2ProtocolGuid,
> - (VOID **) &Fv
> - );
> - VbtBufferSize = 0;
> - Status = Fv->ReadSection (
> - Fv,
> - PcdGetPtr (PcdGraphicsVbtGuid),
> - EFI_SECTION_RAW,
> - 0,
> - (VOID **) &Buffer,
> - &VbtBufferSize,
> - &AuthenticationStatus
> - );
> - if (!EFI_ERROR (Status)) {
> - *VbtAddress = (EFI_PHYSICAL_ADDRESS)Buffer;
> - *VbtSize = (UINT32)VbtBufferSize;
> - mVbtAddress = *VbtAddress;
> - mVbtSize = *VbtSize;
> - Status = EFI_SUCCESS;
> - break;
> - }
> - }
> - } else {
> - Status = EFI_NOT_FOUND;
> - }
> -
> - if (FvHandles != NULL) {
> - FreePool (FvHandles);
> - FvHandles = NULL;
> - }
> - } else {
> - *VbtAddress = mVbtAddress;
> - *VbtSize = mVbtSize;
> - Status = EFI_SUCCESS;
> - }
> -
> - return Status;
> -}
> -
> -
> -
> -/**
> -Initialize GOP DXE Policy
> -
> - at param[in] ImageHandle Image handle of this driver.
> -
> - at retval EFI_SUCCESS Initialization complete.
> - at retval EFI_UNSUPPORTED The chipset is unsupported by this
> driver.
> - at retval EFI_OUT_OF_RESOURCES Do not have enough resources to
> initialize the driver.
> - at retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
> -**/
> -
> -EFI_STATUS
> -EFIAPI
> -GopPolicyInitDxe (
> - IN EFI_HANDLE ImageHandle
> - )
> -{
> - EFI_STATUS Status;
> -
> - //
> - // Initialize the EFI Driver Library
> - //
> - SetMem (&mGOPPolicy, sizeof (GOP_POLICY_PROTOCOL), 0);
> -
> - mGOPPolicy.Revision =
> GOP_POLICY_PROTOCOL_REVISION_03;
> - mGOPPolicy.GetPlatformLidStatus = GetPlatformLidStatus;
> - mGOPPolicy.GetVbtData = GetVbtData;
> - mGOPPolicy.GetPlatformDockStatus = GetPlatformDockStatus;
> -
> - //
> - // Install protocol to allow access to this Policy.
> - //
> - Status = gBS->InstallMultipleProtocolInterfaces (
> - &ImageHandle,
> - &gGopPolicyProtocolGuid,
> - &mGOPPolicy,
> - NULL
> - );
> -
> - return Status;
> -}
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPoli
> cyUpdateLib/DxeSaPolicyUpdate.c
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPoli
> cyUpdateLib/DxeSaPolicyUpdate.c
> deleted file mode 100644
> index d140237576..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPoli
> cyUpdateLib/DxeSaPolicyUpdate.c
> +++ /dev/null
> @@ -1,65 +0,0 @@
> -/** @file
> - This file is the library for SA DXE Policy initialization.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include "DxeSaPolicyInit.h"
> -
> -#define SA_VTD_RMRR_USB_LENGTH 0x20000
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS
> mAddress;
> -GLOBAL_REMOVE_IF_UNREFERENCED UINTN
> mSize;
> -
> -/**
> - Update RMRR Base and Limit Address for USB.
> -
> -**/
> -VOID
> -UpdateRmrrUsbAddress (
> - IN OUT SA_POLICY_PROTOCOL *SaPolicy
> - )
> -{
> - EFI_STATUS Status;
> - MISC_DXE_CONFIG *MiscDxeConfig;
> -
> - Status = GetConfigBlock ((VOID *)SaPolicy, &gMiscDxeConfigGuid, (VOID
> *)&MiscDxeConfig);
> - ASSERT_EFI_ERROR (Status);
> -
> - if (1) {
> - mSize = EFI_SIZE_TO_PAGES(SA_VTD_RMRR_USB_LENGTH);
> - mAddress = SIZE_4GB;
> -
> - Status = (gBS->AllocatePages) (
> - AllocateMaxAddress,
> - EfiReservedMemoryType,
> - mSize,
> - &mAddress
> - );
> - ASSERT_EFI_ERROR (Status);
> -
> - MiscDxeConfig->RmrrUsbBaseAddress[0] = mAddress;
> - MiscDxeConfig->RmrrUsbBaseAddress[1] = mAddress +
> SA_VTD_RMRR_USB_LENGTH - 1;
> - }
> -}
> -
> -/**
> - Get data for platform policy from setup options.
> -
> - @param[in] SaPolicy The pointer to get SA Policy
> protocol instance
> -
> - @retval EFI_SUCCESS Operation success.
> -
> -**/
> -EFI_STATUS
> -EFIAPI
> -UpdateDxeSaPolicy (
> - IN OUT SA_POLICY_PROTOCOL *SaPolicy
> - )
> -{
> - UpdateRmrrUsbAddress (SaPolicy);
> - return EFI_SUCCESS;
> -}
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPoli
> cyUpdateLib/DxeSiliconPolicyUpdateLib.c
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPoli
> cyUpdateLib/DxeSiliconPolicyUpdateLib.c
> deleted file mode 100644
> index 5c7f388213..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPoli
> cyUpdateLib/DxeSiliconPolicyUpdateLib.c
> +++ /dev/null
> @@ -1,54 +0,0 @@
> -/** @file
> - DXE silicon policy update library.
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <Library/SiliconPolicyUpdateLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/DebugLib.h>
> -
> -#include "DxeSaPolicyInit.h"
> -#include "DxeGopPolicyInit.h"
> -
> -/**
> - Performs silicon late policy update.
> -
> - The meaning of Policy is defined by silicon code.
> - It could be the raw data, a handle, a Protocol, etc.
> -
> - The input Policy must be returned by SiliconPolicyDoneLate().
> -
> - In FSP or non-FSP path, the board may use additional way to get
> - the silicon policy data field based upon the input Policy.
> -
> - @param[in, out] Policy Pointer to policy.
> -
> - @return the updated policy.
> -**/
> -VOID *
> -EFIAPI
> -SiliconPolicyUpdateLate (
> - IN VOID *Policy
> - )
> -{
> - SA_POLICY_PROTOCOL *SaPolicy;
> - EFI_STATUS Status;
> -
> - SaPolicy = Policy;
> - UpdateDxeSaPolicy (SaPolicy);
> -
> - if (PcdGetBool(PcdIntelGopEnable)) {
> - //
> - // GOP Dxe Policy Initialization
> - //
> - Status = GopPolicyInitDxe(gImageHandle);
> - DEBUG((DEBUG_INFO, "GOP Dxe Policy Initialization done\n"));
> - ASSERT_EFI_ERROR(Status);
> - }
> -
> - return Policy;
> -}
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/ALS.ASL
> b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/ALS.ASL
> deleted file mode 100644
> index bcc3405e33..0000000000
> --- a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/ALS.ASL
> +++ /dev/null
> @@ -1,37 +0,0 @@
> -/** @file
> - ACPI DSDT table
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -Device(ALSD)
> -{
> - Name(_HID,"ACPI0008")
> -
> - Method(_STA,0)
> - {
> - If(LEqual(ALSE,2))
> - {
> - Return(0x000B) // ALS Enabled. Don't show it in UI.
> - }
> -
> - Return(0x0000) // ALS Disabled. Hide it.
> - }
> -
> - Method(_ALI)
> - {
> - Return (Or(ShiftLeft(LHIH,8),LLOW))
> - }
> -
> - Name(_ALR, Package()
> - {
> - Package() {70, 0},
> - Package() {73, 10},
> - Package() {85, 80},
> - Package() {100, 300},
> - Package() {150, 1000}
> - })
> -
> -}
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl
> b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl
> deleted file mode 100644
> index 30b3e57c4b..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl
> +++ /dev/null
> @@ -1,21 +0,0 @@
> -/** @file
> - ACPI DSDT table
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -
> -
> -///////////////////////////////////////////////////////////////////////////////
> ////
> -//Values are set like this to have ASL compiler reserve enough space for
> objects
> -///////////////////////////////////////////////////////////////////////////////
> ////
> -//
> -// Available Sleep states
> -//
> -Name(SS1,0)
> -Name(SS2,0)
> -Name(SS3,1)
> -Name(SS4,1)
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/CPU.asl
> b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/CPU.asl
> deleted file mode 100644
> index 84c151cbf6..0000000000
> --- a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/CPU.asl
> +++ /dev/null
> @@ -1,246 +0,0 @@
> -/** @file
> - ACPI DSDT table
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -Scope(\_PR)
> -{
> - Processor(PR00, // Unique name for Processor 0.
> - 1, // Unique ID for Processor 0.
> - 0x1810, // P_BLK address = ACPIBASE + 10h.
> - 6) // P_BLK length = 6 bytes.
> - {}
> -
> - Processor(PR01, // Unique name for Processor 1.
> - 2, // Unique ID for Processor 1.
> - 0x1810, // P_BLK address = ACPIBASE + 10h.
> - 6) // P_BLK length = 6 bytes.
> - {}
> -
> - Processor(PR02, // Unique name for Processor 2.
> - 3, // Unique ID for Processor 2.
> - 0x1810, // P_BLK address = ACPIBASE + 10h.
> - 6) // P_BLK length = 6 bytes.
> - {}
> -
> - Processor(PR03, // Unique name for Processor 3.
> - 4, // Unique ID for Processor 3.
> - 0x1810, // P_BLK address = ACPIBASE + 10h.
> - 6) // P_BLK length = 6 bytes.
> - {}
> -
> - Processor(PR04, // Unique name for Processor 4.
> - 5, // Unique ID for Processor 4.
> - 0x1810, // P_BLK address = ACPIBASE + 10h.
> - 6) // P_BLK length = 6 bytes.
> - {}
> -
> - Processor(PR05, // Unique name for Processor 5.
> - 6, // Unique ID for Processor 5.
> - 0x1810, // P_BLK address = ACPIBASE + 10h.
> - 6) // P_BLK length = 6 bytes.
> - {}
> -
> - Processor(PR06, // Unique name for Processor 6.
> - 7, // Unique ID for Processor 6.
> - 0x1810, // P_BLK address = ACPIBASE + 10h.
> - 6) // P_BLK length = 6 bytes.
> - {}
> -
> - Processor(PR07, // Unique name for Processor 7.
> - 8, // Unique ID for Processor 7.
> - 0x1810, // P_BLK address = ACPIBASE + 10h.
> - 6) // P_BLK length = 6 bytes.
> - {}
> -
> - Processor(PR08, // Unique name for Processor 8.
> - 9, // Unique ID for Processor 8.
> - 0x1810, // P_BLK address = ACPIBASE + 10h.
> - 6) // P_BLK length = 6 bytes.
> - {}
> -
> - Processor(PR09, // Unique name for Processor 9.
> - 10, // Unique ID for Processor 9.
> - 0x1810, // P_BLK address = ACPIBASE + 10h.
> - 6) // P_BLK length = 6 bytes.
> - {}
> -
> - Processor(PR10, // Unique name for Processor 10.
> - 11, // Unique ID for Processor 10.
> - 0x1810, // P_BLK address = ACPIBASE + 10h.
> - 6) // P_BLK length = 6 bytes.
> - {}
> -
> - Processor(PR11, // Unique name for Processor 11.
> - 12, // Unique ID for Processor 11.
> - 0x1810, // P_BLK address = ACPIBASE + 10h.
> - 6) // P_BLK length = 6 bytes.
> - {}
> -
> - Processor(PR12, // Unique name for Processor 12.
> - 13, // Unique ID for Processor 12.
> - 0x1810, // P_BLK address = ACPIBASE + 10h.
> - 6) // P_BLK length = 6 bytes.
> - {}
> -
> - Processor(PR13, // Unique name for Processor 13.
> - 14, // Unique ID for Processor 13.
> - 0x1810, // P_BLK address = ACPIBASE + 10h.
> - 6) // P_BLK length = 6 bytes.
> - {}
> -
> - Processor(PR14, // Unique name for Processor 14.
> - 15, // Unique ID for Processor 14.
> - 0x1810, // P_BLK address = ACPIBASE + 10h.
> - 6) // P_BLK length = 6 bytes.
> - {}
> -
> - Processor(PR15, // Unique name for Processor 15.
> - 16, // Unique ID for Processor 15.
> - 0x1810, // P_BLK address = ACPIBASE + 10h.
> - 6) // P_BLK length = 6 bytes.
> - {}
> -} // End Scope(\_PR)
> -
> -//
> -// _CPC (Continuous Performance Control) Package declaration
> -// Package
> -// {
> -// NumEntries, // Integer
> -// Revision, // Integer
> -// HighestPerformance, // Generic Register
> Descriptor
> -// NominalPerformance, // Generic Register
> Descriptor
> -// LowestNonlinearPerformance, // Generic Register
> Descriptor
> -// LowestPerformance, // Generic Register
> Descriptor
> -// GuaranteedPerformanceRegister, // Generic Register
> Descriptor
> -// DesiredPerformanceRegister, // Generic Register
> Descriptor
> -// MinimumPerformanceRegister, // Generic Register
> Descriptor
> -// MaximumPerformanceRegister, // Generic Register
> Descriptor
> -// PerformanceReductionToleranceRegister,// Generic Register
> Descriptor
> -// TimeWindowRegister, // Generic Register
> Descriptor
> -// CounterWraparoundTime, // Generic Register
> Descriptor
> -// NominalCounterRegister, // Generic Register
> Descriptor
> -// DeliveredCounterRegister, // Generic Register
> Descriptor
> -// PerformanceLimitedRegister, // Generic Register
> Descriptor
> -// EnableRegister // Generic Register
> Descriptor
> -// }
> -//
> -Scope(\_PR.PR00)
> -{
> - Name(CPC2, Package()
> - {
> - 21, // Number of entries
> - 02, // Revision
> - //
> - // Describe processor capabilities
> - //
> - ResourceTemplate() {Register(FFixedHW, 8, 0, 0x771, 4)}, //
> HighestPerformance
> - ResourceTemplate() {Register(FFixedHW, 8, 8, 0xCE, 4)}, // Nominal
> Performance - Maximum Non Turbo Ratio
> - ResourceTemplate() {Register(FFixedHW, 8, 16, 0x771, 4)},//Lowest
> nonlinear Performance
> - ResourceTemplate() {Register(FFixedHW, 8, 24, 0x771, 4)}, //
> LowestPerformance
> - ResourceTemplate() {Register(FFixedHW, 8, 8, 0x0771, 4)}, //
> Guaranteed Performance
> - ResourceTemplate() {Register(FFixedHW, 8, 16, 0x0774, 4)}, // Desired
> PerformanceRegister
> - ResourceTemplate() {Register(FFixedHW, 8, 0, 0x774, 4)}, // Minimum
> PerformanceRegister
> - ResourceTemplate() {Register(FFixedHW, 8, 8, 0x774, 4)}, // Maximum
> PerformanceRegister
> - ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, //
> Performance ReductionToleranceRegister (Null)
> - ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Time
> window register(Null)
> - ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Counter
> wrap around time(Null)
> - ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE7, 4)}, // Reference
> counter register (PPERF)
> - ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE8, 4)}, // Delivered
> counter register (APERF)
> - ResourceTemplate() {Register(FFixedHW, 2, 1, 0x777, 4)}, // Performance
> limited register
> - ResourceTemplate() {Register(FFixedHW, 1, 0, 0x770, 4)}, // Enable
> register
> - 1, // Autonomous selection enable register (Exclusively autonomous)
> - ResourceTemplate() {Register(FFixedHW, 10, 32, 0x774, 4)}, //
> Autonomous activity window register
> - ResourceTemplate() {Register(FFixedHW, 8, 24, 0x774, 4)}, //
> Autonomous energy performance preference register
> - 0 // Reference performance (not supported)
> - })
> -
> - Name(CPOC, Package()
> - {
> - 21, // Number of entries
> - 02, // Revision
> - //
> - // Describe processor capabilities
> - //
> - 255, // HighestPerformance
> - ResourceTemplate() {Register(FFixedHW, 8, 8, 0xCE, 4)}, // Nominal
> Performance - Maximum Non Turbo Ratio
> - ResourceTemplate() {Register(FFixedHW, 8, 16, 0x771, 4)},//Lowest
> nonlinear Performance
> - ResourceTemplate() {Register(FFixedHW, 8, 24, 0x771, 4)}, //
> LowestPerformance
> - ResourceTemplate() {Register(FFixedHW, 8, 8, 0x0771, 4)}, //
> Guaranteed Performance
> - ResourceTemplate() {Register(FFixedHW, 8, 16, 0x0774, 4)}, // Desired
> PerformanceRegister
> - ResourceTemplate() {Register(FFixedHW, 8, 0, 0x774, 4)}, // Minimum
> PerformanceRegister
> - ResourceTemplate() {Register(FFixedHW, 8, 8, 0x774, 4)}, // Maximum
> PerformanceRegister
> - ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, //
> Performance ReductionToleranceRegister (Null)
> - ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Time
> window register(Null)
> - ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Counter
> wrap around time(Null)
> - ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE7, 4)}, // Reference
> counter register (PPERF)
> - ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE8, 4)}, // Delivered
> counter register (APERF)
> - ResourceTemplate() {Register(FFixedHW, 2, 1, 0x777, 4)}, // Performance
> limited register
> - ResourceTemplate() {Register(FFixedHW, 1, 0, 0x770, 4)}, // Enable
> register
> - 1, // Autonomous selection enable register (Exclusively autonomous)
> - ResourceTemplate() {Register(FFixedHW, 10, 32, 0x774, 4)}, //
> Autonomous activity window register
> - ResourceTemplate() {Register(FFixedHW, 8, 24, 0x774, 4)}, //
> Autonomous energy performance preference register
> - 0 // Reference performance (not supported)
> - })
> -
> -}// end Scope(\_PR.PR00)
> -
> -#ifndef SPS_SUPPORT // SPS is using Processor Aggregator Device different
> way
> -Scope(\_SB)
> -{
> - // The Processor Aggregator Device provides a control point that enables
> the platform to perform
> - // specific processor configuration and control that applies to all
> processors in the platform.
> - Device (PAGD)
> - {
> - Name (_HID, "ACPI000C") // Processor Aggregator Device
> -
> - // _STA (Status)
> - //
> - // This object returns the current status of a device.
> - //
> - // Arguments: (0)
> - // None
> - // Return Value:
> - // An Integer containing a device status bitmap:
> - // Bit 0 - Set if the device is present.
> - // Bit 1 - Set if the device is enabled and decoding its resources.
> - // Bit 2 - Set if the device should be shown in the UI.
> - // Bit 3 - Set if the device is functioning properly (cleared if device
> failed its diagnostics).
> - // Bit 4 - Set if the battery is present.
> - // Bits 5-31 - Reserved (must be cleared).
> - //
> - Method(_STA)
> - {
> - If(\_OSI("Processor Aggregator Device")){
> - Return (0x0F) // Processor Aggregator Device is supported by this
> OS.
> - } Else {
> - Return (0) // No support in this OS.
> - }
> - }
> -
> -
> - // _PUR (Processor Utilization Request)
> - //
> - // The _PUR object is an optional object that may be declared under
> the Processor Aggregator Device
> - // and provides a means for the platform to indicate to OSPM the
> number of logical processors
> - // to be idled. OSPM evaluates the _PUR object as a result of the
> processing of a Notify event
> - // on the Processor Aggregator device object of type 0x80.
> - //
> - // Arguments: (0)
> - // None
> - // Return Value:
> - // Package
> - //
> - Name (_PUR, Package() // Requests a number of logical processors to
> be placed in an idle state.
> - {
> - 1, // RevisionID, Integer: Current
> value is 1
> - 0 // NumProcessors, Integer
> - })
> -
> - } // end Device(PAGD)
> -}// end Scope(\_SB)
> -#endif // ndef SPS_SUPPORT
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.ASL
> b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.ASL
> deleted file mode 100644
> index 93bca6827e..0000000000
> --- a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.ASL
> +++ /dev/null
> @@ -1,121 +0,0 @@
> -/** @file
> - ACPI DSDT table
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -DefinitionBlock (
> - "DSDT.aml",
> - "DSDT",
> - 0x02, // DSDT revision.
> - // A Revision field value greater than or equal to 2 signifies that
> integers
> - // declared within the Definition Block are to be evaluated as
> 64-bit values
> - "INTEL", // OEM ID (6 byte string)
> - "SKL ",// OEM table ID (8 byte string)
> - 0x0 // OEM version of DSDT table (4 byte Integer)
> -)
> -
> -// BEGIN OF ASL SCOPE
> -{
> - External(LHIH)
> - External(LLOW)
> - External(IGDS)
> - External(LIDS)
> - External(BRTL)
> - External(ALSE)
> - External(GSMI)
> - External(\_SB.PCI0.GFX0.ALSI)
> - External(\_SB.PCI0.GFX0.CDCK)
> - External(\_SB.PCI0.GFX0.CBLV)
> - External(\_SB.PCI0.GFX0.GSSE)
> - External(\_SB.PCI0.PEG0, DeviceObj)
> - External(\_SB.PCI0.PEG0.PEGP, DeviceObj)
> - External(\_SB.PCI0.PEG1, DeviceObj)
> - External(\_SB.PCI0.PEG2, DeviceObj)
> - External(\_SB.PCI0.GFX0.DD1F, DeviceObj)
> - External(\_SB.PCI0.GFX0.GDCK, MethodObj)
> - External(\_SB.PCI0.GFX0.GHDS, MethodObj)
> - External(\_SB.PCI0.GFX0.AINT, MethodObj)
> - External(\_SB.PCI0.GFX0.GLID, MethodObj)
> - External(\_SB.PCI0.GFX0.GSCI, MethodObj)
> - External(\_PR.PR00._PSS, MethodObj)
> - External(\_PR.PR00.LPSS, PkgObj)
> - External(\_PR.PR00.TPSS, PkgObj)
> - External(\_PR.PR00._PPC, MethodObj)
> - External(\_PR.CPPC, IntObj)
> - External(\_TZ.TZ00, DeviceObj)
> - External(\_TZ.TZ01, DeviceObj)
> - External(\_TZ.ETMD, IntObj)
> - External(\_TZ.FN00._OFF, MethodObj)
> - // Miscellaneous services enabled in Project
> - Include ("AMLUPD.asl")
> - Include ("Acpi/GlobalNvs.asl")
> - Include ("PciTree.asl")
> -
> - if(LEqual(ECR1,1)){
> - Scope(\_SB.PCI0) {
> - //
> - // PCI-specific method's GUID
> - //
> - Name(PCIG, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))
> - //
> - // PCI's _DSM - an attempt at modular _DSM implementation
> - // When writing your own _DSM function that needs to include
> PCI-specific methods, do this:
> - //
> - // Method(_YOUR_DSM,4){
> - // if(Lequal(Arg0,PCIG)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }
> - // ...continue your _DSM by checking different GUIDs...
> - // else { return(0) }
> - // }
> - //
> - Method(PCID, 4, Serialized) {
> - If(LEqual(Arg0, PCIG)) { // PCIE capabilities UUID
> - If(LGreaterEqual(Arg1,3))
> { // revision at least 3
> - If(LEqual(Arg2,0)) { Return (Buffer(2){0x01,0x03}) }
> // function 0: list of supported functions
> - If(LEqual(Arg2,8)) { Return (1) }
> // function 8: Avoiding Power-On Reset Delay Duplication on Sx Resume
> - If(LEqual(Arg2,9)) { Return
> (Package(5){50000,Ones,Ones,50000,Ones}) } // function 9: Specifying Device
> Readiness Durations
> - }
> - }
> - return (Buffer(1){0})
> - }
> - }//scope
> - }//if
> -
> - Scope(\_SB.PCI0) {
> - //PciCheck, Arg0=UUID, returns true if support for 'PCI delays
> optimization ECR' is enabled and the UUID is correct
> - Method(PCIC,1,Serialized) {
> - If(LEqual(ECR1,1)) {
> - If(LEqual(Arg0, PCIG)) {
> - return (1)
> - }
> - }
> - return (0)
> - }
> - }
> -
> - Include ("Pch.asl") // Not in this package. Refer to the PCH Reference
> Code accordingly
> - Include ("LpcB.asl")
> - Include ("Platform.asl")
> - Include ("CPU.asl")
> - Include ("PCI_DRC.ASL")
> - Include ("Video.asl")
> - Include ("PlatformGnvs.asl")
> - Include ("Gpe.asl")
> -
> - Name(\_S0, Package(4){0x0,0x0,0,0}) // mandatory System state
> - if(SS1) { Name(\_S1, Package(4){0x1,0x0,0,0})}
> - if(SS3) { Name(\_S3, Package(4){0x5,0x0,0,0})}
> - if(SS4) { Name(\_S4, Package(4){0x6,0x0,0,0})}
> - Name(\_S5, Package(4){0x7,0x0,0,0}) // mandatory System state
> -
> - Method(PTS, 1) { // METHOD CALLED FROM _PTS PRIOR TO
> ENTER ANY SLEEP STATE
> - If(Arg0) // entering any sleep state
> - {
> - }
> - }
> - Method(WAK, 1) { // METHOD CALLED FROM _WAK RIGHT AFTER
> WAKE UP
> - }
> -}// End of ASL File
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl
> b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl
> deleted file mode 100644
> index 8976c7a0ff..0000000000
> --- a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl
> +++ /dev/null
> @@ -1,850 +0,0 @@
> -/** @file
> - ACPI DSDT table
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> - // General Purpose Events. This Scope handles the Run-time and
> - // Wake-time SCIs. The specific method called will be determined by
> - // the _Lxx value, where xx equals the bit location in the General
> - // Purpose Event register(s).
> -
> -
> - External(D1F0)
> - External(D1F1)
> - External(D1F2)
> - External(\_SB.PCI0.PEG0.HPME, MethodObj)
> - External(\_SB.PCI0.PEG1.HPME, MethodObj)
> - External(\_SB.PCI0.PEG2.HPME, MethodObj)
> - External(\_GPE.AL6F, MethodObj)
> - External(\_SB.THDR, MethodObj)
> - External(\_GPE.P0L6, MethodObj)
> - External(\_GPE.P1L6, MethodObj)
> - External(\_GPE.P2L6, MethodObj)
> - External(SGGP)
> - External(P1GP)
> - External(P2GP)
> - External(P0WK)
> - External(P1WK)
> - External(P2WK)
> - External(\CPG0)
> - External(\RPS0)
> - External(\RPT0)
> - External(\_PR.HWPI, IntObj)
> - External(\_PR.DTSI, IntObj)
> -
> - Scope(\_GPE)
> - {
> - // Note:
> - // Originally, the two GPE methods below are automatically generated,
> but, for ASL code restructuring,
> - // disabled the automatic generation and declare the ASL code here.
> - //
> -
> - //
> - // This PME event (PCH's GPE 69h) is received on one or more of the PCI
> Express* ports or
> - // an assert PMEGPE message received via DMI
> - //
> - Method(_L69, 0, serialized) {
> - \_SB.PCI0.RP01.HPME()
> - \_SB.PCI0.RP02.HPME()
> - \_SB.PCI0.RP03.HPME()
> - \_SB.PCI0.RP04.HPME()
> - \_SB.PCI0.RP05.HPME()
> - \_SB.PCI0.RP06.HPME()
> - \_SB.PCI0.RP07.HPME()
> - \_SB.PCI0.RP08.HPME()
> - \_SB.PCI0.RP09.HPME()
> - \_SB.PCI0.RP10.HPME()
> - \_SB.PCI0.RP11.HPME()
> - \_SB.PCI0.RP12.HPME()
> - \_SB.PCI0.RP13.HPME()
> - \_SB.PCI0.RP14.HPME()
> - \_SB.PCI0.RP15.HPME()
> - \_SB.PCI0.RP16.HPME()
> - \_SB.PCI0.RP17.HPME()
> - \_SB.PCI0.RP18.HPME()
> - \_SB.PCI0.RP19.HPME()
> - \_SB.PCI0.RP20.HPME()
> - \_SB.PCI0.RP21.HPME()
> - \_SB.PCI0.RP22.HPME()
> - \_SB.PCI0.RP23.HPME()
> - \_SB.PCI0.RP24.HPME()
> -
> - If(LEqual(D1F0,1))
> - {
> - \_SB.PCI0.PEG0.HPME()
> - Notify(\_SB.PCI0.PEG0, 0x02)
> - Notify(\_SB.PCI0.PEG0.PEGP, 0x02)
> - }
> -
> - If(LEqual(D1F1,1))
> - {
> - \_SB.PCI0.PEG1.HPME()
> - Notify(\_SB.PCI0.PEG1, 0x02)
> - }
> -
> - If(LEqual(D1F2,1))
> - {
> - \_SB.PCI0.PEG2.HPME()
> - Notify(\_SB.PCI0.PEG2, 0x02)
> - }
> - }
> -
> - // PCI Express Hot-Plug caused the wake event.
> -
> - Method(_L61)
> - {
> - Add(L01C,1,L01C) // Increment L01 Entry Count.
> -
> - P8XH(0,0x01) // Output information to Port 80h.
> - P8XH(1,L01C)
> -
> -
> - // Check Root Port 1 for a Hot Plug Event if the Port is
> - // enabled.
> -
> -
> If(LAnd(LNotEqual(\_SB.PCI0.RP01.VDID,0xFFFFFFFF),\_SB.PCI0.RP01.HPSX))
> - {
> - // Delay for 100ms to meet the timing requirements
> - // of the PCI Express Base Specification, Revision
> - // 1.0A, Section 6.6 ("...software must wait at
> - // least 100ms from the end of reset of one or more
> - // device before it is permitted to issue
> - // Configuration Requests to those devices").
> -
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x1),LNotEqual(TBS1,0x1)))) {
> - Sleep(100)
> - }
> -
> - If(\_SB.PCI0.RP01.PDCX)
> - {
> - // Clear all status bits first.
> -
> - Store(1,\_SB.PCI0.RP01.PDCX)
> - Store(1,\_SB.PCI0.RP01.HPSX)
> -
> - //
> - // PCH BIOS Spec Update Rev 1.03, Section 8.9 PCI Express*
> Hot-Plug BIOS Support
> - // In addition, BIOS should intercept Presence Detect Changed
> interrupt, enable L0s on
> - // hot plug and disable L0s on hot unplug. BIOS should also make
> sure the L0s is
> - // disabled on empty slots prior booting to OS.
> - //
> - If(LNot(\_SB.PCI0.RP01.PDSX)) {
> - // The PCI Express slot is empty, so disable L0s on hot unplug
> - //
> - Store(0,\_SB.PCI0.RP01.L0SE)
> -
> - }
> -
> - // Perform proper notification
> - // to the OS.
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x1),LNotEqual(TBS1,0x1)))) {
> - Notify(\_SB.PCI0.RP01,0)
> - }
> - }
> - Else
> - {
> - // False event. Clear Hot-Plug Status
> - // then exit.
> -
> - Store(1,\_SB.PCI0.RP01.HPSX)
> - }
> - }
> -
> - // Check Root Port 2 for a Hot Plug Event if the Port is
> - // enabled.
> -
> -
> If(LAnd(LNotEqual(\_SB.PCI0.RP02.VDID,0xFFFFFFFF),\_SB.PCI0.RP02.HPSX))
> - {
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x2),LNotEqual(TBS1,0x2)))) {
> - Sleep(100)
> - }
> -
> - If(\_SB.PCI0.RP02.PDCX)
> - {
> - Store(1,\_SB.PCI0.RP02.PDCX)
> - Store(1,\_SB.PCI0.RP02.HPSX)
> -
> - If(LNot(\_SB.PCI0.RP02.PDSX)) {
> - Store(0,\_SB.PCI0.RP02.L0SE)
> - }
> -
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x2),LNotEqual(TBS1,0x2)))) {
> - Notify(\_SB.PCI0.RP02,0)
> - }
> - }
> - Else
> - {
> - Store(1,\_SB.PCI0.RP02.HPSX)
> - }
> - }
> -
> - // Check Root Port 3 for a Hot Plug Event if the Port is
> - // enabled.
> -
> -
> If(LAnd(LNotEqual(\_SB.PCI0.RP03.VDID,0xFFFFFFFF),\_SB.PCI0.RP03.HPSX))
> - {
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x3),LNotEqual(TBS1,0x3)))) {
> - Sleep(100)
> - }
> -
> - If(\_SB.PCI0.RP03.PDCX)
> - {
> - Store(1,\_SB.PCI0.RP03.PDCX)
> - Store(1,\_SB.PCI0.RP03.HPSX)
> -
> - If(LNot(\_SB.PCI0.RP03.PDSX)) {
> - Store(0,\_SB.PCI0.RP03.L0SE)
> - }
> -
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x3),LNotEqual(TBS1,0x3)))) {
> - Notify(\_SB.PCI0.RP03,0)
> - }
> - }
> - Else
> - {
> - Store(1,\_SB.PCI0.RP03.HPSX)
> - }
> - }
> -
> - // Check Root Port 4 for a Hot Plug Event if the Port is
> - // enabled.
> -
> -
> If(LAnd(LNotEqual(\_SB.PCI0.RP04.VDID,0xFFFFFFFF),\_SB.PCI0.RP04.HPSX))
> - {
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x4),LNotEqual(TBS1,0x4)))) {
> - Sleep(100)
> - }
> -
> - If(\_SB.PCI0.RP04.PDCX)
> - {
> - Store(1,\_SB.PCI0.RP04.PDCX)
> - Store(1,\_SB.PCI0.RP04.HPSX)
> -
> - If(LNot(\_SB.PCI0.RP04.PDSX)) {
> - Store(0,\_SB.PCI0.RP04.L0SE)
> - }
> -
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x4),LNotEqual(TBS1,0x4)))) {
> - Notify(\_SB.PCI0.RP04,0)
> - }
> - }
> - Else
> - {
> - Store(1,\_SB.PCI0.RP04.HPSX)
> - }
> - }
> -
> - // Check Root Port 5 for a Hot Plug Event if the Port is
> - // enabled.
> -
> -
> If(LAnd(LNotEqual(\_SB.PCI0.RP05.VDID,0xFFFFFFFF),\_SB.PCI0.RP05.HPSX))
> - {
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x5),LNotEqual(TBS1,0x5)))) {
> - Sleep(100)
> - }
> -
> - If(\_SB.PCI0.RP05.PDCX)
> - {
> - Store(1,\_SB.PCI0.RP05.PDCX)
> - Store(1,\_SB.PCI0.RP05.HPSX)
> -
> - If(LNot(\_SB.PCI0.RP05.PDSX)) {
> - Store(0,\_SB.PCI0.RP05.L0SE)
> - }
> -
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x5),LNotEqual(TBS1,0x5)))) {
> - Notify(\_SB.PCI0.RP05,0)
> - }
> - }
> - Else
> - {
> - Store(1,\_SB.PCI0.RP05.HPSX)
> - }
> - }
> -
> - // Check Root Port 6 for a Hot Plug Event if the Port is
> - // enabled.
> -
> -
> If(LAnd(LNotEqual(\_SB.PCI0.RP06.VDID,0xFFFFFFFF),\_SB.PCI0.RP06.HPSX))
> - {
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x6),LNotEqual(TBS1,0x6)))) {
> - Sleep(100)
> - }
> -
> - If(\_SB.PCI0.RP06.PDCX)
> - {
> - Store(1,\_SB.PCI0.RP06.PDCX)
> - Store(1,\_SB.PCI0.RP06.HPSX)
> -
> - If(LNot(\_SB.PCI0.RP06.PDSX)) {
> - Store(0,\_SB.PCI0.RP06.L0SE)
> - }
> -
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x6),LNotEqual(TBS1,0x6)))) {
> - Notify(\_SB.PCI0.RP06,0)
> - }
> - }
> - Else
> - {
> - Store(1,\_SB.PCI0.RP06.HPSX)
> - }
> - }
> -
> - // Check Root Port 7 for a Hot Plug Event if the Port is
> - // enabled.
> -
> -
> If(LAnd(LNotEqual(\_SB.PCI0.RP07.VDID,0xFFFFFFFF),\_SB.PCI0.RP07.HPSX))
> - {
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x7),LNotEqual(TBS1,0x7)))) {
> - Sleep(100)
> - }
> -
> - If(\_SB.PCI0.RP07.PDCX)
> - {
> - Store(1,\_SB.PCI0.RP07.PDCX)
> - Store(1,\_SB.PCI0.RP07.HPSX)
> -
> - If(LNot(\_SB.PCI0.RP07.PDSX)) {
> - Store(0,\_SB.PCI0.RP07.L0SE)
> - }
> -
> - }
> - Else
> - {
> - Store(1,\_SB.PCI0.RP07.HPSX)
> - }
> - }
> -
> - // Check Root Port 8 for a Hot Plug Event if the Port is
> - // enabled.
> -
> -
> If(LAnd(LNotEqual(\_SB.PCI0.RP08.VDID,0xFFFFFFFF),\_SB.PCI0.RP08.HPSX))
> - {
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x8),LNotEqual(TBS1,0x8)))) {
> - Sleep(100)
> - }
> -
> - If(\_SB.PCI0.RP08.PDCX)
> - {
> - Store(1,\_SB.PCI0.RP08.PDCX)
> - Store(1,\_SB.PCI0.RP08.HPSX)
> -
> - If(LNot(\_SB.PCI0.RP08.PDSX)) {
> - Store(0,\_SB.PCI0.RP08.L0SE)
> - }
> -
> - }
> - Else
> - {
> - Store(1,\_SB.PCI0.RP08.HPSX)
> - }
> - }
> -
> - // Check Root Port 9 for a Hot Plug Event if the Port is
> - // enabled.
> -
> -
> If(LAnd(LNotEqual(\_SB.PCI0.RP09.VDID,0xFFFFFFFF),\_SB.PCI0.RP09.HPSX))
> - {
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x9),LNotEqual(TBS1,0x9)))) {
> - Sleep(100)
> - }
> -
> - If(\_SB.PCI0.RP09.PDCX)
> - {
> - Store(1,\_SB.PCI0.RP09.PDCX)
> - Store(1,\_SB.PCI0.RP09.HPSX)
> -
> - If(LNot(\_SB.PCI0.RP09.PDSX)) {
> - Store(0,\_SB.PCI0.RP09.L0SE)
> - }
> -
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x9),LNotEqual(TBS1,0x9)))) {
> - Notify(\_SB.PCI0.RP09,0)
> - }
> - }
> - Else
> - {
> - Store(1,\_SB.PCI0.RP09.HPSX)
> - }
> - }
> -
> - // Check Root Port 10 for a Hot Plug Event if the Port is
> - // enabled.
> -
> -
> If(LAnd(LNotEqual(\_SB.PCI0.RP10.VDID,0xFFFFFFFF),\_SB.PCI0.RP10.HPSX))
> - {
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0xA),LNotEqual(TBS1,0xA)))) {
> - Sleep(100)
> - }
> -
> - If(\_SB.PCI0.RP10.PDCX)
> - {
> - Store(1,\_SB.PCI0.RP10.PDCX)
> - Store(1,\_SB.PCI0.RP10.HPSX)
> -
> - If(LNot(\_SB.PCI0.RP10.PDSX)) {
> - Store(0,\_SB.PCI0.RP10.L0SE)
> - }
> -
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0xA),LNotEqual(TBS1,0xA)))) {
> - Notify(\_SB.PCI0.RP10,0)
> - }
> - }
> - Else
> - {
> - Store(1,\_SB.PCI0.RP10.HPSX)
> - }
> - }
> -
> - // Check Root Port 11 for a Hot Plug Event if the Port is
> - // enabled.
> -
> -
> If(LAnd(LNotEqual(\_SB.PCI0.RP11.VDID,0xFFFFFFFF),\_SB.PCI0.RP11.HPSX))
> - {
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0xB),LNotEqual(TBS1,0xB)))) {
> - Sleep(100)
> - }
> -
> - If(\_SB.PCI0.RP11.PDCX)
> - {
> - Store(1,\_SB.PCI0.RP11.PDCX)
> - Store(1,\_SB.PCI0.RP11.HPSX)
> -
> - If(LNot(\_SB.PCI0.RP11.PDSX)) {
> - Store(0,\_SB.PCI0.RP11.L0SE)
> - }
> -
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0xB),LNotEqual(TBS1,0xB)))) {
> - Notify(\_SB.PCI0.RP11,0)
> - }
> - }
> - Else
> - {
> - Store(1,\_SB.PCI0.RP11.HPSX)
> - }
> - }
> -
> - // Check Root Port 12 for a Hot Plug Event if the Port is
> - // enabled.
> -
> -
> If(LAnd(LNotEqual(\_SB.PCI0.RP12.VDID,0xFFFFFFFF),\_SB.PCI0.RP12.HPSX))
> - {
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0xC),LNotEqual(TBS1,0xC)))) {
> - Sleep(100)
> - }
> -
> - If(\_SB.PCI0.RP12.PDCX)
> - {
> - Store(1,\_SB.PCI0.RP12.PDCX)
> - Store(1,\_SB.PCI0.RP12.HPSX)
> -
> - If(LNot(\_SB.PCI0.RP12.PDSX)) {
> - Store(0,\_SB.PCI0.RP12.L0SE)
> - }
> -
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0xC),LNotEqual(TBS1,0xC)))) {
> - Notify(\_SB.PCI0.RP12,0)
> - }
> - }
> - Else
> - {
> - Store(1,\_SB.PCI0.RP12.HPSX)
> - }
> - }
> -
> - // Check Root Port 13 for a Hot Plug Event if the Port is
> - // enabled.
> -
> -
> If(LAnd(LNotEqual(\_SB.PCI0.RP13.VDID,0xFFFFFFFF),\_SB.PCI0.RP13.HPSX))
> - {
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0xD),LNotEqual(TBS1,0xD)))) {
> - Sleep(100)
> - }
> -
> - If(\_SB.PCI0.RP13.PDCX)
> - {
> - Store(1,\_SB.PCI0.RP13.PDCX)
> - Store(1,\_SB.PCI0.RP13.HPSX)
> -
> - If(LNot(\_SB.PCI0.RP13.PDSX)) {
> - Store(0,\_SB.PCI0.RP13.L0SE)
> - }
> -
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0xD),LNotEqual(TBS1,0xD)))) {
> - Notify(\_SB.PCI0.RP13,0)
> - }
> - }
> - Else
> - {
> - Store(1,\_SB.PCI0.RP13.HPSX)
> - }
> - }
> -
> - // Check Root Port 14 for a Hot Plug Event if the Port is
> - // enabled.
> -
> -
> If(LAnd(LNotEqual(\_SB.PCI0.RP14.VDID,0xFFFFFFFF),\_SB.PCI0.RP14.HPSX))
> - {
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0xE),LNotEqual(TBS1,0xE)))) {
> - Sleep(100)
> - }
> -
> - If(\_SB.PCI0.RP14.PDCX)
> - {
> - Store(1,\_SB.PCI0.RP14.PDCX)
> - Store(1,\_SB.PCI0.RP14.HPSX)
> -
> - If(LNot(\_SB.PCI0.RP14.PDSX)) {
> - Store(0,\_SB.PCI0.RP14.L0SE)
> - }
> -
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0xE),LNotEqual(TBS1,0xE)))) {
> - Notify(\_SB.PCI0.RP14,0)
> - }
> - }
> - Else
> - {
> - Store(1,\_SB.PCI0.RP14.HPSX)
> - }
> - }
> -
> - // Check Root Port 15 for a Hot Plug Event if the Port is
> - // enabled.
> -
> -
> If(LAnd(LNotEqual(\_SB.PCI0.RP15.VDID,0xFFFFFFFF),\_SB.PCI0.RP15.HPSX))
> - {
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0xF),LNotEqual(TBS1,0xF)))) {
> - Sleep(100)
> - }
> -
> - If(\_SB.PCI0.RP15.PDCX)
> - {
> - Store(1,\_SB.PCI0.RP15.PDCX)
> - Store(1,\_SB.PCI0.RP15.HPSX)
> -
> - If(LNot(\_SB.PCI0.RP15.PDSX)) {
> - Store(0,\_SB.PCI0.RP15.L0SE)
> - }
> -
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0xF),LNotEqual(TBS1,0xF)))) {
> - Notify(\_SB.PCI0.RP15,0)
> - }
> - }
> - Else
> - {
> - Store(1,\_SB.PCI0.RP15.HPSX)
> - }
> - }
> -
> - // Check Root Port 16 for a Hot Plug Event if the Port is
> - // enabled.
> -
> -
> If(LAnd(LNotEqual(\_SB.PCI0.RP16.VDID,0xFFFFFFFF),\_SB.PCI0.RP16.HPSX))
> - {
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x10),LNotEqual(TBS1,0x10)))) {
> - Sleep(100)
> - }
> -
> - If(\_SB.PCI0.RP16.PDCX)
> - {
> - Store(1,\_SB.PCI0.RP16.PDCX)
> - Store(1,\_SB.PCI0.RP16.HPSX)
> -
> - If(LNot(\_SB.PCI0.RP16.PDSX)) {
> - Store(0,\_SB.PCI0.RP16.L0SE)
> - }
> -
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x10),LNotEqual(TBS1,0x10)))) {
> - Notify(\_SB.PCI0.RP16,0)
> - }
> - }
> - Else
> - {
> - Store(1,\_SB.PCI0.RP16.HPSX)
> - }
> - }
> -
> - // Check Root Port 17 for a Hot Plug Event if the Port is
> - // enabled.
> -
> -
> If(LAnd(LNotEqual(\_SB.PCI0.RP17.VDID,0xFFFFFFFF),\_SB.PCI0.RP17.HPSX))
> - {
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x11),LNotEqual(TBS1,0x11)))) {
> - Sleep(100)
> - }
> -
> - If(\_SB.PCI0.RP17.PDCX)
> - {
> - Store(1,\_SB.PCI0.RP17.PDCX)
> - Store(1,\_SB.PCI0.RP17.HPSX)
> -
> - If(LNot(\_SB.PCI0.RP17.PDSX)) {
> - Store(0,\_SB.PCI0.RP17.L0SE)
> - }
> -
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x11),LNotEqual(TBS1,0x11)))) {
> - Notify(\_SB.PCI0.RP17,0)
> - }
> - }
> - Else
> - {
> - Store(1,\_SB.PCI0.RP17.HPSX)
> - }
> - }
> -
> - // Check Root Port 18 for a Hot Plug Event if the Port is
> - // enabled.
> -
> -
> If(LAnd(LNotEqual(\_SB.PCI0.RP18.VDID,0xFFFFFFFF),\_SB.PCI0.RP18.HPSX))
> - {
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x12),LNotEqual(TBS1,0x12)))) {
> - Sleep(100)
> - }
> -
> - If(\_SB.PCI0.RP18.PDCX)
> - {
> - Store(1,\_SB.PCI0.RP18.PDCX)
> - Store(1,\_SB.PCI0.RP18.HPSX)
> -
> - If(LNot(\_SB.PCI0.RP18.PDSX)) {
> - Store(0,\_SB.PCI0.RP18.L0SE)
> - }
> -
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x12),LNotEqual(TBS1,0x12)))) {
> - Notify(\_SB.PCI0.RP18,0)
> - }
> - }
> - Else
> - {
> - Store(1,\_SB.PCI0.RP18.HPSX)
> - }
> - }
> -
> - // Check Root Port 19 for a Hot Plug Event if the Port is
> - // enabled.
> -
> -
> If(LAnd(LNotEqual(\_SB.PCI0.RP19.VDID,0xFFFFFFFF),\_SB.PCI0.RP19.HPSX))
> - {
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x13),LNotEqual(TBS1,0x13)))) {
> - Sleep(100)
> - }
> -
> - If(\_SB.PCI0.RP19.PDCX)
> - {
> - Store(1,\_SB.PCI0.RP19.PDCX)
> - Store(1,\_SB.PCI0.RP19.HPSX)
> -
> - If(LNot(\_SB.PCI0.RP19.PDSX)) {
> - Store(0,\_SB.PCI0.RP19.L0SE)
> - }
> -
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x13),LNotEqual(TBS1,0x13)))) {
> - Notify(\_SB.PCI0.RP19,0)
> - }
> - }
> - Else
> - {
> - Store(1,\_SB.PCI0.RP19.HPSX)
> - }
> - }
> -
> - // Check Root Port 20 for a Hot Plug Event if the Port is
> - // enabled.
> -
> -
> If(LAnd(LNotEqual(\_SB.PCI0.RP20.VDID,0xFFFFFFFF),\_SB.PCI0.RP20.HPSX))
> - {
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x14),LNotEqual(TBS1,0x14)))) {
> - Sleep(100)
> - }
> -
> - If(\_SB.PCI0.RP20.PDCX)
> - {
> - Store(1,\_SB.PCI0.RP20.PDCX)
> - Store(1,\_SB.PCI0.RP20.HPSX)
> -
> - If(LNot(\_SB.PCI0.RP20.PDSX)) {
> - Store(0,\_SB.PCI0.RP20.L0SE)
> - }
> -
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x14),LNotEqual(TBS1,0x14)))) {
> - Notify(\_SB.PCI0.RP20,0)
> - }
> - }
> - Else
> - {
> - Store(1,\_SB.PCI0.RP20.HPSX)
> - }
> - }
> -
> - // Check Root Port 21 for a Hot Plug Event if the Port is
> - // enabled.
> -
> -
> If(LAnd(LNotEqual(\_SB.PCI0.RP21.VDID,0xFFFFFFFF),\_SB.PCI0.RP21.HPSX))
> - {
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x21),LNotEqual(TBS1,0x21)))) {
> - Sleep(100)
> - }
> -
> - If(\_SB.PCI0.RP21.PDCX)
> - {
> - Store(1,\_SB.PCI0.RP21.PDCX)
> - Store(1,\_SB.PCI0.RP21.HPSX)
> -
> - If(LNot(\_SB.PCI0.RP21.PDSX)) {
> - Store(0,\_SB.PCI0.RP21.L0SE)
> - }
> -
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x21),LNotEqual(TBS1,0x21)))) {
> - Notify(\_SB.PCI0.RP21,0)
> - }
> - }
> - Else
> - {
> - Store(1,\_SB.PCI0.RP21.HPSX)
> - }
> - }
> -
> - // Check Root Port 22 for a Hot Plug Event if the Port is
> - // enabled.
> -
> -
> If(LAnd(LNotEqual(\_SB.PCI0.RP22.VDID,0xFFFFFFFF),\_SB.PCI0.RP22.HPSX))
> - {
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x22),LNotEqual(TBS1,0x22)))) {
> - Sleep(100)
> - }
> -
> - If(\_SB.PCI0.RP22.PDCX)
> - {
> - Store(1,\_SB.PCI0.RP22.PDCX)
> - Store(1,\_SB.PCI0.RP22.HPSX)
> -
> - If(LNot(\_SB.PCI0.RP22.PDSX)) {
> - Store(0,\_SB.PCI0.RP22.L0SE)
> - }
> -
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x22),LNotEqual(TBS1,0x22)))) {
> - Notify(\_SB.PCI0.RP22,0)
> - }
> - }
> - Else
> - {
> - Store(1,\_SB.PCI0.RP22.HPSX)
> - }
> - }
> -
> - // Check Root Port 23 for a Hot Plug Event if the Port is
> - // enabled.
> -
> -
> If(LAnd(LNotEqual(\_SB.PCI0.RP23.VDID,0xFFFFFFFF),\_SB.PCI0.RP23.HPSX))
> - {
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x23),LNotEqual(TBS1,0x23)))) {
> - Sleep(100)
> - }
> -
> - If(\_SB.PCI0.RP23.PDCX)
> - {
> - Store(1,\_SB.PCI0.RP23.PDCX)
> - Store(1,\_SB.PCI0.RP23.HPSX)
> -
> - If(LNot(\_SB.PCI0.RP23.PDSX)) {
> - Store(0,\_SB.PCI0.RP23.L0SE)
> - }
> -
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x23),LNotEqual(TBS1,0x23)))) {
> - Notify(\_SB.PCI0.RP23,0)
> - }
> - }
> - Else
> - {
> - Store(1,\_SB.PCI0.RP23.HPSX)
> - }
> - }
> -
> - // Check Root Port 24 for a Hot Plug Event if the Port is
> - // enabled.
> -
> -
> If(LAnd(LNotEqual(\_SB.PCI0.RP24.VDID,0xFFFFFFFF),\_SB.PCI0.RP24.HPSX))
> - {
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x24),LNotEqual(TBS1,0x24)))) {
> - Sleep(100)
> - }
> -
> - If(\_SB.PCI0.RP24.PDCX)
> - {
> - Store(1,\_SB.PCI0.RP24.PDCX)
> - Store(1,\_SB.PCI0.RP24.HPSX)
> -
> - If(LNot(\_SB.PCI0.RP24.PDSX)) {
> - Store(0,\_SB.PCI0.RP24.L0SE)
> - }
> -
> - If(LOr(LNotEqual(TBTS,
> 0x01),LOr(LNotEqual(TBSE,0x24),LNotEqual(TBS1,0x24)))) {
> - Notify(\_SB.PCI0.RP24,0)
> - }
> - }
> - Else
> - {
> - Store(1,\_SB.PCI0.RP24.HPSX)
> - }
> - }
> - }
> -
> - //
> - // Software GPE caused the event.
> - //
> - Method(_L62)
> - {
> - // Clear GPE status bit.
> - Store(0,GPEC)
> -
> - //
> - // Handle DTS Thermal SCI Event.
> - //
> - If(CondRefOf(\_PR.DTSE)){
> - If(LGreaterEqual(\_PR.DTSE, 0x01)){
> - If(LEqual(\_PR.DTSI, 1)){
> - Notify(\_TZ.TZ00,0x80)
> - Notify(\_TZ.TZ01,0x80)
> - ///
> - /// Clear HWP interrupt status
> - ///
> - Store(0,\_PR.DTSI)
> - }
> - }
> - }
> - ///
> - /// Handle HWP SCI event
> - ///
> - External(\_GPE.HLVT, MethodObj)
> - If(LEqual(\_PR.HWPI, 1)){
> - If(CondRefOf(\_GPE.HLVT)){
> - \_GPE.HLVT()
> - }
> - ///
> - /// Clear HWP interrupt status
> - ///
> - Store(0,\_PR.HWPI)
> - }
> - }
> -
> - // IGD OpRegion SCI event (see IGD OpRegion/Software SCI BIOS SPEC).
> -
> - Method(_L66)
> - {
> - If(LAnd(\_SB.PCI0.GFX0.GSSE, LNot(GSMI))) // Graphics software SCI
> event?
> - {
> - \_SB.PCI0.GFX0.GSCI() // Handle the SWSCI
> - }
> - }
> - //
> - // BIOS Needs to implement appropriate handler based on
> CIO_PLUG_EVENT GPIO
> - // This is generic 2-tier GPIO handler
> - //
> - Method(_L6F)
> - {
> - \_SB.THDR(\CPG0,\RPS0,\RPT0) // Check for TBT Hotplug Handler event
> (2-tier GPI GPE event architecture)
> - }
> -}
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.asl
> b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.asl
> deleted file mode 100644
> index 827a37fbab..0000000000
> --- a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.asl
> +++ /dev/null
> @@ -1,33 +0,0 @@
> -/** @file
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -
> -// ITSS
> -// Define the needed ITSS registers used by ASL on Interrupt
> -// mapping.
> -
> -scope(\_SB){
> - OperationRegion(ITSS, SystemMemory, 0xfdc43100, 0x208)
> - Field(ITSS, ByteAcc, NoLock, Preserve)
> - {
> - PARC, 8,
> - PBRC, 8,
> - PCRC, 8,
> - PDRC, 8,
> - PERC, 8,
> - PFRC, 8,
> - PGRC, 8,
> - PHRC, 8,
> - Offset(0x200), // Offset 3300h ITSSPRC - ITSS Power Reduction
> Control
> - , 1,
> - , 1,
> - SCGE, 1, // ITSSPRC[2]: 8254 Static Clock Gating Enable
> (8254CGE)
> -
> - }
> -}
> -
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/LPC_DEV.ASL
> b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/LPC_DEV.ASL
> deleted file mode 100644
> index ea09363b84..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/LPC_DEV.ASL
> +++ /dev/null
> @@ -1,199 +0,0 @@
> -/** @file
> - ACPI DSDT table
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -Device(FWHD) // Firmware Hub Device
> -{
> - Name(_HID,EISAID("INT0800"))
> -
> - Name(_CRS,ResourceTemplate()
> - {
> - Memory32Fixed(ReadOnly,0xFF000000,0x1000000)
> - })
> -}
> -
> -
> -Device(HPET) // High Performance Event Timer
> -{
> - Name(_HID,EISAID("PNP0103"))
> - Name(_UID, 0)
> -
> - Name(BUF0,ResourceTemplate()
> - {
> - Memory32Fixed(ReadWrite,0xFED00000,0x400,FED0)
> - })
> -
> - Method(_STA,0)
> - {
> - // Show this Device only if the OS is WINXP or beyond.
> - If(HPTE)
> - {
> - Return(0x000F) // Enabled, do Display.
> - }
> -
> - Return(0x0000) // Return Nothing.
> - }
> -
> - Method(_CRS,0,Serialized)
> - {
> - If(HPTE)
> - {
> - // Check if HPETimer Base should be modified.
> - CreateDwordField(BUF0,^FED0._BAS,HPT0)
> - Store(HPTB,HPT0)
> - }
> -
> - Return(BUF0)
> - }
> -}
> -
> -Device(IPIC) // 8259 PIC
> -{
> - Name(_HID,EISAID("PNP0000"))
> -
> - Name(_CRS,ResourceTemplate()
> - {
> - IO(Decode16,0x20,0x20,0x01,0x02)
> - IO(Decode16,0x24,0x24,0x01,0x02)
> - IO(Decode16,0x28,0x28,0x01,0x02)
> - IO(Decode16,0x2C,0x2C,0x01,0x02)
> - IO(Decode16,0x30,0x30,0x01,0x02)
> - IO(Decode16,0x34,0x34,0x01,0x02)
> - IO(Decode16,0x38,0x38,0x01,0x02)
> - IO(Decode16,0x3C,0x3C,0x01,0x02)
> - IO(Decode16,0xA0,0xA0,0x01,0x02)
> - IO(Decode16,0xA4,0xA4,0x01,0x02)
> - IO(Decode16,0xA8,0xA8,0x01,0x02)
> - IO(Decode16,0xAC,0xAC,0x01,0x02)
> - IO(Decode16,0xB0,0xB0,0x01,0x02)
> - IO(Decode16,0xB4,0xB4,0x01,0x02)
> - IO(Decode16,0xB8,0xB8,0x01,0x02)
> - IO(Decode16,0xBC,0xBC,0x01,0x02)
> - IO(Decode16,0x4D0,0x4D0,0x01,0x02)
> - IRQNoFlags() {2}
> - })
> -}
> -
> -
> -Device(MATH) // Math Co-Processor
> -{
> - Name(_HID,EISAID("PNP0C04"))
> -
> - Name(_CRS,ResourceTemplate()
> - {
> - IO(Decode16,0xF0,0xF0,0x01,0x01)
> - IRQNoFlags() {13}
> - })
> -
> - //
> - // Report device present for LPT-H.
> - //
> - Method (_STA, 0x0, NotSerialized)
> - {
> - If(LEqual(PCHV(), SPTH)) {
> - Return(0x1F)
> - } else {
> - Return(0x0)
> - }
> - }
> -}
> -
> -
> -Device(LDRC) // LPC Device Resource Consumption
> -{
> - Name(_HID,EISAID("PNP0C02"))
> -
> - Name(_UID,2)
> -
> - Name(_CRS,ResourceTemplate() // This is for
> Cougar Point
> - {
> - IO(Decode16,0x2E,0x2E,0x1,0x02) // SIO Access.
> - IO(Decode16,0x4E,0x4E,0x1,0x02) // LPC Slot Access.
> - IO(Decode16,0x61,0x61,0x1,0x1) // NMI Status.
> - IO(Decode16,0x63,0x63,0x1,0x1) // Processor I/F.
> - IO(Decode16,0x65,0x65,0x1,0x1) // Processor I/F.
> - IO(Decode16,0x67,0x67,0x1,0x1) // Processor I/F.
> - IO(Decode16,0x70,0x70,0x1,0x1) // NMI Enable.
> - IO(Decode16,0x80,0x80,0x1,0x1) // Port 80h.
> - IO(Decode16,0x92,0x92,0x1,0x1) // Processor I/F.
> - IO(Decode16,0xB2,0xB2,0x01,0x02) // Software SMI.
> - IO(Decode16,0x680,0x680,0x1,0x20) // 32 Byte I/O.
> - IO(Decode16,0xFFFF,0xFFFF,0x1,0x1) // ACPI IO Trap.
> - IO(Decode16,0xFFFF,0xFFFF,0x1,0x1) // DTS IO Trap.
> - IO(Decode16,0xFFFF,0xFFFF,0x1,0x1) // HotKey IO Trap.
> -
> - IO(Decode16, 0x1800,0x1800,0x1,0xFF) // PCH ACPI Base
> -
> - IO(Decode16,0x164e,0x164e,0x1,0x02) // 16 Byte I/O.
> - })
> -}
> -
> -Device(LDR2) // LPC Device Resource Consumption for PCH GPIO
> -{
> - Name(_HID,EISAID("PNP0C02"))
> -
> - Name(_UID, "LPC_DEV")
> -
> - // LPT-H GPIO resource map
> - Name(_CRS,ResourceTemplate()
> - {
> - IO(Decode16, 0x800,0x800,0x1,0x80) // PCH GPIO Base.
> - })
> -
> - Method(_STA, 0, NotSerialized)
> - {
> - If(LEqual(PCHV(), SPTH)) {
> - Return(0xF)
> - } else {
> - Return(0)
> - }
> - }
> -}
> -
> -Device(RTC) // RTC
> -{
> - Name(_HID,EISAID("PNP0B00"))
> -
> - Name(_CRS,ResourceTemplate()
> - {
> - IO(Decode16,0x70,0x70,0x01,0x08)
> - IRQNoFlags() {8}
> - })
> -}
> -
> -Device(TIMR) // 8254 Timer
> -{
> - Name(_HID,EISAID("PNP0100"))
> -
> - Name(_CRS,ResourceTemplate()
> - {
> - IO(Decode16,0x40,0x40,0x01,0x04)
> - IO(Decode16,0x50,0x50,0x10,0x04)
> - IRQNoFlags() {0}
> - })
> -}
> -
> -Device(CWDT)
> -{
> - Name(_HID,EISAID("INT3F0D"))
> - Name(_CID,EISAID("PNP0C02"))
> - Name(BUF0,ResourceTemplate()
> - {
> - IO(Decode16, 0x1854, 0x1854, 0x4, 0x4) // PMBS 0x1800 + Offset
> 0x54
> - }
> - )
> -
> - Method(_STA,0,Serialized)
> - {
> - Return(0x0F)
> - }
> -
> - Method(_CRS,0,Serialized)
> - {
> - Return(BUF0)
> - }
> -}
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/LpcB.asl
> b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/LpcB.asl
> deleted file mode 100644
> index 6fbaf3a97f..0000000000
> --- a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/LpcB.asl
> +++ /dev/null
> @@ -1,88 +0,0 @@
> -/** @file
> - ACPI DSDT table
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -
> -// LPC Bridge - Device 31, Function 0
> -scope (\_SB.PCI0.LPCB) {
> - Include ("LPC_DEV.ASL")
> -
> - // Define the KBC_COMMAND_REG-64, KBC_DATA_REG-60 Registers
> as an ACPI Operating
> - // Region. These registers will be used to skip kbd mouse
> - // resource settings if not present.
> - OperationRegion(PKBS, SystemIO, 0x60, 0x05)
> - Field(PKBS, ByteAcc, Lock, Preserve)
> - {
> - PKBD, 8,
> - , 8,
> - , 8,
> - , 8,
> - PKBC, 8
> - }
> - Device(PS2K) // PS2 Keyboard
> - {
> - Name(_HID,"MSFT0001")
> - Name(_CID,EISAID("PNP0303"))
> -
> - Method(_STA)
> - {
> - If (P2MK) //Ps2 Keyboard and Mouse Enable
> - {
> - Return(0x000F)
> - }
> - Return(0x0000)
> - }
> -
> - Name(_CRS,ResourceTemplate()
> - {
> - IO(Decode16,0x60,0x60,0x01,0x01)
> - IO(Decode16,0x64,0x64,0x01,0x01)
> - IRQ(Edge,ActiveHigh,Exclusive){0x01}
> - })
> -
> - Name(_PRS, ResourceTemplate(){
> - StartDependentFn(0, 0) {
> - FixedIO(0x60,0x01)
> - FixedIO(0x64,0x01)
> - IRQNoFlags(){1}
> - }
> - EndDependentFn()
> - })
> -
> - }
> -
> - Device(PS2M) // PS/2 Mouse
> - {
> - Name(_HID,"MSFT0003")
> - Name(_CID,EISAID("PNP0F03"))
> -
> - Method(_STA)
> - {
> - If (P2ME) //Ps2 Mouse Enable
> - {
> - If (P2MK) //Ps2 Keyboard and Mouse Enable
> - {
> - Return(0x000F)
> - }
> - }
> - Return(0x0000)
> - }
> -
> - Name(_CRS,ResourceTemplate()
> - {
> - IRQ(Edge,ActiveHigh,Exclusive){0x0C}
> - })
> -
> - Name(_PRS, ResourceTemplate(){
> - StartDependentFn(0, 0) {
> - IRQNoFlags(){12}
> - }
> - EndDependentFn()
> - })
> - }
> -
> -}
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PCI_DRC.ASL
> b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PCI_DRC.ASL
> deleted file mode 100644
> index fba792642d..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PCI_DRC.ASL
> +++ /dev/null
> @@ -1,116 +0,0 @@
> -/** @file
> - ACPI DSDT table
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -
> -Scope (\_SB.PCI0){
> -
> - Device(PDRC)
> - {
> - //
> - // PCI Device Resource Consumption
> - //
> -
> - Name(_HID,EISAID("PNP0C02"))
> -
> - Name(_UID,1)
> -
> - Name(BUF0,ResourceTemplate()
> - {
> - //
> - // MCH BAR _BAS will be updated in _CRS below according to
> B0:D0:F0:Reg.48h
> - //
> - Memory32Fixed(ReadWrite,0,0x08000,MCHB)
> - //
> - // DMI BAR _BAS will be updated in _CRS below according to
> B0:D0:F0:Reg.68h
> - //
> - Memory32Fixed(ReadWrite,0,0x01000,DMIB)
> - //
> - // EP BAR _BAS will be updated in _CRS below according to
> B0:D0:F0:Reg.40h
> - //
> - Memory32Fixed(ReadWrite,0,0x01000,EGPB)
> - //
> - // PCI Express BAR _BAS and _LEN will be updated in _CRS below
> according to B0:D0:F0:Reg.60h
> - //
> - Memory32Fixed(ReadWrite,0,0,PCIX)
> -
> - //
> - // MISC ICH TTT base address reserved for the TxT module use.
> Check if the hard code meets the real configuration.
> - // If not, dynamically update it like the _CRS method below.
> - //
> - Memory32Fixed(ReadWrite,0xFED20000,0x20000)
> -
> - //
> - // VTD engine memory range. Check if the hard code meets the real
> configuration.
> - // If not, dynamically update it like the _CRS method below.
> - //
> - Memory32Fixed(ReadOnly, 0xFED90000, 0x00004000)
> -
> - //
> - // MISC ICH. Check if the hard code meets the real configuration.
> - // If not, dynamically update it like the _CRS method below.
> - //
> - Memory32Fixed(ReadWrite,0xFED45000,0x4B000,TPMM)
> -
> - //
> - // FLASH range
> - //
> - Memory32Fixed (ReadOnly, 0xFF000000, 0x1000000, FIOH) //16MB
> as per IOH spec
> -
> - //
> - // Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF)
> - //
> - Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000, LIOH)
> -
> - //
> - // Sx handler reserved MMIO
> - //
> - Memory32Fixed (ReadWrite, 0, 0, SXRE)
> -
> - //
> - // Reserve HPET address decode range
> - //
> - Memory32Fixed (ReadWrite, 0, 0, HPET)
> -
> - })
> -
> -
> - Method(_CRS,0,Serialized)
> - {
> -
> - CreateDwordField(BUF0,^MCHB._BAS,MBR0)
> - Store(\_SB.PCI0.GMHB(), MBR0)
> -
> - CreateDwordField(BUF0,^DMIB._BAS,DBR0)
> - Store(\_SB.PCI0.GDMB(), DBR0)
> -
> - CreateDwordField(BUF0,^EGPB._BAS,EBR0)
> - Store(\_SB.PCI0.GEPB(), EBR0)
> -
> - CreateDwordField(BUF0,^PCIX._BAS,XBR0)
> - Store(\_SB.PCI0.GPCB(), XBR0)
> -
> - CreateDwordField(BUF0,^PCIX._LEN,XSZ0)
> - Store(\_SB.PCI0.GPCL(), XSZ0)
> -
> - CreateDwordField(BUF0,^SXRE._BAS,SXRA)
> - Store(SXRB, SXRA)
> - CreateDwordField(BUF0,^SXRE._LEN,SXRL)
> - Store(SXRS, SXRL)
> -
> - // HPET device claims the resource in LPC_DEV.ASL.
> - If(LNOT(HPTE)){
> - CreateDwordField(BUF0,^HPET._BAS,HBAS)
> - CreateDwordField(BUF0,^HPET._LEN,HLEN)
> - Store(HPTB, HBAS)
> - Store(0x400, HLEN)
> - }
> -
> - Return(BUF0)
> - }
> - } //end of PDRC
> -} // end of SB
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciTree.asl
> b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciTree.asl
> deleted file mode 100644
> index ef65cea0af..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciTree.asl
> +++ /dev/null
> @@ -1,306 +0,0 @@
> -/** @file
> - ACPI DSDT table
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -Scope(\_SB) {
> - Name(PR00, Package(){
> -// PCI Bridge
> -// D31: cAVS, SMBus, GbE, Nothpeak
> - Package(){0x001FFFFF, 0, LNKA, 0 },
> - Package(){0x001FFFFF, 1, LNKB, 0 },
> - Package(){0x001FFFFF, 2, LNKC, 0 },
> - Package(){0x001FFFFF, 3, LNKD, 0 },
> -// D30: SerialIo and SCS - can't use PIC
> -// D29: PCI Express Port 9-16
> - Package(){0x001DFFFF, 0, LNKA, 0 },
> - Package(){0x001DFFFF, 1, LNKB, 0 },
> - Package(){0x001DFFFF, 2, LNKC, 0 },
> - Package(){0x001DFFFF, 3, LNKD, 0 },
> -// D28: PCI Express Port 1-8
> - Package(){0x001CFFFF, 0, LNKA, 0 },
> - Package(){0x001CFFFF, 1, LNKB, 0 },
> - Package(){0x001CFFFF, 2, LNKC, 0 },
> - Package(){0x001CFFFF, 3, LNKD, 0 },
> -// D27: PCI Express Port 17-20
> - Package(){0x001BFFFF, 0, LNKA, 0 },
> - Package(){0x001BFFFF, 1, LNKB, 0 },
> - Package(){0x001BFFFF, 2, LNKC, 0 },
> - Package(){0x001BFFFF, 3, LNKD, 0 },
> -// D25: SerialIo - can't use PIC
> -// D23: SATA controller
> - Package(){0x0017FFFF, 0, LNKA, 0 },
> -// D22: CSME (HECI, IDE-R, Keyboard and Text redirection
> - Package(){0x0016FFFF, 0, LNKA, 0 },
> - Package(){0x0016FFFF, 1, LNKB, 0 },
> - Package(){0x0016FFFF, 2, LNKC, 0 },
> - Package(){0x0016FFFF, 3, LNKD, 0 },
> -// D21: SerialIo - can't use PIC
> -// D20: xHCI, Thermal Subsystem, Camera IO Host Controller
> - Package(){0x0014FFFF, 0, LNKA, 0 },
> - Package(){0x0014FFFF, 1, LNKB, 0 },
> - Package(){0x0014FFFF, 2, LNKC, 0 },
> - Package(){0x0014FFFF, 3, LNKD, 0 },
> -// D19: Integrated Sensor Hub - can't use PIC
> -
> -// Host Bridge
> -// P.E.G. Root Port D1F0
> - Package(){0x0001FFFF, 0, LNKA, 0 },
> - Package(){0x0001FFFF, 1, LNKB, 0 },
> - Package(){0x0001FFFF, 2, LNKC, 0 },
> - Package(){0x0001FFFF, 3, LNKD, 0 },
> -// P.E.G. Root Port D1F1
> -// P.E.G. Root Port D1F2
> -// SA IGFX Device
> - Package(){0x0002FFFF, 0, LNKA, 0 },
> -// SA Thermal Device
> - Package(){0x0004FFFF, 0, LNKA, 0 },
> -// SA SkyCam Device
> - Package(){0x0005FFFF, 0, LNKA, 0 },
> -// SA GMM Device
> - Package(){0x0008FFFF, 0, LNKA, 0 },
> - })
> - Name(AR00, Package(){
> -// PCI Bridge
> -// D31: cAVS, SMBus, GbE, Nothpeak
> - Package(){0x001FFFFF, 0, 0, 16 },
> - Package(){0x001FFFFF, 1, 0, 17 },
> - Package(){0x001FFFFF, 2, 0, 18 },
> - Package(){0x001FFFFF, 3, 0, 19 },
> -// D30: SerialIo and SCS
> - Package(){0x001EFFFF, 0, 0, 20 },
> - Package(){0x001EFFFF, 1, 0, 21 },
> - Package(){0x001EFFFF, 2, 0, 22 },
> - Package(){0x001EFFFF, 3, 0, 23 },
> -// D29: PCI Express Port 9-16
> - Package(){0x001DFFFF, 0, 0, 16 },
> - Package(){0x001DFFFF, 1, 0, 17 },
> - Package(){0x001DFFFF, 2, 0, 18 },
> - Package(){0x001DFFFF, 3, 0, 19 },
> -// D28: PCI Express Port 1-8
> - Package(){0x001CFFFF, 0, 0, 16 },
> - Package(){0x001CFFFF, 1, 0, 17 },
> - Package(){0x001CFFFF, 2, 0, 18 },
> - Package(){0x001CFFFF, 3, 0, 19 },
> -// D27: PCI Express Port 17-20
> - Package(){0x001BFFFF, 0, 0, 16 },
> - Package(){0x001BFFFF, 1, 0, 17 },
> - Package(){0x001BFFFF, 2, 0, 18 },
> - Package(){0x001BFFFF, 3, 0, 19 },
> -// D25: SerialIo
> - Package(){0x0019FFFF, 0, 0, 32 },
> - Package(){0x0019FFFF, 1, 0, 33 },
> - Package(){0x0019FFFF, 2, 0, 34 },
> -// D23: SATA controller
> - Package(){0x0017FFFF, 0, 0, 16 },
> -// D22: CSME (HECI, IDE-R, Keyboard and Text redirection
> - Package(){0x0016FFFF, 0, 0, 16 },
> - Package(){0x0016FFFF, 1, 0, 17 },
> - Package(){0x0016FFFF, 2, 0, 18 },
> - Package(){0x0016FFFF, 3, 0, 19 },
> -// D21: SerialIo
> - Package(){0x0015FFFF, 0, 0, 16 },
> - Package(){0x0015FFFF, 1, 0, 17 },
> - Package(){0x0015FFFF, 2, 0, 18 },
> - Package(){0x0015FFFF, 3, 0, 19 },
> -// D20: xHCI, OTG, Thermal Subsystem, Camera IO Host Controller
> - Package(){0x0014FFFF, 0, 0, 16 },
> - Package(){0x0014FFFF, 1, 0, 17 },
> - Package(){0x0014FFFF, 2, 0, 18 },
> - Package(){0x0014FFFF, 3, 0, 19 },
> -// D19: Integrated Sensor Hub
> - Package(){0x0013FFFF, 0, 0, 20 },
> -
> -// Host Bridge
> -// P.E.G. Root Port D1F0
> - Package(){0x0001FFFF, 0, 0, 16 },
> - Package(){0x0001FFFF, 1, 0, 17 },
> - Package(){0x0001FFFF, 2, 0, 18 },
> - Package(){0x0001FFFF, 3, 0, 19 },
> -// P.E.G. Root Port D1F1
> -// P.E.G. Root Port D1F2
> -// SA IGFX Device
> - Package(){0x0002FFFF, 0, 0, 16 },
> -// SA Thermal Device
> - Package(){0x0004FFFF, 0, 0, 16 },
> -// SA SkyCam Device
> - Package(){0x0005FFFF, 0, 0, 16 },
> -// SA GMM Device
> - Package(){0x0008FFFF, 0, 0, 16 },
> - })
> - Name(PR04, Package(){
> - Package(){0x0000FFFF, 0, LNKA, 0 },
> - Package(){0x0000FFFF, 1, LNKB, 0 },
> - Package(){0x0000FFFF, 2, LNKC, 0 },
> - Package(){0x0000FFFF, 3, LNKD, 0 },
> - })
> - Name(AR04, Package(){
> - Package(){0x0000FFFF, 0, 0, 16 },
> - Package(){0x0000FFFF, 1, 0, 17 },
> - Package(){0x0000FFFF, 2, 0, 18 },
> - Package(){0x0000FFFF, 3, 0, 19 },
> - })
> - Name(PR05, Package(){
> - Package(){0x0000FFFF, 0, LNKB, 0 },
> - Package(){0x0000FFFF, 1, LNKC, 0 },
> - Package(){0x0000FFFF, 2, LNKD, 0 },
> - Package(){0x0000FFFF, 3, LNKA, 0 },
> - })
> - Name(AR05, Package(){
> - Package(){0x0000FFFF, 0, 0, 17 },
> - Package(){0x0000FFFF, 1, 0, 18 },
> - Package(){0x0000FFFF, 2, 0, 19 },
> - Package(){0x0000FFFF, 3, 0, 16 },
> - })
> - Name(PR06, Package(){
> - Package(){0x0000FFFF, 0, LNKC, 0 },
> - Package(){0x0000FFFF, 1, LNKD, 0 },
> - Package(){0x0000FFFF, 2, LNKA, 0 },
> - Package(){0x0000FFFF, 3, LNKB, 0 },
> - })
> - Name(AR06, Package(){
> - Package(){0x0000FFFF, 0, 0, 18 },
> - Package(){0x0000FFFF, 1, 0, 19 },
> - Package(){0x0000FFFF, 2, 0, 16 },
> - Package(){0x0000FFFF, 3, 0, 17 },
> - })
> - Name(PR07, Package(){
> - Package(){0x0000FFFF, 0, LNKD, 0 },
> - Package(){0x0000FFFF, 1, LNKA, 0 },
> - Package(){0x0000FFFF, 2, LNKB, 0 },
> - Package(){0x0000FFFF, 3, LNKC, 0 },
> - })
> - Name(AR07, Package(){
> - Package(){0x0000FFFF, 0, 0, 19 },
> - Package(){0x0000FFFF, 1, 0, 16 },
> - Package(){0x0000FFFF, 2, 0, 17 },
> - Package(){0x0000FFFF, 3, 0, 18 },
> - })
> - Name(PR08, Package(){
> - Package(){0x0000FFFF, 0, LNKA, 0 },
> - Package(){0x0000FFFF, 1, LNKB, 0 },
> - Package(){0x0000FFFF, 2, LNKC, 0 },
> - Package(){0x0000FFFF, 3, LNKD, 0 },
> - })
> - Name(AR08, Package(){
> - Package(){0x0000FFFF, 0, 0, 16 },
> - Package(){0x0000FFFF, 1, 0, 17 },
> - Package(){0x0000FFFF, 2, 0, 18 },
> - Package(){0x0000FFFF, 3, 0, 19 },
> - })
> - Name(PR09, Package(){
> - Package(){0x0000FFFF, 0, LNKB, 0 },
> - Package(){0x0000FFFF, 1, LNKC, 0 },
> - Package(){0x0000FFFF, 2, LNKD, 0 },
> - Package(){0x0000FFFF, 3, LNKA, 0 },
> - })
> - Name(AR09, Package(){
> - Package(){0x0000FFFF, 0, 0, 17 },
> - Package(){0x0000FFFF, 1, 0, 18 },
> - Package(){0x0000FFFF, 2, 0, 19 },
> - Package(){0x0000FFFF, 3, 0, 16 },
> - })
> - Name(PR0E, Package(){
> - Package(){0x0000FFFF, 0, LNKC, 0 },
> - Package(){0x0000FFFF, 1, LNKD, 0 },
> - Package(){0x0000FFFF, 2, LNKA, 0 },
> - Package(){0x0000FFFF, 3, LNKB, 0 },
> - })
> - Name(AR0E, Package(){
> - Package(){0x0000FFFF, 0, 0, 18 },
> - Package(){0x0000FFFF, 1, 0, 19 },
> - Package(){0x0000FFFF, 2, 0, 16 },
> - Package(){0x0000FFFF, 3, 0, 17 },
> - })
> - Name(PR0F, Package(){
> - Package(){0x0000FFFF, 0, LNKD, 0 },
> - Package(){0x0000FFFF, 1, LNKA, 0 },
> - Package(){0x0000FFFF, 2, LNKB, 0 },
> - Package(){0x0000FFFF, 3, LNKC, 0 },
> - })
> - Name(AR0F, Package(){
> - Package(){0x0000FFFF, 0, 0, 19 },
> - Package(){0x0000FFFF, 1, 0, 16 },
> - Package(){0x0000FFFF, 2, 0, 17 },
> - Package(){0x0000FFFF, 3, 0, 18 },
> - })
> - Name(PR02, Package(){
> - Package(){0x0000FFFF, 0, LNKA, 0 },
> - Package(){0x0000FFFF, 1, LNKB, 0 },
> - Package(){0x0000FFFF, 2, LNKC, 0 },
> - Package(){0x0000FFFF, 3, LNKD, 0 },
> - })
> - Name(AR02, Package(){
> -// P.E.G. Port Slot x16
> - Package(){0x0000FFFF, 0, 0, 16 },
> - Package(){0x0000FFFF, 1, 0, 17 },
> - Package(){0x0000FFFF, 2, 0, 18 },
> - Package(){0x0000FFFF, 3, 0, 19 },
> - })
> - Name(PR0A, Package(){
> -// P.E.G. Port Slot x8
> - Package(){0x0000FFFF, 0, LNKB, 0 },
> - Package(){0x0000FFFF, 1, LNKC, 0 },
> - Package(){0x0000FFFF, 2, LNKD, 0 },
> - Package(){0x0000FFFF, 3, LNKA, 0 },
> - })
> - Name(AR0A, Package(){
> -// P.E.G. Port Slot x8
> - Package(){0x0000FFFF, 0, 0, 17 },
> - Package(){0x0000FFFF, 1, 0, 18 },
> - Package(){0x0000FFFF, 2, 0, 19 },
> - Package(){0x0000FFFF, 3, 0, 16 },
> - })
> - Name(PR0B, Package(){
> -// P.E.G. Port Slot x4
> - Package(){0x0000FFFF, 0, LNKC, 0 },
> - Package(){0x0000FFFF, 1, LNKD, 0 },
> - Package(){0x0000FFFF, 2, LNKA, 0 },
> - Package(){0x0000FFFF, 3, LNKB, 0 },
> - })
> - Name(AR0B, Package(){
> -// P.E.G. Port Slot x4
> - Package(){0x0000FFFF, 0, 0, 18 },
> - Package(){0x0000FFFF, 1, 0, 19 },
> - Package(){0x0000FFFF, 2, 0, 16 },
> - Package(){0x0000FFFF, 3, 0, 17 },
> - })
> -//---------------------------------------------------------------------------
> -// List of IRQ resource buffers compatible with _PRS return format.
> -//---------------------------------------------------------------------------
> -// Naming legend:
> -// RSxy, PRSy - name of the IRQ resource buffer to be returned by _PRS, "xy"
> - last two characters of IRQ Link name.
> -// Note. PRSy name is generated if IRQ Link name starts from "LNK".
> -// HLxy , LLxy - reference names, can be used to access bit mask of available
> IRQs. HL and LL stand for active High(Low) Level triggered Irq model.
> -//---------------------------------------------------------------------------
> - Name(PRSA, ResourceTemplate(){ // Link name: LNKA
> - IRQ(Level, ActiveLow, Shared, LLKA) {3,4,5,6,10,11,12,14,15}
> - })
> - Alias(PRSA,PRSB) // Link name: LNKB
> - Alias(PRSA,PRSC) // Link name: LNKC
> - Alias(PRSA,PRSD) // Link name: LNKD
> - Alias(PRSA,PRSE) // Link name: LNKE
> - Alias(PRSA,PRSF) // Link name: LNKF
> - Alias(PRSA,PRSG) // Link name: LNKG
> - Alias(PRSA,PRSH) // Link name: LNKH
> -//---------------------------------------------------------------------------
> -// Begin PCI tree object scope
> -//---------------------------------------------------------------------------
> - Device(PCI0) { // PCI Bridge "Host Bridge"
> - Name(_HID, EISAID("PNP0A08")) // Indicates PCI Express/PCI-X Mode2
> host hierarchy
> - Name(_CID, EISAID("PNP0A03")) // To support legacy OS that doesn't
> understand the new HID
> - Name(_ADR, 0x00000000)
> - Method(^BN00, 0){ return(0x0000) } // Returns default Bus number
> for Peer PCI busses. Name can be overriden with control method placed
> directly under Device scope
> - Method(_BBN, 0){ return(BN00()) } // Bus number, optional for the
> Root PCI Bus
> - Name(_UID, 0x0000) // Unique Bus ID, optional
> - Method(_PRT,0) {
> - If(PICM) {Return(AR00)} // APIC mode
> - Return (PR00) // PIC Mode
> - } // end _PRT
> -
> - Include("HostBus.asl")
> - } // end PCI0 Bridge "Host Bridge"
> -} // end _SB scope
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl
> b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl
> deleted file mode 100644
> index 063093a08c..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl
> +++ /dev/null
> @@ -1,1129 +0,0 @@
> -/** @file
> - ACPI DSDT table
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#define TRAP_TYPE_DTS 0x02
> -#define TRAP_TYPE_IGD 0x03
> -#define TRAP_TYPE_BGD 0x04 // BIOS Guard
> -
> -// Define the following External variables to prevent a WARNING when
> -// using ASL.EXE and an ERROR when using IASL.EXE.
> -
> -External(\PC00, IntObj) // PR00 _PDC Flags
> -External(\PC01)
> -External(\PC02)
> -External(\PC03)
> -External(\PC04)
> -External(\PC05)
> -External(\PC06)
> -External(\PC07)
> -External(\PC08)
> -External(\PC09)
> -External(\PC10)
> -External(\PC11)
> -External(\PC12)
> -External(\PC13)
> -External(\PC14)
> -External(\PC15)
> -External(\_PR.CFGD)
> -External(\SGMD)
> -
> -//
> -// DTS externals
> -//
> -External(\_PR.DTSF)
> -External(\_PR.DTSE)
> -External(\_PR.TRPD)
> -External(\_PR.TRPF)
> -External(\_PR.DSAE)
> -//
> -// SGX
> -//
> -External(\_PR.EPCS)
> -External(\_PR.EMNA)
> -External(\_PR.ELNG)
> -
> -External(\_SB.PCI0.GFX0.TCHE) // Technology enabled indicator
> -External(\_SB.PCI0.GFX0.STAT) // State Indicator
> -
> -External(\_SB.TPM.PTS, MethodObj)
> -External(\_SB.PCI0.PAUD.PUAM, MethodObj) //PUAM - PowerResource User
> Absent Mode
> -External(\_SB.PCI0.XHC.DUAM, MethodObj) //DUAM - Device User Absent
> Mode for XHCI controller
> -External(\_SB.PCI0.I2C4.GEXP.INVC, MethodObj)
> -
> -External(\_SB.PCI0.GFX0.IUEH, MethodObj)
> -
> -#define CONVERTIBLE_BUTTON 6
> -#define DOCK_INDICATOR 7
> -
> -Name(ECUP, 1) // EC State indicator: 1- Normal Mode 0- Low Power Mode
> -Mutex(EHLD, 0) // EC Hold indicator: 0- No one accessing the EC Power State
> 1- Someone else is accessing the EC Power State
> -
> -
> -
> -External(TBTD, MethodObj)
> -External(TBTF, MethodObj)
> -External(MMRP, MethodObj)
> -External(MMTB, MethodObj)
> -External(TBFF, MethodObj)
> -External(FFTB, MethodObj)
> -External(SXTB, MethodObj)
> -
> -
> -// Interrupt specific registers
> -include("Itss.asl")
> -
> -// Create a Global MUTEX.
> -
> -Mutex(MUTX,0)
> -
> -// OS Up mutex
> -Mutex(OSUM, 0)
> -// _WAK Finished Event
> -Event(WFEV)
> -
> -// Define Port 80 as an ACPI Operating Region to use for debugging.
> Please
> -// note that the Intel CRBs have the ability to ouput an entire DWord to
> -// Port 80h for debugging purposes, so the model implemented here may
> not be
> -// able to be used on OEM Designs.
> -
> -OperationRegion(PRT0,SystemIO,0x80,4)
> -Field(PRT0,DwordAcc,Lock,Preserve)
> -{
> - P80H, 32
> -}
> -
> -// Port 80h Update:
> -// Update 8 bits of the 32-bit Port 80h.
> -//
> -// Arguments:
> -// Arg0: 0 = Write Port 80h, Bits 7:0 Only.
> -// 1 = Write Port 80h, Bits 15:8 Only.
> -// 2 = Write Port 80h, Bits 23:16 Only.
> -// 3 = Write Port 80h, Bits 31:24 Only.
> -// Arg1: 8-bit Value to write
> -//
> -// Return Value:
> -// None
> -
> -Method(D8XH,2,Serialized)
> -{
> - If(LEqual(Arg0,0)) // Write Port 80h, Bits 7:0.
> - {
> - Store(Or(And(P80D,0xFFFFFF00),Arg1),P80D)
> - }
> -
> - If(LEqual(Arg0,1)) // Write Port 80h, Bits 15:8.
> - {
> - Store(Or(And(P80D,0xFFFF00FF),ShiftLeft(Arg1,8)),P80D)
> - }
> -
> - If(LEqual(Arg0,2)) // Write Port 80h, Bits 23:16.
> - {
> - Store(Or(And(P80D,0xFF00FFFF),ShiftLeft(Arg1,16)),P80D)
> - }
> -
> - If(LEqual(Arg0,3)) // Write Port 80h, Bits 31:24.
> - {
> - Store(Or(And(P80D,0x00FFFFFF),ShiftLeft(Arg1,24)),P80D)
> - }
> -
> - Store(P80D,P80H)
> -}
> -
> -// Debug Port 80h Update:
> -// If Acpidebug is enabled only then call D8XH to update 8 bits of the
> 32-bit Port 80h.
> -//
> -// Arguments:
> -// Arg0: 0 = Write Port 80h, Bits 7:0 Only.
> -// 1 = Write Port 80h, Bits 15:8 Only.
> -// 2 = Write Port 80h, Bits 23:16 Only.
> -// 3 = Write Port 80h, Bits 31:24 Only.
> -// Arg1: 8-bit Value to write
> -//
> -// Return Value:
> -// None
> -Method(P8XH,2,Serialized)
> -{
> - // If ACPI debug is enabled, then display post codes on Port 80h
> - If(CondRefOf(MDBG)) {// Check if ACPI Debug SSDT is loaded
> - D8XH(Arg0,Arg1)
> - }
> -}
> -
> -Method(ADBG,1,Serialized)
> -{
> - Return(0)
> -}
> -
> -//
> -// Define SW SMI port as an ACPI Operating Region to use for generate SW
> SMI.
> -//
> -OperationRegion(SPRT,SystemIO, 0xB2,2)
> -Field (SPRT, ByteAcc, Lock, Preserve) {
> - SSMP, 8
> -}
> -
> -// The _PIC Control Method is optional for ACPI design. It allows the
> -// OS to inform the ASL code which interrupt controller is being used,
> -// the 8259 or APIC. The reference code in this document will address
> -// PCI IRQ Routing and resource allocation for both cases.
> -//
> -// The values passed into _PIC are:
> -// 0 = 8259
> -// 1 = IOAPIC
> -
> -Method(\_PIC,1)
> -{
> - Store(Arg0,GPIC)
> - Store(Arg0,PICM)
> -}
> -
> -// Prepare to Sleep. The hook is called when the OS is about to
> -// enter a sleep state. The argument passed is the numeric value of
> -// the Sx state.
> -
> -Method(_PTS,1)
> -{
> - Store(0,P80D) // Zero out the entire Port 80h DWord.
> - D8XH(0,Arg0) // Output Sleep State to Port 80h, Byte 0.
> -
> - ADBG(Concatenate("_PTS=",ToHexString(Arg0)))
> -
> -
> - // If code is executed, Wake from RI# via Serial Modem will be
> - // enabled. If code is not executed, COM Port Debugging throughout
> - // all Sx states will be enabled.
> -
> - If(LEqual(Arg0,3))
> - {
> - //
> - // Disable update DTS temperature and threshold value in every SMI
> - //
> - If(CondRefOf(\_PR.DTSE)){
> - If(LAnd(\_PR.DTSE, LGreater(TCNT, 1)))
> - {
> - TRAP(TRAP_TYPE_DTS,30)
> - }
> - }
> - }
> -
> -
> - // Generate a SW SMI trap to save some NVRAM data back to CMOS.
> -
> - // Don't enable IGD OpRegion support yet.
> - // TRAP(1, 81)
> - //
> - // Call TPM.PTS
> - //
> - If(CondRefOf(\_SB.TPM.PTS))
> - {
> - //
> - // Call TPM PTS method
> - //
> - \_SB.TPM.PTS (Arg0)
> - }
> -
> -}
> -
> -// Wake. This hook is called when the OS is about to wake from a
> -// sleep state. The argument passed is the numeric value of the
> -// sleep state the system is waking from.
> -
> -Method(_WAK,1,Serialized)
> -{
> - D8XH(1,0xAB) // Beginning of _WAK.
> -
> - ADBG("_WAK")
> -
> - //
> - // Only set 8254 CG if Low Power S0 Idle Capability is enabled
> - //
> - If (LEqual(S0ID, One)) {
> - //
> - // Set ITSSPRC.8254CGE: Offset 3300h ITSSPRC[2]
> - //
> - Store(0x01, \_SB.SCGE)
> - }
> -
> - If(NEXP)
> - {
> - // Reinitialize the Native PCI Express after resume
> -
> - If(And(OSCC,0x02))
> - {
> - \_SB.PCI0.NHPG()
> - }
> - If(And(OSCC,0x04)) // PME control granted?
> - {
> - \_SB.PCI0.NPME()
> - }
> - }
> -
> -
> - If(LOr(LEqual(Arg0,3), LEqual(Arg0,4))) // If S3 or S4 Resume
> - {
> -
> - // Check to send Convertible/Dock state changes upon resume from Sx.
> - If(And(GBSX,0x40))
> - {
> - \_SB.PCI0.GFX0.IUEH(6)
> -
> - //
> - // Do the same thing for Virtul Button device.
> - // Toggle Bit3 of PB1E(Slate/Notebook status)
> - //
> - Xor(PB1E, 0x08, PB1E)
> -
> - }
> -
> - If(And(GBSX,0x80))
> - {
> - \_SB.PCI0.GFX0.IUEH(7)
> -
> - //
> - // Do the same thing for Virtul Button device.
> - // Toggle Bit4 of PB1E (Dock/Undock status)
> - //
> - Xor(PB1E, 0x10, PB1E)
> -
> - }
> -
> -
> - If(CondRefOf(\_PR.DTSE)){
> - If(LAnd(\_PR.DTSE, LGreater(TCNT, 1)))
> - {
> - TRAP(TRAP_TYPE_DTS, 20)
> - }
> - }
> -
> -
> - // For PCI Express Express Cards, it is possible a device was
> - // either inserted or removed during an Sx State. The problem
> - // is that no wake event will occur for a given warm insertion
> - // or removal, so the OS will not become aware of any change.
> - // To get around this, re-enumerate all Express Card slots.
> - //
> - // If the Root Port is enabled, it may be assumed to be hot-pluggable.
> -
> - If(LNotEqual(\_SB.PCI0.RP01.VDID,0xFFFFFFFF))
> - {
> - Notify (\_SB.PCI0.RP01,0)
> - }
> -
> - If(LNotEqual(\_SB.PCI0.RP02.VDID,0xFFFFFFFF))
> - {
> - Notify (\_SB.PCI0.RP02,0)
> - }
> -
> - If(LNotEqual(\_SB.PCI0.RP03.VDID,0xFFFFFFFF))
> - {
> - Notify (\_SB.PCI0.RP03,0)
> - }
> -
> - If(LNotEqual(\_SB.PCI0.RP04.VDID,0xFFFFFFFF))
> - {
> - Notify (\_SB.PCI0.RP04,0)
> - }
> -
> - If(LNotEqual(\_SB.PCI0.RP05.VDID,0xFFFFFFFF))
> - {
> - Notify (\_SB.PCI0.RP05,0)
> - }
> -
> - If(LNotEqual(\_SB.PCI0.RP06.VDID,0xFFFFFFFF))
> - {
> - Notify (\_SB.PCI0.RP06,0)
> - }
> -
> - If(LNotEqual(\_SB.PCI0.RP07.VDID,0xFFFFFFFF))
> - {
> - Notify (\_SB.PCI0.RP07,0)
> - }
> -
> - If(LNotEqual(\_SB.PCI0.RP08.VDID,0xFFFFFFFF))
> - {
> - Notify (\_SB.PCI0.RP08,0)
> - }
> -
> - If(LNotEqual(\_SB.PCI0.RP09.VDID,0xFFFFFFFF))
> - {
> - Notify (\_SB.PCI0.RP09,0)
> - }
> -
> - If(LNotEqual(\_SB.PCI0.RP10.VDID,0xFFFFFFFF))
> - {
> - Notify (\_SB.PCI0.RP10,0)
> - }
> -
> - If(LNotEqual(\_SB.PCI0.RP11.VDID,0xFFFFFFFF))
> - {
> - Notify (\_SB.PCI0.RP11,0)
> - }
> -
> - If(LNotEqual(\_SB.PCI0.RP12.VDID,0xFFFFFFFF))
> - {
> - Notify (\_SB.PCI0.RP12,0)
> - }
> -
> - If(LNotEqual(\_SB.PCI0.RP13.VDID,0xFFFFFFFF))
> - {
> - Notify (\_SB.PCI0.RP13,0)
> - }
> -
> - If(LNotEqual(\_SB.PCI0.RP14.VDID,0xFFFFFFFF))
> - {
> - Notify (\_SB.PCI0.RP14,0)
> - }
> -
> - If(LNotEqual(\_SB.PCI0.RP15.VDID,0xFFFFFFFF))
> - {
> - Notify (\_SB.PCI0.RP15,0)
> - }
> -
> - If(LNotEqual(\_SB.PCI0.RP16.VDID,0xFFFFFFFF))
> - {
> - Notify (\_SB.PCI0.RP16,0)
> - }
> -
> - If(LNotEqual(\_SB.PCI0.RP17.VDID,0xFFFFFFFF))
> - {
> - Notify (\_SB.PCI0.RP17,0)
> - }
> -
> - If(LNotEqual(\_SB.PCI0.RP18.VDID,0xFFFFFFFF))
> - {
> - Notify (\_SB.PCI0.RP18,0)
> - }
> -
> - If(LNotEqual(\_SB.PCI0.RP19.VDID,0xFFFFFFFF))
> - {
> - Notify (\_SB.PCI0.RP19,0)
> - }
> -
> - If(LNotEqual(\_SB.PCI0.RP20.VDID,0xFFFFFFFF))
> - {
> - Notify (\_SB.PCI0.RP20,0)
> - }
> - }
> -
> -
> - Return(Package(){0,0})
> -}
> -
> -// Get Buffer:
> -// This method will take a buffer passed into the method and
> -// create then return a smaller buffer based on the pointer
> -// and size parameters passed in.
> -//
> -// Arguments:
> -// Arg0: Pointer to start of new Buffer in passed in Buffer.
> -// Arg1: Size of Buffer to create.
> -// Arg2: Original Buffer
> -//
> -// Return Value:
> -// Newly created buffer.
> -
> -Method(GETB,3,Serialized)
> -{
> - Multiply(Arg0,8,Local0) // Convert Index.
> - Multiply(Arg1,8,Local1) // Convert Size.
> - CreateField(Arg2,Local0,Local1,TBF3) // Create Buffer.
> -
> - Return(TBF3) // Return Buffer.
> -}
> -
> -// Power Notification:
> -// Perform all needed OS notifications during a
> -// Power Switch.
> -//
> -// Arguments:
> -// None
> -//
> -// Return Value:
> -// None
> -
> -Method(PNOT,0,Serialized)
> -{
> - //
> - // If MP enabled and driver support is present, notify all
> - // processors.
> - //
> - If(LGreater(TCNT, 1))
> - {
> - If(And(\PC00,0x0008)){
> - Notify(\_PR.PR00,0x80) // Eval PR00 _PPC.
> - }
> - If(And(\PC01,0x0008)){
> - Notify(\_PR.PR01,0x80) // Eval PR01 _PPC.
> - }
> - If(And(\PC02,0x0008)){
> - Notify(\_PR.PR02,0x80) // Eval PR02 _PPC.
> - }
> - If(And(\PC03,0x0008)){
> - Notify(\_PR.PR03,0x80) // Eval PR03 _PPC.
> - }
> - If(And(\PC04,0x0008)){
> - Notify(\_PR.PR04,0x80) // Eval PR04 _PPC.
> - }
> - If(And(\PC05,0x0008)){
> - Notify(\_PR.PR05,0x80) // Eval PR05 _PPC.
> - }
> - If(And(\PC06,0x0008)){
> - Notify(\_PR.PR06,0x80) // Eval PR06 _PPC.
> - }
> - If(And(\PC07,0x0008)){
> - Notify(\_PR.PR07,0x80) // Eval PR07 _PPC.
> - }
> - If(And(\PC08,0x0008)){
> - Notify(\_PR.PR08,0x80) // Eval PR08 _PPC.
> - }
> - If(And(\PC09,0x0008)){
> - Notify(\_PR.PR09,0x80) // Eval PR09 _PPC.
> - }
> - If(And(\PC10,0x0008)){
> - Notify(\_PR.PR10,0x80) // Eval PR10 _PPC.
> - }
> - If(And(\PC11,0x0008)){
> - Notify(\_PR.PR11,0x80) // Eval PR11 _PPC.
> - }
> - If(And(\PC12,0x0008)){
> - Notify(\_PR.PR12,0x80) // Eval PR12 _PPC.
> - }
> - If(And(\PC13,0x0008)){
> - Notify(\_PR.PR13,0x80) // Eval PR13 _PPC.
> - }
> - If(And(\PC14,0x0008)){
> - Notify(\_PR.PR14,0x80) // Eval PR14 _PPC.
> - }
> - If(And(\PC15,0x0008)){
> - Notify(\_PR.PR15,0x80) // Eval PR15 _PPC.
> - }
> - }Else{
> - Notify(\_PR.PR00,0x80) // Eval _PPC.
> - }
> -
> - If(LGreater(TCNT, 1)){
> - If(LAnd(And(\PC00,0x0008),And(\PC00,0x0010))){
> - Notify(\_PR.PR00,0x81) // Eval PR00 _CST.
> - }
> - If(LAnd(And(\PC01,0x0008),And(\PC01,0x0010))){
> - Notify(\_PR.PR01,0x81) // Eval PR01 _CST.
> - }
> - If(LAnd(And(\PC02,0x0008),And(\PC02,0x0010))){
> - Notify(\_PR.PR02,0x81) // Eval PR02 _CST.
> - }
> - If(LAnd(And(\PC03,0x0008),And(\PC03,0x0010))){
> - Notify(\_PR.PR03,0x81) // Eval PR03 _CST.
> - }
> - If(LAnd(And(\PC04,0x0008),And(\PC04,0x0010))){
> - Notify(\_PR.PR04,0x81) // Eval PR04 _CST.
> - }
> - If(LAnd(And(\PC05,0x0008),And(\PC05,0x0010))){
> - Notify(\_PR.PR05,0x81) // Eval PR05 _CST.
> - }
> - If(LAnd(And(\PC06,0x0008),And(\PC06,0x0010))){
> - Notify(\_PR.PR06,0x81) // Eval PR06 _CST.
> - }
> - If(LAnd(And(\PC07,0x0008),And(\PC07,0x0010))){
> - Notify(\_PR.PR07,0x81) // Eval PR07 _CST.
> - }
> - If(LAnd(And(\PC08,0x0008),And(\PC08,0x0010))){
> - Notify(\_PR.PR08,0x81) // Eval PR08 _CST.
> - }
> - If(LAnd(And(\PC09,0x0008),And(\PC09,0x0010))){
> - Notify(\_PR.PR09,0x81) // Eval PR09 _CST.
> - }
> - If(LAnd(And(\PC10,0x0008),And(\PC10,0x0010))){
> - Notify(\_PR.PR10,0x81) // Eval PR10 _CST.
> - }
> - If(LAnd(And(\PC11,0x0008),And(\PC11,0x0010))){
> - Notify(\_PR.PR11,0x81) // Eval PR11 _CST.
> - }
> - If(LAnd(And(\PC12,0x0008),And(\PC12,0x0010))){
> - Notify(\_PR.PR12,0x81) // Eval PR12 _CST.
> - }
> - If(LAnd(And(\PC13,0x0008),And(\PC13,0x0010))){
> - Notify(\_PR.PR13,0x81) // Eval PR13 _CST.
> - }
> - If(LAnd(And(\PC14,0x0008),And(\PC14,0x0010))){
> - Notify(\_PR.PR14,0x81) // Eval PR14 _CST.
> - }
> - If(LAnd(And(\PC15,0x0008),And(\PC15,0x0010))){
> - Notify(\_PR.PR15,0x81) // Eval PR15 _CST.
> - }
> - } Else {
> - Notify(\_PR.PR00,0x81) // Eval _CST.
> - }
> -
> -
> -} // end of Method(PNOT)
> -
> -//
> -// Memory window to the CTDP registers starting at MCHBAR+5000h.
> -//
> - OperationRegion (MBAR, SystemMemory, Add(\_SB.PCI0.GMHB(),0x5000),
> 0x1000)
> - Field (MBAR, ByteAcc, NoLock, Preserve)
> - {
> - Offset (0x938), // PACKAGE_POWER_SKU_UNIT (MCHBAR+0x5938)
> - PWRU, 4, // Power Units [3:0] unit value is calculated by 1 W /
> Power(2,PWR_UNIT). The default value of 0011b corresponds to 1/8 W.
> - Offset (0x9A0), // TURBO_POWER_LIMIT1 (MCHBAR+0x59A0)
> - PPL1, 15, // PKG_PWR_LIM_1 [14:0]
> - PL1E,1, // PKG_PWR_LIM1_EN [15]
> - CLP1,1, // Package Clamping Limitation 1
> - }
> -Name(CLMP, 0) // save the clamp bit
> -Name(PLEN,0) // save the power limit enable bit
> -Name(PLSV,0x8000) // save value of PL1 upon entering CS
> -Name(CSEM, 0) //semaphore to avoid multiple calls to SPL1. SPL1/RPL1
> must always be called in pairs, like push/pop off a stack
> -//
> -// SPL1 (Set PL1 to 4.5 watts with clamp bit set)
> -// Per Legacy Thermal management CS requirements, we would like to
> set the PL1 limit when entering CS to 4.5W with clamp bit set via MMIO.
> -// This can be done in the ACPI object which gets called by graphics
> driver during CS Entry.
> -// Likewise, during CS exit, the BIOS must reset the PL1 value to the
> previous value prior to CS entry and reset the clamp bit.
> -//
> -// Arguments:
> -// None
> -//
> -// Return Value:
> -// None
> -Method(SPL1,0,Serialized)
> -{
> - Name(PPUU,0) // units
> - If (LEqual(CSEM, 1))
> - {
> - Return() // we have already been called, must have CS exit before
> calling again
> - }
> - Store(1, CSEM) // record first call
> -
> - Store (PPL1, PLSV) // save PL1 value upon entering CS
> - Store (PL1E, PLEN) // save PL1 Enable bit upon entering CS
> - Store (CLP1, CLMP) // save PL1 Clamp bit upon entering CS
> -
> - If (LEqual(PWRU,0)) { // use PACKAGE_POWER_SKU_UNIT - Power
> Units[3:0]
> - Store(1,PPUU)
> - } Else {
> - ShiftLeft(Decrement(PWRU),2,PPUU) // get units
> - }
> -
> - Multiply(PLVL,PPUU,Local0) // convert SETUP value to power units in
> milli-watts
> - Divide(Local0,1000,,Local1) // convert SETUP value to power units in
> watts
> - Store(Local1, PPL1) // copy value to PL1
> - Store(1, PL1E) // set Enable bit
> - Store(1, CLP1) // set Clamp bit
> -}
> -//
> -// RPL1 (Restore the PL1 register to the values prior to CS entry)
> -//
> -// Arguments:
> -// None
> -//
> -// Return Value:
> -// None
> -Method(RPL1,0,Serialized)
> -{
> - Store (PLSV, PPL1) // restore value of PL1 upon exiting CS
> - Store(PLEN, PL1E) // restore the PL1 enable bit
> - Store(CLMP, CLP1) // restore the PL1 Clamp bit
> - Store(0, CSEM) // restore semaphore
> -}
> -
> -Name(UAMS, 0) // User Absent Mode state, Zero - User Present; non-Zero -
> User not present
> -Name(GLCK, 0) // a spin lock to avoid multi execution of GUAM
> -// GUAM - Global User Absent Mode
> -// Run when a change to User Absent mode is made, e.g.
> screen/display on/off events.
> -// Any device that needs notifications of these events includes its own
> UAMN Control Method.
> -//
> -// Arguments:
> -// Power State:
> -// 00h = On
> -// 01h = Standby
> -// other value = do nothing & return
> -//
> -// Return Value:
> -// None
> -//
> -Method(GUAM,1,Serialized)
> -{
> - Switch(ToInteger(Arg0))
> - {
> - Case(0) // exit CS
> - {
> - If(LEqual(GLCK, 1)){
> - store(0, GLCK)
> -
> - P8XH(0, 0xE1)
> - P8XH(1, 0xAB)
> - ADBG("Exit Resiliency")
> -
> - // @Todo: Exit EC Low Power Mode here
> -
> -
> - If(PSCP){
> - // if P-state Capping s enabled
> - If (CondRefOf(\_PR.PR00._PPC))
> - {
> - Store(Zero, \_PR.CPPC)
> - PNOT()
> - }
> - }
> - If(PLCS){
> - RPL1() // restore PL1 to pre-CS value upon exiting CS
> - }
> - } // end GLCK=1
> - } // end case(0)
> -
> - Case(1) // enter CS
> - {
> - If(LEqual(GLCK, 0)){
> - store(1, GLCK)
> -
> - P8XH(0, 0xE0)
> - P8XH(1, 00)
> - ADBG("Enter Resiliency")
> -
> - //@Todo: Enter EC Low Power Mode here
> -
> -
> - If(PSCP){
> - // if P-state Capping is enabled
> - If (LAnd(CondRefOf(\_PR.PR00._PSS),
> CondRefOf(\_PR.PR00._PPC)))
> - {
> - If(And(\PC00,0x0400))
> - {
> - Subtract(SizeOf(\_PR.PR00.TPSS), One, \_PR.CPPC)
> - } Else {
> - Subtract(SizeOf(\_PR.PR00.LPSS), One, \_PR.CPPC)
> - }
> - PNOT()
> - }
> - }
> - If(PLCS){
> - SPL1() // set PL1 to low value upon CS entry
> - }
> - } // end GLCK=0
> - } // end case(1)
> - Default{
> - Return() // do nothing
> - }
> - } // end switch(arg0)
> -
> - Store(LAnd(Arg0, LNot(PWRS)), UAMS) // UAMS: User Absent Mode
> state, Zero - User Present; non-Zero - User not present
> - P_CS() // Powergating during CS
> -
> -} // end method GUAM()
> -
> -// Power CS Powergated Devices:
> -// Method to enable/disable power during CS
> -Method(P_CS,0,Serialized)
> -{
> - // NOTE: Do not turn ON Touch devices from here. Touch does not
> have PUAM
> - If(CondRefOf(\_SB.PCI0.PAUD.PUAM)){ // Notify
> Codec(HD-A/ADSP)
> - \_SB.PCI0.PAUD.PUAM()
> - }
> - // Adding back USB powergating (ONLY for Win8) until RTD3 walkup
> port setup implementation is complete */
> - If(LEqual(OSYS,2012)){ // ONLY for Win8 OS
> - If(CondRefOf(\_SB.PCI0.XHC.DUAM)){ // Notify USB port- RVP
> - \_SB.PCI0.XHC.DUAM()
> - }
> - }
> - // TODO: Add calls to UAMN methods for
> - // * USB controller(s)
> - // * Embedded Controller
> - // * Sensor devices
> - // * Audio DSP?
> - // * Any other devices dependent on User Absent mode for power
> controls
> -}
> -
> -// SMI I/O Trap:
> -// Generate a Mutex protected SMI I/O Trap.
> -//
> -// Arguments:
> -// Arg0: I/O Trap type.
> -// 2 - For DTS
> -// 3 - For IGD
> -// 4 - For BIOS Guard Tools
> -// Arg1: SMI I/O Trap Function to call.
> -//
> -// Return Value:
> -// SMI I/O Trap Return value.
> -// 0 = Success. Non-zero = Failure.
> -
> -Scope(\)
> -{
> - //
> - // The IO address in this ACPI Operating Region will be updated during
> POST.
> - // This address range is used as a HotKey I/O Trap SMI so that ASL and
> SMI can
> - // communicate when needed.
> - //
> - OperationRegion(IO_H,SystemIO,0x1000,0x4)
> - Field(IO_H,ByteAcc,NoLock,Preserve) {
> - TRPH, 8
> - }
> -}
> -
> -Method(TRAP,2,Serialized)
> -{
> - Store(Arg1,SMIF) // Store SMI Function.
> -
> - If(LEqual(Arg0,TRAP_TYPE_DTS)) // Is DTS IO Trap?
> - {
> - Store(Arg1,\_PR.DTSF) // Store the function number global NVS
> - Store(0,\_PR.TRPD) // Generate IO Trap.
> - Return(\_PR.DTSF) // Return status from SMI handler
> - }
> -
> - If(LEqual(Arg0,TRAP_TYPE_IGD)) // Is IGD IO Trap?
> - {
> - Store(0,TRPH) // Generate IO Trap.
> - }
> -
> - If(LEqual(Arg0,TRAP_TYPE_BGD)) // Is BIOS Guard TOOLS IO Trap?
> - {
> - Store(0,\_PR.TRPF) // Generate IO Trap
> - }
> -
> - Return(SMIF) // Return SMIF. 0 = Success.
> -}
> -
> -// Note: Only add the indicator device needed by the platform.
> -
> -//
> -// System Bus
> -//
> -Scope(\_SB.PCI0)
> -{
> -
> - Method(_INI,0, Serialized)
> - {
> -
> - // Determine the OS and store the value, where:
> - //
> - // OSYS = 1000 = Linux.
> - // OSYS = 2000 = WIN2000.
> - // OSYS = 2001 = WINXP, RTM or SP1.
> - // OSYS = 2002 = WINXP SP2.
> - // OSYS = 2006 = Vista.
> - // OSYS = 2009 = Windows 7 and Windows Server 2008 R2.
> - // OSYS = 2012 = Windows 8 and Windows Server 2012.
> - // OSYS = 2013 = Windows Blue.
> - //
> - // Assume Windows 2000 at a minimum.
> -
> - Store(2000,OSYS)
> -
> - // Check for a specific OS which supports _OSI.
> -
> - If(CondRefOf(\_OSI))
> - {
> - If(\_OSI("Linux"))
> - {
> - Store(1000,OSYS)
> - }
> -
> - If(\_OSI("Windows 2001")) // Windows XP
> - {
> - Store(2001,OSYS)
> - }
> -
> - If(\_OSI("Windows 2001 SP1")) //Windows XP SP1
> - {
> - Store(2001,OSYS)
> - }
> -
> - If(\_OSI("Windows 2001 SP2")) //Windows XP SP2
> - {
> - Store(2002,OSYS)
> - }
> -
> - If (\_OSI( "Windows 2001.1")) //Windows Server 2003
> - {
> - Store(2003,OSYS)
> - }
> -
> - If(\_OSI("Windows 2006")) //Windows Vista
> - {
> - Store(2006,OSYS)
> - }
> -
> - If(\_OSI("Windows 2009")) //Windows 7 and Windows Server 2008
> R2
> - {
> - Store(2009,OSYS)
> - }
> -
> - If(\_OSI("Windows 2012")) //Windows 8 and Windows Server 2012
> - {
> - Store(2012,OSYS)
> - }
> -
> - If(\_OSI("Windows 2013")) //Windows 8.1 and Windows Server 2012
> R2
> - {
> - Store(2013,OSYS)
> - }
> -
> - If(\_OSI("Windows 2015")) //Windows 10
> - {
> - Store(2015,OSYS)
> - }
> - }
> -
> - //
> - // Set DTS NVS data means in OS ACPI mode enabled insteads of
> GlobalNvs OperatingSystem (OSYS)
> - //
> - If(CondRefOf(\_PR.DTSE)){
> - If(LGreaterEqual(\_PR.DTSE, 0x01)){
> - Store(0x01, \_PR.DSAE)
> - }
> - }
> -
> - }
> -
> - Method(NHPG,0,Serialized)
> - {
> - Store(0,^RP01.HPEX) // clear the hot plug SCI enable bit
> - Store(0,^RP02.HPEX) // clear the hot plug SCI enable bit
> - Store(0,^RP03.HPEX) // clear the hot plug SCI enable bit
> - Store(0,^RP04.HPEX) // clear the hot plug SCI enable bit
> - Store(0,^RP05.HPEX) // clear the hot plug SCI enable bit
> - Store(0,^RP06.HPEX) // clear the hot plug SCI enable bit
> - Store(0,^RP07.HPEX) // clear the hot plug SCI enable bit
> - Store(0,^RP08.HPEX) // clear the hot plug SCI enable bit
> - Store(0,^RP09.HPEX) // clear the hot plug SCI enable bit
> - Store(0,^RP10.HPEX) // clear the hot plug SCI enable bit
> - Store(0,^RP11.HPEX) // clear the hot plug SCI enable bit
> - Store(0,^RP12.HPEX) // clear the hot plug SCI enable bit
> - Store(0,^RP13.HPEX) // clear the hot plug SCI enable bit
> - Store(0,^RP14.HPEX) // clear the hot plug SCI enable bit
> - Store(0,^RP15.HPEX) // clear the hot plug SCI enable bit
> - Store(0,^RP16.HPEX) // clear the hot plug SCI enable bit
> - Store(0,^RP17.HPEX) // clear the hot plug SCI enable bit
> - Store(0,^RP18.HPEX) // clear the hot plug SCI enable bit
> - Store(0,^RP19.HPEX) // clear the hot plug SCI enable bit
> - Store(0,^RP20.HPEX) // clear the hot plug SCI enable bit
> -
> - Store(1,^RP01.HPSX) // clear the hot plug SCI status bit
> - Store(1,^RP02.HPSX) // clear the hot plug SCI status bit
> - Store(1,^RP03.HPSX) // clear the hot plug SCI status bit
> - Store(1,^RP04.HPSX) // clear the hot plug SCI status bit
> - Store(1,^RP05.HPSX) // clear the hot plug SCI status bit
> - Store(1,^RP06.HPSX) // clear the hot plug SCI status bit
> - Store(1,^RP07.HPSX) // clear the hot plug SCI status bit
> - Store(1,^RP08.HPSX) // clear the hot plug SCI status bit
> - Store(1,^RP09.HPSX) // clear the hot plug SCI status bit
> - Store(1,^RP10.HPSX) // clear the hot plug SCI status bit
> - Store(1,^RP11.HPSX) // clear the hot plug SCI status bit
> - Store(1,^RP12.HPSX) // clear the hot plug SCI status bit
> - Store(1,^RP13.HPSX) // clear the hot plug SCI status bit
> - Store(1,^RP14.HPSX) // clear the hot plug SCI status bit
> - Store(1,^RP15.HPSX) // clear the hot plug SCI status bit
> - Store(1,^RP16.HPSX) // clear the hot plug SCI status bit
> - Store(1,^RP17.HPSX) // clear the hot plug SCI status bit
> - Store(1,^RP18.HPSX) // clear the hot plug SCI status bit
> - Store(1,^RP19.HPSX) // clear the hot plug SCI status bit
> - Store(1,^RP20.HPSX) // clear the hot plug SCI status bit
> - }
> -
> - Method(NPME,0,Serialized)
> - {
> - Store(0,^RP01.PMEX) // clear the PME SCI enable bit
> - Store(0,^RP02.PMEX) // clear the PME SCI enable bit
> - Store(0,^RP03.PMEX) // clear the PME SCI enable bit
> - Store(0,^RP04.PMEX) // clear the PME SCI enable bit
> - Store(0,^RP05.PMEX) // clear the PME SCI enable bit
> - Store(0,^RP06.PMEX) // clear the PME SCI enable bit
> - Store(0,^RP07.PMEX) // clear the PME SCI enable bit
> - Store(0,^RP08.PMEX) // clear the PME SCI enable bit
> - Store(0,^RP09.PMEX) // clear the PME SCI enable bit
> - Store(0,^RP10.PMEX) // clear the PME SCI enable bit
> - Store(0,^RP11.PMEX) // clear the PME SCI enable bit
> - Store(0,^RP12.PMEX) // clear the PME SCI enable bit
> - Store(0,^RP13.PMEX) // clear the PME SCI enable bit
> - Store(0,^RP14.PMEX) // clear the PME SCI enable bit
> - Store(0,^RP15.PMEX) // clear the PME SCI enable bit
> - Store(0,^RP16.PMEX) // clear the PME SCI enable bit
> - Store(0,^RP17.PMEX) // clear the PME SCI enable bit
> - Store(0,^RP18.PMEX) // clear the PME SCI enable bit
> - Store(0,^RP19.PMEX) // clear the PME SCI enable bit
> - Store(0,^RP20.PMEX) // clear the PME SCI enable bit
> -
> - Store(1,^RP01.PMSX) // clear the PME SCI status bit
> - Store(1,^RP02.PMSX) // clear the PME SCI status bit
> - Store(1,^RP03.PMSX) // clear the PME SCI status bit
> - Store(1,^RP04.PMSX) // clear the PME SCI status bit
> - Store(1,^RP05.PMSX) // clear the PME SCI status bit
> - Store(1,^RP06.PMSX) // clear the PME SCI enable bit
> - Store(1,^RP07.PMSX) // clear the PME SCI status bit
> - Store(1,^RP08.PMSX) // clear the PME SCI status bit
> - Store(1,^RP09.PMSX) // clear the PME SCI status bit
> - Store(1,^RP10.PMSX) // clear the PME SCI status bit
> - Store(1,^RP11.PMSX) // clear the PME SCI status bit
> - Store(1,^RP12.PMSX) // clear the PME SCI status bit
> - Store(1,^RP13.PMSX) // clear the PME SCI status bit
> - Store(1,^RP14.PMSX) // clear the PME SCI status bit
> - Store(1,^RP15.PMSX) // clear the PME SCI status bit
> - Store(1,^RP16.PMSX) // clear the PME SCI status bit
> - Store(1,^RP17.PMSX) // clear the PME SCI status bit
> - Store(1,^RP18.PMSX) // clear the PME SCI status bit
> - Store(1,^RP19.PMSX) // clear the PME SCI status bit
> - Store(1,^RP20.PMSX) // clear the PME SCI status bit
> - }
> -}
> -
> -Scope (\)
> -{
> - //
> - // Global Name, returns current Interrupt controller mode;
> - // updated from _PIC control method
> - //
> - Name(PICM, 0)
> -
> - //
> - // Procedure: GPRW
> - //
> - // Description: Generic Wake up Control Method ("Big brother")
> - // to detect the Max Sleep State available in ASL Name
> scope
> - // and Return the Package compatible with _PRW format.
> - // Input: Arg0 = bit offset within GPE register space device event will be
> triggered to.
> - // Arg1 = Max Sleep state, device can resume the System from.
> - // If Arg1 = 0, Update Arg1 with Max _Sx state enabled
> in the System.
> - // Output: _PRW package
> - //
> - Name(PRWP, Package(){Zero, Zero}) // _PRW Package
> -
> - Method(GPRW, 2)
> - {
> - Store(Arg0, Index(PRWP, 0)) // copy GPE#
> - //
> - // SS1-SS4 - enabled in BIOS Setup Sleep states
> - //
> - Store(ShiftLeft(SS1,1),Local0) // S1 ?
> - Or(Local0,ShiftLeft(SS2,2),Local0) // S2 ?
> - Or(Local0,ShiftLeft(SS3,3),Local0) // S3 ?
> - Or(Local0,ShiftLeft(SS4,4),Local0) // S4 ?
> - //
> - // Local0 has a bit mask of enabled Sx(1 based)
> - // bit mask of enabled in BIOS Setup Sleep states(1 based)
> - //
> - If(And(ShiftLeft(1, Arg1), Local0))
> - {
> - //
> - // Requested wake up value (Arg1) is present in Sx list of available
> Sleep states
> - //
> - Store(Arg1, Index(PRWP, 1)) // copy Sx#
> - }
> - Else
> - {
> - //
> - // Not available -> match Wake up value to the higher Sx state
> - //
> - ShiftRight(Local0, 1, Local0)
> - // If(LOr(LEqual(OSFL, 1), LEqual(OSFL, 2))) { // ??? Win9x
> - // FindSetLeftBit(Local0, Index(PRWP,1)) // Arg1 == Max Sx
> - // } Else { // ??? Win2k / XP
> - FindSetLeftBit(Local0, Index(PRWP,1)) // Arg1 == Min Sx
> - // }
> - }
> -
> - Return(PRWP)
> - }
> -}
> -
> -
> -Scope (\_SB)
> -{
> - Name(OSCI, 0) // \_SB._OSC DWORD2 input
> - Name(OSCO, 0) // \_SB._OSC DWORD2 output
> - Name(OSCP, 0) // \_SB._OSC CAPABILITIES
> - // _OSC (Operating System Capabilities)
> - // _OSC under \_SB scope is used to convey platform wide OSPM
> capabilities.
> - // For a complete description of _OSC ACPI Control Method, refer to
> ACPI 5.0
> - // specification, section 6.2.10.
> - // Arguments: (4)
> - // Arg0 - A Buffer containing the UUID
> "0811B06E-4A27-44F9-8D60-3CBBC22E7B48"
> - // Arg1 - An Integer containing the Revision ID of the buffer format
> - // Arg2 - An Integer containing a count of entries in Arg3
> - // Arg3 - A Buffer containing a list of DWORD capabilities
> - // Return Value:
> - // A Buffer containing the list of capabilities
> - //
> - Method(_OSC,4,Serialized)
> - {
> - //
> - // Point to Status DWORD in the Arg3 buffer (STATUS)
> - //
> - CreateDWordField(Arg3, 0, STS0)
> - //
> - // Point to Caps DWORDs of the Arg3 buffer (CAPABILITIES)
> - //
> - CreateDwordField(Arg3, 4, CAP0)
> -
> -
> - //
> - // Only set 8254 CG if Low Power S0 Idle Capability is enabled
> - //
> - If (LEqual(S0ID, One)) {
> - //
> - // Set ITSSPRC.8254CGE: Offset 3300h ITSSPRC[2]
> - //
> - Store(0x01, \_SB.SCGE)
> - }
> -
> - //
> - // Check UUID
> - //
> - If(LEqual(Arg0,ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48")))
> - {
> - //
> - // Check Revision
> - //
> - If(LEqual(Arg1,One))
> - {
> - Store(CAP0, OSCP)
> - If(And(CAP0,0x04)) // Check _PR3 Support(BIT2)
> - {
> - Store(0x04, OSCO)
> - If(LNotEqual(And(SGMD,0x0F),2)) // Check Switchable/Hybrid
> graphics is not enabled in bios setup [SgModeMuxless]?
> - {
> - If(LEqual(RTD3,0)) // Is RTD3 support disabled in Bios Setup?
> - {
> - // RTD3 is disabled via BIOS Setup.
> - And(CAP0, 0x3B, CAP0) // Clear _PR3 capability
> - Or(STS0, 0x10, STS0) // Indicate capability bit is cleared
> - }
> - }
> - }
> - } Else{
> - And(STS0,0xFFFFFF00,STS0)
> - Or(STS0,0xA, STS0) // Unrecognised Revision and report OSC
> failure
> - }
> - } Else {
> - And(STS0,0xFFFFFF00,STS0)
> - Or (STS0,0x6, STS0) // Unrecognised UUID and report OSC failure
> - }
> -
> - Return(Arg3)
> - } // End _OSC
> -
> -} // End of Scope(\_SB)
> -
> -//
> -// CS Wake up event support
> -//
> -Scope (\_SB)
> -{
> - // Define Sleep button to put the system in sleep
> - Device (SLPB)
> - {
> - Name (_HID, EISAID ("PNP0C0E"))
> - Name (_STA, 0x0B)
> - // Bit0 - the device is present: Yes.
> - // Bit1 - the device is enabled and decoding its resources: Yes.
> - // Bit2 - the device should be shown in the UI: No.
> - // Bit3 - the device is functioning properly: Yes.
> - // Bit4 - the battery is present: N/A
> - }
> -} // End of Scope(\_SB)
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGnv
> s.asl
> b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGnv
> s.asl
> deleted file mode 100644
> index 788a8ec491..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGnv
> s.asl
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -/** @file
> - ACPI DSDT table
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Video.asl
> b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Video.asl
> deleted file mode 100644
> index b15b754fb0..0000000000
> --- a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Video.asl
> +++ /dev/null
> @@ -1,27 +0,0 @@
> -/** @file
> - ACPI DSDT table
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -External(DIDX)
> -
> -// Brightness Notification:
> -// Generate a brightness related notification
> -// to the LFP if its populated.
> -//
> -// Arguments:
> -// Arg0: Notification value.
> -//
> -// Return Value:
> -// None
> -
> -Method(BRTN,1,Serialized)
> -{
> - If(LEqual(And(DIDX,0x0F00),0x400))
> - {
> - Notify(\_SB.PCI0.GFX0.DD1F,Arg0)
> - }
> -}
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/AcpiTables/Rtd3SptPcieT
> bt.asl
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/AcpiTables/Rtd3SptPcieT
> bt.asl
> deleted file mode 100644
> index c082988fa9..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/AcpiTables/Rtd3SptPcieT
> bt.asl
> +++ /dev/null
> @@ -1,403 +0,0 @@
> -/** @file
> - ACPI RTD3 SSDT table for SPT PCIe
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -#define PID_ICC 0xDC
> -#define R_PCH_PCR_ICC_MSKCKRQ 0x100C
> ///< Mask Control CLKREQ
> -
> -External(PCRA,MethodObj)
> -External(PCRO,MethodObj)
> -External(\MMRP, MethodObj)
> -External(\MMTB, MethodObj)
> -External(\TRDO, IntObj)
> -External(\TRD3, IntObj)
> -External(\TBPE, IntObj)
> -External(\TOFF, IntObj)
> -External(\TBSE, IntObj)
> -External(\TBOD, IntObj)
> -External(\TBRP, IntObj)
> -External(\TBHR, IntObj)
> -External(\RTBC, IntObj)
> -External(\TBCD, IntObj)
> -
> -Name(G2SD, 0) // Go2Sx done, set by GO2S, cleaned by _ON
> -
> -Name(WKEN, 0)
> -
> - Method(_S0W, 0)
> - {
> - /// This method returns the lowest D-state supported by PCIe root port
> during S0 state
> -
> - ///- PMEs can be generated from D3hot for ULT
> - Return(4)
> -
> - /** @defgroup pcie_s0W PCIE _S0W **/
> - } // End _S0W
> -
> - Method (_DSD, 0) {
> - Return (
> - Package () {
> - ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"),
> - Package () {
> - Package (2) {"HotPlugSupportInD3", 1},
> - }
> - }
> - ) // End of Return ()
> - }
> -
> - Method(_DSW, 3)
> - {
> - /// This method is used to enable/disable wake from PCIe (WKEN)
> - If (LGreaterEqual(Arg1, 1)) { /// If entering Sx, need to disable WAKE#
> from generating runtime PME
> - /// Also set 2 to TOFF.
> - Store(0, WKEN)
> - Store (2, TOFF)
> - } Else { /// If Staying in S0
> - If(LAnd(Arg0, Arg2)) ///- Check if Exiting D0 and arming for wake
> - { ///- Set PME
> - Store(1, WKEN)
> - Store (1, TOFF)
> - } Else { ///- Disable runtime PME, either because staying in D0 or
> disabling wake
> - Store(0, WKEN)
> - Store(0, TOFF)
> - }
> - }
> -
> - /** @defgroup pcie_dsw PCIE _DSW **/
> - } // End _DSW
> -
> -
> - PowerResource(PXP, 0, 0)
> - {
> - /// Define the PowerResource for PCIe slot
> - /// Method: _STA(), _ON(), _OFF()
> - /** @defgroup pcie_pxp PCIE Power Resource **/
> -
> - Method(_STA, 0)
> - {
> - Return(PSTA())
> - } /** @defgroup pcie_sta PCIE _STA method **/
> -
> - Method(_ON) /// Turn on core power to PCIe Slot
> - {
> - Store(1, TRDO)
> - PON()
> - Store(0, TRDO)
> - } /** @defgroup pcie_on PCIE _ON method **/
> -
> - Method(_OFF) /// Turn off core power to PCIe Slot
> - {
> - Store(1, TRD3)
> - POFF()
> - Store(0, TRD3)
> - } // End of Method_OFF
> - } // End PXP
> -
> - Method(PSTA, 0)
> - {
> - /// Returns the status of PCIe slot core power
> - // detect power pin status
> - if(LNotEqual(DeRefOf(Index(PWRG, 0)),0)) {
> - if(LEqual(DeRefOf(Index(PWRG, 0)),1)) { // GPIO mode
> - if(LEqual(\_SB.GGOV(DeRefOf(Index(PWRG,
> 2))),DeRefOf(Index(PWRG, 3)))){
> - Return (1)
> - } Else {
> - Return (0)
> - }
> - } // GPIO mode
> - if(LEqual(DeRefOf(Index(PWRG, 0)),2)) { // IOEX mode
> - if(LEqual(\_SB.PCI0.GEXP.GEPS(DeRefOf(Index(PWRG,
> 1)),DeRefOf(Index(PWRG, 2))),DeRefOf(Index(PWRG, 3)))){
> - Return (1)
> - } Else {
> - Return (0)
> - }
> - } // IOEX mode
> - }
> - // detect reset pin status
> - if(LNotEqual(DeRefOf(Index(RSTG, 0)),0)) {
> - if(LEqual(DeRefOf(Index(RSTG, 0)),1)) { // GPIO mode
> - if(LEqual(\_SB.GGOV(DeRefOf(Index(RSTG,
> 2))),DeRefOf(Index(RSTG, 3)))){
> - Return (1)
> - } Else {
> - Return (0)
> - }
> - } // GPIO mode
> - if(LEqual(DeRefOf(Index(RSTG, 0)),2)) { // IOEX mode
> - if(LEqual(\_SB.PCI0.GEXP.GEPS(DeRefOf(Index(RSTG,
> 1)),DeRefOf(Index(RSTG, 2))),DeRefOf(Index(RSTG, 3)))){
> - Return (1)
> - } Else {
> - Return (0)
> - }
> - } // IOEX mode
> - }
> - Return (0)
> - } /** @defgroup pcie_sta PCIE _STA method **/
> -
> - Method (SXEX, 0, Serialized) {
> -
> - Store(\MMTB(TBSE), Local7)
> - OperationRegion(TBDI, SystemMemory, Local7, 0x550)// TBT HR
> PCICFG MMIO
> - Field(TBDI,DWordAcc, NoLock, Preserve) {
> - DIVI, 32,
> - CMDR, 32,
> - Offset(0x548),
> - TB2P, 32,
> - P2TB, 32
> - }
> -
> - Store(100, Local1)
> - Store(0x09, P2TB) // Write SX_EXIT_TBT_CONNECTED to PCIe2TBT
> - While (LGreater(Local1, 0)) {
> -
> - Store(Subtract(Local1, 1), Local1)
> - Store(TB2P, Local2)
> - If (LEqual(Local2, 0xFFFFFFFF)) { // Device gone
> - Return()
> - }
> - If (And(Local2, 1)) { // Done
> - break
> - }
> - Sleep(5)
> - }
> - Store(0x0, P2TB) // Write 0 to PCIe2TBT
> -
> - // Fast Link bring-up flow
> - Store(500, Local1)
> - While (LGreater(Local1, 0)) {
> - Store(Subtract(Local1, 1), Local1)
> - Store(TB2P, Local2)
> - If (LEqual(Local2, 0xFFFFFFFF)) {// Device gone
> - Return()
> - }
> - If (LNotEqual(DIVI, 0xFFFFFFFF)) {
> - break
> - }
> - Sleep(10)
> - }
> - } // End of Method(SXEX, 0, Serialized)
> -
> - Method(PON) /// Turn on core power to PCIe Slot
> - {
> -
> - Store(\MMRP(\TBSE), Local7)
> - OperationRegion(L23P,SystemMemory,Local7,0xE4)
> - Field(L23P,WordAcc, NoLock, Preserve)
> - {
> - Offset(0xA4),// PMCSR
> - PSD0, 2, // PowerState
> - Offset(0xE2),// 0xE2, RPPGEN - Root Port Power Gating Enable
> - , 2,
> - L2TE, 1, // 2, L23_Rdy Entry Request (L23ER)
> - L2TR, 1, // 3, L23_Rdy to Detect Transition (L23R2DT)
> - }
> -
> - Store(\MMTB(\TBSE), Local6)
> - OperationRegion(TBDI, SystemMemory, Local6, 0x550)// TBT HR
> PCICFG MMIO
> - Field(TBDI,DWordAcc, NoLock, Preserve) {
> - DIVI, 32,
> - CMDR, 32,
> - Offset(0xA4),
> - TBPS, 2, // PowerState of TBT
> - Offset(0x548),
> - TB2P, 32,
> - P2TB, 32
> - }
> -
> - Store(0, TOFF)
> - // Check RTD3 power enable, if already ON, no need to execute
> sx_exit
> - If (TBPE) {
> - Return()
> - }
> -
> - Store(0,G2SD)
> - If (\RTBC) {
> - /// de-assert CLK_REQ MSK
> - if(LNotEqual(DeRefOf(Index(SCLK, 0)),0)) { // if power gating
> enabled
> -
> PCRA(PID_ICC,R_PCH_PCR_ICC_MSKCKRQ,Not(DeRefOf(Index(SCLK, 1)))) //
> And ~SCLK to clear bit
> - }
> - Sleep(\TBCD)
> - }
> -
> - /// Turn ON Power for PCIe Slot
> - if(LNotEqual(DeRefOf(Index(PWRG, 0)),0)) { // if power gating
> enabled
> - if(LEqual(DeRefOf(Index(PWRG, 0)),1)) { // GPIO mode
> - \_SB.SGOV(DeRefOf(Index(PWRG, 2)),DeRefOf(Index(PWRG, 3)))
> - Store(1, TBPE)
> - Sleep(PEP0) /// Sleep for programmable delay
> - }
> - if(LEqual(DeRefOf(Index(PWRG, 0)),2)) { // IOEX mode
> - \_SB.PCI0.GEXP.SGEP(DeRefOf(Index(PWRG,
> 1)),DeRefOf(Index(PWRG, 2)),DeRefOf(Index(PWRG, 3)))
> - Store(1, TBPE)
> - Sleep(PEP0) /// Sleep for programmable delay
> - }
> - }
> -
> - /// De-Assert Reset Pin
> - if(LNotEqual(DeRefOf(Index(RSTG, 0)),0)) { // if reset pin enabled
> - if(LEqual(DeRefOf(Index(RSTG, 0)),1)) { // GPIO mode
> - \_SB.SGOV(DeRefOf(Index(RSTG, 2)),DeRefOf(Index(RSTG, 3)))
> - }
> - if(LEqual(DeRefOf(Index(RSTG, 0)),2)) { // IOEX mode
> - \_SB.PCI0.GEXP.SGEP(DeRefOf(Index(RSTG,
> 1)),DeRefOf(Index(RSTG, 2)),DeRefOf(Index(RSTG, 3)))
> - }
> - }
> -
> - /// Clear DLSULPPGE, then set L23_Rdy to Detect Transition
> (L23R2DT)
> - Store(0, DPGE)
> - Store(1, L2TR)
> - Sleep(16)
> - Store(0, Local0)
> - /// Wait up to 12 ms for transition to Detect
> - While(L2TR) {
> - If(Lgreater(Local0, 4)) // Debug - Wait for 5 ms
> - {
> - Break
> - }
> - Sleep(16)
> - Increment(Local0)
> - }
> - /// Once in Detect, wait up to 124 ms for Link Active (typically
> happens in under 70ms)
> - /// Worst case per PCIe spec from Detect to Link Active is:
> - /// 24ms in Detect (12+12), 72ms in Polling (24+48), 28ms in Config
> (24+2+2+2+2)
> - Store(1, DPGE)
> - Store(0, Local0)
> - While(LEqual(LASX,0)) {
> - If(Lgreater(Local0, 8))
> - {
> - Break
> - }
> - Sleep(16)
> - Increment(Local0)
> - }
> - Store(0, LEDM) /// Set PCIEDBG.DMIL1EDM (324[3]) = 0
> -
> - // TBT special sleep.
> - Store(PSD0, Local1)
> - Store(0, PSD0)// D0
> - Store(20, Local2) // Poll for TBT, up to 200 ms
> -
> - While (LGreater(Local2, 0)) {
> - Store(Subtract(Local2, 1), Local2)
> - Store(TB2P, Local3)
> - If (LNotEqual(Local3, 0xFFFFFFFF)) { // Done
> - break
> - }
> - Sleep(10)
> - }
> -
> - If (LLessEqual(Local2, 0)) {
> - }
> - SXEX()
> - Store(Local1, PSD0) // Back to Local1
> - } /** @defgroup pcie_on PCIE _ON method **/
> -
> - Method(POFF) { /// Turn off core power to PCIe Slot
> - If (LEqual(TOFF, 0)) {
> - Return()
> - }
> - Store(\MMRP(\TBSE), Local7)
> - OperationRegion(L23P, SystemMemory, Local7, 0xE4)
> - Field(L23P,WordAcc, NoLock, Preserve)
> - {
> - Offset(0xA4),// PMCSR
> - PSD0, 2, // PowerState
> - Offset(0xE2),// 0xE2, RPPGEN - Root Port Power Gating Enable
> - , 2,
> - L2TE, 1, // 2, L23_Rdy Entry Request (L23ER)
> - L2TR, 1, // 3, L23_Rdy to Detect Transition (L23R2DT)
> - }
> -
> - Store(\MMTB(TBSE), Local6)
> - OperationRegion(TBDI, SystemMemory, Local6, 0x550)// TBT HR
> PCICFG MMIO
> - Field(TBDI,DWordAcc, NoLock, Preserve) {
> - DIVI, 32,
> - CMDR, 32,
> - Offset(0xA4),
> - TBPS, 2, // PowerState of TBT
> - Offset(0x548),
> - TB2P, 32,
> - P2TB, 32
> - }
> -
> - Store(PSD0, Local1)
> - Store(0, PSD0)// D0
> -
> - Store(P2TB, Local3)
> -
> - If (Lgreater(TOFF, 1)) {
> - Sleep(10)
> - Store(Local1, PSD0) // Back to Local1
> - Return()
> - }
> - Store(0, TOFF)
> -
> - Store(Local1, PSD0) // Back to Local1
> -
> - /// Set L23_Rdy Entry Request (L23ER)
> - Store(1, L2TE)
> - Sleep(16)
> - Store(0, Local0)
> - While(L2TE) {
> - If(Lgreater(Local0, 4)) /// Debug - Wait for 5 ms
> - {
> - Break
> - }
> - Sleep(16)
> - Increment(Local0)
> - }
> - Store(1, LEDM) /// PCIEDBG.DMIL1EDM (324[3]) = 1
> -
> - /// Assert Reset Pin
> - if(LNotEqual(DeRefOf(Index(RSTG, 0)),0)) { // if reset pin enabled
> - if(LEqual(DeRefOf(Index(RSTG, 0)),1)) { // GPIO mode
> - \_SB.SGOV(DeRefOf(Index(RSTG, 2)),Xor(DeRefOf(Index(RSTG,
> 3)),1))
> - }
> - if(LEqual(DeRefOf(Index(RSTG, 0)),2)) { // IOEX mode
> - \_SB.PCI0.GEXP.SGEP(DeRefOf(Index(RSTG,
> 1)),DeRefOf(Index(RSTG, 2)),Xor(DeRefOf(Index(RSTG, 3)),1))
> - }
> - }
> - If (\RTBC) {
> - /// assert CLK_REQ MSK
> - if(LNotEqual(DeRefOf(Index(SCLK, 0)),0)) { // if power gating
> enabled
> - PCRO(PID_ICC,R_PCH_PCR_ICC_MSKCKRQ,DeRefOf(Index(SCLK,
> 1))) // Or SCLK to set bit
> - Sleep(16)
> - }
> - }
> -
> - /// Power OFF for TBT
> - if(LNotEqual(DeRefOf(Index(PWRG, 0)),0)) { // if power gating
> enabled
> - if(LEqual(DeRefOf(Index(PWRG, 0)),1)) { // GPIO mode
> - \_SB.SGOV(DeRefOf(Index(PWRG, 2)),Xor(DeRefOf(Index(PWRG,
> 3)),1))
> - }
> - if(LEqual(DeRefOf(Index(PWRG, 0)),2)) { // IOEX mode
> - \_SB.PCI0.GEXP.SGEP(DeRefOf(Index(PWRG,
> 1)),DeRefOf(Index(PWRG, 2)),Xor(DeRefOf(Index(PWRG, 3)),1))
> - }
> - }
> -
> - Store(0, TBPE)
> -
> - Store(1, LDIS) /// Set Link Disable
> - Store(0, LDIS) /// Toggle link disable
> -
> - /// enable WAKE
> - If (WKEN) {
> - If (LNotEqual(DeRefOf(Index(WAKG, 0)),0)) { // if power gating
> enabled
> - If (LEqual(DeRefOf(Index(WAKG, 0)),1)) { // GPIO mode
> - \_SB.SGOV(DeRefOf(Index(WAKG, 2)),DeRefOf(Index(WAKG,
> 3)))
> - \_SB.SHPO(DeRefOf(Index(WAKG, 2)), 0) // set gpio ownership
> to ACPI(0=ACPI mode, 1=GPIO mode)
> - }
> - If (LEqual(DeRefOf(Index(WAKG, 0)),2)) { // IOEX mode
> - \_SB.PCI0.GEXP.SGEP(DeRefOf(Index(WAKG,
> 1)),DeRefOf(Index(WAKG, 2)),DeRefOf(Index(WAKG, 3)))
> - }
> - }
> - }
> - Sleep(\TBOD)
> - /** @defgroup pcie_off PCIE _OFF method **/
> - } // End of Method_OFF
> -
> - Name(_PR0, Package(){PXP})
> - Name(_PR3, Package(){PXP})
> -
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/AcpiTables/Tbt.asl
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/AcpiTables/Tbt.asl
> deleted file mode 100644
> index 2efe1a54f3..0000000000
> --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/AcpiTables/Tbt.asl
> +++ /dev/null
> @@ -1,1894 +0,0 @@
> -/** @file
> - Thunderbolt ACPI methods
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -#define DTBT_CONTROLLER 0x00
> -#define DTBT_TYPE_PCH 0x01
> -#define DTBT_TYPE_PEG 0x02
> -#define DTBT_SMI_HANDLER_NUMBER 0xF7
> -#define TBT_SMI_ENUMERATION_FUNCTION 21
> -#define TBT_SMI_RESET_SWITCH_FUNCTION 22
> -#define TBT_SMI_DISABLE_MSI_FUNCTION 23
> -#ifndef BIT29
> -#define BIT29 0x20000000
> -#endif
> -
> -Name(LDLY, 300) //300 ms
> -Name (TNVB, 0xFFFF0000) // TBT NVS Base address
> -Name (TNVL, 0xAA55) // TBT NVS Length
> -Include ("Acpi/TbtNvs.asl")
> -
> -External(\_SB.PCI0.RP02.L23D, MethodObj)
> -External(\_SB.PCI0.RP03.L23D, MethodObj)
> -External(\_SB.PCI0.RP04.L23D, MethodObj)
> -External(\_SB.PCI0.RP05.L23D, MethodObj)
> -External(\_SB.PCI0.RP06.L23D, MethodObj)
> -External(\_SB.PCI0.RP07.L23D, MethodObj)
> -External(\_SB.PCI0.RP08.L23D, MethodObj)
> -External(\_SB.PCI0.RP09.L23D, MethodObj)
> -External(\_SB.PCI0.RP10.L23D, MethodObj)
> -External(\_SB.PCI0.RP11.L23D, MethodObj)
> -External(\_SB.PCI0.RP12.L23D, MethodObj)
> -External(\_SB.PCI0.RP13.L23D, MethodObj)
> -External(\_SB.PCI0.RP14.L23D, MethodObj)
> -External(\_SB.PCI0.RP15.L23D, MethodObj)
> -External(\_SB.PCI0.RP16.L23D, MethodObj)
> -External(\_SB.PCI0.RP17.L23D, MethodObj)
> -External(\_SB.PCI0.RP18.L23D, MethodObj)
> -External(\_SB.PCI0.RP19.L23D, MethodObj)
> -External(\_SB.PCI0.RP20.L23D, MethodObj)
> -External(\_SB.PCI0.RP21.L23D, MethodObj)
> -External(\_SB.PCI0.RP22.L23D, MethodObj)
> -External(\_SB.PCI0.RP23.L23D, MethodObj)
> -External(\_SB.PCI0.RP24.L23D, MethodObj)
> -
> -External(\_SB.PCI0.RP01.DL23, MethodObj)
> -External(\_SB.PCI0.RP02.DL23, MethodObj)
> -External(\_SB.PCI0.RP03.DL23, MethodObj)
> -External(\_SB.PCI0.RP04.DL23, MethodObj)
> -External(\_SB.PCI0.RP05.DL23, MethodObj)
> -External(\_SB.PCI0.RP06.DL23, MethodObj)
> -External(\_SB.PCI0.RP07.DL23, MethodObj)
> -External(\_SB.PCI0.RP08.DL23, MethodObj)
> -External(\_SB.PCI0.RP09.DL23, MethodObj)
> -External(\_SB.PCI0.RP10.DL23, MethodObj)
> -External(\_SB.PCI0.RP11.DL23, MethodObj)
> -External(\_SB.PCI0.RP12.DL23, MethodObj)
> -External(\_SB.PCI0.RP13.DL23, MethodObj)
> -External(\_SB.PCI0.RP14.DL23, MethodObj)
> -External(\_SB.PCI0.RP15.DL23, MethodObj)
> -External(\_SB.PCI0.RP16.DL23, MethodObj)
> -External(\_SB.PCI0.RP17.DL23, MethodObj)
> -External(\_SB.PCI0.RP18.DL23, MethodObj)
> -External(\_SB.PCI0.RP19.DL23, MethodObj)
> -External(\_SB.PCI0.RP20.DL23, MethodObj)
> -External(\_SB.PCI0.RP21.DL23, MethodObj)
> -External(\_SB.PCI0.RP22.DL23, MethodObj)
> -External(\_SB.PCI0.RP23.DL23, MethodObj)
> -External(\_SB.PCI0.RP24.DL23, MethodObj)
> -
> -External(\_SB.PCI0.RTEN, MethodObj)
> -External(\_SB.PCI0.RTDS, MethodObj)
> -External(\_SB.PCI0.RP01.PON, MethodObj)
> -External(\_SB.PCI0.RP02.PON, MethodObj)
> -External(\_SB.PCI0.RP03.PON, MethodObj)
> -External(\_SB.PCI0.RP04.PON, MethodObj)
> -External(\_SB.PCI0.RP05.PON, MethodObj)
> -External(\_SB.PCI0.RP06.PON, MethodObj)
> -External(\_SB.PCI0.RP07.PON, MethodObj)
> -External(\_SB.PCI0.RP08.PON, MethodObj)
> -External(\_SB.PCI0.RP09.PON, MethodObj)
> -External(\_SB.PCI0.RP10.PON, MethodObj)
> -External(\_SB.PCI0.RP11.PON, MethodObj)
> -External(\_SB.PCI0.RP12.PON, MethodObj)
> -External(\_SB.PCI0.RP13.PON, MethodObj)
> -External(\_SB.PCI0.RP14.PON, MethodObj)
> -External(\_SB.PCI0.RP15.PON, MethodObj)
> -External(\_SB.PCI0.RP16.PON, MethodObj)
> -External(\_SB.PCI0.RP17.PON, MethodObj)
> -External(\_SB.PCI0.RP18.PON, MethodObj)
> -External(\_SB.PCI0.RP19.PON, MethodObj)
> -External(\_SB.PCI0.RP20.PON, MethodObj)
> -External(\_SB.PCI0.RP21.PON, MethodObj)
> -External(\_SB.PCI0.RP22.PON, MethodObj)
> -External(\_SB.PCI0.RP23.PON, MethodObj)
> -External(\_SB.PCI0.RP24.PON, MethodObj)
> -External(\_SB.PCI0.PEG0.PG00._ON, MethodObj)
> -External(\_SB.PCI0.PEG1.PG01._ON, MethodObj)
> -External(\_SB.PCI0.PEG2.PG02._ON, MethodObj)
> -
> -Name(TRDO, 0) // 1 during TBT RTD3 _ON
> -Name(TRD3, 0) // 1 during TBT RTD3 _OFF
> -Name(TBPE, 0) // Reflects RTD3_PWR_EN value
> -Name(TOFF, 0) // param to TBT _OFF method
> -
> - Method (TBON, 0, Serialized) {
> - // TBT On process before entering Sx state.
> - Store(1, TRDO)
> - Switch (ToInteger(\RPS0)) { // TBT Root port Selector
> - Case (1) {
> - If (CondRefOf(\_SB.PCI0.RP01.PON)) {
> - \_SB.PCI0.RP01.PON()
> - }
> - }
> - Case (2) {
> - If (CondRefOf(\_SB.PCI0.RP02.PON)) {
> - \_SB.PCI0.RP02.PON()
> - }
> - }
> - Case (3) {
> - If (CondRefOf(\_SB.PCI0.RP03.PON)) {
> - \_SB.PCI0.RP03.PON()
> - }
> - }
> - Case (4) {
> - If (CondRefOf(\_SB.PCI0.RP04.PON)) {
> - \_SB.PCI0.RP04.PON()
> - }
> - }
> - Case (5) {
> - If (CondRefOf(\_SB.PCI0.RP05.PON)) {
> - \_SB.PCI0.RP05.PON()
> - }
> - }
> - Case (6) {
> - If (CondRefOf(\_SB.PCI0.RP06.PON)) {
> - \_SB.PCI0.RP06.PON()
> - }
> - }
> - Case (7) {
> - If (CondRefOf(\_SB.PCI0.RP07.PON)) {
> - \_SB.PCI0.RP07.PON()
> - }
> - }
> - Case (8) {
> - If (CondRefOf(\_SB.PCI0.RP08.PON)) {
> - \_SB.PCI0.RP08.PON()
> - }
> - }
> - Case (9) {
> - If (CondRefOf(\_SB.PCI0.RP09.PON)) {
> - \_SB.PCI0.RP09.PON()
> - }
> - }
> - Case (10) {
> - If (CondRefOf(\_SB.PCI0.RP10.PON)) {
> - \_SB.PCI0.RP10.PON()
> - }
> - }
> - Case (11) {
> - If (CondRefOf(\_SB.PCI0.RP11.PON)) {
> - \_SB.PCI0.RP11.PON()
> - }
> - }
> - Case (12) {
> - If (CondRefOf(\_SB.PCI0.RP12.PON)) {
> - \_SB.PCI0.RP12.PON()
> - }
> - }
> - Case (13) {
> - If (CondRefOf(\_SB.PCI0.RP13.PON)) {
> - \_SB.PCI0.RP13.PON()
> - }
> - }
> - Case (14) {
> - If (CondRefOf(\_SB.PCI0.RP14.PON)) {
> - \_SB.PCI0.RP14.PON()
> - }
> - }
> - Case (15) {
> - If (CondRefOf(\_SB.PCI0.RP15.PON)) {
> - \_SB.PCI0.RP15.PON()
> - }
> - }
> - Case (16) {
> - If (CondRefOf(\_SB.PCI0.RP16.PON)) {
> - \_SB.PCI0.RP16.PON()
> - }
> - }
> - Case (17) {
> - If (CondRefOf(\_SB.PCI0.RP17.PON)) {
> - \_SB.PCI0.RP17.PON()
> - }
> - }
> - Case (18) {
> - If (CondRefOf(\_SB.PCI0.RP18.PON)) {
> - \_SB.PCI0.RP18.PON()
> - }
> - }
> - Case (19) {
> - If (CondRefOf(\_SB.PCI0.RP19.PON)) {
> - \_SB.PCI0.RP19.PON()
> - }
> - }
> - Case (20) {
> - If (CondRefOf(\_SB.PCI0.RP20.PON)) {
> - \_SB.PCI0.RP20.PON()
> - }
> - }
> - Case (21) {
> - If (CondRefOf(\_SB.PCI0.RP21.PON)) {
> - \_SB.PCI0.RP21.PON()
> - }
> - }
> - Case (22) {
> - If (CondRefOf(\_SB.PCI0.RP22.PON)) {
> - \_SB.PCI0.RP22.PON()
> - }
> - }
> - Case (23) {
> - If (CondRefOf(\_SB.PCI0.RP23.PON)) {
> - \_SB.PCI0.RP23.PON()
> - }
> - }
> - Case (24) {
> - If (CondRefOf(\_SB.PCI0.RP24.PON)) {
> - \_SB.PCI0.RP24.PON()
> - }
> - }
> - }//Switch(ToInteger(RPS0)) // TBT Selector
> - Store(0, TRDO)
> - } // End of TBON
> - //
> - // Name: TBTD
> - // Description: Function to return the TBT RP# device no
> - // Input: Arg0 -> Tbt Root Port value from Tbt NVS
> - // Input: Arg1 -> Tbt port type value from Tbt NVS
> - // Return: TBT RP# device no
> - //
> - Method(TBTD,2)
> - {
> - ADBG("TBTD")
> - If (LEqual(Arg1, DTBT_TYPE_PCH)) {
> - Switch(ToInteger(Arg0))
> - {
> - Case (Package () {1, 2, 3, 4, 5, 6, 7, 8})
> - {
> - Store(0x1C, Local0) //Device28-Function0...Function7 =
> 11100.000...111
> - }
> - Case (Package () {9, 10, 11, 12, 13, 14, 15, 16})
> - {
> - Store(0x1D, Local0) //Device29-Function0...Function7 =
> 11101.000...111
> - }
> - Case (Package () {17, 18, 19, 20, 21, 22, 23, 24})
> - {
> - Store(0x1B, Local0) //Device27-Function0...Function3 =
> 11011.000...011
> - }
> - }
> - } ElseIf (LEqual(Arg1, DTBT_TYPE_PEG)) {
> - Switch(ToInteger(Arg0))
> - {
> - Case (Package () {1, 2, 3})
> - {
> - Store(0x1, Local0) //Device1-Function0...Function2 =
> 00001.000...010
> - }
> -#ifndef CPU_CFL
> - Case (Package () {4})
> - {
> - Store(0x6, Local0) //Device6-Function0 = 00110.000
> - }
> -#endif
> - }
> - } Else {
> - Store(0xFF, Local0)
> - }
> -
> - ADBG("Device no")
> - ADBG(Local0)
> -
> - Return(Local0)
> - } // End of Method(TBTD,1)
> -
> - //
> - // Name: TBTF
> - // Description: Function to return the TBT RP# function no
> - // Input: Arg0 -> Tbt Root Port value from Tbt NVS
> - // Input: Arg1 -> Tbt port type value from Tbt NVS
> - // Return: TBT RP# function no
> - //
> - Method(TBTF,2)
> - {
> - ADBG("TBTF")
> - If (LEqual(Arg1, DTBT_TYPE_PCH)) {
> - Switch(ToInteger(Arg0))
> - {
> - Case (1)
> - {
> - Store(And(\RPA1,0xF), Local0) //Device28-Function0 =
> 11100.000
> - }
> - Case (2)
> - {
> - Store(And(\RPA2,0xF), Local0) //Device28-Function1 =
> 11100.001
> - }
> - Case (3)
> - {
> - Store(And(\RPA3,0xF), Local0) //Device28-Function2 =
> 11100.010
> - }
> - Case (4)
> - {
> - Store(And(\RPA4,0xF), Local0) //Device28-Function3 =
> 11100.011
> - }
> - Case (5)
> - {
> - Store(And(\RPA5,0xF), Local0) //Device28-Function4 =
> 11100.100
> - }
> - Case (6)
> - {
> - Store(And(\RPA6,0xF), Local0) //Device28-Function5 =
> 11100.101
> - }
> - Case (7)
> - {
> - Store(And(\RPA7,0xF), Local0) //Device28-Function6 =
> 11100.110
> - }
> - Case (8)
> - {
> - Store(And(\RPA8,0xF), Local0) //Device28-Function7 =
> 11100.111
> - }
> - Case (9)
> - {
> - Store(And(\RPA9,0xF), Local0) //Device29-Function0 =
> 11101.000
> - }
> - Case (10)
> - {
> - Store(And(\RPAA,0xF), Local0) //Device29-Function1 =
> 11101.001
> - }
> - Case (11)
> - {
> - Store(And(\RPAB,0xF), Local0) //Device29-Function2 =
> 11101.010
> - }
> - Case (12)
> - {
> - Store(And(\RPAC,0xF), Local0) //Device29-Function3 =
> 11101.011
> - }
> - Case (13)
> - {
> - Store(And(\RPAD,0xF), Local0) //Device29-Function4 =
> 11101.100
> - }
> - Case (14)
> - {
> - Store(And(\RPAE,0xF), Local0) //Device29-Function5 =
> 11101.101
> - }
> - Case (15)
> - {
> - Store(And(\RPAF,0xF), Local0) //Device29-Function6 = 11101.110
> - }
> - Case (16)
> - {
> - Store(And(\RPAG,0xF), Local0) //Device29-Function7 =
> 11101.111
> - }
> - Case (17)
> - {
> - Store(And(\RPAH,0xF), Local0) //Device27-Function0 =
> 11011.000
> - }
> - Case (18)
> - {
> - Store(And(\RPAI,0xF), Local0) //Device27-Function1 = 11011.001
> - }
> - Case (19)
> - {
> - Store(And(\RPAJ,0xF), Local0) //Device27-Function2 = 11011.010
> - }
> - Case (20)
> - {
> - Store(And(\RPAK,0xF), Local0) //Device27-Function3 =
> 11011.011
> - }
> - Case (21)
> - {
> - Store(And(\RPAL,0xF), Local0) //Device27-Function4 = 11011.100
> - }
> - Case (22)
> - {
> - Store(And(\RPAM,0xF), Local0) //Device27-Function5 =
> 11011.101
> - }
> - Case (23)
> - {
> - Store(And(\RPAN,0xF), Local0) //Device27-Function6 =
> 11011.110
> - }
> - Case (24)
> - {
> - Store(And(\RPAO,0xF), Local0) //Device27-Function7 =
> 11011.111
> - }
> - }
> - } ElseIf (LEqual(Arg1, DTBT_TYPE_PEG)) {
> - Switch(ToInteger(Arg0))
> - {
> - Case (1)
> - {
> - Store(0x0, Local0) //Device1-Function0 = 00001.000
> - }
> - Case (2)
> - {
> - Store(0x1, Local0) //Device1-Function1 = 00001.001
> - }
> - Case (3)
> - {
> - Store(0x2, Local0) //Device1-Function2 = 00001.010
> - }
> -#ifndef CPU_CFL
> - Case (4)
> - {
> - Store(0x0, Local0) //Device6-Function0 = 00110.000
> - }
> -#endif
> - }
> - } Else {
> - Store(0xFF, Local0)
> - }
> -
> - ADBG("Function no")
> - ADBG(Local0)
> -
> - Return(Local0)
> - } // End of Method(TBTF,1)
> -
> - //
> - // Name: MMRP
> - // Description: Function to return the Pci base address of TBT rootport
> - // Input: Arg0 -> Tbt Root Port value from Tbt NVS
> - // Input: Arg1 -> Tbt port type value from Tbt NVS
> - //
> -
> - Method(MMRP, 2, Serialized)
> - {
> - Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address
> - Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no
> - Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no
> -
> - Return(Local0)
> - } // End of Method(MMRP)
> -
> - //
> - // Name: MMRP
> - // Description: Function to return the Pci base address of TBT Up stream
> port
> - // Input: Arg0 -> Tbt Root Port value from Tbt NVS
> - // Input: Arg1 -> Tbt port type value from Tbt NVS
> - //
> - Method(MMTB, 2, Serialized)
> - {
> - ADBG("MMTB")
> -
> - Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address
> -
> - Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no
> - Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no
> -
> - OperationRegion (MMMM, SystemMemory, Local0, 0x1A)
> - Field (MMMM, AnyAcc, NoLock, Preserve)
> - {
> - Offset(0x19),
> - SBUS, 8
> - }
> - Store(SBUS, Local2)
> - Store(\_SB.PCI0.GPCB(), Local0)
> - Multiply(Local2, 0x100000, Local2)
> - Add(Local2, Local0, Local0) // TBT HR US port
> -
> - ADBG("TBT-US-ADR")
> - ADBG(Local0)
> -
> - Return(Local0)
> - } // End of Method(MMTB, 1, Serialized)
> - //
> - // Name: FFTB
> - // Description: Function to Check for FFFF in TBT PCIe
> - // Input: Arg0 -> Tbt Root Port value from Tbt NVS
> - // Input: Arg1 -> Tbt port type value from Tbt NVS
> - // Return: 1 if TBT PCIe space has value FFFF, 0 if not
> - //
> - Method(FFTB, 2, Serialized)
> - {
> - ADBG("FFTB")
> -
> - Add(MMTB(Arg0, Arg1), 0x548, Local0)
> - OperationRegion(PXVD,SystemMemory,Local0,0x08)
> - Field(PXVD,DWordAcc, NoLock, Preserve)
> - {
> - TB2P, 32,
> - P2TB, 32
> - }
> -
> - Store(TB2P, Local1)
> -
> - If(LEqual(Local1, 0xFFFFFFFF))
> - {
> - ADBG("FFTb 1")
> - Return (1)
> - }
> - Else
> - {
> - ADBG("FFTb 0")
> - Return (0)
> - }
> - } // End of Method(FFTB)
> -
> -Name(TDMA, 0x80000000) // Address of Thunderbolt(TM) debug memory
> buffer, fixed up during POST
> -
> -Scope(\_GPE)
> -{
> - //
> - //
> - //OS up Mail Box command execution to host router upstream port each
> time
> - //exiting from Sx State .Avoids intermediate
> - //PCIe Scan by OS during resorce allocation
> - // Arg0 : PCIe Base address
> - // Arg1 : Controller Type 0x00 : DTBT
> - //Developer notes: Called twice
> - // 1. During OS INIT (booting to OS from S3-S5/Reboot)
> - // 2. Up on Hot plug
> - //
> - Method(OSUP, 2, Serialized)
> - {
> - ADBG("OSUP")
> -
> - Add(Arg0, 0x540, Local0)
> - OperationRegion(PXVD,SystemMemory,Local0,0x10)
> - Field(PXVD,DWordAcc, NoLock, Preserve)
> - {
> - IT2P, 32,
> - IP2T, 32,
> - DT2P, 32,
> - DP2T, 32
> - }
> -
> - Store(100, Local1)
> - Store(0x0D, DP2T) // Write OS_Up to PCIe2TBT
> -
> - While(LGreater(Local1, 0))
> - {
> - Store(Subtract(Local1, 1), Local1)
> - Store(DT2P, Local2)
> -
> - If(LAnd(LEqual(Local2, 0xFFFFFFFF),LEqual(Arg1,
> DTBT_CONTROLLER)))// Device gone
> - {
> - ADBG("Dev gone")
> - Return(2)
> - }
> - If(And(Local2, 1)) // Done
> - {
> - ADBG("Cmd acknowledged")
> - break
> - }
> - Sleep(50)
> - }
> - If(LEqual(TRWA,1))
> - {
> - Store(0xC, DP2T) // Write OSUP to PCIe2TBT
> - }
> - Else
> - {
> - Store(0x0, DP2T) // Write 0 to PCIe2TBT
> - }
> -
> - //Store(0x00, P2TB) // Write 0 to PCIe2TBT
> -
> - ADBG("End-of-OSUP")
> -
> - Return(1)
> - } // End of Method(OSUP, 1, Serialized)
> -
> - //
> - // Check for FFFF in TBT
> - // Input: Arg0 -> Tbt Root Port value from Tbt NVS
> - // Input: Arg1 -> Tbt port type value from Tbt NVS
> - //
> -
> - Method(TBFF, 2, Serialized)
> - {
> - ADBG("TBFF")
> -
> - Store(MMTB(Arg0, Arg1), Local0)
> - OperationRegion (PXVD, SystemMemory, Local0, 0x8)
> - Field (PXVD, DWordAcc, NoLock, Preserve) {
> - VEDI, 32, // Vendor/Device ID
> - CMDR, 32 // CMD register
> - }
> -
> - Store(VEDI, Local1)
> -
> - If (LEqual(Local1, 0xFFFFFFFF)) {
> - If (LNotEqual(\TWIN, 0)) { // TBT Enumeration is Native mode?
> - If (LEqual(CMDR, 0xFFFFFFFF)) { // Device Gone
> - Return (2)// Notify only
> - }
> - Return (1)// Exit w/o notify
> - } Else {
> - Return (OSUP(Local0, DTBT_CONTROLLER))
> - }
> - } Else
> - {
> - ADBG("Dev Present")
> - Return (0)
> - }
> - } // End of Method(TBFF, 1, Serialized)
> -
> - //
> - // Secondary bus of TBT RP
> - // Input: Arg0 -> Tbt Root Port value from Tbt NVS
> - // Input: Arg1 -> Tbt port type value from Tbt NVS
> - //
> -
> - Method(TSUB, 2, Serialized)
> - {
> - ADBG("TSUB")
> -
> - Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address
> -
> - Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no
> - Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no
> -
> - ADBG("ADR")
> - ADBG(Local0)
> -
> - OperationRegion (MMMM, SystemMemory, Local0, 0x1A)
> - Field (MMMM, AnyAcc, NoLock, Preserve)
> - {
> - Offset(0x19),
> - SBUS, 8
> - }
> -
> - ADBG("Sec Bus")
> - ADBG(SBUS)
> -
> - Return(SBUS)
> - } // End of Method(TSUB, 0, Serialized)
> -
> - //
> - // Pmem of TBT RP
> - // Input: Arg0 -> Tbt Root Port value from Tbt NVS
> - // Input: Arg1 -> Tbt port type value from Tbt NVS
> - //
> -
> - Method(TSUP, 2, Serialized)
> - {
> - ADBG("TSUB")
> -
> - Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address
> -
> - Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no
> - Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no
> -
> - ADBG("ADR:")
> - ADBG(Local0)
> -
> - OperationRegion (MMMM, SystemMemory, Local0, 0x30)
> - Field (MMMM, AnyAcc, NoLock, Preserve)
> - {
> - CMDS, 32,
> - Offset(0x19),
> - SBUS, 8,
> - SBU5, 8,
> - Offset(0x1C),
> - SEIO, 32,
> - MMBL, 32,
> - PMBL, 32,
> -
> - }
> -
> - ADBG("Pmem of TBT RP:")
> - ADBG(PMBL)
> -
> - Return(PMBL)
> - } // End of Method(TSUP, 0, Serialized)
> -
> - //
> - // Wait for secondary bus in TBT RP
> - // Input: Arg0 -> Tbt Root Port value from Tbt NVS
> - // Input: Arg1 -> Tbt port type value from Tbt NVS
> - //
> -
> - Method(WSUB, 2, Serialized)
> - {
> - ADBG(Concatenate("WSUB=", ToHexString(Arg0)))
> - ADBG(ToHexString(Timer))
> -
> - Store(0, Local0)
> - Store(0, Local1)
> - While(1)
> - {
> - Store(TSUP(Arg0, Arg1), Local1)
> - If(LGreater(Local1, 0x1FFF1))
> - {
> - ADBG("WSUB-Finished")
> - Break
> - }
> - Else
> - {
> - Add(Local0, 1, Local0)
> - If(LGreater(Local0, 1000))
> - {
> - Sleep(1000)
> - ADBG("WSUB-Deadlock")
> - }
> - Else
> - {
> - Sleep(16)
> - }
> - }
> - }
> - ADBG(Concatenate("WSUb=", ToHexString(Local1)))
> - } // End of Method(WSUB)
> -
> - // Wait for _WAK finished
> - Method(WWAK)
> - {
> - ADBG("WWAK")
> -
> - Wait(WFEV, 0xFFFF)
> - Signal(WFEV) // Set it, to enter on next HP
> - } // End of Method(WWAK)
> -
> - Method(NTFY, 2, Serialized)
> - {
> - ADBG("NTFY")
> -
> - If(LEqual(NOHP,1))
> - {
> - If (LEqual(Arg1, DTBT_TYPE_PCH)) {
> - Switch(ToInteger(Arg0)) // TBT Selector
> - {
> - Case (1)
> - {
> - ADBG("Notify RP01")
> - Notify(\_SB.PCI0.RP01,0)
> - }
> - Case (2)
> - {
> - ADBG("Notify RP02")
> - Notify(\_SB.PCI0.RP02,0)
> - }
> - Case (3)
> - {
> - ADBG("Notify RP03")
> - Notify(\_SB.PCI0.RP03,0)
> - }
> - Case (4)
> - {
> - ADBG("Notify RP04")
> - Notify(\_SB.PCI0.RP04,0)
> - }
> - Case (5)
> - {
> - ADBG("Notify RP05")
> - Notify(\_SB.PCI0.RP05,0)
> - }
> - Case (6)
> - {
> - ADBG("Notify RP06")
> - Notify(\_SB.PCI0.RP06,0)
> - }
> - Case (7)
> - {
> - ADBG("Notify RP07")
> - Notify(\_SB.PCI0.RP07,0)
> - }
> - Case (8)
> - {
> - ADBG("Notify RP08")
> - Notify(\_SB.PCI0.RP08,0)
> - }
> - Case (9)
> - {
> - ADBG("Notify RP09")
> - Notify(\_SB.PCI0.RP09,0)
> - }
> - Case (10)
> - {
> - ADBG("Notify RP10")
> - Notify(\_SB.PCI0.RP10,0)
> - }
> - Case (11)
> - {
> - ADBG("Notify RP11")
> - Notify(\_SB.PCI0.RP11,0)
> - }
> - Case (12)
> - {
> - ADBG("Notify RP12")
> - Notify(\_SB.PCI0.RP12,0)
> - }
> - Case (13)
> - {
> - ADBG("Notify RP13")
> - Notify(\_SB.PCI0.RP13,0)
> - }
> - Case (14)
> - {
> - ADBG("Notify RP14")
> - Notify(\_SB.PCI0.RP14,0)
> - }
> - Case (15)
> - {
> - ADBG("Notify RP15")
> - Notify(\_SB.PCI0.RP15,0)
> - }
> - Case (16)
> - {
> - ADBG("Notify RP16")
> - Notify(\_SB.PCI0.RP16,0)
> - }
> - Case (17)
> - {
> - ADBG("Notify RP17")
> - Notify(\_SB.PCI0.RP17,0)
> - }
> - Case (18)
> - {
> - ADBG("Notify RP18")
> - Notify(\_SB.PCI0.RP18,0)
> - }
> - Case (19)
> - {
> - ADBG("Notify RP19")
> - Notify(\_SB.PCI0.RP19,0)
> - }
> - Case (20)
> - {
> - ADBG("Notify RP20")
> - Notify(\_SB.PCI0.RP20,0)
> - }
> - Case (21)
> - {
> - ADBG("Notify RP21")
> - Notify(\_SB.PCI0.RP21,0)
> - }
> - Case (22)
> - {
> - ADBG("Notify RP22")
> - Notify(\_SB.PCI0.RP22,0)
> - }
> - Case (23)
> - {
> - ADBG("Notify RP23")
> - Notify(\_SB.PCI0.RP23,0)
> - }
> - Case (24)
> - {
> - ADBG("Notify RP24")
> - Notify(\_SB.PCI0.RP24,0)
> - }
> - }//Switch(ToInteger(TBSS)) // TBT Selector
> - } ElseIf (LEqual(Arg1, DTBT_TYPE_PEG)) {
> - Switch(ToInteger(Arg0))
> - {
> - Case (1)
> - {
> - ADBG("Notify PEG0")
> - Notify(\_SB.PCI0.PEG0,0)
> - }
> - Case (2)
> - {
> - ADBG("Notify PEG1")
> - Notify(\_SB.PCI0.PEG1,0)
> - }
> - Case (3)
> - {
> - ADBG("Notify PEG2")
> - Notify(\_SB.PCI0.PEG2,0)
> - }
> -#ifndef CPU_CFL
> - Case (4)
> - {
> - ADBG("Notify PEG3")
> - Notify(\_SB.PCI0.PEG3,0)
> - }
> -#endif
> - }
> - }//Switch(ToInteger(TBSS)) // TBT Selector
> - }//If(NOHP())
> - P8XH(0,0xC2)
> - P8XH(1,0xC2)
> - }// End of Method(NTFY)
> -
> -//
> -// TBT BIOS, GPIO 5 filtering,
> -// Hot plug of 12V USB devices, into TBT host router, cause electrical noise
> on PCH GPIOs,
> -// This noise cause false hot-plug events, and negatively influence BIOS
> assisted hot-plug.
> -// SKL-PCH GPIO does not implement Glitch Filter logic (refer to GPIO HAS)
> on any GPIO pad. Native functions have to implement their own digital
> glitch-filter logic
> -// if needed. As HW filter was not implemented on SKL PCH, because of
> that SW workaround should be implemented in BIOS.
> -// Register 0x544(Bios mailbox) bit 0 definition:
> -// if BIOS reads bit as 1, BIOS will clear the bit and continue normal flow, if
> bit is 0 BIOS will exit from method
> -//
> -
> - Method(GNIS,2, Serialized)
> - {
> -
> - ADBG("GNIS")
> - If(LEqual(GP5F, 0))
> - {
> - ADBG("GNIS_Dis=0")
> - Return(0)
> - }
> - //
> - // BIOS mailbox command for GPIO filter
> - //
> - Add(MMTB(Arg0, Arg1), 0x544, Local0)
> - OperationRegion(PXVD,SystemMemory,Local0,0x08)
> -
> - Field(PXVD,DWordAcc, NoLock, Preserve)
> - {
> - HPFI, 1,
> - Offset(0x4),
> - TB2P, 32
> - }
> - Store(TB2P, Local1)
> - ADBG(Concatenate("TB2P=", ToHexString(Local1)))
> - If(LEqual(Local1, 0xFFFFFFFF)) // Disconnect?
> - {
> - ADBG("GNIS=0")
> - Return(0)
> - }
> - Store(HPFI, Local2)
> - ADBG(Concatenate("HPFI=", ToHexString(Local2)))
> - If(LEqual(Local2, 0x01))
> - {
> - Store(0x00, HPFI)
> - ADBG("GNIS=0")
> - Return(0)
> - }
> - // Any other values treated as a GPIO noise
> - ADBG("GNIS=1")
> - Return(1)
> - }
> -
> - Method(CHKP,2, Serialized)
> - {
> - Add(MMTB(Arg0, Arg1), 0x544, Local0)
> - OperationRegion(PXVE,SystemMemory,Local0,0x08)
> -
> - Field(PXVE,DWordAcc, NoLock, Preserve)
> - {
> - HPFI, 1,
> - Offset(0x4),
> - TB2P, 32
> - }
> - Store(TB2P, Local1)
> - And(Local1,BIT29,Local1)
> - ADBG(Concatenate("Local1=", ToHexString(Local1)))
> - //ADBG(Concatenate("BIT29=", ToHexString(LAnd(Local1,BIT29))))
> - If(LEqual(Local1, BIT29))
> - {
> - Return(1)
> - }
> - Else
> - {
> - Return(0)
> - }
> - }
> -
> - //
> - // Method to Handle enumerate PCIe structure through
> - // SMI for Thunderbolt(TM) devices
> - //
> - Method(XTBT,2, Serialized)
> - {
> - ADBG("XTBT")
> - ADBG("RP :")
> - ADBG(Arg0)
> - Store(Arg0, DTCP) // Root port to enumerate
> - Store(Arg1, DTPT) // Root port Type
> - If(LEqual(Arg0, RPS0)) {
> - Store (1, Local0)
> - } ElseIf (LEqual(Arg0, RPS1)) {
> - Store (2, Local0)
> - } Else {
> - Store (0, Local0)
> - Return ()
> - }
> -
> - If (TRDO) {
> - ADBG("Durng TBT_ON")
> - Return ()
> - }
> -
> - If (TRD3) {
> - ADBG("During TBT_OFF")
> - Return ()
> - }
> - WWAK()
> - WSUB(Arg0, Arg1)
> - If(GNIS(Arg0, Arg1))
> - {
> - Return()
> - }
> -
> - OperationRegion(SPRT,SystemIO, 0xB2,2)
> - Field (SPRT, ByteAcc, Lock, Preserve)
> - {
> - SSMP, 8
> - }
> -
> - ADBG("TBT-HP-Handler")
> -
> - Acquire(OSUM, 0xFFFF)
> - Store(TBFF(Arg0, Arg1), Local1)
> - If(LEqual(Local1, 1))// Only HR
> - {
> - Sleep(16)
> - Release(OSUM)
> - ADBG("OS_Up_Received")
> - Return ()
> - }
> - If(LEqual(Local1, 2)) // Disconnect
> - {
> - NTFY(Arg0, Arg1)
> - Sleep(16)
> - Release(OSUM)
> - ADBG("Disconnect")
> - Return ()
> - }
> -
> - // HR and EP
> - If(LEqual(SOHP, 1))
> - {
> - // Trigger SMI to enumerate PCIe Structure
> - ADBG("TBT SW SMI")
> - Store(21, TBSF)
> - Store(0xF7, SSMP)
> - }
> - NTFY(Arg0, Arg1)
> - Sleep(16)
> - Release(OSUM)
> -
> - ADBG("End-of-XTBT")
> - } // End of Method(XTBT)
> -
> - //
> - // Calling Method to Handle enumerate PCIe structure through
> - // SMI for Thunderbolt(TM) devices for Tier 1 GPIOs
> - // Used in Two ways ,
> - // If CIO GPIO(1 Tier) is Different for the Controllers, this will be used as 1
> Tier GPIO Handler for 1st controller
> - // If CIO GPIO(1 Tier) is Same for all the controllers, this will be used as 1
> Tier GPIO Handler for All the controllers
> - //
> - Method(ATBT)
> - {
> - ADBG("ATBT")
> - //
> - // Calling Method to Handle enumerate PCIe structure through
> - //
> - If(LEqual(CGST,0)) { // If GPIO is Different for each controller
> - If(LEqual(RPN0,1))
> - {
> - XTBT(RPS0, RPT0)
> - }
> - } Else {
> - If(LEqual(RPN0,1))
> - {
> - XTBT(RPS0, RPT0)
> - }
> - ElseIf(LEqual(RPN1,1))
> - {
> - XTBT(RPS1, RPT1)
> - }
> - }
> - ADBG("End-of-ATBT")
> - } // End of Method(ATBT)
> -
> - Method(BTBT)
> - {
> - ADBG("BTBT")
> - //
> - // Calling Method to Handle enumerate PCIe structure through
> - //
> - If(LEqual(CGST,0)) { // If GPIO is Different for each controller
> - If(LEqual(RPN1,1))
> - {
> - XTBT(RPS1, RPT1)
> - }
> - }
> - ADBG("End-of-BTBT")
> - } // End of Method(BTBT)
> - //
> - // Method to call OSPU Mail box command
> - // Arg0 : Controller type 0x00 : Discrete 0x80 : Integrated TBT
> - // Arg1 : TBT RP Selector / DMA
> - // Arg2 : TBT Type (PCH or PEG)
> - //
> - Method(TINI, 3, Serialized)
> - {
> - ADBG("TINI")
> - If(Lequal (Arg0, DTBT_CONTROLLER))
> - {
> - //ADBG("DTBT")
> - Store(MMRP(Arg1, Arg2), Local0)
> - OperationRegion(RP_X,SystemMemory,Local0,0x20)
> - Field(RP_X,DWordAcc, NoLock, Preserve)
> - {
> - REG0, 32,
> - REG1, 32,
> - REG2, 32,
> - REG3, 32,
> - REG4, 32,
> - REG5, 32,
> - REG6, 32,
> - REG7, 32
> - }
> - Store(REG6, Local1)
> - Store(0x00F0F000, REG6)
> - Store(MMTB(Arg1, Arg2), Local2)
> - OSUP(Local2, DTBT_CONTROLLER)
> - Store(Local1, REG6)
> - }
> - ADBG("End-of-TINI")
> - }
> -
> -} // End of Scope (\_GPE)
> -
> -Scope (\_SB)
> -{
> - //
> - // The code needs to be executed for TBT Hotplug Handler event (2-tier
> GPI GPE event architecture) is presented here
> - //
> - Method(THDR, 3, Serialized)
> - {
> - ADBG("THDR")
> - \_SB.CAGS(Arg0)
> - \_GPE.XTBT(Arg1, Arg2)
> - } // End of Method(THDR, 3, Serialized)
> -} // End of Scope(\_SB)
> -
> -Scope (\_SB)
> -{
> - //
> - // Name: CGWR [Combined GPIO Write]
> - // Description: Function to write into GPIO
> - // Input: Arg0 -> GpioPad / Expander pin
> - // Arg1 -> Value
> - // Return: Nothing
> - //
> - Method(CGWR, 2, Serialized)
> - {
> - // PCH
> - If (CondRefOf(\_SB.SGOV))
> - {
> - \_SB.SGOV(Arg0, Arg1)
> - }
> - } // End of Method(CGWR, 4, Serialized)
> -
> - //
> - // Name: CGRD [Combined GPIO Read]
> - // Description: Function to read from GPIO
> - // Input: Arg0 -> GpioPad / Expander pin
> - // Arg1 -> 0: GPO [GPIO TX State]
> - // 1: GPI [GPIO RX State]
> - // Return: Value
> - //
> - Method(CGRD, 2, Serialized)
> - {
> - Store(1, Local0)
> - // PCH
> - If (LEqual(Arg1, 0))
> - {
> - // GPIO TX State
> - If (CondRefOf(\_SB.GGOV))
> - {
> - Store(\_SB.GGOV(Arg0), Local0)
> - }
> - }
> - ElseIf (LEqual(Arg1, 1))
> - {
> - // GPIO RX State
> - If (CondRefOf(\_SB.GGIV))
> - {
> - Store(\_SB.GGIV(Arg0), Local0)
> - }
> - }
> - Return(Local0)
> - } // End of Method(CGRD, 4, Serialized)
> - //
> - // Name: WRGP [GPIO Write]
> - // Description: Function to write into GPIO
> - // Input: Arg0 -> COMMON_GPIO_CONFIG GpioInfo
> - // Arg1 -> Value
> - // Return: Nothing
> - //
> - Method(WRGP, 2, Serialized)
> - {
> - Store(Arg0, Local0)
> - Store(Arg0, Local1)
> - And(Local0, 0xFFFFFFFF, Local0) // Low 32 bits (31:00)
> - ShiftRight(Local1, 32, Local1) // High 32 bits (63:32)
> - If (LEqual(And(Local0, 0xFF), 1))
> - {
> - // PCH
> - \_SB.CGWR(Local1, Arg1)
> - }
> - } // End of Method(WRGP, 2, Serialized)
> -
> - //
> - // Name: RDGP [GPIO Read]
> - // Description: Function to write into GPIO
> - // Input: Arg0 -> COMMON_GPIO_CONFIG GpioInfo
> - // Arg1 -> In case of PCH Gpio Read {GPIO TX(0)/RX(1) State
> indicator}
> - // Return: Value
> - //
> - Method(RDGP, 2, Serialized)
> - {
> - Store(1, Local7)
> - Store(Arg0, Local0)
> - Store(Arg0, Local1)
> - And(Local0, 0xFFFFFFFF, Local0) // Low 32 bits (31:00)
> - ShiftRight(Local1, 32, Local1) // High 32 bits (63:32)
> - If (LEqual(And(Local0, 0xFF), 1))
> - {
> - // PCH
> - Store(\_SB.CGRD(Local1, Arg1), Local7)
> - }
> - Return(Local7)
> - } // End of Method(RDGP, 2, Serialized)
> -
> -} // End of Scope(\_SB)
> -
> -Scope(\_SB)
> -{
> - // Asserts/De-asserts TBT force power
> - Method(TBFP, 2)
> - {
> - If(Arg0)
> - {
> - // Implementation dependent way to assert TBT force power
> - If(LEqual(Arg1, 1)) {
> - CGWR(FPG0, FP0L)
> - }
> - Else {
> - CGWR(FPG1, FP1L)
> - }
> - }
> - Else
> - {
> - // Implementation dependent way to de-assert TBT force power
> - If(LEqual(Arg1, 1)) {
> - CGWR(FPG0, LNot(FP0L))
> - }
> - Else {
> - CGWR(FPG1, LNot(FP1L))
> - }
> - }
> - }
> -
> - // WMI ACPI device to control TBT force power
> - Device(WMTF)
> - {
> - // pnp0c14 is pnp id assigned to WMI mapper
> - Name(_HID, "PNP0C14")
> - Name(_UID, "TBFP")
> -
> - Name(_WDG, Buffer() {
> - // {86CCFD48-205E-4A77-9C48-2021CBEDE341}
> - 0x48, 0xFD, 0xCC, 0x86,
> - 0x5E, 0x20,
> - 0x77, 0x4A,
> - 0x9C, 0x48,
> - 0x20, 0x21, 0xCB, 0xED, 0xE3, 0x41,
> - 84, 70, // Object Id (TF)
> - 1, // Instance Count
> - 0x02 // Flags (WMIACPI_REGFLAG_METHOD)
> - })
> -
> - // Set TBT force power
> - // Arg2 is force power value
> - Method(WMTF, 3)
> - {
> - CreateByteField(Arg2,0,FP)
> -
> - If(FP)
> - {
> - TBFP(1, 1)
> - }
> - Else
> - {
> - TBFP(0, 1)
> - }
> - }
> - }
> -} // End of Scope(\_SB)
> -
> -
> -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 1),LEqual(RPS1, 1))))
> -{
> - Scope(\_SB.PCI0.RP01)
> - {
> - Device(HRUS)// Host router Upstream port
> - {
> - Name(_ADR, 0x00000000)
> -
> - Method(_RMV)
> - {
> - Return(TARS)
> - } // end _RMV
> - }
> - }//End of Scope(\_SB.PCI0.RP01)
> -}
> -
> -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 2),LEqual(RPS1, 2))))
> -{
> - Scope(\_SB.PCI0.RP02)
> - {
> - Device(HRUS)// Host router Upstream port
> - {
> - Name(_ADR, 0x00000000)
> -
> - Method(_RMV)
> - {
> - Return(TARS)
> - } // end _RMV
> - }
> - }//End of Scope(\_SB.PCI0.RP02)
> -}
> -
> -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 3),LEqual(RPS1, 3))))
> -{
> - Scope(\_SB.PCI0.RP03)
> - {
> - Device(HRUS)// Host router Upstream port
> - {
> - Name(_ADR, 0x00000000)
> -
> - Method(_RMV)
> - {
> - Return(TARS)
> - } // end _RMV
> - }
> - }//End of Scope(\_SB.PCI0.RP03)
> -}
> -
> -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 4),LEqual(RPS1, 4))))
> -{
> - Scope(\_SB.PCI0.RP04)
> - {
> - Device(HRUS)// Host router Upstream port
> - {
> - Name(_ADR, 0x00000000)
> -
> - Method(_RMV)
> - {
> - Return(TARS)
> - } // end _RMV
> - }
> - }//End of Scope(\_SB.PCI0.RP04)
> -}
> -
> -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 5),LEqual(RPS1, 5))))
> -{
> - Scope(\_SB.PCI0.RP05)
> - {
> - Device(HRUS)// Host router Upstream port
> - {
> - Name(_ADR, 0x00000000)
> -
> - Method(_RMV)
> - {
> - Return(TARS)
> - } // end _RMV
> - }
> - }//End of Scope(\_SB.PCI0.RP05)
> -}
> -
> -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 6),LEqual(RPS1, 6))))
> -{
> - Scope(\_SB.PCI0.RP06)
> - {
> - Device(HRUS)// Host router Upstream port
> - {
> - Name(_ADR, 0x00000000)
> -
> - Method(_RMV)
> - {
> - Return(TARS)
> - } // end _RMV
> - }
> - }//End of Scope(\_SB.PCI0.RP06)
> -}
> -
> -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 7),LEqual(RPS1, 7))))
> -{
> - Scope(\_SB.PCI0.RP07)
> - {
> - Device(HRUS)// Host router Upstream port
> - {
> - Name(_ADR, 0x00000000)
> -
> - Method(_RMV)
> - {
> - Return(TARS)
> - } // end _RMV
> - }
> - }//End of Scope(\_SB.PCI0.RP07)
> -}
> -
> -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 8),LEqual(RPS1, 8))))
> -{
> - Scope(\_SB.PCI0.RP08)
> - {
> - Device(HRUS)// Host router Upstream port
> - {
> - Name(_ADR, 0x00000000)
> -
> - Method(_RMV)
> - {
> - Return(TARS)
> - } // end _RMV
> - }
> - }//End of Scope(\_SB.PCI0.RP08)
> -}
> -
> -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 9),LEqual(RPS1, 9))))
> -{
> - Scope(\_SB.PCI0.RP09)
> - {
> - Device(HRUS)// Host router Upstream port
> - {
> - Name(_ADR, 0x00000000)
> -
> - Method(_RMV)
> - {
> - Return(TARS)
> - } // end _RMV
> - }
> - }//End of Scope(\_SB.PCI0.RP09)
> -}
> -
> -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 10),LEqual(RPS1, 10))))
> -{
> - Scope(\_SB.PCI0.RP10)
> - {
> - Device(HRUS)// Host router Upstream port
> - {
> - Name(_ADR, 0x00000000)
> -
> - Method(_RMV)
> - {
> - Return(TARS)
> - } // end _RMV
> - }
> - }//End of Scope(\_SB.PCI0.RP10)
> -}
> -
> -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 11),LEqual(RPS1, 11))))
> -{
> - Scope(\_SB.PCI0.RP11)
> - {
> - Device(HRUS)// Host router Upstream port
> - {
> - Name(_ADR, 0x00000000)
> -
> - Method(_RMV)
> - {
> - Return(TARS)
> - } // end _RMV
> - }
> - }//End of Scope(\_SB.PCI0.RP11)
> -}
> -
> -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 12),LEqual(RPS1, 12))))
> -{
> - Scope(\_SB.PCI0.RP12)
> - {
> - Device(HRUS)// Host router Upstream port
> - {
> - Name(_ADR, 0x00000000)
> -
> - Method(_RMV)
> - {
> - Return(TARS)
> - } // end _RMV
> - }
> - }//End of Scope(\_SB.PCI0.RP12)
> -}
> -
> -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 13),LEqual(RPS1, 13))))
> -{
> - Scope(\_SB.PCI0.RP13)
> - {
> - Device(HRUS)// Host router Upstream port
> - {
> - Name(_ADR, 0x00000000)
> -
> - Method(_RMV)
> - {
> - Return(TARS)
> - } // end _RMV
> - }
> - }//End of Scope(\_SB.PCI0.RP13)
> -}
> -
> -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 14),LEqual(RPS1, 14))))
> -{
> - Scope(\_SB.PCI0.RP14)
> - {
> - Device(HRUS)// Host router Upstream port
> - {
> - Name(_ADR, 0x00000000)
> -
> - Method(_RMV)
> - {
> - Return(TARS)
> - } // end _RMV
> - }
> - }//End of Scope(\_SB.PCI0.RP14)
> -}
> -
> -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 15),LEqual(RPS1, 15))))
> -{
> - Scope(\_SB.PCI0.RP15)
> - {
> - Device(HRUS)// Host router Upstream port
> - {
> - Name(_ADR, 0x00000000)
> -
> - Method(_RMV)
> - {
> - Return(TARS)
> - } // end _RMV
> - }
> - }//End of Scope(\_SB.PCI0.RP15)
> -}
> -
> -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 16),LEqual(RPS1, 16))))
> -{
> - Scope(\_SB.PCI0.RP16)
> - {
> - Device(HRUS)// Host router Upstream port
> - {
> - Name(_ADR, 0x00000000)
> -
> - Method(_RMV)
> - {
> - Return(TARS)
> - } // end _RMV
> - }
> - }//End of Scope(\_SB.PCI0.RP16)
> -}
> -
> -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 17),LEqual(RPS1, 17))))
> -{
> - Scope(\_SB.PCI0.RP17)
> - {
> - Device(HRUS)// Host router Upstream port
> - {
> - Name(_ADR, 0x00000000)
> -
> - Method(_RMV)
> - {
> - Return(TARS)
> - } // end _RMV
> - }
> - }//End of Scope(\_SB.PCI0.RP17)
> -}
> -
> -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 18),LEqual(RPS1, 18))))
> -{
> - Scope(\_SB.PCI0.RP18)
> - {
> - Device(HRUS)// Host router Upstream port
> - {
> - Name(_ADR, 0x00000000)
> -
> - Method(_RMV)
> - {
> - Return(TARS)
> - } // end _RMV
> - }
> - }//End of Scope(\_SB.PCI0.RP18)
> -}
> -
> -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 19),LEqual(RPS1, 19))))
> -{
> - Scope(\_SB.PCI0.RP19)
> - {
> - Device(HRUS)// Host router Upstream port
> - {
> - Name(_ADR, 0x00000000)
> -
> - Method(_RMV)
> - {
> - Return(TARS)
> - } // end _RMV
> - }
> - }//End of Scope(\_SB.PCI0.RP19)
> -}
> -
> -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 20),LEqual(RPS1, 20))))
> -{
> - Scope(\_SB.PCI0.RP20)
> - {
> - Device(HRUS)// Host router Upstream port
> - {
> - Name(_ADR, 0x00000000)
> -
> - Method(_RMV)
> - {
> - Return(TARS)
> - } // end _RMV
> - }
> - }//End of Scope(\_SB.PCI0.RP20)
> -}
> -
> -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 21),LEqual(RPS1, 21))))
> -{
> - Scope(\_SB.PCI0.PEG0)
> - {
> - Device(HRUS)// Host router Upstream port
> - {
> - Name(_ADR, 0x00000000)
> -
> - Method(_RMV)
> - {
> - Return(TARS)
> - } // end _RMV
> - }
> - }//End of Scope(\_SB.PCI0.PEG0)
> -}
> -
> -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 22),LEqual(RPS1, 22))))
> -{
> - Scope(\_SB.PCI0.PEG1)
> - {
> - Device(HRUS)// Host router Upstream port
> - {
> - Name(_ADR, 0x00000000)
> -
> - Method(_RMV)
> - {
> - Return(TARS)
> - } // end _RMV
> - }
> - }//End of Scope(\_SB.PCI0.PEG1)
> -}
> -
> -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 23),LEqual(RPS1, 23))))
> -{
> - Scope(\_SB.PCI0.PEG2)
> - {
> - Device(HRUS)// Host router Upstream port
> - {
> - Name(_ADR, 0x00000000)
> -
> - Method(_RMV)
> - {
> - Return(TARS)
> - } // end _RMV
> - }
> - }//End of Scope(\_SB.PCI0.PEG2)
> -}
> -
> -Scope(\_SB)
> -{
> - //
> - // Name: PERB
> - // Description: Function to read a Byte from PCIE-MMIO
> - // Input: Arg0 -> PCIE base address
> - // Arg1 -> Bus
> - // Arg2 -> Device
> - // Arg3 -> Function
> - // Arg4 -> Register offset
> - // Return: Byte data read from PCIE-MMIO
> - //
> - Method(PERB,5,Serialized)
> - {
> - ADBG("PERB")
> -
> - Store(Arg0, Local7)
> - Or(Local7, ShiftLeft(Arg1, 20), Local7)
> - Or(Local7, ShiftLeft(Arg2, 15), Local7)
> - Or(Local7, ShiftLeft(Arg3, 12), Local7)
> - Or(Local7, Arg4, Local7)
> -
> - OperationRegion(PCI0, SystemMemory, Local7, 1)
> - Field(PCI0, ByteAcc,NoLock,Preserve)
> - {
> - TEMP, 8
> - }
> -
> - Return(TEMP)
> - } // End of Method(PERB,5,Serialized)
> -
> - //
> - // Name: PEWB
> - // Description: Function to write a Byte into PCIE-MMIO
> - // Input: Arg0 -> PCIE base address
> - // Arg1 -> Bus
> - // Arg2 -> Device
> - // Arg3 -> Function
> - // Arg4 -> Register offset
> - // Arg5 -> Data
> - // Return: Nothing
> - //
> - Method(PEWB,6,Serialized)
> - {
> - ADBG("PEWB")
> -
> - Store(Arg0, Local7)
> - Or(Local7, ShiftLeft(Arg1, 20), Local7)
> - Or(Local7, ShiftLeft(Arg2, 15), Local7)
> - Or(Local7, ShiftLeft(Arg3, 12), Local7)
> - Or(Local7, Arg4, Local7)
> -
> - OperationRegion(PCI0, SystemMemory, Local7, 1)
> - Field(PCI0, ByteAcc,NoLock,Preserve)
> - {
> - TEMP, 8
> - }
> -
> - Store(Arg5,TEMP)
> - } // End of Method(PEWB,6,Serialized)
> -
> - //
> - // Name: PERW
> - // Description: Function to read a Word from PCIE-MMIO
> - // Input: Arg0 -> PCIE base address
> - // Arg1 -> Bus
> - // Arg2 -> Device
> - // Arg3 -> Function
> - // Arg4 -> Register offset
> - // Return: Word data read from PCIE-MMIO
> - //
> - Method(PERW,5,Serialized)
> - {
> - ADBG("PERW")
> -
> - Store(Arg0, Local7)
> - Or(Local7, ShiftLeft(Arg1, 20), Local7)
> - Or(Local7, ShiftLeft(Arg2, 15), Local7)
> - Or(Local7, ShiftLeft(Arg3, 12), Local7)
> - Or(Local7, Arg4, Local7)
> -
> - OperationRegion(PCI0, SystemMemory, Local7, 2)
> - Field(PCI0, ByteAcc,NoLock,Preserve)
> - {
> - TEMP, 16
> - }
> -
> - Return(TEMP)
> - } // End of Method(PERW,5,Serialized)
> -
> - //
> - // Name: PEWW
> - // Description: Function to write a Word into PCIE-MMIO
> - // Input: Arg0 -> PCIE base address
> - // Arg1 -> Bus
> - // Arg2 -> Device
> - // Arg3 -> Function
> - // Arg4 -> Register offset
> - // Arg5 -> Data
> - // Return: Nothing
> - //
> - Method(PEWW,6,Serialized)
> - {
> - ADBG("PEWW")
> -
> - Store(Arg0, Local7)
> - Or(Local7, ShiftLeft(Arg1, 20), Local7)
> - Or(Local7, ShiftLeft(Arg2, 15), Local7)
> - Or(Local7, ShiftLeft(Arg3, 12), Local7)
> - Or(Local7, Arg4, Local7)
> -
> - OperationRegion(PCI0, SystemMemory, Local7, 2)
> - Field(PCI0, ByteAcc,NoLock,Preserve)
> - {
> - TEMP, 16
> - }
> -
> - Store(Arg5,TEMP)
> - } // End of Method(PEWW,6,Serialized)
> -
> - //
> - // Name: PERD
> - // Description: Function to read a Dword from PCIE-MMIO
> - // Input: Arg0 -> PCIE base address
> - // Arg1 -> Bus
> - // Arg2 -> Device
> - // Arg3 -> Function
> - // Arg4 -> Register offset
> - // Return: Dword data read from PCIE-MMIO
> - //
> - Method(PERD,5,Serialized)
> - {
> - ADBG("PERD")
> -
> - Store(Arg0, Local7)
> - Or(Local7, ShiftLeft(Arg1, 20), Local7)
> - Or(Local7, ShiftLeft(Arg2, 15), Local7)
> - Or(Local7, ShiftLeft(Arg3, 12), Local7)
> - Or(Local7, Arg4, Local7)
> -
> - OperationRegion(PCI0, SystemMemory, Local7, 4)
> - Field(PCI0, ByteAcc,NoLock,Preserve)
> - {
> - TEMP, 32
> - }
> -
> - Return(TEMP)
> - } // End of Method(PERD,5,Serialized)
> -
> - //
> - // Name: PEWD
> - // Description: Function to write a Dword into PCIE-MMIO
> - // Input: Arg0 -> PCIE base address
> - // Arg1 -> Bus
> - // Arg2 -> Device
> - // Arg3 -> Function
> - // Arg4 -> Register offset
> - // Arg5 -> Data
> - // Return: Nothing
> - //
> - Method(PEWD,6,Serialized)
> - {
> - ADBG("PEWD")
> -
> - Store(Arg0, Local7)
> - Or(Local7, ShiftLeft(Arg1, 20), Local7)
> - Or(Local7, ShiftLeft(Arg2, 15), Local7)
> - Or(Local7, ShiftLeft(Arg3, 12), Local7)
> - Or(Local7, Arg4, Local7)
> -
> - OperationRegion(PCI0, SystemMemory, Local7, 4)
> - Field(PCI0, ByteAcc,NoLock,Preserve)
> - {
> - TEMP, 32
> - }
> -
> - Store(Arg5,TEMP)
> - } // End of Method(PEWD,6,Serialized)
> -
> - //
> - // Name: STDC
> - // Description: Function to get Standard Capability Register Offset
> - // Input: Arg0 -> PCIE base address
> - // Arg1 -> Bus
> - // Arg2 -> Device
> - // Arg3 -> Function
> - // Arg4 -> Capability ID
> - // Return: Capability Register Offset data
> - //
> - Method(STDC,5,Serialized)
> - {
> - ADBG("STDC")
> -
> - //Check for Referenced device is present or not
> - Store(PERW(Arg0, Arg1, Arg2, Arg3, 0x00), Local7) //Vendor ID
> register
> - If(LEqual(Local7, 0xFFFF))
> - {
> - ADBG("Referenced device is not present")
> - Return(0)
> - }
> -
> - Store(PERW(Arg0, Arg1, Arg2, Arg3, 0x06), Local0) //Device Status
> register
> - If (LEqual(And(Local0, 16), 0)) //Bit4 - Capabilities List
> - {
> - //No Capabilities linked list is available
> - ADBG("No Capabilities linked list is available")
> - Return(0)
> - }
> -
> - //Local1 is for storing CapabilityID
> - //Local2 is for storing CapabilityPtr
> - Store(PERB(Arg0, Arg1, Arg2, Arg3, 0x34), Local2) //CapabilityPtr
> -
> - While(1)
> - {
> - And(Local2, 0xFC, Local2) //Each capability must be DWORD
> aligned
> -
> - If(LEqual(Local2, 0)) //A pointer value of 00h is used to indicate the
> last capability in the list
> - {
> - ADBG("Capability ID is not found")
> - Return(0)
> - }
> -
> - Store(PERB(Arg0, Arg1, Arg2, Arg3, Local2), Local1) //CapabilityID
> -
> - If(LEqual(Arg4, Local1)) //CapabilityID match
> - {
> - ADBG("Capability ID is found")
> - ADBG("Capability Offset : ")
> - ADBG(Local2)
> - Return(Local2)
> - }
> - Store(PERB(Arg0, Arg1, Arg2, Arg3, Add(Local2, 1)), Local2)
> //CapabilityPtr
> - Return(0)
> - }
> - } // End of Method(STDC,5,Serialized)
> -
> -} // End Scope(\_SB)
> diff --git
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Acpi/TbtNvs.asl
> b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Acpi/TbtNvs.asl
> deleted file mode 100644
> index 706796f8c5..0000000000
> ---
> a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Acpi/TbtNvs.asl
> +++ /dev/null
> @@ -1,56 +0,0 @@
> -/**@file
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> - //
> - // Define TBT NVS Area operation region.
> - //
> - OperationRegion(BNVS,SystemMemory,TNVB,TNVL)
> - Field(BNVS,AnyAcc,Lock,Preserve)
> - { Offset(0), TBSF, 8, // Offset(0), Thunderbolt(TM) SMI
> Function Number
> - Offset(1), SOHP, 8, // Offset(1), SMI on Hot Plug for TBT
> devices
> - Offset(2), TWIN, 8, // Offset(2), TbtWin10Support
> - Offset(3), GP5F, 8, // Offset(3), Gpio filter to detect USB
> Hotplug event
> - Offset(4), NOHP, 8, // Offset(4), Notify on Hot Plug for TBT
> devices
> - Offset(5), TBSE, 8, // Offset(5), Thunderbolt(TM) Root port
> selector
> - Offset(6), WKFN, 8, // Offset(6), WAK Finished
> - Offset(7), TBTS, 8, // Offset(7), Thunderbolt(TM) support
> - Offset(8), TARS, 8, // Offset(8), TbtAcpiRemovalSupport
> - Offset(9), FPEN, 32, // Offset(9), TbtFrcPwrEn
> - Offset(13), FPG0, 32, // Offset(13), TbtFrcPwrGpioNo
> - Offset(17), FP0L, 8, // Offset(17), TbtFrcPwrGpioLevel
> - Offset(18), CPG0, 32, // Offset(18), TbtCioPlugEventGpioNo
> - Offset(22), RSG0, 32, // Offset(22), TbtPcieRstGpioNo
> - Offset(26), RS0L, 8, // Offset(26), TbtPcieRstGpioLevel
> - Offset(27), DTCP, 8, // Offset(27), Current Port that has plug
> event
> - Offset(28), RPS0, 8, // Offset(28), Root port Selected by the
> User
> - Offset(29), RPT0, 8, // Offset(29), Root port Type
> - Offset(30), RPS1, 8, // Offset(30), Root port Selected by the
> User
> - Offset(31), RPT1, 8, // Offset(31), Root port Type
> - Offset(32), RPN0, 8, // Offset(32), Root port Enabled by the
> User
> - Offset(33), RPN1, 8, // Offset(33), Root port Enabled by the
> User
> - Offset(34), FPG1, 32, // Offset(34), TbtFrcPwrGpioNo
> - Offset(38), FP1L, 8, // Offset(38), TbtFrcPwrGpioLevel
> - Offset(39), CPG1, 32, // Offset(39), TbtCioPlugEventGpioNo
> - Offset(43), RSG1, 32, // Offset(43), TbtPcieRstGpioNo
> - Offset(47), RS1L, 8, // Offset(47), TbtPcieRstGpioLevel
> - Offset(48), CGST, 8, // Offset(48), Set if Single GPIO is used for
> Multi/Different Controller Hot plug support
> - Offset(49), DTPT, 8, // Offset(49), Root Port type for which SCI
> Triggered
> - Offset(50), TRWA, 8, // Offset(50), Titan Ridge Osup command
> - Offset(51), ACDC, 8, // Offset(51), TBT Dynamic AcDc L1
> - Offset(52), DT0E, 8, // Offset(52), DTbtController0 is enabled
> or not.
> - Offset(53), DT1E, 8, // Offset(53), DTbtController1 is enabled
> or not.
> - Offset(54), TASP, 8, // Offset(54), ASPM setting for all the PCIe
> device in TBT daisy chain.
> - Offset(55), TL1S, 8, // Offset(55), L1 SubState for for all the
> PCIe device in TBT daisy chain.
> - Offset(56), TCLK, 8, // Offset(56), CLK REQ for all the PCIe
> device in TBT daisy chain.
> - Offset(57), TLTR, 8, // Offset(57), LTR for for all the PCIe device
> in TBT daisy chain.
> - Offset(58), TPTM, 8, // Offset(58), PTM for for all the PCIe
> device in TBT daisy chain.
> - Offset(59), TWAK, 8, // Offset(59), Send Go2SxNoWake or
> GoSxWake according to TbtWakeupSupport
> - Offset(60), TBOD, 16, // Offset(60), Rtd3TbtOffDelay TBT RTD3
> Off Delay
> - Offset(62), TSXW, 8, // Offset(62),
> TbtSxWakeSwitchLogicEnable Set True if TBT_WAKE_N will be routed to PCH
> WakeB at Sx entry point. HW logic is required.
> - Offset(63), RTBT, 8, // Offset(63), Enable Rtd3 support for TBT.
> Corresponding to Rtd3Tbt in Setup.
> - Offset(64), RTBC, 8, // Offset(64), Enable TBT RTD3 CLKREQ
> mask.
> - Offset(65), TBCD, 16, // Offset(65), TBT RTD3 CLKREQ mask delay.
> - }
> \ No newline at end of file
> diff --git a/Platform/Intel/ClevoOpenBoardPkg/Include/Acpi/GlobalNvs.asl
> b/Platform/Intel/ClevoOpenBoardPkg/Include/Acpi/GlobalNvs.asl
> deleted file mode 100644
> index e3b0a1da85..0000000000
> --- a/Platform/Intel/ClevoOpenBoardPkg/Include/Acpi/GlobalNvs.asl
> +++ /dev/null
> @@ -1,114 +0,0 @@
> -/** @file
> - ACPI DSDT table
> -
> -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> - // Define a Global region of ACPI NVS Region that may be used for any
> - // type of implementation. The starting offset and size will be fixed
> - // up by the System BIOS during POST. Note that the Size must be a
> word
> - // in size to be fixed up correctly.
> -
> -
> -
> -
> - OperationRegion(GNVS,SystemMemory,0xFFFF0000,0xAA55)
> - Field(GNVS,AnyAcc,Lock,Preserve)
> - {
> - //
> - // Miscellaneous Dynamic Registers:
> - //
> - Offset(0), OSYS, 16, // Offset(0), Operating System
> - Offset(2), SMIF, 8, // Offset(2), SMI Function Call (ASL to SMI
> via I/O Trap)
> - Offset(3), P80D, 32, // Offset(3), Port 80 Debug Port Value
> - Offset(7), PWRS, 8, // Offset(7), Power State (AC Mode = 1)
> - //
> - // Thermal Policy Registers:
> - //
> - Offset(8), DTSE, 8, // Offset(8), Digital Thermal Sensor Enable
> - Offset(9), DTSF, 8, // Offset(9), DTS SMI Function Call
> - //
> - // CPU Identification Registers:
> - //
> - Offset(10), APIC, 8, // Offset(10), APIC Enabled by SBIOS (APIC
> Enabled = 1)
> - Offset(11), TCNT, 8, // Offset(11), Number of Enabled Threads
> - //
> - // PCIe Hot Plug
> - //
> - Offset(12), OSCC, 8, // Offset(12), PCIE OSC Control
> - Offset(13), NEXP, 8, // Offset(13), Native PCIE Setup Value
> - //
> - // Global Variables
> - //
> - Offset(14), DSEN, 8, // Offset(14), _DOS Display Support Flag.
> - Offset(15), GPIC, 8, // Offset(15), Global IOAPIC/8259 Interrupt
> Mode Flag.
> - Offset(16), L01C, 8, // Offset(16), Global L01 Counter.
> - Offset(17), LTR1, 8, // Offset(17), Latency Tolerance Reporting
> Enable
> - Offset(18), LTR2, 8, // Offset(18), Latency Tolerance Reporting
> Enable
> - Offset(19), LTR3, 8, // Offset(19), Latency Tolerance Reporting
> Enable
> - Offset(20), LTR4, 8, // Offset(20), Latency Tolerance Reporting
> Enable
> - Offset(21), LTR5, 8, // Offset(21), Latency Tolerance Reporting
> Enable
> - Offset(22), LTR6, 8, // Offset(22), Latency Tolerance Reporting
> Enable
> - Offset(23), LTR7, 8, // Offset(23), Latency Tolerance Reporting
> Enable
> - Offset(24), LTR8, 8, // Offset(24), Latency Tolerance Reporting
> Enable
> - Offset(25), LTR9, 8, // Offset(25), Latency Tolerance Reporting
> Enable
> - Offset(26), LTRA, 8, // Offset(26), Latency Tolerance Reporting
> Enable
> - Offset(27), LTRB, 8, // Offset(27), Latency Tolerance Reporting
> Enable
> - Offset(28), LTRC, 8, // Offset(28), Latency Tolerance Reporting
> Enable
> - Offset(29), LTRD, 8, // Offset(29), Latency Tolerance Reporting
> Enable
> - Offset(30), LTRE, 8, // Offset(30), Latency Tolerance Reporting
> Enable
> - Offset(31), LTRF, 8, // Offset(31), Latency Tolerance Reporting
> Enable
> - Offset(32), LTRG, 8, // Offset(32), Latency Tolerance Reporting
> Enable
> - Offset(33), LTRH, 8, // Offset(33), Latency Tolerance Reporting
> Enable
> - Offset(34), LTRI, 8, // Offset(34), Latency Tolerance Reporting
> Enable
> - Offset(35), LTRJ, 8, // Offset(35), Latency Tolerance Reporting
> Enable
> - Offset(36), LTRK, 8, // Offset(36), Latency Tolerance Reporting
> Enable
> - Offset(37), LTRL, 8, // Offset(37), Latency Tolerance Reporting
> Enable
> - Offset(38), LTRM, 8, // Offset(38), Latency Tolerance Reporting
> Enable
> - Offset(39), LTRN, 8, // Offset(39), Latency Tolerance Reporting
> Enable
> - Offset(40), LTRO, 8, // Offset(40), Latency Tolerance Reporting
> Enable
> - Offset(41), OBF1, 8, // Offset(41), Optimized Buffer Flush and
> Fill
> - Offset(42), OBF2, 8, // Offset(42), Optimized Buffer Flush and
> Fill
> - Offset(43), OBF3, 8, // Offset(43), Optimized Buffer Flush and
> Fill
> - Offset(44), OBF4, 8, // Offset(44), Optimized Buffer Flush and
> Fill
> - Offset(45), OBF5, 8, // Offset(45), Optimized Buffer Flush and
> Fill
> - Offset(46), OBF6, 8, // Offset(46), Optimized Buffer Flush and
> Fill
> - Offset(47), OBF7, 8, // Offset(47), Optimized Buffer Flush and
> Fill
> - Offset(48), OBF8, 8, // Offset(48), Optimized Buffer Flush and
> Fill
> - Offset(49), OBF9, 8, // Offset(49), Optimized Buffer Flush and
> Fill
> - Offset(50), OBFA, 8, // Offset(50), Optimized Buffer Flush and
> Fill
> - Offset(51), OBFB, 8, // Offset(51), Optimized Buffer Flush and
> Fill
> - Offset(52), OBFC, 8, // Offset(52), Optimized Buffer Flush and
> Fill
> - Offset(53), OBFD, 8, // Offset(53), Optimized Buffer Flush and
> Fill
> - Offset(54), OBFE, 8, // Offset(54), Optimized Buffer Flush and
> Fill
> - Offset(55), OBFF, 8, // Offset(55), Optimized Buffer Flush and
> Fill
> - Offset(56), OBFG, 8, // Offset(56), Optimized Buffer Flush and
> Fill
> - Offset(57), OBFH, 8, // Offset(57), Optimized Buffer Flush and
> Fill
> - Offset(58), OBFI, 8, // Offset(58), Optimized Buffer Flush and
> Fill
> - Offset(59), OBFJ, 8, // Offset(59), Optimized Buffer Flush and
> Fill
> - Offset(60), OBFK, 8, // Offset(60), Optimized Buffer Flush and
> Fill
> - Offset(61), OBFL, 8, // Offset(61), Optimized Buffer Flush and
> Fill
> - Offset(62), OBFM, 8, // Offset(62), Optimized Buffer Flush and
> Fill
> - Offset(63), OBFN, 8, // Offset(63), Optimized Buffer Flush and
> Fill
> - Offset(64), OBFO, 8, // Offset(64), Optimized Buffer Flush and
> Fill
> - Offset(65), RTD3, 8, // Offset(65), Runtime D3 support.
> - Offset(66), S0ID, 8, // Offset(66), Low Power S0 Idle Enable
> - Offset(67), GBSX, 8, // Offset(67), Virtual GPIO button Notify
> Sleep State Change
> - Offset(68), PSCP, 8, // Offset(68), P-state Capping
> - Offset(69), P2ME, 8, // Offset(69), Ps2 Mouse Enable
> - Offset(70), P2MK, 8, // Offset(70), Ps2 Keyboard and Mouse
> Enable
> - //
> - // Driver Mode
> - //
> - Offset(71), GIRQ, 32, // Offset(71), GPIO IRQ
> - Offset(75), PLCS, 8, // Offset(75), set PL1 limit when entering
> CS
> - Offset(76), PLVL, 16, // Offset(76), PL1 limit value
> - Offset(78), PB1E, 8, // Offset(78), 10sec Power button support
> - Offset(79), ECR1, 8, // Offset(79), Pci Delay Optimization Ecr
> - Offset(80), TBTS, 8, // Offset(80), Thunderbolt(TM) support
> - Offset(81), TNAT, 8, // Offset(81), TbtNativeOsHotPlug
> - Offset(82), TBSE, 8, // Offset(82), Thunderbolt(TM) Root port
> selector
> - Offset(83), TBS1, 8, // Offset(83), Thunderbolt(TM) Root port
> selector
> - }
> diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/build_config.cfg
> b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/build_config.cfg
> deleted file mode 100644
> index 3edc2b14e8..0000000000
> --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/build_config.cfg
> +++ /dev/null
> @@ -1,33 +0,0 @@
> -# @ build_config.cfg
> -# This is the N1xxWU board specific build settings
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -
> -
> -[CONFIG]
> -WORKSPACE_PLATFORM_BIN =
> edk2-non-osi/Platform/Intel/ClevoOpenBoardBinPkg
> -EDK_SETUP_OPTION =
> -openssl_path =
> -PLATFORM_BOARD_PACKAGE = ClevoOpenBoardPkg
> -PROJECT = ClevoOpenBoardPkg/N1xxWU
> -BOARD = N1xxWU
> -FLASH_MAP_FDF =
> ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclude.fdf
> -PROJECT_DSC = ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc
> -BOARD_PKG_PCD_DSC =
> ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc
> -PrepRELEASE = DEBUG
> -SILENT_MODE = FALSE
> -EXT_CONFIG_CLEAR =
> -CapsuleBuild = FALSE
> -EXT_BUILD_FLAGS =
> -CAPSULE_BUILD = 0
> -TARGET = DEBUG
> -TARGET_SHORT = D
> -PERFORMANCE_BUILD = FALSE
> -FSP_WRAPPER_BUILD = TRUE
> -FSP_BIN_PKG = KabylakeFspBinPkg
> -FSP_PKG_NAME = KabylakeFspPkg
> -FSP_BINARY_BUILD = FALSE
> -FSP_TEST_RELEASE = FALSE
> -SECURE_BOOT_ENABLE = FALSE
> --
> 2.16.2.windows.1
>
>
>
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