[edk2-devel] [edk2-platforms][PATCH v1 4/4] Platform/ARM/N1SDP: Enable devices connected over PCIe
Pranav Madhu
pranav.madhu at arm.com
Fri Apr 24 11:58:29 UTC 2020
From: Deepak Pandey <deepak.pandey at arm.com>
N1SDP platform includes a PCIe root complex to which a AHCI, GbE and
USB controllers are attached as an endpoint. So implement the
PciHostBridgeLib glue layer and enable support for PCIe controller
and all the devices connected over the PCIe bus.
Signed-off-by: Pranav Madhu <pranav.madhu at arm.com>
---
Platform/ARM/N1SdpPkg/N1SdpPlatform.dec | 20 +++
Platform/ARM/N1SdpPkg/N1SdpPlatform.dsc | 35 ++++
Platform/ARM/N1SdpPkg/N1SdpPlatform.fdf | 22 +++
Platform/ARM/N1SdpPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 49 +++++
Platform/ARM/N1SdpPkg/Library/PlatformLib/PlatformLib.inf | 12 ++
Platform/ARM/N1SdpPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c | 187 ++++++++++++++++++++
Platform/ARM/N1SdpPkg/Library/PlatformLib/PlatformLibMem.c | 28 ++-
7 files changed, 352 insertions(+), 1 deletion(-)
diff --git a/Platform/ARM/N1SdpPkg/N1SdpPlatform.dec b/Platform/ARM/N1SdpPkg/N1SdpPlatform.dec
index c8efe7b31d51..eebc62fea23b 100644
--- a/Platform/ARM/N1SdpPkg/N1SdpPlatform.dec
+++ b/Platform/ARM/N1SdpPkg/N1SdpPlatform.dec
@@ -24,6 +24,26 @@ [Guids.common]
[PcdsFixedAtBuild]
+ # PCIe
+ gArmN1SdpTokenSpaceGuid.PcdPcieBusCount|18|UINT32|0x00000004
+ gArmN1SdpTokenSpaceGuid.PcdPcieBusMax|17|UINT32|0x00000005
+ gArmN1SdpTokenSpaceGuid.PcdPcieBusMin|0|UINT32|0x00000006
+ gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000|UINT32|0x00000007
+ gArmN1SdpTokenSpaceGuid.PcdPcieIoBase|0x0|UINT32|0x00000008
+ gArmN1SdpTokenSpaceGuid.PcdPcieIoMaxBase|0x00FFFFFF|UINT32|0x00000009
+ gArmN1SdpTokenSpaceGuid.PcdPcieIoSize|0x01000000|UINT32|0x0000000A
+ gArmN1SdpTokenSpaceGuid.PcdPcieIoTranslation|0x75200000|UINT32|0x0000000B
+ gArmN1SdpTokenSpaceGuid.PcdPcieMmio32Base|0x71200000|UINT32|0x0000000C
+ gArmN1SdpTokenSpaceGuid.PcdPcieMmio32MaxBase|0x751FFFFF|UINT32|0x0000000D
+ gArmN1SdpTokenSpaceGuid.PcdPcieMmio32Size|0x04000000|UINT32|0x0000000E
+ gArmN1SdpTokenSpaceGuid.PcdPcieMmio32Translation|0x0|UINT32|0x0000000F
+ gArmN1SdpTokenSpaceGuid.PcdPcieMmio64Base|0x0900000000|UINT64|0x00000010
+ gArmN1SdpTokenSpaceGuid.PcdPcieMmio64MaxBase|0x28FFFFFFFF|UINT64|0x00000011
+ gArmN1SdpTokenSpaceGuid.PcdPcieMmio64Size|0x2000000000|UINT64|0x00000012
+ gArmN1SdpTokenSpaceGuid.PcdPcieMmio64Translation|0x0|UINT64|0x00000013
+ gArmN1SdpTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress|0x60000000|UINT32|0x00000014
+ gArmN1SdpTokenSpaceGuid.PcdPcieRootPortConfigBaseSize|0x00001000|UINT32|0x00000015
+
# Secondary DDR memory
gArmN1SdpTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x00000001
diff --git a/Platform/ARM/N1SdpPkg/N1SdpPlatform.dsc b/Platform/ARM/N1SdpPkg/N1SdpPlatform.dsc
index 53be9699d99e..3ee524349281 100644
--- a/Platform/ARM/N1SdpPkg/N1SdpPlatform.dsc
+++ b/Platform/ARM/N1SdpPkg/N1SdpPlatform.dsc
@@ -35,6 +35,9 @@ [LibraryClasses.common]
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+ #USB Requirement
+ UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+
[LibraryClasses.common.SEC]
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
@@ -86,6 +89,9 @@ [LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION, Libr
#
################################################################################
+[PcdsFeatureFlag.common]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
+
[PcdsFixedAtBuild.common]
gArmTokenSpaceGuid.PcdVFPEnabled|1
@@ -109,6 +115,10 @@ [PcdsFixedAtBuild.common]
gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000
gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000
+ # PCIe
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
+
# PL011 - Serial Terminal
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x2A400000
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
@@ -202,6 +212,9 @@ [Components.common]
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
}
+ # Human Interface Support
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
# FAT filesystem + GPT/MBR partitioning
MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
@@ -221,6 +234,28 @@ [Components.common]
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
}
+ # Required by PCI
+ ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+
+ # PCI Support
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
+ }
+
# AHCI Support
MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+ # SATA Controller
+ MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+
+ # Usb Support
+ MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+ MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+ MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
diff --git a/Platform/ARM/N1SdpPkg/N1SdpPlatform.fdf b/Platform/ARM/N1SdpPkg/N1SdpPlatform.fdf
index f2fee1c4d467..1d86e92cafa8 100644
--- a/Platform/ARM/N1SdpPkg/N1SdpPlatform.fdf
+++ b/Platform/ARM/N1SdpPkg/N1SdpPlatform.fdf
@@ -92,10 +92,32 @@ [FV.FvMain]
INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ # Human Interface Support
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+ # Required by PCI
+ INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+
+ # PCI Support
+ INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+ INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+
# AHCI Support
INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ # SATA Controller
+ INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+
+ # Usb Support
+ INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+ INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+
# Multiple Console IO support
INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
diff --git a/Platform/ARM/N1SdpPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Platform/ARM/N1SdpPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
new file mode 100644
index 000000000000..504e05ea2c83
--- /dev/null
+++ b/Platform/ARM/N1SdpPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
@@ -0,0 +1,49 @@
+## @file
+# PCI Host Bridge Library instance for ARM N1SDP platform.
+#
+# Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = PciHostBridgeLib
+ FILE_GUID = 6879CEAD-DC94-42EB-895C-096D36B8083C
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PciHostBridgeLib|DXE_DRIVER
+
+[Sources]
+ PciHostBridgeLib.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Platform/ARM/N1SdpPkg/N1SdpPlatform.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ DevicePathLib
+ IoLib
+ MemoryAllocationLib
+ UefiBootServicesTableLib
+
+[FixedPcd]
+ gArmN1SdpTokenSpaceGuid.PcdPcieBusMin
+ gArmN1SdpTokenSpaceGuid.PcdPcieBusMax
+ gArmN1SdpTokenSpaceGuid.PcdPcieIoBase
+ gArmN1SdpTokenSpaceGuid.PcdPcieIoSize
+ gArmN1SdpTokenSpaceGuid.PcdPcieMmio32Base
+ gArmN1SdpTokenSpaceGuid.PcdPcieMmio32Size
+ gArmN1SdpTokenSpaceGuid.PcdPcieMmio64Base
+ gArmN1SdpTokenSpaceGuid.PcdPcieMmio64Size
+
+[Protocols]
+ gEfiCpuIo2ProtocolGuid
+
+[Depex]
+ gEfiCpuIo2ProtocolGuid
diff --git a/Platform/ARM/N1SdpPkg/Library/PlatformLib/PlatformLib.inf b/Platform/ARM/N1SdpPkg/Library/PlatformLib/PlatformLib.inf
index 1ba29657cbf6..8e4c5e9f0579 100644
--- a/Platform/ARM/N1SdpPkg/Library/PlatformLib/PlatformLib.inf
+++ b/Platform/ARM/N1SdpPkg/Library/PlatformLib/PlatformLib.inf
@@ -40,10 +40,22 @@ [Sources.AARCH64]
[FixedPcd]
gArmTokenSpaceGuid.PcdSystemMemoryBase
gArmTokenSpaceGuid.PcdSystemMemorySize
+ gArmTokenSpaceGuid.PcdFvBaseAddress
gArmTokenSpaceGuid.PcdArmPrimaryCore
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+ gArmN1SdpTokenSpaceGuid.PcdPcieBusMax
+ gArmN1SdpTokenSpaceGuid.PcdPcieBusMin
+ gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress
+ gArmN1SdpTokenSpaceGuid.PcdPcieMmio32Base
+ gArmN1SdpTokenSpaceGuid.PcdPcieMmio32Size
+ gArmN1SdpTokenSpaceGuid.PcdPcieMmio64Base
+ gArmN1SdpTokenSpaceGuid.PcdPcieMmio64Size
+ gArmN1SdpTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress
+ gArmN1SdpTokenSpaceGuid.PcdPcieRootPortConfigBaseSize
+
gArmN1SdpTokenSpaceGuid.PcdDramBlock2Base
+ gArmN1SdpTokenSpaceGuid.PcdExtMemorySpace
[Guids]
gEfiHobListGuid ## CONSUMES ## SystemTable
diff --git a/Platform/ARM/N1SdpPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Platform/ARM/N1SdpPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
new file mode 100644
index 000000000000..cfc6de23b897
--- /dev/null
+++ b/Platform/ARM/N1SdpPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
@@ -0,0 +1,187 @@
+/** @file
+* PCI Host Bridge Library instance for ARM N1SDP platform
+*
+* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <PiDxe.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciHostBridgeLib.h>
+#include <Protocol/PciHostBridgeResourceAllocation.h>
+#include <Protocol/PciRootBridgeIo.h>
+
+GLOBAL_REMOVE_IF_UNREFERENCED
+STATIC CHAR16 CONST * CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
+ L"Mem", L"I/O", L"Bus"
+};
+
+#pragma pack (1)
+typedef struct {
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
+#pragma pack ()
+
+STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
+ // PCIe
+ {
+ {
+ {
+ ACPI_DEVICE_PATH,
+ ACPI_DP,
+ {
+ (UINT8)sizeof (ACPI_HID_DEVICE_PATH),
+ (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
+ }
+ },
+ EISA_PNP_ID (0x0A08), // PCIe
+ 0
+ },
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+ }
+};
+
+STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = {
+ {
+ 0, // Segment
+ 0, // Supports
+ 0, // Attributes
+ TRUE, // DmaAbove4G
+ FALSE, // NoExtendedConfigSpace
+ FALSE, // ResourceAssigned
+ EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+ {
+ // Bus
+ FixedPcdGet32 (PcdPcieBusMin),
+ FixedPcdGet32 (PcdPcieBusMax)
+ }, {
+ // Io
+ FixedPcdGet64 (PcdPcieIoBase),
+ FixedPcdGet64 (PcdPcieIoBase) + FixedPcdGet64 (PcdPcieIoSize) - 1
+ }, {
+ // Mem
+ FixedPcdGet32 (PcdPcieMmio32Base),
+ FixedPcdGet32 (PcdPcieMmio32Base) + FixedPcdGet32 (PcdPcieMmio32Size) - 1
+ }, {
+ // MemAbove4G
+ FixedPcdGet64 (PcdPcieMmio64Base),
+ FixedPcdGet64 (PcdPcieMmio64Base) + FixedPcdGet64 (PcdPcieMmio64Size) - 1
+ }, {
+ // PMem
+ MAX_UINT64,
+ 0
+ }, {
+ // PMemAbove4G
+ MAX_UINT64,
+ 0
+ },
+ (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0]
+ }
+};
+
+/**
+ Return all the root bridge instances in an array.
+
+ @param Count Return the count of root bridge instances.
+
+ @return All the root bridge instances in an array.
+ The array should be passed into PciHostBridgeFreeRootBridges()
+ when it's not used.
+**/
+PCI_ROOT_BRIDGE *
+EFIAPI
+PciHostBridgeGetRootBridges (
+ UINTN *Count
+ )
+{
+ *Count = ARRAY_SIZE (mPciRootBridge);
+ return mPciRootBridge;
+}
+
+/**
+ Free the root bridge instances array returned from PciHostBridgeGetRootBridges().
+
+ @param Bridges The root bridge instances array.
+ @param Count The count of the array.
+**/
+VOID
+EFIAPI
+PciHostBridgeFreeRootBridges (
+ PCI_ROOT_BRIDGE *Bridges,
+ UINTN Count
+ )
+{
+}
+
+/**
+ Inform the platform that the resource conflict happens.
+
+ @param HostBridgeHandle Handle of the Host Bridge.
+ @param Configuration Pointer to PCI I/O and PCI memory resource
+ descriptors. The Configuration contains the resources
+ for all the root bridges. The resource for each root
+ bridge is terminated with END descriptor and an
+ additional END is appended indicating the end of the
+ entire resources. The resource descriptor field
+ values follow the description in
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\
+ SubmitResources().
+**/
+VOID
+EFIAPI
+PciHostBridgeResourceConflict (
+ EFI_HANDLE HostBridgeHandle,
+ VOID *Configuration
+ )
+{
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+ UINTN RootBridgeIndex = 0;
+
+ DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happened!\n"));
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
+
+ while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
+ DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
+
+ for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
+ ASSERT (Descriptor->ResType <
+ (sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr) /
+ sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr[0])
+ )
+ );
+ DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
+ mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
+ Descriptor->AddrLen, Descriptor->AddrRangeMax
+ ));
+ if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
+ DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n",
+ Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
+ ((Descriptor->SpecificFlag &
+ EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
+ ) != 0) ? L" (Prefetchable)" : L""
+ ));
+ }
+ }
+ //
+ // Skip the END descriptor for root bridge
+ //
+ ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
+ (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
+ );
+ }
+}
diff --git a/Platform/ARM/N1SdpPkg/Library/PlatformLib/PlatformLibMem.c b/Platform/ARM/N1SdpPkg/Library/PlatformLib/PlatformLibMem.c
index 7fae090cdb8d..693c9469ab33 100644
--- a/Platform/ARM/N1SdpPkg/Library/PlatformLib/PlatformLibMem.c
+++ b/Platform/ARM/N1SdpPkg/Library/PlatformLib/PlatformLibMem.c
@@ -15,7 +15,7 @@
#include <N1SdpPlatform.h>
// The total number of descriptors, including the final "end-of-table" descriptor.
-#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 9
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 13
/**
Returns the Virtual Memory Map of the platform.
@@ -90,6 +90,32 @@ ArmPlatformGetVirtualMemoryMap (
VirtualMemoryTable[Index].Length = N1SDP_NON_SECURE_SRAM_SZ;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+ // PCIe RC Configuration Space
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdPcieRootPortConfigBaseAddress);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdPcieRootPortConfigBaseAddress);
+ VirtualMemoryTable[Index].Length = PcdGet32 (PcdPcieRootPortConfigBaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe ECAM Configuration Space
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdPcieExpressBaseAddress);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdPcieExpressBaseAddress);
+ VirtualMemoryTable[Index].Length = (FixedPcdGet32 (PcdPcieBusMax) -
+ FixedPcdGet32 (PcdPcieBusMin) + 1) *
+ SIZE_1MB;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe MMIO32 Memory Space
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdPcieMmio32Base);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdPcieMmio32Base);
+ VirtualMemoryTable[Index].Length = PcdGet32 (PcdPcieMmio32Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe MMIO64 Memory Space
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPcieMmio64Base);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPcieMmio64Base);
+ VirtualMemoryTable[Index].Length = PcdGet64 (PcdPcieMmio64Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
// SubSystem Pheripherals - UART0
VirtualMemoryTable[++Index].PhysicalBase = N1SDP_UART0_BASE;
VirtualMemoryTable[Index].VirtualBase = N1SDP_UART0_BASE;
--
2.7.4
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