[edk2-devel] [edk2-platforms] [PATCH v2 4/5] Platform/ARM/Sgi: Add ACPI tables for dual-chip RD-N1-Edge platform
Vijayenthiran Subramaniam
vijayenthiran.subramaniam at arm.com
Wed Feb 12 13:29:26 UTC 2020
RD-N1-Edge supports a dual-chip configuration in which two RD-N1-Edge
platforms are connected through high speed CCIX link. In this dual-chip
configuration, the CPU and core GIC Redistributors count are doubled.
Add ACPI tables for dual-chip RD-N1-Edge platform.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam at arm.com>
---
Platform/ARM/SgiPkg/SgiPlatform.dec | 1 +
Platform/ARM/SgiPkg/SgiPlatform.dsc | 1 +
Platform/ARM/SgiPkg/SgiPlatform.fdf | 1 +
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf | 59 ++++++
Platform/ARM/SgiPkg/Include/SgiPlatform.h | 3 +
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc | 198 ++++++++++++++++++++
6 files changed, 263 insertions(+)
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec b/Platform/ARM/SgiPkg/SgiPlatform.dec
index 229552ea7842..9d70ec677776 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dec
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
@@ -28,6 +28,7 @@ [Guids.common]
gArmSgiTokenSpaceGuid = { 0x577d6941, 0xaea1, 0x40b4, { 0x90, 0x93, 0x2a, 0x86, 0x61, 0x72, 0x5a, 0x57 } }
gSgi575AcpiTablesFileGuid = { 0xc712719a, 0x0aaf, 0x438c, { 0x9c, 0xdd, 0x35, 0xab, 0x4d, 0x60, 0x20, 0x7d } }
gRdN1EdgeAcpiTablesFileGuid = { 0x4b0b91d0, 0x4a05, 0x45c4, { 0x88, 0xa7, 0x88, 0xe1, 0x70, 0xe7, 0x66, 0x94 } }
+ gRdN1EdgeX2AcpiTablesFileGuid = { 0x82a34150, 0x0fc6, 0x45f4, { 0x8e, 0xa0, 0xf0, 0xa4, 0x66, 0x0c, 0xf3, 0x5d } }
gRdE1EdgeAcpiTablesFileGuid = { 0x2af40815, 0xa84e, 0x4de9, { 0x8c, 0x38, 0x91, 0x40, 0xb3, 0x54, 0x40, 0x73 } }
[PcdsFeatureFlag.common]
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc b/Platform/ARM/SgiPkg/SgiPlatform.dsc
index e38cc7da52a5..5226c5751e98 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dsc
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc
@@ -279,6 +279,7 @@ [Components.common]
MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
+ Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.fdf b/Platform/ARM/SgiPkg/SgiPlatform.fdf
index 44e571a184bf..3d13998015b9 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.fdf
+++ b/Platform/ARM/SgiPkg/SgiPlatform.fdf
@@ -101,6 +101,7 @@ [FV.FvMain]
INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
INF RuleOverride=ACPITABLE Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf
INF RuleOverride=ACPITABLE Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
+ INF RuleOverride=ACPITABLE Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
INF RuleOverride=ACPITABLE Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
new file mode 100644
index 000000000000..1b584b152455
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
@@ -0,0 +1,59 @@
+## @file
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (c) 2020, ARM Ltd. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = RdN1EdgeX2AcpiTables
+ FILE_GUID = 82a34150-0fc6-45f4-8ea0-f0a4660cf35d
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Dbg2.aslc
+ Fadt.aslc
+ Gtdt.aslc
+ Iort.aslc
+ Mcfg.aslc
+ RdN1Edge/Dsdt.asl
+ RdN1EdgeX2/Madt.aslc
+ Spcr.aslc
+ Ssdt.asl
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ Platform/ARM/SgiPkg/SgiPlatform.dec
+
+[FixedPcd]
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+ gArmPlatformTokenSpaceGuid.PcdClusterCount
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
+ gArmPlatformTokenSpaceGuid.PL011UartInterrupt
+
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+ gArmTokenSpaceGuid.PcdPciBusMin
+ gArmTokenSpaceGuid.PcdPciBusMax
+
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkSize
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt
+ gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress
+ gArmSgiTokenSpaceGuid.PcdVirtioNetSize
+ gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt
+
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
diff --git a/Platform/ARM/SgiPkg/Include/SgiPlatform.h b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
index 7c9322d1cda9..e36a412155ff 100644
--- a/Platform/ARM/SgiPkg/Include/SgiPlatform.h
+++ b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
@@ -82,6 +82,9 @@
#define MULTI_CHIP_MODE_DISABLED 0x0
#define MULTI_CHIP_MODE_ENABLED 0x1
+// Remote chip address offset (4TB per chip)
+#define SGI_REMOTE_CHIP_MEM_OFFSET(n) ((1ULL << 42) * (n))
+
// ARM platform description data.
typedef struct {
UINTN PlatformId;
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc
new file mode 100644
index 000000000000..d4538233d760
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc
@@ -0,0 +1,198 @@
+/** @file
+* Multiple APIC Description Table (MADT)
+*
+* Copyright (c) 2019, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+
+#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
+ FixedPcdGet32 (PcdCoreCount))
+
+#define CHIP_CNT 2
+
+// EFI_ACPI_6_2_GIC_STRUCTURE
+#define EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, \
+ PmuIrq, GicBase, GicVBase, GicHBase, GsivId, GicRBase, Efficiency) \
+ { \
+ EFI_ACPI_6_2_GIC, /* Type */ \
+ sizeof (EFI_ACPI_6_2_GIC_STRUCTURE), /* Length */ \
+ EFI_ACPI_RESERVED_WORD, /* Reserved */ \
+ GicId, /* CPUInterfaceNumber */ \
+ AcpiCpuUid, /* AcpiProcessorUid */ \
+ Flags, /* Flags */ \
+ 0, /* ParkingProtocolVersion */ \
+ PmuIrq, /* PerformanceInterruptGsiv */ \
+ 0, /* ParkedAddress */ \
+ GicBase, /* PhysicalBaseAddress */ \
+ GicVBase, /* GICV */ \
+ GicHBase, /* GICH */ \
+ GsivId, /* VGICMaintenanceInterrupt */ \
+ GicRBase, /* GICRBaseAddress */ \
+ Mpidr, /* MPIDR */ \
+ Efficiency, /* ProcessorPowerEfficiencyClass */ \
+ { \
+ EFI_ACPI_RESERVED_BYTE, /* Reserved2[0] */ \
+ EFI_ACPI_RESERVED_BYTE, /* Reserved2[1] */ \
+ EFI_ACPI_RESERVED_BYTE /* Reserved2[2] */ \
+ } \
+ }
+
+// EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE
+#define EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(GicDistHwId, GicDistBase, \
+ GicDistVector, GicVersion) \
+ { \
+ EFI_ACPI_6_2_GICD, /* Type */ \
+ sizeof (EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE), \
+ EFI_ACPI_RESERVED_WORD, /* Reserved1 */ \
+ GicDistHwId, /* GicId */ \
+ GicDistBase, /* PhysicalBaseAddress */ \
+ GicDistVector, /* SystemVectorBase */ \
+ GicVersion, /* GicVersion */ \
+ { \
+ EFI_ACPI_RESERVED_BYTE, /* Reserved2[0] */ \
+ EFI_ACPI_RESERVED_BYTE, /* Reserved2[1] */ \
+ EFI_ACPI_RESERVED_BYTE /* Reserved2[2] */ \
+ } \
+ }
+
+// EFI_ACPI_6_2_GICR_STRUCTURE
+#define EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(RedisRegionAddr, RedisDiscLength) \
+ { \
+ EFI_ACPI_6_2_GICR, /* Type */ \
+ sizeof (EFI_ACPI_6_2_GICR_STRUCTURE), /* Length */ \
+ EFI_ACPI_RESERVED_WORD, /* Reserved */ \
+ RedisRegionAddr, /* DiscoveryRangeBaseAddress */ \
+ RedisDiscLength /* DiscoveryRangeLength */ \
+ }
+
+// Multiple APIC Description Table
+#pragma pack (1)
+
+typedef struct {
+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE_CNT * CHIP_CNT];
+ EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor[CHIP_CNT];
+} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ ),
+ // MADT specific fields
+ 0, // LocalApicAddress
+ 0 // Flags
+ },
+ {
+ // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
+ // PmuIrq, GicBase, GicVBase,
+ // GicHBase, GsivId, GicRBase,
+ // Efficiency)
+ // Note: The GIC Structure of the primary CPU must be the first entry
+ // (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
+
+ // Chip - 0 CPUs
+
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-1
+ 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-2
+ 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-3
+ 0, 3, GET_MPID(0x0, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-4
+ 0, 4, GET_MPID(0x100, 0x00), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-5
+ 0, 5, GET_MPID(0x100, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-6
+ 0, 6, GET_MPID(0x100, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-7
+ 0, 7, GET_MPID(0x100, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+
+ // Chip - 1 CPUs
+
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-8
+ 0, 8, GET_MPID(0x01000000ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-9
+ 0, 9, GET_MPID(0x01000000ULL, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-10
+ 0, 10, GET_MPID(0x01000000ULL, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-11
+ 0, 11, GET_MPID(0x01000000ULL, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-12
+ 0, 12, GET_MPID(0x01000100ULL, 0x00ULL), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-13
+ 0, 13, GET_MPID(0x01000100ULL, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-14
+ 0, 14, GET_MPID(0x01000100ULL, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-15
+ 0, 15, GET_MPID(0x01000100ULL, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */)
+ },
+ // GIC Distributor Entry
+ EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
+ 0, 3),
+ {
+ // GIC Redistributor for Chip 0
+ EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
+ SIZE_1MB),
+ // GIC Redistributor for Chip 1
+ EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase)
+ + SGI_REMOTE_CHIP_MEM_OFFSET(1),
+ SIZE_1MB)
+ }
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing
+// the data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Madt;
--
2.7.4
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