[edk2-devel] [edk2-platforms] [PATCH v2 4/4] WhiskeylakeOpenBoardPkg/UpXtreme: Add DSC and build files
Chiu, Chasel
chasel.chiu at intel.com
Fri Feb 14 06:09:29 UTC 2020
Reviewed-by: Chasel Chiu <chasel.chiu at intel.com>
> -----Original Message-----
> From: Agyeman, Prince <prince.agyeman at intel.com>
> Sent: Friday, February 14, 2020 1:55 AM
> To: devel at edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu at intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone at intel.com>
> Subject: [edk2-platforms] [PATCH v2 4/4]
> WhiskeylakeOpenBoardPkg/UpXtreme: Add DSC and build files
>
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2191
>
> Adds the DSC and build files necessary to build the
> UpXtreme board instance.
>
> Key files
> =========
> * build_config.cfg - Board-specific build configuration file.
> * OpenBoardPkg.dsc - The UpXtreme board description file.
> * OpenBoardPkgPcd.dsc - Used for other PCD customization.
> * OpenBoardPkg.fdf - The UpXtreme board flash file.
> * OpenBoardPkgBuildOption.dsc - Sets build options Based
> on PCD values.
>
> Co-authored-by: Michael Kubacki <michael.a.kubacki at intel.com>
> Cc: Chasel Chiu <chasel.chiu at intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone at intel.com>
> Signed-off-by: Prince Agyeman <prince.agyeman at intel.com>
> ---
> Platform/Intel/Readme.md | 19 +-
> .../UpXtreme/OpenBoardPkg.dsc | 448 +++++++++++
> .../UpXtreme/OpenBoardPkg.fdf | 708
> ++++++++++++++++++
> .../UpXtreme/OpenBoardPkgBuildOption.dsc | 154 ++++
> .../UpXtreme/OpenBoardPkgPcd.dsc | 409 ++++++++++
> .../UpXtreme/build_config.cfg | 35 +
> Platform/Intel/build.cfg | 1 +
> 7 files changed, 1772 insertions(+), 2 deletions(-)
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.dsc
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgBuildOpt
> ion.dsc
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/build_config.cfg
>
> diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md
> index 02d9517d19..55cf02a8ca 100644
> --- a/Platform/Intel/Readme.md
> +++ b/Platform/Intel/Readme.md
> @@ -59,6 +59,12 @@ A UEFI firmware implementation using MinPlatformPkg
> is constructed using the fol
>
> ### **Supported Hardware**
>
> +#### AAEON
> +
> +| Machine Name | Supported Chipsets
> | BoardPkg | Board Name |
> +----------------------------------------|--------------------------------------------|------------
> ------------------|--------------------|
> +| UP Xtreme | Whiskey Lake
> | WhiskeylakeOpenBoardPkg | UpXtreme |
> +
> #### Intel
>
> ***Intel Reference and Validation Platform***
> @@ -233,6 +239,9 @@ return back to the minimum platform caller.
> | | |
> build settings, environment variables.
> | | |
> | | |------WhiskeylakeOpenBoardPkg
> + | | | |------UpXtreme
> + | | | |---build_config.cfg:
> UpXtreme specific build
> + | | |
> settings environment variables.
> | | | |------WhiskeylakeURvp
> | | | |---build_config.cfg:
> WhiskeylakeURvp specific build
> | | |
> settings environment variables.
> @@ -254,8 +263,14 @@ return back to the minimum platform caller.
> 1. This firmware project has only been tested booting to Microsoft Windows
> 10 x64 and Ubuntu 17.10 with AHCI mode.
>
> **WhiskeylakeOpenBoardPkg**
> -1. This firmware project has only been tested booting to Microsoft Windows
> 10 x64 with AHCI mode and Integrated Graphic
> +1. This firmware project has mainly been tested booting to Microsoft
> Windows 10 x64 with AHCI mode and Integrated Graphic
> Device.
> +2. UP Xtreme boards might hang during Windows 10 boot.
> +3. Not all UP Xtreme boards are supported at this time.
> + * The model below boots to x64 windows 10 home edition and Ubuntu
> 18.04
> + * Xtreme Intel(R) Core(TM) i3-8145UE CPU @ 2.20GHz with 8GB RAM
> + * Xtreme Intel(R) Core(TM) i7-8565U CPU @ 1.80GHz with 16GB RAM
> + * Intel(R) Celeron(R) CPU 4305UE @ 2.00GHz with 4GB RAM hangs
> during memory initialization
>
> ### **Package Builds**
>
> @@ -293,5 +308,5 @@ If you would like to help but are not sure where to
> start some areas currently i
> * Adding board ports for more motherboards and systems
> * Adding Clang support
>
> -Please feel free to contact Michael Kubacki (michael.a.kubacki at intel.com)
> and Isaac Oram (isaac.w.oram at intel.com)
> +Please feel free to contact Isaac Oram (isaac.w.oram at intel.com)
> if you would like to discuss contribution ideas.
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.dsc
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.dsc
> new file mode 100644
> index 0000000000..2ab9cb03ea
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.dsc
> @@ -0,0 +1,448 @@
> +## @file
> +# The main build description file for the UpXtreme board.
> +#
> +# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + DEFINE PLATFORM_PACKAGE = MinPlatformPkg
> + DEFINE PLATFORM_SI_PACKAGE = CoffeelakeSiliconPkg
> + DEFINE PLATFORM_SI_BIN_PACKAGE = CoffeelakeSiliconBinPkg
> + DEFINE PLATFORM_FSP_BIN_PACKAGE = CoffeeLakeFspBinPkg
> + DEFINE PLATFORM_BOARD_PACKAGE =
> WhiskeylakeOpenBoardPkg
> + DEFINE BOARD = UpXtreme
> + DEFINE PROJECT =
> $(PLATFORM_BOARD_PACKAGE)/$(BOARD)
> + DEFINE PEI_ARCH = IA32
> + DEFINE DXE_ARCH = X64
> + DEFINE TOP_MEMORY_ADDRESS = 0x0
> +
> + #
> + # Default value for OpenBoardPkg.fdf use
> + #
> + DEFINE BIOS_SIZE_OPTION = SIZE_80
> +
> + PLATFORM_NAME = $(PLATFORM_PACKAGE)
> + PLATFORM_GUID =
> A12B2802-BF37-4886-A307-C060F7929F8F
> + PLATFORM_VERSION = 0.1
> + DSC_SPECIFICATION = 0x00010005
> + OUTPUT_DIRECTORY = Build/$(PROJECT)
> + SUPPORTED_ARCHITECTURES = IA32|X64
> + BUILD_TARGETS = DEBUG|RELEASE
> + SKUID_IDENTIFIER = ALL
> +
> + FLASH_DEFINITION =
> $(PROJECT)/OpenBoardPkg.fdf
> + FIX_LOAD_TOP_MEMORY_ADDRESS = 0x0
> +
> + #
> + # Include PCD configuration for this board.
> + #
> + !include
> AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkarou
> nd.dsc
> + !include OpenBoardPkgPcd.dsc
> + !include AdvancedFeaturePkg/Include/AdvancedFeatures.dsc
> +
> +###############################################################
> #################
> +#
> +# SKU Identification section - list of all SKU IDs supported by this board.
> +#
> +###############################################################
> #################
> +[SkuIds]
> + 0|DEFAULT # 0|DEFAULT is reserved and always required.
> + 0x10|UpXtreme
> +
> +###############################################################
> #################
> +#
> +# Includes section - other DSC file contents included for this board build.
> +#
> +###############################################################
> #################
> +
> +#######################################
> +# Library Includes
> +#######################################
> +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc
> +!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc
> +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc
> +!include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc
> +!include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc
> +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc
> +
> +#######################################
> +# Component Includes
> +#######################################
> +# @todo: Change below line to [Components.$(PEI_ARCH)] after
> https://bugzilla.tianocore.org/show_bug.cgi?id=2308
> +# is completed
> +[Components.IA32]
> +!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc
> +!include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc
> +
> +# @todo: Change below line to [Components.$(DXE_ARCH)] after
> https://bugzilla.tianocore.org/show_bug.cgi?id=2308
> +# is completed
> +[Components.X64]
> +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc
> +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc
> +
> +#######################################
> +# Build Option Includes
> +#######################################
> +!include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc
> +!include OpenBoardPkgBuildOption.dsc
> +
> +###############################################################
> #################
> +#
> +# Library Class section - list of all Library Classes needed by this board.
> +#
> +###############################################################
> #################
> +
> +[LibraryClasses.common]
> + #######################################
> + # Edk2 Packages
> + #######################################
> +
> FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/Bas
> eFspWrapperApiLib.inf
> +
> FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLi
> b/PeiFspWrapperApiTestLib.inf
> +
> + #######################################
> + # Silicon Initialization Package
> + #######################################
> +
> ConfigBlockLib|IntelSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib
> .inf
> +
> MmPciLib|$(PLATFORM_SI_PACKAGE)/Library/PeiDxeSmmMmPciLib/PeiDxeS
> mmMmPciLib.inf
> +
> PchHsioLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchHsioLib/P
> eiDxeSmmPchHsioLib.inf
> +
> PchPmcLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchPmcLib/Pe
> iDxeSmmPchPmcLib.inf
> +
> + #####################################
> + # Platform Package
> + #####################################
> +
> BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/BoardInitLibNull/B
> oardInitLibNull.inf
> +
> FspWrapperHobProcessLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiF
> spWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf
> +
> FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFsp
> WrapperPlatformLib/PeiFspWrapperPlatformLib.inf
> +
> PciHostBridgeLib|$(PLATFORM_PACKAGE)/Pci/Library/PciHostBridgeLibSimple
> /PciHostBridgeLibSimple.inf
> +
> PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSim
> ple/PciSegmentInfoLibSimple.inf
> + PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf
> +
> PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformB
> ootManagerLib/DxePlatformBootManagerLib.inf
> +
> ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/Pei
> ReportFvLib.inf
> +
> TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNul
> l/TestPointCheckLibNull.inf
> +
> + #######################################
> + # Board Package
> + #######################################
> +
> GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpande
> rLib/BaseGpioExpanderLib.inf
> +
> HdaVerbTableLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiHdaVerbTableLi
> b/PeiHdaVerbTableLib.inf
> +
> I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2c
> AccessLib.inf
> +
> PlatformSecLib|$(PROJECT)/FspWrapper/Library/SecFspWrapperPlatformSecLi
> b/SecFspWrapperPlatformSecLib.inf
> +
> TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTim
> erLib.inf
> + # Thunderbolt
> +!if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
> +
> TbtCommonLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiDxe
> SmmTbtCommonLib/TbtCommonLib.inf
> +!endif
> +
> + #######################################
> + # Board-specific
> + #######################################
> +
> PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHoo
> kLib.inf
> +
> +[LibraryClasses.IA32.SEC]
> + #######################################
> + # Platform Package
> + #######################################
> +
> TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Se
> cTestPointCheckLib.inf
> +
> SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLib
> Null/SecBoardInitLibNull.inf
> +
> + #######################################
> + # Board Package
> + #######################################
> +
> SiliconPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiF
> spPolicyInitLib/PeiFspPolicyInitLib.inf
> +
> SiliconPolicyUpdateLib|$(PROJECT)/FspWrapper/Library/PeiSiliconPolicyUpdat
> eLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
> +
> TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTim
> erLib.inf
> +
> +[LibraryClasses.common.PEIM]
> + #######################################
> + # Silicon Initialization Package
> + #######################################
> +
> SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconInitLib/PeiSiliconIni
> tLib.inf
> +
> + #######################################
> + # Platform Package
> + #######################################
> +
> BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSup
> portLib/PeiMultiBoardInitSupportLib.inf
> +
> FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFsp
> WrapperPlatformLib/PeiFspWrapperPlatformLib.inf
> +
> MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/Multi
> BoardInitSupportLib/PeiMultiBoardInitSupportLib.inf
> +
> TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointLib
> .inf
> +!if $(TARGET) == DEBUG
> +
> TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Pe
> iTestPointCheckLib.inf
> +!endif
> +
> SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCache
> MtrrLibNull.inf
> +
> + #######################################
> + # Board Package
> + #######################################
> + # Thunderbolt
> +!if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
> +
> PeiDTbtInitLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Private/
> PeiDTbtInitLib/PeiDTbtInitLib.inf
> +
> PeiTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiTbtP
> olicyLib/PeiTbtPolicyLib.inf
> +!endif
> +
> PeiPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/PeiPolicyInitLi
> b/PeiPolicyInitLib.inf
> +
> PeiPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/PeiPolicy
> UpdateLib/PeiPolicyUpdateLib.inf
> +
> SiliconPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiF
> spPolicyInitLib/PeiFspPolicyInitLib.inf
> +
> SiliconPolicyUpdateLib|$(PROJECT)/FspWrapper/Library/PeiSiliconPolicyUpdat
> eLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
> +
> TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTim
> erLib.inf
> +
> + #######################################
> + # Board-specific
> + #######################################
> +
> PeiPlatformHookLib|$(PROJECT)/Library/PeiPlatformHookLib/PeiPlatformHoo
> kLib.inf
> +
> PeiPolicyBoardConfigLib|$(PROJECT)/Library/PeiPolicyBoardConfigLib/PeiPolic
> yBoardConfigLib.inf
> +
> +!if $(TARGET) == DEBUG
> +
> GpioCheckConflictLib|$(PROJECT)/Library/BaseGpioCheckConflictLib/BaseGpi
> oCheckConflictLib.inf
> +!else
> +
> GpioCheckConflictLib|$(PROJECT)/Library/BaseGpioCheckConflictLibNull/Base
> GpioCheckConflictLibNull.inf
> +!endif
> +
> +[LibraryClasses.common.DXE_DRIVER]
> + #######################################
> + # Edk2 Packages
> + #######################################
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.i
> nf
> +
> + #######################################
> + # Platform Package
> + #######################################
> +
> BoardAcpiTableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSup
> portLib/DxeMultiBoardAcpiSupportLib.inf
> +
> BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSup
> portLib/DxeMultiBoardInitSupportLib.inf
> +
> FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/DxeFsp
> WrapperPlatformLib/DxeFspWrapperPlatformLib.inf
> +
> MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoard
> AcpiSupportLib/DxeMultiBoardAcpiSupportLib.inf
> +
> MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/Multi
> BoardInitSupportLib/DxeMultiBoardInitSupportLib.inf
> +
> TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPointLi
> b.inf
> +
> +!if $(TARGET) == DEBUG
> +
> TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Dx
> eTestPointCheckLib.inf
> +!endif
> +
> + #######################################
> + # Board Package
> + #######################################
> +
> DxePolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/DxePolic
> yUpdateLib/DxePolicyUpdateLib.inf
> +
> DxeTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/DxeTb
> tPolicyLib/DxeTbtPolicyLib.inf
> +
> + #######################################
> + # Board-specific
> + #######################################
> +
> DxePolicyBoardConfigLib|$(PROJECT)/Library/DxePolicyBoardConfigLib/DxePo
> licyBoardConfigLib.inf
> +
> +[LibraryClasses.X64.DXE_RUNTIME_DRIVER]
> + #######################################
> + # Edk2 Packages
> + #######################################
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.i
> nf
> +
> + #######################################
> + # Silicon Initialization Package
> + #######################################
> +
> ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeResetSys
> temLib/DxeRuntimeResetSystemLib.inf
> +
> +[LibraryClasses.X64.DXE_SMM_DRIVER]
> + #######################################
> + # Edk2 Packages
> + #######################################
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.i
> nf
> +
> + #######################################
> + # Silicon Initialization Package
> + #######################################
> +
> SpiFlashCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/SmmSpiFlashCo
> mmonLib/SmmSpiFlashCommonLib.inf
> +
> + #######################################
> + # Platform Package
> + #######################################
> +
> BoardAcpiEnableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSu
> pportLib/SmmMultiBoardAcpiSupportLib.inf
> +
> MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoard
> AcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf
> +
> TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestPoint
> Lib.inf
> +!if $(TARGET) == DEBUG
> +
> TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/S
> mmTestPointCheckLib.inf
> +!endif
> +
> +#######################################
> +# PEI Components
> +#######################################
> +# @todo: Change below line to [Components.$(PEI_ARCH)] after
> https://bugzilla.tianocore.org/show_bug.cgi?id=2308
> +# is completed
> +[Components.IA32]
> + #######################################
> + # Edk2 Packages
> + #######################################
> + UefiCpuPkg/SecCore/SecCore.inf {
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> + }
> +
> + #
> + # In FSP API mode the policy has to be installed before FSP Wrapper
> updating UPD.
> + # Add policy as dependency for FSP Wrapper
> + #
> + IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
> + IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
> +
> + #######################################
> + # Silicon Initialization Package
> + #######################################
> + IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf
> +
> IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSampl
> ePei.inf
> +
> + #######################################
> + # Platform Package
> + #######################################
> + $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
> +
> $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
> {
> + <LibraryClasses>
> + !if
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport == FALSE
> +
> BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
> + !else
> +
> NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
> + !endif
> + NULL|$(PROJECT)/Library/BaseFuncLib/BaseFuncLib.inf
> + }
> +
> +
> $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
> {
> + <LibraryClasses>
> + !if
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport == FALSE
> +
> BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
> + !else
> +
> NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
> + !endif
> + }
> +
> +
> $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem
> .inf
> +
> $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMe
> m.inf
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
> + $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf
> +!endif
> +
> +
> + #######################################
> + # Board Package
> + #######################################
> + # Thunderbolt
> +!if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
> + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf
> +!endif
> + $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf
> +
> +#######################################
> +# DXE Components
> +#######################################
> +# @todo: Change below line to [Components.$(DXE_ARCH)] after
> https://bugzilla.tianocore.org/show_bug.cgi?id=2308
> +# is completed
> +[Components.X64]
> + #######################################
> + # Edk2 Packages
> + #######################################
> + IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf
> + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
> + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
> + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
> + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
> +
> MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.i
> nf
> + UefiCpuPkg/CpuDxe/CpuDxe.inf
> +
> + #
> + # eMMC/SD Card
> + #
> + MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf
> + MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf
> + MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf
> +
> + ShellPkg/Application/Shell/Shell.inf {
> + <PcdsFixedAtBuild>
> + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
> + <LibraryClasses>
> +
> NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comman
> dsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comman
> dsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comman
> dsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Comm
> andsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1Comm
> andsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Com
> mandsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1C
> ommandsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2C
> ommandsLib.inf
> +
> ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComman
> dLib.inf
> +
> HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLi
> b.inf
> +
> BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgC
> ommandLib.inf
> +
> ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
> + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
> + }
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
> + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80080046
> + <LibraryClasses>
> + !if $(TARGET) == DEBUG
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.i
> nf
> + !endif
> + }
> +!endif
> +
> + #######################################
> + # Silicon Initialization Package
> + #######################################
> + IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf
> + $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf
> + $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf
> +
> + #######################################
> + # Platform Package
> + #######################################
> +
> $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfi
> g.inf
> + $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf
> + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
> + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf
> {
> + <LibraryClasses>
> +
> SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyInitLibN
> ull/SiliconPolicyInitLibNull.inf
> +
> SiliconPolicyUpdateLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyUpd
> ateLibNull/SiliconPolicyUpdateLibNull.inf
> + }
> + $(PLATFORM_PACKAGE)/Test/TestPointDumpApp/TestPointDumpApp.inf
> + $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
> + $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
> +!endif
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
> +
> + $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
> +
> $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
> +
> + $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf {
> + <LibraryClasses>
> + !if
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport == FALSE
> +
> BoardAcpiEnableLib|$(PROJECT)/Library/BoardAcpiLib/SmmBoardAcpiEnable
> Lib.inf
> + !else
> +
> NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
> + !endif
> + }
> +
> + $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf
> +
> +!endif
> +
> + #######################################
> + # Board Package
> + #######################################
> + $(PLATFORM_BOARD_PACKAGE)/Policy/PolicyInitDxe/PolicyInitDxe.inf{
> + <LibraryClasses>
> + NULL|$(PROJECT)/Library/BaseFuncLib/BaseFuncLib.inf
> + }
> +
> + # Thunderbolt
> +!if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
> + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf
> + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf
> + $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf
> +!endif
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
> + $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
> +!endif
> + BoardModulePkg/LegacySioDxe/LegacySioDxe.inf
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf
> new file mode 100644
> index 0000000000..36a7e05a49
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf
> @@ -0,0 +1,708 @@
> +## @file
> +# FDF file for the UpXtreme.
> +#
> +#
> +# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +##
> +
> +[Defines]
> + !include $(PROJECT)/Include/Fdf/FlashMapInclude.fdf
> +
> +###############################################################
> #################
> +#
> +# FD Section
> +# The [FD] Section is made up of the definition statements and a
> +# description of what goes into the Flash Device Image. Each FD section
> +# defines one flash "device" image. A flash device image may be one of
> +# the following: Removable media bootable image (like a boot floppy
> +# image,) an Option ROM image (that would be "flashed" into an add-in
> +# card,) a System "Flash" image (that would be burned into a system's
> +# flash) or an Update ("Capsule") image that will be used to update and
> +# existing system flash.
> +#
> +###############################################################
> #################
> +[FD.UpXtreme]
> +#
> +# FD Tokens, BaseAddress, Size, ErasePolarity, BlockSize, and NumBlocks,
> cannot be
> +# assigned with PCD values. Instead, it uses the definitions for its variety,
> which
> +# are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and
> FLASH_NUM_BLOCKS.
> +#
> +BaseAddress = $(FLASH_BASE) |
> gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress #The base address of the
> FLASH Device.
> +Size = $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdBiosSize
> #The size in bytes of the FLASH Device
> +ErasePolarity = 1
> +BlockSize = $(FLASH_BLOCK_SIZE)
> +NumBlocks = $(FLASH_NUM_BLOCKS)
> +
> +DEFINE SIPKG_DXE_SMM_BIN = INF
> +DEFINE SIPKG_PEI_BIN = INF
> +
> +# Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase,
> because macro expression is not supported.
> +# So, PlatformSecLib uses PcdBiosAreaBaseAddress +
> PcdNemCodeCacheBase to get the real CodeCache base address.
> +SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase =
> $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset)
> +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =
> $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) +
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
> +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
> +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60
> +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
> +SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress =
> $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) +
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
> +SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
> +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset = 0x60
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
> +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =
> gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
> +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =
> gSiPkgTokenSpaceGuid.PcdBiosSize
> +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =
> $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) +
> $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset)
> +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =
> $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) +
> $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset)
> +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =
> $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) +
> $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =
> gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =
> gSiPkgTokenSpaceGuid.PcdBiosSize
> +###############################################################
> #################
> +#
> +# Following are lists of FD Region layout which correspond to the locations of
> different
> +# images within the flash device.
> +#
> +# Regions must be defined in ascending order and may not overlap.
> +#
> +# A Layout Region start with a eight digit hex offset (leading "0x" required)
> followed by
> +# the pipe "|" character, followed by the size of the region, also in hex with
> the leading
> +# "0x" characters. Like:
> +# Offset|Size
> +# PcdOffsetCName|PcdSizeCName
> +# RegionType <FV, DATA, or FILE>
> +# Fv Size can be adjusted
> +#
> +###############################################################
> #################
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMde
> ModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMd
> eModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
> +#NV_VARIABLE_STORE
> +DATA = {
> + ## This is the EFI_FIRMWARE_VOLUME_HEADER
> + # ZeroVector []
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + # FileSystemGuid
> + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
> + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
> + # FvLength: 0x40000
> + 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
> + #Signature "_FVH" #Attributes
> + 0x5F, 0x46, 0x56, 0x48, 0xFF, 0xFE, 0x04, 0x00,
> + #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
> + #
> + # Be careful on CheckSum field.
> + #
> + 0x48, 0x00, 0x32, 0x09, 0x00, 0x00, 0x00, 0x02,
> + #Blockmap[0]: 4 Blocks 0x10000 Bytes / Block
> + 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
> + #Blockmap[1]: End
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + ## This is the VARIABLE_STORE_HEADER
> +!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE
> + # Signature: gEfiAuthenticatedVariableGuid = { 0xaaf32c78, 0x947b,
> 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
> + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
> + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
> +!else
> + # Signature: gEfiVariableGuid = { 0xddcf3616, 0x3275, 0x4164, { 0x98,
> 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
> + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
> + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
> +!endif
> + #Size: 0x1E000
> (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48
> (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x1DFB8
> + # This can speed up the Variable Dispatch a bit.
> + 0xB8, 0xDF, 0x01, 0x00,
> + #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1:
> UINT32
> + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> +}
> +
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfi
> MdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEf
> iMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> +#NV_FTW_WORKING
> +DATA = {
> + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =
> gEdkiiWorkingBlockSignatureGuid =
> + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f,
> 0x1b, 0x95 }}
> + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
> + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
> + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1,
> Reserved
> + 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
> + # WriteQueueSize: UINT64
> + 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> +}
> +
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMd
> eModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiM
> deModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> +#NV_FTW_SPARE
> +
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatform
> PkgTokenSpaceGuid.PcdFlashFvAdvancedSize
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformP
> kgTokenSpaceGuid.PcdFlashFvAdvancedSize
> +FV = FvAdvanced
> +
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPk
> gTokenSpaceGuid.PcdFlashFvSecuritySize
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformPkg
> TokenSpaceGuid.PcdFlashFvSecuritySize
> +FV = FvSecurity
> +
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkg
> TokenSpaceGuid.PcdFlashFvOsBootSize
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|gMinPlatformPkgT
> okenSpaceGuid.PcdFlashFvOsBootSize
> +FV = FvOsBoot
> +
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformP
> kgTokenSpaceGuid.PcdFlashFvUefiBootSize
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformPk
> gTokenSpaceGuid.PcdFlashFvUefiBootSize
> +FV = FvUefiBoot
> +
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatfor
> mPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatfor
> mPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
> +FV = FvPostMemory
> +
> +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.P
> cdFlashMicrocodeFvSize
> +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.Pc
> dFlashMicrocodeFvSize
> +#Microcode
> +FV = FvMicrocode
> +
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTo
> kenSpaceGuid.PcdFlashFvFspSSize
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgTok
> enSpaceGuid.PcdFlashFvFspSSize
> +# FSP_S Section
> +FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_S.fd
> +
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgT
> okenSpaceGuid.PcdFlashFvFspMSize
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkgTo
> kenSpaceGuid.PcdFlashFvFspMSize
> +# FSP_M Section
> +FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_M.fd
> +
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTo
> kenSpaceGuid.PcdFlashFvFspTSize
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|gMinPlatformPkgTok
> enSpaceGuid.PcdFlashFvFspTSize
> +# FSP_T Section
> +FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_T.fd
> +
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset|g
> MinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryBase|gMi
> nPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize
> +FV = FvAdvancedPreMemory
> +
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatfor
> mPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatform
> PkgTokenSpaceGuid.PcdFlashFvPreMemorySize
> +FV = FvPreMemory
> +
> +###############################################################
> #################
> +#
> +# FV Section
> +#
> +# [FV] section is used to define what components or modules are placed
> within a flash
> +# device file. This section also defines order the components and modules
> are positioned
> +# within the image. The [FV] section consists of define statements, set
> statements and
> +# module statements.
> +#
> +###############################################################
> #################
> +[FV.FvMicrocode]
> +BlockSize = $(FLASH_BLOCK_SIZE)
> +FvAlignment = 16
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = FALSE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = FALSE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> +FILE RAW = 197DB236-F856-4924-90F8-CDF12FB875F3 {
> +
> $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/X64/MicrocodeUpd
> ates.bin
> +}
> +
> +[FV.FvPreMemory]
> +BlockSize = $(FLASH_BLOCK_SIZE)
> +FvAlignment = 16
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +FvNameGuid = FC8FE6B5-CD9B-411E-BD8F-31824D0CDE3D
> +
> +INF UefiCpuPkg/SecCore/SecCore.inf
> +INF MdeModulePkg/Core/Pei/PeiMain.inf
> +!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf
> +
> +INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
> +INF
> $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
> +INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
> +INF
> $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem
> .inf
> +INF $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf
> +
> +[FV.FvPostMemoryUncompact]
> +BlockSize = $(FLASH_BLOCK_SIZE)
> +FvAlignment = 16
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +FvNameGuid = 7C4DCFC6-AECA-4707-85B9-FD4B2EEA49E7
> +
> +!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePostMemoryInclude.fdf
> +
> +# Init Board Config PCD
> +INF
> $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
> +INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
> +INF
> $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMe
> m.inf
> +
> +FILE RAW = C9505BC0-AA3D-4056-9995-870C8DE8594E {
> +
> $(PLATFORM_SI_BIN_PACKAGE)/ChipsetInit/CnlPchLpChipsetInitTable_Dx.bin
> + }
> +!if gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable == TRUE
> +FILE FREEFORM
> =PCD(gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid) {
> + SECTION RAW =
> $(PLATFORM_FSP_BIN_PACKAGE)/SampleCode/Vbt/Vbt.bin
> + SECTION UI = "Vbt"
> +}
> +FILE FREEFORM = 7BB28B99-61BB-11D5-9A5D-0090273FC14D {
> + SECTION RAW = MdeModulePkg/Logo/Logo.bmp
> +}
> +!endif # PcdPeiDisplayEnable
> +
> +
> +[FV.FvPostMemory]
> +BlockSize = $(FLASH_BLOCK_SIZE)
> +FvAlignment = 16
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +FvNameGuid = 9DFE49DB-8EF0-4D9C-B273-0036144DE917
> +
> +FILE FV_IMAGE = 244FAAF4-FAE1-4892-8B7D-7EF84CBFA709 {
> + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF
> PROCESSING_REQUIRED = TRUE {
> + SECTION FV_IMAGE = FvPostMemoryUncompact
> + }
> +}
> +
> +[FV.FvUefiBootUncompact]
> +BlockSize = $(FLASH_BLOCK_SIZE)
> +FvAlignment = 16
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +FvNameGuid = A881D567-6CB0-4eee-8435-2E72D33E45B5
> +
> +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreUefiBootInclude.fdf
> +INF $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxeCnl.inf
> +
> +INF UefiCpuPkg/CpuDxe/CpuDxe.inf
> +INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
> +
> +INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
> +INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
> +INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> +INF
> MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.i
> nf
> +INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
> +INF BoardModulePkg/LegacySioDxe/LegacySioDxe.inf
> +
> +#
> +# eMMC/SD Card
> +#
> +INF MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf
> +INF MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf
> +INF MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf
> +
> +INF ShellPkg/Application/Shell/Shell.inf
> +
> +INF
> $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
> +INF $(PLATFORM_BOARD_PACKAGE)/Policy/PolicyInitDxe/PolicyInitDxe.inf
> +INF
> $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf
> +INF IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf
> +
> +INF $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf
> +
> +
> +[FV.FvUefiBoot]
> +BlockSize = $(FLASH_BLOCK_SIZE)
> +FvAlignment = 16
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +FvNameGuid = 0496D33D-EA79-495C-B65D-ABF607184E3B
> +
> +FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
> + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF
> PROCESSING_REQUIRED = TRUE {
> + SECTION FV_IMAGE = FvUefiBootUncompact
> + }
> + }
> +
> +[FV.FvOsBootUncompact]
> +BlockSize = $(FLASH_BLOCK_SIZE)
> +FvAlignment = 16
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +FvNameGuid = A0F04529-B715-44C6-BCA4-2DEBDD01EEEC
> +
> +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
> +INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
> +INF
> $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
> +INF $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
> +
> +INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf
> +INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf
> +
> +INF RuleOverride = DRIVER_ACPITABLE
> $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
> +INF
> $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfi
> g.inf
> +
> +!endif
> +
> +[FV.FvLateSilicon]
> +BlockSize = $(FLASH_BLOCK_SIZE)
> +FvAlignment = 16
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +FvNameGuid = 97F09B89-9E83-4DDC-A3D1-10C4AF539D1E
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
> +$(SIPKG_DXE_SMM_BIN)
> $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf
> +$(SIPKG_DXE_SMM_BIN)
> $(PLATFORM_SI_PACKAGE)/SystemAgent/SmmAccess/Dxe/SmmAccess.inf
> +$(SIPKG_DXE_SMM_BIN)
> $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSmiDispatcher.inf
> +$(SIPKG_DXE_SMM_BIN)
> $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmControl.inf
> +$(SIPKG_DXE_SMM_BIN)
> $(PLATFORM_SI_PACKAGE)/Pch/Spi/Smm/PchSpiSmm.inf
> +$(SIPKG_DXE_SMM_BIN)
> $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Smm/PchInitSmm.inf
> +
> +INF RuleOverride = ACPITABLE
> $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaAcpiTables.inf
> +INF RuleOverride = ACPITABLE
> $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf
> +
> +!endif
> +
> +[FV.FvOsBoot]
> +BlockSize = $(FLASH_BLOCK_SIZE)
> +FvAlignment = 16
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +FvNameGuid = 13BF8810-75FD-4B1A-91E6-E16C4201F80A
> +
> +FILE FV_IMAGE = B9020753-84A8-4BB6-947C-CE7D41F5CE39 {
> + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF
> PROCESSING_REQUIRED = TRUE {
> + SECTION FV_IMAGE = FvOsBootUncompact
> + }
> + }
> +
> +FILE FV_IMAGE = D4632741-510C-44E3-BE21-C3D6D7881485 {
> + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF
> PROCESSING_REQUIRED = TRUE {
> + SECTION FV_IMAGE = FvLateSilicon
> + }
> + }
> +
> +[FV.FvSecurityPreMemory]
> +BlockSize = $(FLASH_BLOCK_SIZE)
> +FvAlignment = 16 #FV alignment and FV attributes
> setting.
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +FvNameGuid = 9B7FA59D-71C6-4A36-906E-9725EA6ADD5B
> +
> +!include
> $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPreMemoryInclude.fdf
> +
> +INF
> IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSampl
> ePei.inf
> +
> +INF IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf
> +
> +[FV.FvSecurityPostMemory]
> +BlockSize = $(FLASH_BLOCK_SIZE)
> +FvAlignment = 16 #FV alignment and FV attributes
> setting.
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +FvNameGuid = 4199E560-54AE-45E5-91A4-F7BC3804E14A
> +
> +!include
> $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPostMemoryInclude.fdf
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
> +INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf
> +!endif
> +
> +[FV.FvSecurityLate]
> +BlockSize = $(FLASH_BLOCK_SIZE)
> +FvAlignment = 16
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +FvNameGuid = F753FE9A-EEFD-485B-840B-E032D538102C
> +
> +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityLateInclude.fdf
> +INF IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
> +INF
> $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf
> +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
> +INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
> +!endif
> +!endif
> +
> +[FV.FvSecurity]
> +BlockSize = $(FLASH_BLOCK_SIZE)
> +FvAlignment = 16
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +FvNameGuid = 5A9A8B4E-149A-4CB2-BDC7-C8D62DE2C8CF
> +
> +FILE FV_IMAGE = 757CC075-1428-423D-A73C-22639706C119 {
> + SECTION FV_IMAGE = FvSecurityPreMemory
> + }
> +
> +FILE FV_IMAGE = 80BB8482-44D5-4BEC-82B5-8D87A933830B {
> + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF
> PROCESSING_REQUIRED = TRUE {
> + SECTION FV_IMAGE = FvSecurityPostMemory
> + }
> + }
> +
> +FILE FV_IMAGE = C83522D9-80A1-4D95-8C25-3F1370497406 {
> + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF
> PROCESSING_REQUIRED = TRUE {
> + SECTION FV_IMAGE = FvSecurityLate
> + }
> + }
> +
> +#
> +# Pre-memory Advanced Features
> +#
> +[FV.FvAdvancedPreMemory]
> +FvAlignment = 16
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +FvNameGuid = 6053D78A-457E-4490-A237-31D0FBE2F305
> +
> +!include AdvancedFeaturePkg/Include/PreMemory.fdf
> +
> +!if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
> +INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf
> +!endif
> +
> +#
> +# Post-Memory Advanced Features
> +#
> +[FV.FvAdvancedUncompact]
> +FvAlignment = 16
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +FvNameGuid = BE3DF86F-E464-44A3-83F7-0D27E6B88C27
> +
> +!include AdvancedFeaturePkg/Include/PostMemory.fdf
> +
> +!if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
> +INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf
> +INF $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf
> +INF
> $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf
> +!endif
> +
> +#
> +# Compressed FV with Post-Memory Advanced Features
> +#
> +[FV.FvAdvanced]
> +BlockSize = $(FLASH_BLOCK_SIZE)
> +FvAlignment = 16
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +FvNameGuid = B23E7388-9953-45C7-9201-0473DDE5487A
> +
> +FILE FV_IMAGE = 5248467B-B87B-4E74-AC02-398AF4BCB712 {
> + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF
> PROCESSING_REQUIRED = TRUE {
> + SECTION FV_IMAGE = FvAdvancedUncompact
> + }
> + }
> +
> +###############################################################
> #################
> +#
> +# Rules are use with the [FV] section's module INF type to define
> +# how an FFS file is created for a given INF file. The following Rule are the
> default
> +# rules for the different module type. User can add the customized rules to
> define the
> +# content of the FFS file.
> +#
> +###############################################################
> #################
> +
> +!include $(PLATFORM_PACKAGE)/Include/Fdf/RuleInclude.fdf
> +
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgBuildO
> ption.dsc
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgBuildO
> ption.dsc
> new file mode 100644
> index 0000000000..4881431e33
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgBuildO
> ption.dsc
> @@ -0,0 +1,154 @@
> +## @file
> +# UpXtreme build option configuration file.
> +#
> +#
> +# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +##
> +
> +[BuildOptions]
> +# Define Build Options both for EDK and EDKII drivers.
> +
> +
> + DEFINE DSC_S3_BUILD_OPTIONS =
> +
> + DEFINE DSC_CSM_BUILD_OPTIONS =
> +
> +!if gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE
> + DEFINE DSC_ACPI_BUILD_OPTIONS = -DACPI_SUPPORT=1
> +!else
> + DEFINE DSC_ACPI_BUILD_OPTIONS =
> +!endif
> +
> + DEFINE BIOS_GUARD_BUILD_OPTIONS =
> +
> + DEFINE OVERCLOCKING_BUILD_OPTION =
> +
> + DEFINE FSP_BINARY_BUILD_OPTIONS =
> +
> + DEFINE FSP_WRAPPER_BUILD_OPTIONS = -DFSP_WRAPPER_FLAG
> +
> + DEFINE SKIP_FSP_TEMPRAM_INIT_AND_EXIT_OPTIONS =
> +
> + DEFINE RESTRICTED_OPTION =
> +
> +
> + DEFINE SV_BUILD_OPTIONS =
> +
> + DEFINE TEST_MENU_BUILD_OPTION =
> +
> +!if gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable == FALSE
> + DEFINE OPTIMIZE_DISABLE_OPTIONS = -Od -GL-
> +!else
> + DEFINE OPTIMIZE_DISABLE_OPTIONS =
> +!endif
> +
> + DEFINE UP_SERVER_SUPPORT_BUILD_OPTIONS =
> +
> +
> + DEFINE TPM_BUILD_OPTION =
> +
> + DEFINE TPM2_BUILD_OPTION =
> +
> + DEFINE DSC_TBT_BUILD_OPTIONS =
> +
> + DEFINE DSC_DCTT_BUILD_OPTIONS =
> +
> + DEFINE EMB_BUILD_OPTIONS =
> +
> + DEFINE DSC_MEMORY_DOWN_BUILD_OPTIONS =
> -DMEM_DOWN_FLAG=1
> +
> + DEFINE DSC_KBCEMUL_BUILD_OPTIONS =
> +
> + DEFINE BOOT_GUARD_BUILD_OPTIONS =
> +
> + DEFINE SECURE_BOOT_BUILD_OPTIONS =
> +
> + DEFINE USBTYPEC_BUILD_OPTION =
> +
> + DEFINE CAPSULE_BUILD_OPTIONS =
> +
> + DEFINE PERFORMANCE_BUILD_OPTION =
> +
> + DEFINE DEBUGUSEUSB_BUILD_OPTION =
> +
> + DEFINE DISABLE_NEW_DEPRECATED_INTERFACES_BUILD_OPTION =
> -DDISABLE_NEW_DEPRECATED_INTERFACES=1
> +
> + DEFINE SINITBIN_BUILD_OPTION =
> +
> + DEFINE MINTREE_FLAG_BUILD_OPTION = -DMINTREE_FLAG=1
> +
> + DEFINE CPUTYPE_BUILD_OPTION = -DCPU_CFL=1
> +
> +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =
> $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OVERCLOCKING_BUILD_OPTION)
> $(PERFORMANCE_BUILD_OPTION) $(EMB_BUILD_OPTIONS)
> $(BIOS_GUARD_BUILD_OPTIONS) $(DSC_TBT_BUILD_OPTIONS)
> +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(BOOT_GUARD_BUILD_OPTIONS)
> $(DSC_MEMORY_DOWN_BUILD_OPTIONS) $(DEBUGUSEUSB_BUILD_OPTION)
> $(DSC_S3_BUILD_OPTIONS)
> +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(FSP_BINARY_BUILD_OPTIONS)
> $(FSP_WRAPPER_BUILD_OPTIONS)
> $(SKIP_FSP_TEMPRAM_INIT_AND_EXIT_OPTIONS)
> +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(DSC_KBCEMUL_BUILD_OPTIONS)
> $(CAPSULE_BUILD_OPTIONS) $(SECURE_BOOT_BUILD_OPTIONS)
> $(DSC_CSM_BUILD_OPTIONS)
> $(DISABLE_NEW_DEPRECATED_INTERFACES_BUILD_OPTION)
> +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(TPM2_BUILD_OPTION)
> $(TPM_BUILD_OPTION) $(DSC_DCTT_BUILD_OPTIONS)
> +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(DSC_ACPI_BUILD_OPTIONS)
> $(UP_SERVER_SUPPORT_BUILD_OPTIONS) $(USBTYPEC_BUILD_OPTION)
> $(SINITBIN_BUILD_OPTION) $(MINTREE_FLAG_BUILD_OPTION)
> +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(CPUTYPE_BUILD_OPTION)
> +[BuildOptions.Common.EDKII]
> +
> +#
> +# For IA32 Global Build Flag
> +#
> + *_*_IA32_CC_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D
> PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI
> + *_*_IA32_VFRPP_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> + *_*_IA32_APP_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> + *_*_IA32_ASLPP_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> + *_*_IA32_ASLCC_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> + *_*_IA32_NASM_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> +
> +#
> +# For IA32 Specific Build Flag
> +#
> +GCC: *_*_IA32_PP_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> +MSFT: *_*_IA32_ASM_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> +MSFT: *_*_IA32_CC_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
> -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI
> +MSFT: *_*_IA32_VFRPP_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
> +MSFT: *_*_IA32_APP_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
> +MSFT: *_*_IA32_ASLPP_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
> +MSFT: *_*_IA32_ASLCC_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
> +
> +#
> +# For X64 Global Build Flag
> +#
> + *_*_X64_CC_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D
> PI_SPECIFICATION_VERSION=0x00010015
> + *_*_X64_VFRPP_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> + *_*_X64_APP_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> + *_*_X64_ASLPP_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> + *_*_X64_ASLCC_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> + *_*_X64_NASM_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> +
> +
> +#
> +# For X64 Specific Build Flag
> +#
> +GCC: *_*_X64_PP_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> +MSFT: *_*_X64_ASM_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> +MSFT: *_*_X64_CC_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
> -D PI_SPECIFICATION_VERSION=0x00010015
> +MSFT: *_*_X64_VFRPP_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
> +MSFT: *_*_X64_APP_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
> +MSFT: *_*_X64_ASLPP_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> +MSFT: *_*_X64_ASLCC_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> +
> +
> +# Force PE/COFF sections to be aligned at 4KB boundaries to support page
> level protection
> +[BuildOptions.common.EDKII.DXE_SMM_DRIVER,
> BuildOptions.common.EDKII.SMM_CORE]
> + MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
> + GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
> +
> +# Force PE/COFF sections to be aligned at 4KB boundaries to support
> MemoryAttribute table
> +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
> + MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
> + GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
> +
> +# Force PE/COFF sections to be aligned at 4KB boundaries to support NX
> protection
> +[BuildOptions.common.EDKII.DXE_DRIVER,
> BuildOptions.common.EDKII.DXE_CORE,
> BuildOptions.common.EDKII.UEFI_DRIVER,
> BuildOptions.common.EDKII.UEFI_APPLICATION]
> + #MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
> + #GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
> +
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.ds
> c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.ds
> c
> new file mode 100644
> index 0000000000..af548dc81b
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.ds
> c
> @@ -0,0 +1,409 @@
> +## @file
> +# PCD configuration build description file for the UpXtreme board.
> +#
> +# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +###############################################################
> #################
> +#
> +# Pcd Section - list of all PCD Entries used by this board.
> +#
> +###############################################################
> #################
> +
> +[PcdsFixedAtBuild.common]
> + ######################################
> + # Key Boot Stage and FSP configuration
> + ######################################
> + #
> + # Please select the Boot Stage here.
> + # Stage 1 - enable debug (system deadloop after debug init)
> + # Stage 2 - mem init (system deadloop after mem init)
> + # Stage 3 - boot to shell only
> + # Stage 4 - boot to OS
> + # Stage 5 - boot to OS with security boot enabled
> + # Stage 6 - boot with advanced features enabled
> + #
> + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4
> +
> + #
> + # 0: FSP Wrapper is running in Dispatch mode.
> + # 1: FSP Wrapper is running in API mode.
> + # Note: Dispatch mode is currently NOT supported for this board.
> + #
> + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|1
> +
> + #
> + # FALSE: The board is not a FSP wrapper (FSP binary not used)
> + # TRUE: The board is a FSP wrapper (FSP binary is used)
> + #
> + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
> +
> + #
> + # FSP Base address PCD will be updated in FDF basing on flash map.
> + #
> + gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0
> + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0
> +
> + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000
> + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
> + gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000
> + gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
> + gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000
> +
> + #
> + # When sharing stack with boot loader, FSP only needs a small temp ram
> for heap
> + #
> + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x10000
> +
> + #
> + # Boot loader stack size has to be large enough for FSP execution
> + #
> + gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x30000
> +
> + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
> +
> gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
> +
> +[PcdsFeatureFlag.common]
> + ######################################
> + # Edk2 Configuration
> + ######################################
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSection
> First|FALSE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
> +!if $(TARGET) == RELEASE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
> +!else
> + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
> +!endif
> + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
> + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
> +
> + ######################################
> + # Silicon Configuration
> + ######################################
> + # Build switches
> + gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE
> +
> + # CPU
> + gSiPkgTokenSpaceGuid.PcdCflCpuEnable|TRUE
> + gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE
> +
> + # SA
> + gSiPkgTokenSpaceGuid.PcdGnaEnable|TRUE
> + gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE
> + gSiPkgTokenSpaceGuid.PcdIpuEnable|TRUE
> + gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE
> + gSiPkgTokenSpaceGuid.PcdSgEnable|TRUE
> + gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE
> + gSiPkgTokenSpaceGuid.PcdSaOcEnable|TRUE
> + gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE
> + gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE
> +
> + # ME
> + gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE
> + gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE
> + gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE
> +
> + # Others
> + gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE
> + gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE
> + gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE
> + gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE
> + gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE
> + gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE
> + gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE
> + gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE
> + gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable|TRUE
> + gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE
> + gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE
> + gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE
> + gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE
> + gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE
> + gSiPkgTokenSpaceGuid.PcdUseHpetTimer|TRUE # TRUE - HPET / FALSE
> - 8254 timer is used.
> +
> + ######################################
> + # Platform Configuration
> + ######################################
> + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
> + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
> + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
> + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE
> + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE
> + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 1
> + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE
> +!endif
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 2
> + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
> + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE
> +!endif
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 3
> + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
> + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE
> +!endif
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 4
> + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
> +!endif
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5
> + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE
> + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE
> +!endif
> +
> +!if $(TARGET) == DEBUG
> + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE
> +!else
> + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE
> +!endif
> +
> + ######################################
> + # Board Configuration
> + ######################################
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIntelGopEnable|TRUE
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport|TRUE
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable|FALSE
> +
> +[PcdsFixedAtBuild.common]
> + ######################################
> + # Edk2 Configuration
> + ######################################
> +!if $(TARGET) == RELEASE
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
> + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
> +!else
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
> + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
> +!endif
> +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
> + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
> +!endif
> +
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01
> + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0
> + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(T
> OP_MEMORY_ADDRESS)
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x40
> 0
> +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140
> +!endif
> + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|TR
> UE
> +!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable == TRUE
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1
> +!endif
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
> +
> + #
> + # Serial UART settings
> + #
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|115200
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|1843200
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable|FALSE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|0x07
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl|0x03
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialPciDeviceInfo|{0x19, 0x02,
> 0x84, 0x00, 0xFF}
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterAccessWidth|8
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0xFE036000
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|4
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALS
> E
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE
> +
> + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80
> + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x00
> + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0x0
> + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|0x1F
> + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x44
> + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2
> + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x1800
> + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC
> + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08
> +
> + # Specifies timeout value in microseconds for the BSP to detect all APs for
> the first time.
> + gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000
> + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
> + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000
> +
> + #
> + # In non-FSP build (EDK2 build) or FSP API mode below PCD are
> FixedAtBuild
> + # (They will be DynamicEx in FSP Dispatch mode)
> + #
> +
> + ## Specifies the size of the microcode Region.
> + # @Prompt Microcode Region size.
> + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0
> +
> + ## Specifies the AP wait loop state during POST phase.
> + # The value is defined as below.
> + # 1: Place AP in the Hlt-Loop state.
> + # 2: Place AP in the Mwait-Loop state.
> + # 3: Place AP in the Run-Loop state.
> + # @Prompt The AP wait loop state.
> + gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
> +
> + ######################################
> + # Silicon Configuration
> + ######################################
> +!if $(TARGET) == DEBUG
> + gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1
> +!endif
> + gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber|2
> +
> gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSp
> aceGuid.PcdPciExpressRegionLength
> +
> + ######################################
> + # Platform Configuration
> + ######################################
> + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1
> + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
> + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
> +
> + #
> + # The PCDs are used to control the Windows SMM Security Mitigations
> Table - Protection Flags
> + #
> + # BIT0: If set, expresses that for all synchronous SMM entries,SMM will
> validate that input and output buffers lie entirely within the expected fixed
> memory regions.
> + # BIT1: If set, expresses that for all synchronous SMM entries, SMM will
> validate that input and output pointers embedded within the fixed
> communication buffer only refer to address ranges \
> + # that lie entirely within the expected fixed memory regions.
> + # BIT2: Firmware setting this bit is an indication that it will not allow
> reconfiguration of system resources via non-architectural mechanisms.
> + # BIT3-31: Reserved
> + #
> + gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07
> +
> +!if $(TARGET) == RELEASE
> +
> gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402
> +!else
> +
> gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188
> B
> +!endif
> +
> + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b
> +!if $(TARGET) == RELEASE
> + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70
> +!else
> + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0
> +!endif
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 1
> + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03,
> 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00}
> +!endif
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 2
> + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03,
> 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00}
> +!endif
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 3
> + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03,
> 0x07, 0x03, 0x05, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00}
> +!endif
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 4
> + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03,
> 0x07, 0x03, 0x05, 0x1F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00}
> +!endif
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 5
> + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03,
> 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00}
> +!endif
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 6
> + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03,
> 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00}
> +!endif
> +
> + ######################################
> + # Board Configuration
> + ######################################
> + gBoardModulePkgTokenSpaceGuid.PcdPs2KbMsEnable|0
> + gBoardModulePkgTokenSpaceGuid.PcdSuperIoPciIsaBridgeDevice|{0x00,
> 0x00, 0x1F, 0x00}
> +
> +[PcdsFixedAtBuild.IA32]
> + ######################################
> + # Edk2 Configuration
> + ######################################
> + gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
> + gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148
> + gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000
> +
> + ######################################
> + # Platform Configuration
> + ######################################
> + gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000
> +
> +[PcdsFixedAtBuild.X64]
> + ######################################
> + # Edk2 Configuration
> + ######################################
> +
> + # Default platform supported RFC 4646 languages: (American) English
> +
> gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-
> US"
> +
> +[PcdsPatchableInModule.common]
> + ######################################
> + # Edk2 Configuration
> + ######################################
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
> +
> +[PcdsDynamicDefault]
> + ######################################
> + # Edk2 Configuration
> + ######################################
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0
> + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0
> +
> + #
> + # Set video to native resolution as Windows 8 WHCK requirement.
> + #
> + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x0
> + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x0
> +
> + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum|0x00
> +
> + #
> + # FSP Base address PCD will be updated in FDF basing on flash map.
> + #
> + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0
> +
> + # Platform will pre-allocate UPD buffer and pass it to FspWrapper
> + # Those dummy address will be patched before FspWrapper executing
> + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x0
> + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x0
> +
> + gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0
> + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16
> +
> + ######################################
> + # Board Configuration
> + ######################################
> +
> + # Thunderbolt Configuration
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcDcSwitch|0x0
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAspm|0x0
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad|0
> x02010011
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtForcepowerGpioPad|13
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpioLevel|0x1
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotNotify|0x1
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotSMI|0x1
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax|
> 26
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax
> |28
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemRsvd|100
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSetClkReq|0x1
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWakeupSupport|0x0
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3Tbt|0x1
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReq|0x1
> +
> +[PcdsDynamicHii.X64.DEFAULT]
> + ######################################
> + # Edk2 Configuration
> + ######################################
> +
> gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupp
> ort"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
> +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
> +
> gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobal
> VariableGuid|0x0|1 # Variable: L"Timeout"
> +!else
> +
> gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobal
> VariableGuid|0x0|5 # Variable: L"Timeout"
> +!endif
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/build_config.cfg
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/build_config.cfg
> new file mode 100644
> index 0000000000..f90df20dbb
> --- /dev/null
> +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/build_config.cfg
> @@ -0,0 +1,35 @@
> +# @ build_config.cfg
> +# This is the UpXtreme board specific build settings
> +#
> +# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +
> +
> +[CONFIG]
> +WORKSPACE_PLATFORM_BIN =
> +EDK_SETUP_OPTION =
> +openssl_path =
> +BIOS_SIZE_OPTION = -DBIOS_SIZE_OPTION=SIZE_80
> +PLATFORM_BOARD_PACKAGE = WhiskeylakeOpenBoardPkg
> +PROJECT = WhiskeylakeOpenBoardPkg/UpXtreme
> +BOARD = UpXtreme
> +FLASH_MAP_FDF =
> WhiskeylakeOpenBoardPkg/UpXtreme/Include/Fdf/FlashMapInclude.fdf
> +PROJECT_DSC = WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.dsc
> +BOARD_PKG_PCD_DSC =
> WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
> +PrepRELEASE = DEBUG
> +SILENT_MODE = FALSE
> +EXT_CONFIG_CLEAR =
> +CapsuleBuild = FALSE
> +EXT_BUILD_FLAGS =
> +CAPSULE_BUILD = 0
> +TARGET = DEBUG
> +TARGET_SHORT = D
> +PERFORMANCE_BUILD = FALSE
> +FSP_WRAPPER_BUILD = TRUE
> +FSP_BIN_PKG = CoffeeLakeFspBinPkg
> +FSP_PKG_NAME = CoffeelakeSiliconPkg
> +FSP_BINARY_BUILD = FALSE
> +FSP_TEST_RELEASE = FALSE
> +SECURE_BOOT_ENABLE = FALSE
> +BIOS_INFO_GUID = A842B2D2-5C88-44E9-A9E2-4830F26662B7
> diff --git a/Platform/Intel/build.cfg b/Platform/Intel/build.cfg
> index 86a9115021..dbaec39876 100644
> --- a/Platform/Intel/build.cfg
> +++ b/Platform/Intel/build.cfg
> @@ -57,4 +57,5 @@ BIOS_INFO_GUID =
> BoardX58Ich10 = SimicsOpenBoardPkg/BoardX58Ich10/build_config.cfg
> GalagoPro3 = KabylakeOpenBoardPkg/GalagoPro3/build_config.cfg
> KabylakeRvp3 = KabylakeOpenBoardPkg/KabylakeRvp3/build_config.cfg
> +UpXtreme = WhiskeylakeOpenBoardPkg/UpXtreme/build_config.cfg
> WhiskeylakeURvp =
> WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/build_config.cfg
> --
> 2.19.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#54411): https://edk2.groups.io/g/devel/message/54411
Mute This Topic: https://groups.io/mt/71247733/1813853
Group Owner: devel+owner at edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [edk2-devel-archive at redhat.com]
-=-=-=-=-=-=-=-=-=-=-=-
More information about the edk2-devel-archive
mailing list