[edk2-devel] [edk2-platforms] [PATCH V1 1/2] CoffeeLakeSiliconPkg: Add Cometlake U Silicon support
Chiu, Chasel
chasel.chiu at intel.com
Wed Feb 19 06:42:50 UTC 2020
Reviewed-by: Chasel Chiu <chasel.chiu at intel.com>
> -----Original Message-----
> From: Esakkithevar, Kathappan <kathappan.esakkithevar at intel.com>
> Sent: Tuesday, February 18, 2020 10:54 PM
> To: devel at edk2.groups.io
> Cc: Chaganty, Rangasai V <rangasai.v.chaganty at intel.com>; Chiu, Chasel
> <chasel.chiu at intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone at intel.com>; Kethi Reddy, Deepika
> <deepika.kethi.reddy at intel.com>; Agyeman, Prince
> <prince.agyeman at intel.com>
> Subject: [edk2-platforms] [PATCH V1 1/2] CoffeeLakeSiliconPkg: Add
> Cometlake U Silicon support
>
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2280
>
> Adds CPU model, SA Device ID, PCH SKU ID for Cometlake U V1.
>
> Key files
> =========
> * CpuReg.h - Add CPU Family Model support.
> * SaRegsHostBridge.h - Add SA Device ID support.
> * MrcInterface.h - Add CPU Family Model support in MRC.
> * PchRegsLpcCnl.h - Add PCH SKU ID support.
>
> Signed-off-by: Kathappan Esakkithevar <kathappan.esakkithevar at intel.com>
> Cc: Sai Chaganty <rangasai.v.chaganty at intel.com>
> Cc: Chasel Chiu <chasel.chiu at intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone at intel.com>
> Cc: Deepika Kethi Reddy <deepika.kethi.reddy at intel.com>
> Cc: Prince Agyeman <prince.agyeman at intel.com>
> ---
> .../Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h | 5 ++++-
> .../PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c | 18
> +++++++++++++++++-
> .../Pch/Include/Register/PchRegsLpcCnl.h | 3 ++-
> .../Pch/Library/PeiDxeSmmPchInfoLib/PchInfoLibCnl.c | 5 ++++-
> .../SystemAgent/Include/Register/SaRegsHostBridge.h | 5 ++++-
> .../MemoryInit/Include/Coffeelake/MrcInterface.h | 5 +++--
> 6 files changed, 34 insertions(+), 7 deletions(-)
>
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h
> index 68f2c019e2..4b9ce8d4d3 100644
> --- a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h
> @@ -9,7 +9,7 @@
> - Definitions beginning with "S_" are register sizes
> - Definitions beginning with "N_" are the bit position
>
> - Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> + Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.
> + <BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -181,6 +181,7 @@
> #define CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX 0x000806E0
> #define CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO 0x000906E0
> #define CPUID_FULL_FAMILY_MODEL_CANNONLAKE_DT_HALO 0x00060670
> +#define CPUID_FULL_FAMILY_MODEL_COMETLAKE_ULT 0x000A0660
>
> #ifndef STALL_ONE_MICRO_SECOND
> #define STALL_ONE_MICRO_SECOND 1
> @@ -206,6 +207,7 @@ typedef enum {
> EnumCpuCflUltUlx =
> CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX,
> EnumCpuCflDtHalo =
> CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO,
> EnumCpuCnlDtHalo =
> CPUID_FULL_FAMILY_MODEL_CANNONLAKE_DT_HALO,
> + EnumCpuCmlUlt =
> CPUID_FULL_FAMILY_MODEL_COMETLAKE_ULT,
> EnumCpuMax = CPUID_FULL_FAMILY_MODEL
> } CPU_FAMILY;
>
> @@ -256,6 +258,7 @@ typedef enum {
> ///
> typedef enum {
> EnumCflCpu = 0,
> + EnumCmlCpu,
> EnumCpuUnknownGeneration = 255
> } CPU_GENERATION;
> #endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/C
> puPlatformLibrary.c
> b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/
> CpuPlatformLibrary.c
> index 18f2028fa9..702a10c9d8 100644
> ---
> a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/C
> puPlatformLibrary.c
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatfor
> +++ mLib/CpuPlatformLibrary.c
> @@ -1,7 +1,7 @@
> /** @file
> CPU Platform Lib implementation.
>
> - Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> + Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.
> + <BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -80,6 +80,15 @@
> GetCpuSku (
> CpuDid = PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM,
> SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_MC_DEVICE_ID));
>
> switch (CpuFamilyModel) {
> + case CPUID_FULL_FAMILY_MODEL_COMETLAKE_ULT:
> + switch (CpuDid) {
> + case V_SA_DEVICE_ID_CML_ULT_1: // CML ULT
> + case V_SA_DEVICE_ID_CML_ULT_2: // CML ULT
> + case V_SA_DEVICE_ID_CML_ULT_3: // CML ULT
> + CpuType = EnumCpuUlt;
> + break;
> + }
> + break;
> case CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX:
> switch (CpuDid) {
> case V_SA_DEVICE_ID_KBL_MB_ULT_1: // KBL ULT OPI
> @@ -87,6 +96,9 @@ GetCpuSku (
> case V_SA_DEVICE_ID_CFL_ULT_2: // CFL ULT
> case V_SA_DEVICE_ID_CFL_ULT_3: // CFL ULT
> case V_SA_DEVICE_ID_CFL_ULT_4: // CFL ULT
> + case V_SA_DEVICE_ID_CML_ULT_1: // CML ULT
> + case V_SA_DEVICE_ID_CML_ULT_2: // CML ULT
> + case V_SA_DEVICE_ID_CML_ULT_3: // CML ULT
> CpuType = EnumCpuUlt;
> break;
>
> @@ -378,6 +390,10 @@ GetCpuGeneration (
> CpuGeneration = EnumCflCpu;
> break;
>
> + case EnumCpuCmlUlt:
> + CpuGeneration = EnumCmlCpu;
> + break;
> +
> default:
> CpuGeneration = EnumCpuUnknownGeneration;
> ASSERT (FALSE);
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpcCnl.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpcCnl.h
> index 74789a87ce..e8a18cac3e 100644
> --- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpcCnl.h
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpc
> +++ Cnl.h
> @@ -21,7 +21,7 @@
> - Registers / bits of new devices introduced in a PCH generation will be just
> named
> as "_PCH_" without [generation_name] inserted.
>
> - Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> + Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.
> + <BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -31,6 +31,7 @@
>
> #define V_LPC_CFG_DID_CNL_H 0xA300
> #define V_LPC_CFG_DID_CNL_LP 0x9D80
> +#define V_LPC_CFG_DID_CML_LP 0x0280
>
> //
> // PCH-LP Device IDs
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInf
> oLibCnl.c
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInf
> oLibCnl.c
> index 431b1470c2..da6479f212 100644
> ---
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInf
> oLibCnl.c
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib
> +++ /PchInfoLibCnl.c
> @@ -4,7 +4,7 @@
> All function in this library is available for PEI, DXE, and SMM,
> But do not support UEFI RUNTIME environment call.
>
> - Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> + Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.
> + <BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -37,6 +37,9 @@
> PchSeriesFromLpcDid (
> case V_LPC_CFG_DID_CNL_LP:
> return PCH_LP;
>
> + case V_LPC_CFG_DID_CML_LP:
> + return PCH_LP;
> +
> default:
> return PCH_UNKNOWN_SERIES;
> }
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsHos
> tBridge.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsHos
> tBridge.h
> index 2cc0e5be68..67bbf13d77 100644
> ---
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsHos
> tBridge.h
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/Sa
> +++ RegsHostBridge.h
> @@ -15,7 +15,7 @@
> - Registers / bits of new devices introduced in a SA generation will be just
> named
> as "_SA_" without [generation_name] inserted.
>
> - Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> + Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.
> + <BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -112,6 +112,9 @@
> #define V_SA_DEVICE_ID_CFL_ULT_4 0x3E35 ///< CoffeeLake
> Mobile (CFL-U 2+(1 or 2)) SA DID
> #define V_SA_DEVICE_ID_CFL_ULT_6 0x3ECC ///< CoffeeLake
> Mobile (CFL-U 2+3e) SA DID
>
> +#define V_SA_DEVICE_ID_CML_ULT_1 0x9B51 ///< CometLake
> (CML-U 6+2) SA DID
> +#define V_SA_DEVICE_ID_CML_ULT_2 0x9B61 ///< CometLake
> (CML-U 4+2) SA DID
> +#define V_SA_DEVICE_ID_CML_ULT_3 0x9B71 ///< CometLake
> (CML-U 2+2) SA DID
> //
> // CoffeeLake CPU Desktop SA Device IDs B0:D0:F0 // diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/Coffeel
> ake/MrcInterface.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/Coffeel
> ake/MrcInterface.h
> index 635906cc2b..b9b390cc71 100644
> ---
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/Coffeel
> ake/MrcInterface.h
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/
> +++ Coffeelake/MrcInterface.h
> @@ -1,7 +1,7 @@
> /** @file
> This file includes all the data structures that the MRC considers "global
> data".
>
> - Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> + Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.
> + <BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -477,7 +477,8 @@
> typedef enum { /// typedef enum {
> cmCFL_ULX_ULT =
> CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX, ///< Coffeelake
> ULT/ULX
> - cmCFL_DT_HALO =
> CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO ///< Coffeelake
> DT/Halo
> + cmCFL_DT_HALO =
> CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO, ///< Coffeelake
> DT/Halo
> + cmCML_ULX_ULT = CPUID_FULL_FAMILY_MODEL_COMETLAKE_ULT
> ///< Cometlake ULT/ULX
> } MrcCpuModel;
>
> ///
> --
> 2.16.2.windows.1
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