[edk2-devel] [edk2-staging/RISC-V-V2: RISC-V EDK2 CI Code Change PATCH v1 6/9] MdePkg/Include: Add RISC-V related definitions EDK2 CI.

[Abner Chang]

HTTP/PXE boot RISC-V related definitions for EDK2 CI.

BZ:2562
https://bugzilla.tianocore.org/show_bug.cgi?id=2562

EDK2 CI report:
https://github.com/tianocore/edk2-staging/pull/196
https://github.com/tianocore/edk2-staging/pull/197

Signed-off-by: Abner Chang <abner.chang at hpe.com>

Cc: Michael D Kinney <michael.d.kinney at intel.com>
Cc: Liming Gao <liming.gao at intel.com>
Cc: Leif Lindholm <leif at nuviainc.com>
Cc: Gilbert Chen <gilbert.chen at hpe.com>
Cc: Daniel Helmut Schaefer <daniel.schaefer at hpe.com>
---
 MdePkg/Include/IndustryStandard/Dhcp.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/MdePkg/Include/IndustryStandard/Dhcp.h b/MdePkg/Include/IndustryStandard/Dhcp.h
index f41f9f2f5b..121c48c42d 100644
--- a/MdePkg/Include/IndustryStandard/Dhcp.h
+++ b/MdePkg/Include/IndustryStandard/Dhcp.h
@@ -3,6 +3,7 @@
   They are used to carry additional information and parameters in DHCP messages.
 
   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
@@ -266,11 +267,17 @@ typedef enum {
 #define PXE_CLIENT_ARCH_EBC              0x0009    /// EBC for PXE
 #define PXE_CLIENT_ARCH_ARM              0x000A    /// Arm uefi 32 for PXE
 #define PXE_CLIENT_ARCH_AARCH64          0x000B    /// Arm uefi 64 for PXE
+#define PXE_CLIENT_ARCH_RISCV32          0x0019    /// RISC-V uefi 32 for PXE
+#define PXE_CLIENT_ARCH_RISCV64          0x001B    /// RISC-V uefi 64 for PXE
+#define PXE_CLIENT_ARCH_RISCV128         0x001D    /// RISC-V uefi 128 for PXE
 
 #define HTTP_CLIENT_ARCH_IA32            0x000F    /// x86 uefi boot from http
 #define HTTP_CLIENT_ARCH_X64             0x0010    /// x64 uefi boot from http
 #define HTTP_CLIENT_ARCH_EBC             0x0011    /// EBC boot from http
 #define HTTP_CLIENT_ARCH_ARM             0x0012    /// Arm uefi 32 boot from http
 #define HTTP_CLIENT_ARCH_AARCH64         0x0013    /// Arm uefi 64 boot from http
+#define HTTP_CLIENT_ARCH_RISCV32         0x001A    /// RISC-V uefi 32 boot from http
+#define HTTP_CLIENT_ARCH_RISCV64         0x001C    /// RISC-V uefi 64 boot from http
+#define HTTP_CLIENT_ARCH_RISCV128        0x001E    /// RISC-V uefi 128 boot from http
 
 #endif
-- 
2.25.0


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