[edk2-devel] [edk2-platforms][PATCH v5 1/5] Silicon/ARM/N1SoC: Add platform library implementation
Leif Lindholm
leif at nuviainc.com
Fri Jul 24 17:29:10 UTC 2020
On Wed, Jul 22, 2020 at 20:55:20 +0530, Pranav Madhu wrote:
> From: Deepak Pandey <deepak.pandey at arm.com>
>
> Add the initial Arm's Neoverse N1 System-on-Chip platform library
> support. This includes the virtual memory map and helper functions for
> platform initialization.
>
> Cc: Ard Biesheuvel <ard.biesheuvel at arm.com>
> Cc: Leif Lindholm <leif at nuviainc.com>
> Signed-off-by: Pranav Madhu <pranav.madhu at arm.com>
> ---
> Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 27 +++++
> Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf | 43 +++++++
> Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h | 66 +++++++++++
> Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c | 67 +++++++++++
> Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c | 125 ++++++++++++++++++++
> Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S | 84 +++++++++++++
> 6 files changed, 412 insertions(+)
>
> diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
> new file mode 100644
> index 000000000000..dba49e6489c0
> --- /dev/null
> +++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
> @@ -0,0 +1,27 @@
> +#
> +# Copyright (c) 2018 - 2020, ARM Limited. All rights reserved.
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +
> +[Defines]
> + DEC_SPECIFICATION = 0x0001001A
> + PACKAGE_NAME = NeoverseN1Soc
> + PACKAGE_GUID = b6d2d197-76d0-401f-a3e0-826a26f350c9
> + PACKAGE_VERSION = 0.1
> +
> +################################################################################
> +#
> +# Include Section - list of Include Paths that are provided by this package.
> +# Comments are used for Keywords and Module Types.
> +#
> +################################################################################
> +[Includes.common]
> + Include # Root include for the package
> +
> +[Guids.common]
> + gArmNeoverseN1SocTokenSpaceGuid = { 0xab93eb78, 0x60d7, 0x4099, { 0xac, 0xeb, 0x6d, 0xb5, 0x02, 0x58, 0x7c, 0x24 } }
> +
> +[PcdsFixedAtBuild]
> + # Secondary DDR memory
> + gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x00000001
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
> new file mode 100644
> index 000000000000..e4d720bd36f5
> --- /dev/null
> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
> @@ -0,0 +1,43 @@
> +## @file
> +#
> +# Copyright (c) 2018-2020, ARM Limited. All rights reserved.
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = ArmNeoverseN1SocLib
> + FILE_GUID = 3d0eafcf-abc1-43d8-9269-709bb24f9d21
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = ArmPlatformLib
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
> +
> +[Sources.common]
> + PlatformLibMem.c
> + PlatformLib.c
> +
> +[Sources.AARCH64]
> + AArch64/Helper.S | GCC
> +
> +[FixedPcd]
> + gArmTokenSpaceGuid.PcdSystemMemoryBase
> + gArmTokenSpaceGuid.PcdSystemMemorySize
> + gArmTokenSpaceGuid.PcdArmPrimaryCore
> + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
> +
> + gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base
> +
> +[Guids]
> + gEfiHobListGuid ## CONSUMES ## SystemTable
> +
> +[Ppis]
> + gArmMpCoreInfoPpiGuid
> diff --git a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
> new file mode 100644
> index 000000000000..52e7f92e833a
> --- /dev/null
> +++ b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
> @@ -0,0 +1,66 @@
> +/** @file
> +*
> +* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved.
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#ifndef NEOVERSEN1SOC_PLATFORM_H_
> +#define NEOVERSEN1SOC_PLATFORM_H_
> +
> +#define NEOVERSEN1SOC_DRAM_BLOCK1_SIZE SIZE_2GB
> +
> +//******************************************************************************
> +// Platform Memory Map
> +//******************************************************************************
> +
> +// SubSystem Peripherals - UART0
> +#define NEOVERSEN1SOC_UART0_BASE 0x2A400000
> +#define NEOVERSEN1SOC_UART0_SZ SIZE_64KB
> +
> +// SubSystem Peripherals - UART1
> +#define NEOVERSEN1SOC_UART1_BASE 0x2A410000
> +#define NEOVERSEN1SOC_UART1_SZ SIZE_64KB
> +
> +// SubSystem Peripherals - Generic Watchdog
> +#define NEOVERSEN1SOC_GENERIC_WDOG_BASE 0x2A440000
> +#define NEOVERSEN1SOC_GENERIC_WDOG_SZ SIZE_128KB
> +
> +// SubSystem Peripherals - GIC(600)
> +#define NEOVERSEN1SOC_GIC_BASE 0x30000000
> +#define NEOVERSEN1SOC_GICR_BASE 0x300C0000
> +#define NEOVERSEN1SOC_GIC_SZ SIZE_256KB
> +#define NEOVERSEN1SOC_GICR_SZ SIZE_1MB
> +
> +// SubSystem non-secure SRAM
> +#define NEOVERSEN1SOC_NON_SECURE_SRAM_BASE 0x06000000
> +#define NEOVERSEN1SOC_NON_SECURE_SRAM_SZ SIZE_64KB
> +
> +// AXI Expansion peripherals
> +#define NEOVERSEN1SOC_EXP_PERIPH_BASE0 0x1C000000
> +#define NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ 0x1300000
> +
> +// Base address to a structure of type NEOVERSEN1SOC_PLAT_INFO which is
> +// pre-populated by a earlier boot stage
> +#define NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE (NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + \
> + 0x00008000)
> +
> +/*
> + * Platform information structure stored in non-secure SRAM. Platform
The architectural terms as Secure an Non-secure. I asked for the
latter. I will fix this up before pushing, but please pay attention to
case for architectural terminology.
Other than this, the patch is fine, so:
Reviewed-by: Leif Lindholm <leif at nuviainc.com>
> + * information are passed from the trusted firmware with the below structure
> + * format. The elements of NEOVERSEN1SOC_PLAT_INFO should be always in sync
> + * with the lower level firmware.
> + */
> +typedef struct {
> + /*! 0 - Single Chip, 1 - Chip to Chip (C2C) */
> + UINT8 MultichipMode;
> + /*! Slave count in C2C mode */
> + UINT8 SlaveCount;
> + /*! Local DDR memory size in GigaBytes */
> + UINT8 LocalDdrSize;
> + /*! Remote DDR memory size in GigaBytes */
> + UINT8 RemoteDdrSize;
> +} NEOVERSEN1SOC_PLAT_INFO;
> +
> +#endif
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c
> new file mode 100644
> index 000000000000..f722080e566b
> --- /dev/null
> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c
> @@ -0,0 +1,67 @@
> +/** @file
> +*
> +* Copyright (c) 2018-2020, ARM Limited. All rights reserved.
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#include <Library/ArmPlatformLib.h>
> +#include <Library/BaseLib.h>
> +#include <Ppi/ArmMpCoreInfo.h>
> +
> +STATIC ARM_CORE_INFO mCoreInfoTable[] = {
> + { 0x0, 0x0 }, // Cluster 0, Core 0
> + { 0x0, 0x1 }, // Cluster 0, Core 1
> + { 0x1, 0x0 }, // Cluster 1, Core 0
> + { 0x1, 0x1 } // Cluster 1, Core 1
> +};
> +
> +EFI_BOOT_MODE
> +ArmPlatformGetBootMode (
> + VOID
> + )
> +{
> + return BOOT_WITH_FULL_CONFIGURATION;
> +}
> +
> +RETURN_STATUS
> +ArmPlatformInitialize (
> + IN UINTN MpId
> + )
> +{
> + return RETURN_SUCCESS;
> +}
> +
> +EFI_STATUS
> +PrePeiCoreGetMpCoreInfo (
> + OUT UINTN *CoreCount,
> + OUT ARM_CORE_INFO **ArmCoreTable
> + )
> +{
> + *CoreCount = sizeof (mCoreInfoTable) / sizeof (ARM_CORE_INFO);
> + *ArmCoreTable = mCoreInfoTable;
> + return EFI_SUCCESS;
> +}
> +
> +STATIC ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = {
> + PrePeiCoreGetMpCoreInfo
> +};
> +
> +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
> + {
> + EFI_PEI_PPI_DESCRIPTOR_PPI,
> + &gArmMpCoreInfoPpiGuid,
> + &mMpCoreInfoPpi
> + }
> +};
> +
> +VOID
> +ArmPlatformGetPlatformPpiList (
> + OUT UINTN *PpiListSize,
> + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
> + )
> +{
> + *PpiListSize = sizeof (gPlatformPpiTable);
> + *PpiList = gPlatformPpiTable;
> +}
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
> new file mode 100644
> index 000000000000..096832be96da
> --- /dev/null
> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
> @@ -0,0 +1,125 @@
> +/** @file
> +*
> +* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved.
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#include <Library/ArmPlatformLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/HobLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <NeoverseN1Soc.h>
> +
> +// The total number of descriptors, including the final "end-of-table" descriptor.
> +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 9
> +
> +/**
> + Returns the Virtual Memory Map of the platform.
> +
> + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU
> + on your platform.
> +
> + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing
> + a Physical-to-Virtual Memory mapping. This array
> + must be ended by a zero-filled entry.
> +**/
> +VOID
> +ArmPlatformGetVirtualMemoryMap (
> + IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap
> + )
> +{
> + UINTN Index = 0;
> + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
> + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
> + NEOVERSEN1SOC_PLAT_INFO *PlatInfo;
> + UINT64 DramBlock2Size;
> +
> + PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
> + DramBlock2Size = ((UINT64)(PlatInfo->LocalDdrSize -
> + NEOVERSEN1SOC_DRAM_BLOCK1_SIZE / SIZE_1GB) *
> + (UINT64)SIZE_1GB);
> +
> + ResourceAttributes =
> + EFI_RESOURCE_ATTRIBUTE_PRESENT |
> + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
> + EFI_RESOURCE_ATTRIBUTE_TESTED;
> +
> + BuildResourceDescriptorHob (
> + EFI_RESOURCE_SYSTEM_MEMORY,
> + ResourceAttributes,
> + FixedPcdGet64 (PcdDramBlock2Base),
> + DramBlock2Size);
> +
> + ASSERT (VirtualMemoryMap != NULL);
> + Index = 0;
> +
> + VirtualMemoryTable = AllocatePool (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) *
> + MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
> + if (VirtualMemoryTable == NULL) {
> + return;
> + }
> +
> + // SubSystem Peripherals - Generic Watchdog
> + VirtualMemoryTable[Index].PhysicalBase = NEOVERSEN1SOC_GENERIC_WDOG_BASE;
> + VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_GENERIC_WDOG_BASE;
> + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_GENERIC_WDOG_SZ;
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // SubSystem Peripherals - GIC-600
> + VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_GIC_BASE;
> + VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_GIC_BASE;
> + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_GIC_SZ;
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // SubSystem Peripherals - GICR-600
> + VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_GICR_BASE;
> + VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_GICR_BASE;
> + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_GICR_SZ;
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // OnChip non-secure SRAM
> + VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE;
> + VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE;
> + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_NON_SECURE_SRAM_SZ;
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
> +
> + // SubSystem Pheripherals - UART0
> + VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_UART0_BASE;
> + VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_UART0_BASE;
> + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_UART0_SZ;
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // DDR Primary (2GB)
> + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);
> + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase);
> + VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
> +
> + // DDR Secondary
> + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdDramBlock2Base);
> + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdDramBlock2Base);
> + VirtualMemoryTable[Index].Length = DramBlock2Size;
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
> +
> + // Expansion Peripherals
> + VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_EXP_PERIPH_BASE0;
> + VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_EXP_PERIPH_BASE0;
> + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ;
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // End of Table
> + VirtualMemoryTable[++Index].PhysicalBase = 0;
> + VirtualMemoryTable[Index].VirtualBase = 0;
> + VirtualMemoryTable[Index].Length = 0;
> + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
> +
> + ASSERT((Index) < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
> + DEBUG ((DEBUG_INIT, "Virtual Memory Table setup complete.\n"));
> +
> + *VirtualMemoryMap = VirtualMemoryTable;
> +}
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S
> new file mode 100644
> index 000000000000..8d2069dea837
> --- /dev/null
> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S
> @@ -0,0 +1,84 @@
> +/** @file
> +*
> +* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#include <AsmMacroIoLibV8.h>
> +#include <Library/ArmLib.h>
> +
> +.text
> +.align 3
> +
> +GCC_ASM_EXPORT(ArmPlatformPeiBootAction)
> +GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
> +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)
> +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
> +
> +//
> +// First platform specific function to be called in the PEI phase
> +//
> +// This function is actually the first function called by the PrePi
> +// or PrePeiCore modules. It allows to retrieve arguments passed to
> +// the UEFI firmware through the CPU registers.
> +//
> +ASM_PFX(ArmPlatformPeiBootAction):
> + ret
> +
> +//
> +// Return the core position from the value of its MpId register
> +//
> +// This function returns core position from the position 0 in the processor.
> +// This function might be called from assembler before any stack is set.
> +//
> +// @return Return the core position
> +//
> +//UINTN
> +//ArmPlatformGetCorePosition (
> +// IN UINTN MpId
> +// );
> +// With this function: CorePos = (ClusterId * 2) + CoreId
> +ASM_PFX(ArmPlatformGetCorePosition):
> + and x1, x0, #ARM_CORE_MASK
> + and x0, x0, #ARM_CLUSTER_MASK
> + add x0, x1, x0, LSR #7
> + ret
> +
> +//
> +// Return the MpId of the primary core
> +//
> +// This function returns the MpId of the primary core.
> +// This function might be called from assembler before any stack is set.
> +//
> +// @return Return the MpId of the primary core
> +//
> +//UINTN
> +//ArmPlatformGetPrimaryCoreMpId (
> +// VOID
> +// );
> +ASM_PFX(ArmPlatformGetPrimaryCoreMpId):
> + MOV32 (w0, FixedPcdGet32(PcdArmPrimaryCore))
> + ret
> +
> +//
> +// Return a non-zero value if the callee is the primary core
> +//
> +// This function returns a non-zero value if the callee is the primary core.
> +// Primary core is the core responsible to initialize hardware and run UEFI.
> +// This function might be called from assembler before any stack is set.
> +//
> +// @return Return a non-zero value if the callee is the primary core.
> +//
> +//UINTN
> +//ArmPlatformIsPrimaryCore (
> +// IN UINTN MpId
> +// );
> +ASM_PFX(ArmPlatformIsPrimaryCore):
> + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCoreMask))
> + and x0, x0, x1
> + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCore))
> + cmp w0, w1
> + cset x0, eq
> + ret
> --
> 2.7.4
>
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