[edk2-devel] [PATCH v9 03/46] MdePkg: Add the MSR definition for the GHCB register

[Lendacky, Thomas]

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198

For SEV-ES, the GHCB page address is stored in the GHCB MSR register
(0xc0010130). Define the register and the format used for register
during GHCB protocol negotiation.

Cc: Michael D Kinney <michael.d.kinney at intel.com>
Cc: Liming Gao <liming.gao at intel.com>
Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com>
---
 MdePkg/Include/Register/Amd/Fam17Msr.h | 42 ++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/MdePkg/Include/Register/Amd/Fam17Msr.h b/MdePkg/Include/Register/Amd/Fam17Msr.h
index 6ef45a9b21d3..466a3143599c 100644
--- a/MdePkg/Include/Register/Amd/Fam17Msr.h
+++ b/MdePkg/Include/Register/Amd/Fam17Msr.h
@@ -17,6 +17,48 @@
 #ifndef __FAM17_MSR_H__

 #define __FAM17_MSR_H__

 

+/**

+  Secure Encrypted Virtualization - Encrypted State (SEV-ES) GHCB register

+

+**/

+#define MSR_SEV_ES_GHCB                    0xc0010130

+

+/**

+  MSR information returned for #MSR_SEV_ES_GHCB

+**/

+typedef union {

+  struct {

+    UINT64  Function:12;

+  } GhcbInfo;

+

+  struct {

+    UINT8   Reserved[3];

+    UINT8   SevEncryptionBitPos;

+    UINT16  SevEsProtocolMin;

+    UINT16  SevEsProtocolMax;

+  } GhcbProtocol;

+

+  struct {

+    UINT64  Function:12;

+    UINT64  ReasonCodeSet:4;

+    UINT64  ReasonCode:8;

+  } GhcbTerminate;

+

+  VOID    *Ghcb;

+

+  UINT64  GhcbPhysicalAddress;

+} MSR_SEV_ES_GHCB_REGISTER;

+

+#define GHCB_INFO_SEV_INFO                 1

+#define GHCB_INFO_SEV_INFO_GET             2

+#define GHCB_INFO_CPUID_REQUEST            4

+#define GHCB_INFO_CPUID_RESPONSE           5

+#define GHCB_INFO_TERMINATE_REQUEST        256

+

+#define GHCB_TERMINATE_GHCB                0

+#define GHCB_TERMINATE_GHCB_GENERAL        0

+#define GHCB_TERMINATE_GHCB_PROTOCOL       1

+

 /**

   Secure Encrypted Virtualization (SEV) status register

 

-- 
2.27.0


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