[edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU generic bug fix

[Yao, Jiewen]

Reviewed-by: jiewen.yao at intel.com

From: De Leon Vazquez, Lorena R <lorena.r.de.leon.vazquez at intel.com>
Sent: Tuesday, March 3, 2020 7:04 AM
To: devel at edk2.groups.io
Cc: Yao, Jiewen <jiewen.yao at intel.com>; Kinney, Michael D <michael.d.kinney at intel.com>
Subject: [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU generic bug fix

Looks like Addresswidth is BIT wise values. Right now these values are not used any

Suggested-by: Star Zeng star.zeng at intel.com<mailto:star.zeng at intel.com>
Signed-off-by: lorena.r.de.leon.vazquez at intel.com<mailto:lorena.r.de.leon.vazquez at intel.com>

--
.../Feature/VTd/IntelVTdDxe/TranslationTable.c        | 11 ++++-------
.../Feature/VTd/IntelVTdDxe/TranslationTableEx.c      | 11 ++++-------
2 files changed, 8 insertions(+), 14 deletions(-)

diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
index cc970c0..61fbb4a 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
@@ -128,14 +128,11 @@ CreateContextEntry (

     DEBUG ((DEBUG_INFO,"Source: S%04x B%02x D%02x F%02x\n", mVtdUnitInformation[VtdIndex].Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function));

-    switch (mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW) {
-    case BIT1:
-      ContextEntry->Bits.AddressWidth = 0x1;
-      break;
-    case BIT2:
-      ContextEntry->Bits.AddressWidth = 0x2;
-      break;
+    if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) == 0) {
+      DEBUG((DEBUG_ERROR, "!!!! 4-level page-table is not supported on VTD %d !!!!\n", VtdIndex));
+      return error;
     }
+    ContextEntry->Bits.AddressWidth = 0x2;
   }

   FlushPageTableMemory (VtdIndex, (UINTN)mVtdUnitInformation[VtdIndex].RootEntryTable, EFI_PAGES_TO_SIZE(EntryTablePages));
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c
index 0da1611..6bd31b7 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c
@@ -78,14 +78,11 @@ CreateExtContextEntry (

     DEBUG ((DEBUG_INFO,"DOMAIN: S%04x, B%02x D%02x F%02x\n", mVtdUnitInformation[VtdIndex].Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function));

-    switch (mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW) {
-    case BIT1:
-      ExtContextEntry->Bits.AddressWidth = 0x1;
-      break;
-    case BIT2:
-      ExtContextEntry->Bits.AddressWidth = 0x2;
-      break;
+    if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) == 0) {
+      DEBUG((DEBUG_ERROR, "!!!! 4-level page-table is not supported on VTD %d !!!!\n", VtdIndex));
+      return error;
     }
+    ContextEntry->Bits.AddressWidth = 0x2;
   }

   FlushPageTableMemory (VtdIndex, (UINTN)mVtdUnitInformation[VtdIndex].ExtRootEntryTable, EFI_PAGES_TO_SIZE(EntryTablePages));
--
2.21.0.windows.1


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