[edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 13/15] MdeModulePkg/PciBusDxe: Enable AtomicOp feature
Javeed, Ashraf
ashraf.javeed at intel.com
Sun May 10 16:14:10 UTC 2020
REF:
https://bugzilla.tianocore.org/show_bug.cgi?id=1954
https://bugzilla.tianocore.org/show_bug.cgi?id=2194
https://bugzilla.tianocore.org/show_bug.cgi?id=2313
https://bugzilla.tianocore.org/show_bug.cgi?id=2499
https://bugzilla.tianocore.org/show_bug.cgi?id=2500
Add the Program phase feature init routine for AtomicOp
PCIe feature.
Signed-off-by: Ashraf Javeed <ashraf.javeed at intel.com>
Signed-off-by: Ray Ni <ray.ni at intel.com>
Cc: Jian J Wang <jian.j.wang at intel.com>
Cc: Hao A Wu <hao.a.wu at intel.com>
Cc: Ray Ni <ray.ni at intel.com>
Cc: Ashraf Javeed <ashraf.javeed at intel.com>
---
MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c | 3 +++
MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c | 62 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h | 16 ++++++++++++++++
3 files changed, 81 insertions(+)
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c
index 35aaffa..401521b 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c
@@ -64,6 +64,8 @@ PCIE_FEATURE_ENTRY mPcieFeatures[] = {
TRUE, { TRUE, TRUE }, { NULL, CompletionTimeoutProgram}},
{ OFFSET_OF (EFI_PCI_EXPRESS_PLATFORM_POLICY, Ltr),
TRUE, { FALSE, TRUE }, { LtrScan, LtrProgram}},
+ { OFFSET_OF (EFI_PCI_EXPRESS_PLATFORM_POLICY, AtomicOp),
+ TRUE, { TRUE, TRUE }, { NULL, AtomicOpProgram}},
};
/**
@@ -241,6 +243,7 @@ PcieNotifyDeviceState (
PcieDeviceState.RelaxedOrdering = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl.Bits.RelaxedOrdering;
PcieDeviceState.NoSnoop = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl.Bits.NoSnoop;
PcieDeviceState.CompletionTimeout = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl2.Uint16 & 0x1F;
+ PcieDeviceState.AtomicOp = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl2.Bits.AtomicOpRequester;
PcieDeviceState.Ltr = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl2.Bits.LtrMechanism;
return mPciePlatformProtocol->NotifyDeviceState (
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c
index 8c7fae0..407c94a 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c
@@ -552,3 +552,65 @@ LtrProgram (
return EFI_SUCCESS;
}
+/**
+ Program AtomicOp.
+
+ @param PciIoDevice A pointer to the PCI_IO_DEVICE.
+ @param Level The level of the PCI device in the heirarchy.
+ Level of root ports is 0.
+ @param Context Pointer to feature specific context.
+
+ @retval EFI_SUCCESS setup of PCI feature AtomicOp is successful.
+ @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
+ valid for the PCI configuration header of the PCI controller.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
+**/
+EFI_STATUS
+AtomicOpProgram (
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN UINTN Level,
+ IN VOID **Context
+ )
+{
+ if (PciIoDevice->DeviceState.AtomicOp == EFI_PCI_EXPRESS_DEVICE_POLICY_AUTO ||
+ PciIoDevice->DeviceState.AtomicOp == EFI_PCI_EXPRESS_DEVICE_POLICY_NOT_APPLICABLE) {
+ return EFI_SUCCESS;
+ }
+
+ //
+ // BIT0 of the policy value is for AtomicOp Requester Enable (BIT6)
+ // BIT1 of the policy value is for AtomicOp Egress Blocking (BIT7)
+ //
+ if ((PciIoDevice->DeviceState.AtomicOp >> 2) != 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (!PciIoDevice->PciExpressCapability.DeviceCapability2.Bits.AtomicOpRouting) {
+ PciIoDevice->DeviceState.AtomicOp &= ~BIT1;
+ }
+ if (PciIoDevice->DeviceState.AtomicOp !=
+ BitFieldRead16 (PciIoDevice->PciExpressCapability.DeviceControl2.Uint16, 6, 7)) {
+
+ DEBUG ((
+ DEBUG_INFO, " %a [%02d|%02d|%02d]: %x -> %x.\n",
+ __FUNCTION__, PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber,
+ BitFieldRead16 (PciIoDevice->PciExpressCapability.DeviceControl2.Uint16, 6, 7),
+ PciIoDevice->DeviceState.AtomicOp
+ ));
+ BitFieldWrite16 (
+ PciIoDevice->PciExpressCapability.DeviceControl2.Uint16, 6, 7,
+ PciIoDevice->DeviceState.AtomicOp
+ );
+ return PciIoDevice->PciIo.Pci.Write (
+ &PciIoDevice->PciIo,
+ EfiPciIoWidthUint16,
+ PciIoDevice->PciExpressCapabilityOffset
+ + OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl2),
+ 1,
+ &PciIoDevice->PciExpressCapability.DeviceControl2.Uint16
+ );
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h
index a9dacf3..5c70e41 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h
@@ -94,4 +94,20 @@ LtrProgram (
IN VOID **Context
);
+/**
+ Program AtomicOp.
+
+ @param PciIoDevice A pointer to the PCI_IO_DEVICE.
+ @param Level The level of the PCI device in the heirarchy.
+ Level of root ports is 0.
+ @param Context Pointer to feature specific context.
+
+ @retval EFI_SUCCESS setup of PCI feature LTR is successful.
+**/
+EFI_STATUS
+AtomicOpProgram (
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN UINTN Level,
+ IN VOID **Context
+ );
#endif
--
2.21.0.windows.1
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