[edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 02/15] MdeModulePkg/PciBusDxe: PciBusDxe Code refactor
Ni, Ray
ray.ni at intel.com
Wed May 13 06:31:53 UTC 2020
Reviewed-by: Ray Ni <ray.ni at intel.com>
> -----Original Message-----
> From: Javeed, Ashraf <ashraf.javeed at intel.com>
> Sent: Monday, May 11, 2020 12:14 AM
> To: devel at edk2.groups.io
> Cc: Wang, Jian J <jian.j.wang at intel.com>; Wu, Hao A <hao.a.wu at intel.com>; Ni, Ray <ray.ni at intel.com>
> Subject: [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 02/15] MdeModulePkg/PciBusDxe: PciBusDxe Code refactor
>
> References:-
> https://bugzilla.tianocore.org/show_bug.cgi?id=1954
> https://bugzilla.tianocore.org/show_bug.cgi?id=2194
> https://bugzilla.tianocore.org/show_bug.cgi?id=2313
> https://bugzilla.tianocore.org/show_bug.cgi?id=2499
> https://bugzilla.tianocore.org/show_bug.cgi?id=2500
>
> This code change represents the code refactoring by expelling the
> previous changes of the PCIe features.
>
> Signed-off-by: Ashraf Javeed <ashraf.javeed at intel.com>
> Cc: Jian J Wang <jian.j.wang at intel.com>
> Cc: Hao A Wu <hao.a.wu at intel.com>
> Cc: Ray Ni <ray.ni at intel.com>
> ---
> MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c | 4 --
> MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 20 ++-------
> MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 10 +----
> MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c | 11 +----
> MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c | 2178 ---------------------------------------------------------------------------------
> ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> ---
> MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h | 399 ----------------------------------------------------------------------------------
> ------------------------------------------------------------------------------------------
> MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c | 1019 ---------------------------------------------------------------------------------
> ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> ----------------
> MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h | 304 ----------------------------------------------------------------------------------
> -------------------------------------------------
> MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c | 902 ----------------------------------------------------------------------------------
> ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> ----------------------------------------------------------------------------------------------------------------------------------------
> MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h | 119 ----------------------------------------------------
> 10 files changed, 6 insertions(+), 4960 deletions(-)
>
> diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c
> index 714101c..53e6dfa 100644
> --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c
> +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c
> @@ -284,10 +284,6 @@ PciBusDriverBindingStart (
> (VOID **) &gPciOverrideProtocol
>
> );
>
> }
>
> - //
>
> - // get the PCI Express Protocol or the PCI Express Override Protocol
>
> - //
>
> - GetPciExpressProtocol ();
>
>
>
> if (mIoMmuProtocol == NULL) {
>
> gBS->LocateProtocol (
>
> diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
> index 34f482d..5a7c1c2 100644
> --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
> +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
> @@ -27,6 +27,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> #include <Protocol/PciOverride.h>
>
> #include <Protocol/PciEnumerationComplete.h>
>
> #include <Protocol/IoMmu.h>
>
> +#include <Protocol/PciExpressOverride.h>
>
> +#include <Protocol/PciExpressPlatform.h>
>
>
>
> #include <Library/DebugLib.h>
>
> #include <Library/UefiDriverEntryPoint.h>
>
> @@ -42,8 +44,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> #include <IndustryStandard/Pci.h>
>
> #include <IndustryStandard/PeImage.h>
>
> #include <IndustryStandard/Acpi.h>
>
> -#include <Protocol/PciExpressOverride.h>
>
> -#include <Protocol/PciExpressPlatform.h>
>
> +
>
>
>
> typedef struct _PCI_IO_DEVICE PCI_IO_DEVICE;
>
> typedef struct _PCI_BAR PCI_BAR;
>
> @@ -81,8 +82,6 @@ typedef enum {
> #include "PciPowerManagement.h"
>
> #include "PciHotPlugSupport.h"
>
> #include "PciLib.h"
>
> -#include "PciPlatformSupport.h"
>
> -#include "PciFeatureSupport.h"
>
>
>
> #define VGABASE1 0x3B0
>
> #define VGALIMIT1 0x3BB
>
> @@ -287,19 +286,6 @@ struct _PCI_IO_DEVICE {
> // This field is used to support this case.
>
> //
>
> UINT16 BridgeIoAlignment;
>
> - //
>
> - // PCI Express features setup flags
>
> - //
>
> - UINT8 SetupMPS;
>
> - UINT8 SetupMRRS;
>
> - PCI_FEATURE_POLICY SetupRO;
>
> - PCI_FEATURE_POLICY SetupNS;
>
> - PCI_FEATURE_POLICY SetupCTO;
>
> - EFI_PCI_EXPRESS_ATOMIC_OP SetupAtomicOp;
>
> - BOOLEAN SetupLtr;
>
> - UINT8 SetupExtTag;
>
> - UINT8 SetupAspm;
>
> - EFI_PCI_EXPRESS_COMMON_CLOCK_CFG SetupCcc;
>
> };
>
>
>
> #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
>
> diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> index e3ad105..3b1559e 100644
> --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> @@ -57,12 +57,6 @@
> PciCommand.h
>
> PciIo.h
>
> PciBus.h
>
> - PciFeatureSupport.c
>
> - PciFeatureSupport.h
>
> - PciPlatformSupport.c
>
> - PciPlatformSupport.h
>
> - PciExpressFeatures.c
>
> - PciExpressFeatures.h
>
>
>
> [Packages]
>
> MdePkg/MdePkg.dec
>
> @@ -97,8 +91,8 @@
> gEfiLoadFile2ProtocolGuid ## SOMETIMES_PRODUCES
>
> gEdkiiIoMmuProtocolGuid ## SOMETIMES_CONSUMES
>
> gEfiLoadedImageDevicePathProtocolGuid ## CONSUMES
>
> - gEfiPciExpressPlatformProtocolGuid ## SOMETIMES_CONSUMES
>
> - gEfiPciExpressOverrideProtocolGuid ## SOMETIMES_CONSUMES
>
> + gEfiPciExpressPlatformProtocolGuid ## SOMETIMES_CONSUMES
>
> + gEfiPciExpressOverrideProtocolGuid ## SOMETIMES_CONSUMES
>
>
>
>
>
> [FeaturePcd]
>
> diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
> index 07ee9ba..5724fd6 100644
> --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
> +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
> @@ -859,16 +859,7 @@ StartPciDevicesOnBridge (
> // the platform is required to indicate its requirement for the initialization
>
> // of PCI Express features by publishing its protocol
>
> //
>
> - if (
>
> - gFullEnumeration
>
> - && IsPciExpressProtocolPresent ()
>
> - ) {
>
> -
>
> - Status = EnumeratePciExpressFeatures (
>
> - Controller,
>
> - RootBridge
>
> - );
>
> - }
>
> +
>
> //
>
> // finally start those PCI bridge port devices only
>
> //
>
> diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c
> b/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c
> deleted file mode 100644
> index 1e2f4a4..0000000
> --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c
> +++ /dev/null
> @@ -1,2178 +0,0 @@
> -/** @file
>
> - PCI standard feature support functions implementation for PCI Bus module..
>
> -
>
> -Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
>
> -
>
> -**/
>
> -
>
> -#include "PciBus.h"
>
> -#include "PciFeatureSupport.h"
>
> -
>
> -VOID
>
> -ReportPciWriteError (
>
> - IN UINT8 Bus,
>
> - IN UINT8 Device,
>
> - IN UINT8 Function,
>
> - IN UINT32 Offset
>
> - )
>
> -{
>
> - DEBUG ((
>
> - DEBUG_ERROR,
>
> - "Unexpected PCI register (%d,%d,%d,0x%x) write error!",
>
> - Bus,
>
> - Device,
>
> - Function,
>
> - Offset
>
> - ));
>
> -}
>
> -
>
> -/**
>
> - Compare and Swap the payload value - between the global variable to maaintain
>
> - common value among all the devices in the PCIe heirarchy from the root bridge
>
> - device and all its child devices; with the device-sepcific setup value.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE.
>
> - @param PciExpressConfigurationTable pointer to PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE
>
> -
>
> - @retval EFI_SUCCESS processing of PCI feature Max_Payload_Size
>
> - is successful.
>
> -**/
>
> -EFI_STATUS
>
> -CasMaxPayloadSize (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfigurationTable
>
> - )
>
> -{
>
> - UINT8 MpsValue;
>
> -
>
> - //
>
> - // align the MPS of the tree to the HCF with this device
>
> - //
>
> - if (PciExpressConfigurationTable) {
>
> - MpsValue = PciExpressConfigurationTable->Max_Payload_Size;
>
> -
>
> - MpsValue = MIN (PciDevice->SetupMPS, MpsValue);
>
> - PciDevice->SetupMPS = MIN (PciDevice->SetupMPS, MpsValue);
>
> -
>
> - if (MpsValue != PciExpressConfigurationTable->Max_Payload_Size) {
>
> - PciExpressConfigurationTable->Max_Payload_Size = MpsValue;
>
> - }
>
> - }
>
> -
>
> - DEBUG ((
>
> - DEBUG_INFO,
>
> - "MPS: %d [DevCap:%d],",
>
> - PciDevice->SetupMPS, PciDevice->PciExpressCapabilityStructure.DeviceCapability.Bits.MaxPayloadSize
>
> - ));
>
> -
>
> - return EFI_SUCCESS;
>
> -}
>
> -
>
> -/**
>
> - The main routine which process the PCI feature Max_Payload_Size as per the
>
> - device-specific platform policy, as well as in complaince with the PCI Base
>
> - specification Revision 4, that aligns the value for the entire PCI heirarchy
>
> - starting from its physical PCI Root port / Bridge device.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE.
>
> - @param PciExpressConfigurationTable pointer to PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE
>
> -
>
> - @retval EFI_SUCCESS processing of PCI feature Max_Payload_Size
>
> - is successful.
>
> -**/
>
> -EFI_STATUS
>
> -SetupMaxPayloadSize (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfigurationTable
>
> - )
>
> -{
>
> - PCI_REG_PCIE_DEVICE_CAPABILITY PciDeviceCap;
>
> - UINT8 MpsValue;
>
> -
>
> -
>
> - PciDeviceCap.Uint32 = PciDevice->PciExpressCapabilityStructure.DeviceCapability.Uint32;
>
> -
>
> - if (PciDevice->SetupMPS == EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_AUTO) {
>
> - //
>
> - // configure this feature as per its PCIe device capabilities
>
> - //
>
> - MpsValue = (UINT8)PciDeviceCap.Bits.MaxPayloadSize;
>
> - //
>
> - // no change to PCI Root ports without any endpoint device
>
> - //
>
> - if (IS_PCI_BRIDGE (&PciDevice->Pci) && PciDeviceCap.Bits.MaxPayloadSize) {
>
> - if (IsListEmpty (&PciDevice->ChildList)) {
>
> - //
>
> - // No device on root bridge
>
> - //
>
> - MpsValue = PCIE_MAX_PAYLOAD_SIZE_128B;
>
> - }
>
> - }
>
> - } else {
>
> - MpsValue = SetDevicePolicyPciExpressMps (PciDevice->SetupMPS);
>
> - }
>
> - //
>
> - // discard device policy override request if greater than PCI device capability
>
> - //
>
> - PciDevice->SetupMPS = MIN ((UINT8)PciDeviceCap.Bits.MaxPayloadSize, MpsValue);
>
> -
>
> - return CasMaxPayloadSize (
>
> - PciDevice,
>
> - PciExpressConfigurationTable
>
> - );
>
> -}
>
> -
>
> -/**
>
> - Overrides the PCI Device Control register MaxPayloadSize register field; if
>
> - the hardware value is different than the intended value.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE instance.
>
> -
>
> - @retval EFI_SUCCESS The data was read from or written to the PCI device.
>
> - @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
>
> - valid for the PCI configuration header of the PCI controller.
>
> - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
>
> -
>
> -**/
>
> -EFI_STATUS
>
> -ProgramMaxPayloadSize (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN VOID *PciExFeatureConfiguration
>
> - )
>
> -{
>
> - PCI_REG_PCIE_DEVICE_CONTROL PcieDev;
>
> - UINT32 Offset;
>
> - EFI_STATUS Status;
>
> - EFI_TPL OldTpl;
>
> -
>
> - PcieDev.Uint16 = 0;
>
> - Offset = PciDevice->PciExpressCapabilityOffset +
>
> - OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl);
>
> - Status = PciDevice->PciIo.Pci.Read (
>
> - &PciDevice->PciIo,
>
> - EfiPciIoWidthUint16,
>
> - Offset,
>
> - 1,
>
> - &PcieDev.Uint16
>
> - );
>
> - ASSERT (Status == EFI_SUCCESS);
>
> -
>
> - if (PcieDev.Bits.MaxPayloadSize != PciDevice->SetupMPS) {
>
> - PcieDev.Bits.MaxPayloadSize = PciDevice->SetupMPS;
>
> - DEBUG (( DEBUG_INFO, "MPS=%d,", PciDevice->SetupMPS));
>
> -
>
> - //
>
> - // Raise TPL to high level to disable timer interrupt while the write operation completes
>
> - //
>
> - OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
>
> -
>
> - Status = PciDevice->PciIo.Pci.Write (
>
> - &PciDevice->PciIo,
>
> - EfiPciIoWidthUint16,
>
> - Offset,
>
> - 1,
>
> - &PcieDev.Uint16
>
> - );
>
> - //
>
> - // Restore TPL to its original level
>
> - //
>
> - gBS->RestoreTPL (OldTpl);
>
> -
>
> - if (!EFI_ERROR(Status)) {
>
> - PciDevice->PciExpressCapabilityStructure.DeviceControl.Uint16 = PcieDev.Uint16;
>
> - } else {
>
> - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber, PciDevice->FunctionNumber, Offset);
>
> - }
>
> - } else {
>
> - DEBUG (( DEBUG_INFO, "No MPS=%d,", PciDevice->SetupMPS));
>
> - }
>
> -
>
> - return Status;
>
> -}
>
> -
>
> -EFI_STATUS
>
> -ConditionalCasMaxReadReqSize (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfigurationTable
>
> - )
>
> -{
>
> - //
>
> - // align the Max_Read_Request_Size of the PCI tree based on 3 conditions:
>
> - // first, if user defines MRRS for any one PCI device in the tree than align
>
> - // all the devices in the PCI tree.
>
> - // second, if user override is not define for this PCI tree than setup the MRRS
>
> - // based on MPS value of the tree to meet the criteria for the isochronous
>
> - // traffic.
>
> - // third, if no user override, or platform firmware policy has not selected
>
> - // this PCI bus driver to configure the MPS; than configure the MRRS to a
>
> - // highest common value of PCI device capability for the MPS found among all
>
> - // the PCI devices in this tree
>
> - //
>
> - if (PciExpressConfigurationTable) {
>
> - if (PciExpressConfigurationTable->Lock_Max_Read_Request_Size) {
>
> - PciDevice->SetupMRRS = PciExpressConfigurationTable->Max_Read_Request_Size;
>
> - } else {
>
> - if (mPciExpressPlatformPolicy.Mps) {
>
> - PciDevice->SetupMRRS = PciDevice->SetupMPS;
>
> - } else {
>
> - PciDevice->SetupMRRS = MIN (
>
> - PciDevice->SetupMRRS,
>
> - PciExpressConfigurationTable->Max_Read_Request_Size
>
> - );
>
> - }
>
> - PciExpressConfigurationTable->Max_Read_Request_Size = PciDevice->SetupMRRS;
>
> - }
>
> - }
>
> - DEBUG (( DEBUG_INFO, "MRRS: %d,", PciDevice->SetupMRRS));
>
> -
>
> - return EFI_SUCCESS;
>
> -}
>
> -
>
> -/**
>
> - The main routine which process the PCI feature Max_Read_Req_Size as per the
>
> - device-specific platform policy, as well as in complaince with the PCI Base
>
> - specification Revision 4, that aligns the value for the entire PCI heirarchy
>
> - starting from its physical PCI Root port / Bridge device.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE.
>
> - @param PciExpressConfigurationTable pointer to PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE
>
> -
>
> - @retval EFI_SUCCESS processing of PCI feature Max_Read_Req_Size
>
> - is successful.
>
> -**/
>
> -EFI_STATUS
>
> -SetupMaxReadReqSize (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfigurationTable
>
> - )
>
> -{
>
> - PCI_REG_PCIE_DEVICE_CAPABILITY PciDeviceCap;
>
> - UINT8 MrrsValue;
>
> -
>
> - PciDeviceCap.Uint32 = PciDevice->PciExpressCapabilityStructure.DeviceCapability.Uint32;
>
> -
>
> - if (PciDevice->SetupMRRS == EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_AUTO) {
>
> - //
>
> - // The maximum read request size is not the data packet size of the TLP,
>
> - // but the memory read request size, and set to the function as a requestor
>
> - // to not exceed this limit.
>
> - // However, for the PCI device capable of isochronous traffic; this memory read
>
> - // request size should not extend beyond the Max_Payload_Size. Thus, in case if
>
> - // device policy return by platform indicates to set as per device capability
>
> - // than set as per Max_Payload_Size configuration value
>
> - //
>
> - if (mPciExpressPlatformPolicy.Mps) {
>
> - MrrsValue = PciDevice->SetupMPS;
>
> - } else {
>
> - //
>
> - // in case this driver is not required to configure the Max_Payload_Size
>
> - // than consider programming HCF of the device capability's Max_Payload_Size
>
> - // in this PCI hierarchy; thus making this an implementation specific feature
>
> - // which the platform should avoid. For better results, the platform should
>
> - // make both the Max_Payload_Size & Max_Read_Request_Size to be configured
>
> - // by this driver
>
> - //
>
> - MrrsValue = (UINT8)PciDeviceCap.Bits.MaxPayloadSize;
>
> - }
>
> - } else {
>
> - //
>
> - // override as per platform based device policy
>
> - //
>
> - MrrsValue = SetDevicePolicyPciExpressMrrs (PciDevice->SetupMRRS);
>
> - //
>
> - // align this device's Max_Read_Request_Size value to the entire PCI tree
>
> - //
>
> - if (PciExpressConfigurationTable) {
>
> - if (!PciExpressConfigurationTable->Lock_Max_Read_Request_Size) {
>
> - PciExpressConfigurationTable->Lock_Max_Read_Request_Size = TRUE;
>
> - PciExpressConfigurationTable->Max_Read_Request_Size = MrrsValue;
>
> - } else {
>
> - //
>
> - // in case of another user enforced value of MRRS within the same tree,
>
> - // pick the smallest between the locked value and this value; to set
>
> - // across entire PCI tree nodes
>
> - //
>
> - MrrsValue = MIN (
>
> - MrrsValue,
>
> - PciExpressConfigurationTable->Max_Read_Request_Size
>
> - );
>
> - PciExpressConfigurationTable->Max_Read_Request_Size = MrrsValue;
>
> - }
>
> - }
>
> - }
>
> - //
>
> - // align this device's Max_Read_Request_Size to derived configuration value
>
> - //
>
> - PciDevice->SetupMRRS = MrrsValue;
>
> -
>
> - return ConditionalCasMaxReadReqSize (
>
> - PciDevice,
>
> - PciExpressConfigurationTable
>
> - );
>
> -}
>
> -
>
> -
>
> -/**
>
> - Overrides the PCI Device Control register Max_Read_Req_Size register field; if
>
> - the hardware value is different than the intended value.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE instance.
>
> -
>
> - @retval EFI_SUCCESS The data was read from or written to the PCI controller.
>
> - @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
>
> - valid for the PCI configuration header of the PCI controller.
>
> - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
>
> -
>
> -**/
>
> -EFI_STATUS
>
> -ProgramMaxReadReqSize (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN VOID *PciExFeatureConfiguration
>
> - )
>
> -{
>
> - PCI_REG_PCIE_DEVICE_CONTROL PcieDev;
>
> - UINT32 Offset;
>
> - EFI_STATUS Status;
>
> - EFI_TPL OldTpl;
>
> -
>
> - PcieDev.Uint16 = 0;
>
> - Offset = PciDevice->PciExpressCapabilityOffset +
>
> - OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl);
>
> - Status = PciDevice->PciIo.Pci.Read (
>
> - &PciDevice->PciIo,
>
> - EfiPciIoWidthUint16,
>
> - Offset,
>
> - 1,
>
> - &PcieDev.Uint16
>
> - );
>
> - ASSERT (Status == EFI_SUCCESS);
>
> -
>
> - if (PcieDev.Bits.MaxReadRequestSize != PciDevice->SetupMRRS) {
>
> - PcieDev.Bits.MaxReadRequestSize = PciDevice->SetupMRRS;
>
> - DEBUG (( DEBUG_INFO, "MRRS: %d,", PciDevice->SetupMRRS));
>
> -
>
> - //
>
> - // Raise TPL to high level to disable timer interrupt while the write operation completes
>
> - //
>
> - OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
>
> -
>
> - Status = PciDevice->PciIo.Pci.Write (
>
> - &PciDevice->PciIo,
>
> - EfiPciIoWidthUint16,
>
> - Offset,
>
> - 1,
>
> - &PcieDev.Uint16
>
> - );
>
> - //
>
> - // Restore TPL to its original level
>
> - //
>
> - gBS->RestoreTPL (OldTpl);
>
> -
>
> - if (!EFI_ERROR(Status)) {
>
> - PciDevice->PciExpressCapabilityStructure.DeviceControl.Uint16 = PcieDev.Uint16;
>
> - } else {
>
> - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber, PciDevice->FunctionNumber, Offset);
>
> - }
>
> - } else {
>
> - DEBUG (( DEBUG_INFO, "No MRRS=%d,", PciDevice->SetupMRRS));
>
> - }
>
> -
>
> - return Status;
>
> -}
>
> -
>
> -/**
>
> - Overrides the PCI Device Control register Relax Order register field; if
>
> - the hardware value is different than the intended value.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE instance.
>
> -
>
> - @retval EFI_SUCCESS The data was read from or written to the PCI device.
>
> - @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
>
> - valid for the PCI configuration header of the PCI controller.
>
> - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
>
> -
>
> -**/
>
> -EFI_STATUS
>
> -ProgramRelaxOrder (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN VOID *PciExFeatureConfiguration
>
> - )
>
> -{
>
> - PCI_REG_PCIE_DEVICE_CONTROL PcieDev;
>
> - UINT32 Offset;
>
> - EFI_STATUS Status;
>
> - EFI_TPL OldTpl;
>
> -
>
> - PcieDev.Uint16 = 0;
>
> - Offset = PciDevice->PciExpressCapabilityOffset +
>
> - OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl);
>
> - Status = PciDevice->PciIo.Pci.Read (
>
> - &PciDevice->PciIo,
>
> - EfiPciIoWidthUint16,
>
> - Offset,
>
> - 1,
>
> - &PcieDev.Uint16
>
> - );
>
> - ASSERT (Status == EFI_SUCCESS);
>
> -
>
> - if (PciDevice->SetupRO.Override
>
> - && PcieDev.Bits.RelaxedOrdering != PciDevice->SetupRO.Act
>
> - ) {
>
> - PcieDev.Bits.RelaxedOrdering = PciDevice->SetupRO.Act;
>
> - DEBUG (( DEBUG_INFO, "RO=%d,", PciDevice->SetupRO.Act));
>
> -
>
> - //
>
> - // Raise TPL to high level to disable timer interrupt while the write operation completes
>
> - //
>
> - OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
>
> -
>
> - Status = PciDevice->PciIo.Pci.Write (
>
> - &PciDevice->PciIo,
>
> - EfiPciIoWidthUint16,
>
> - Offset,
>
> - 1,
>
> - &PcieDev.Uint16
>
> - );
>
> - //
>
> - // Restore TPL to its original level
>
> - //
>
> - gBS->RestoreTPL (OldTpl);
>
> -
>
> - if (!EFI_ERROR(Status)) {
>
> - PciDevice->PciExpressCapabilityStructure.DeviceControl.Uint16 = PcieDev.Uint16;
>
> - } else {
>
> - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber, PciDevice->FunctionNumber, Offset);
>
> - }
>
> - } else {
>
> - DEBUG (( DEBUG_INFO, "No RO,", PciDevice->SetupRO.Act));
>
> - }
>
> -
>
> - return Status;
>
> -}
>
> -
>
> -/**
>
> - Overrides the PCI Device Control register No-Snoop register field; if
>
> - the hardware value is different than the intended value.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE instance.
>
> -
>
> - @retval EFI_SUCCESS The data was read from or written to the PCI device.
>
> - @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
>
> - valid for the PCI configuration header of the PCI controller.
>
> - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
>
> -
>
> -**/
>
> -EFI_STATUS
>
> -ProgramNoSnoop (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN VOID *PciExFeatureConfiguration
>
> - )
>
> -{
>
> - PCI_REG_PCIE_DEVICE_CONTROL PcieDev;
>
> - UINT32 Offset;
>
> - EFI_STATUS Status;
>
> - EFI_TPL OldTpl;
>
> -
>
> - PcieDev.Uint16 = 0;
>
> - Offset = PciDevice->PciExpressCapabilityOffset +
>
> - OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl);
>
> - Status = PciDevice->PciIo.Pci.Read (
>
> - &PciDevice->PciIo,
>
> - EfiPciIoWidthUint16,
>
> - Offset,
>
> - 1,
>
> - &PcieDev.Uint16
>
> - );
>
> - ASSERT (Status == EFI_SUCCESS);
>
> -
>
> - if (PciDevice->SetupNS.Override
>
> - && PcieDev.Bits.NoSnoop != PciDevice->SetupNS.Act
>
> - ) {
>
> - PcieDev.Bits.NoSnoop = PciDevice->SetupNS.Act;
>
> - DEBUG (( DEBUG_INFO, "NS=%d", PciDevice->SetupNS.Act));
>
> -
>
> - //
>
> - // Raise TPL to high level to disable timer interrupt while the write operation completes
>
> - //
>
> - OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
>
> -
>
> - Status = PciDevice->PciIo.Pci.Write (
>
> - &PciDevice->PciIo,
>
> - EfiPciIoWidthUint16,
>
> - Offset,
>
> - 1,
>
> - &PcieDev.Uint16
>
> - );
>
> - //
>
> - // Restore TPL to its original level
>
> - //
>
> - gBS->RestoreTPL (OldTpl);
>
> -
>
> - if (!EFI_ERROR(Status)) {
>
> - PciDevice->PciExpressCapabilityStructure.DeviceControl.Uint16 = PcieDev.Uint16;
>
> - } else {
>
> - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber, PciDevice->FunctionNumber, Offset);
>
> - }
>
> - } else {
>
> - DEBUG (( DEBUG_INFO, "No NS,", PciDevice->SetupRO.Act));
>
> - }
>
> -
>
> - return Status;
>
> -}
>
> -
>
> -/**
>
> - To determine the CTO Range A values
>
> -
>
> - @param CtoValue input CTO range value from 0 to 14
>
> - @retval TRUE the given CTO value belongs to Range A
>
> - FALSE the given value does not belong to Range A
>
> -**/
>
> -BOOLEAN
>
> -IsCtoRangeA (
>
> - IN UINT8 CtoValue
>
> - )
>
> -{
>
> - switch (CtoValue) {
>
> - case PCIE_COMPLETION_TIMEOUT_50US_100US:
>
> - case PCIE_COMPLETION_TIMEOUT_1MS_10MS:
>
> - return TRUE;
>
> - }
>
> - return FALSE;
>
> -}
>
> -
>
> -/**
>
> - To determine the CTO Range B values
>
> -
>
> - @param CtoValue input CTO range value from 0 to 14
>
> - @retval TRUE the given CTO value belongs to Range B
>
> - FALSE the given value does not belong to Range B
>
> -**/
>
> -BOOLEAN
>
> -IsCtoRangeB (
>
> - IN UINT8 CtoValue
>
> - )
>
> -{
>
> - switch (CtoValue) {
>
> - case PCIE_COMPLETION_TIMEOUT_16MS_55MS:
>
> - case PCIE_COMPLETION_TIMEOUT_65MS_210MS:
>
> - return TRUE;
>
> - }
>
> - return FALSE;
>
> -}
>
> -
>
> -/**
>
> - To determine the CTO Range C values
>
> -
>
> - @param CtoValue input CTO range value from 0 to 14
>
> - @retval TRUE the given CTO value belongs to Range C
>
> - FALSE the given value does not belong to Range C
>
> -**/
>
> -BOOLEAN
>
> -IsCtoRangeC (
>
> - IN UINT8 CtoValue
>
> - )
>
> -{
>
> - switch (CtoValue) {
>
> - case PCIE_COMPLETION_TIMEOUT_260MS_900MS:
>
> - case PCIE_COMPLETION_TIMEOUT_1S_3_5S:
>
> - return TRUE;
>
> - }
>
> - return FALSE;
>
> -}
>
> -
>
> -/**
>
> - To determine the CTO Range D values
>
> -
>
> - @param CtoValue input CTO range value from 0 to 14
>
> - @retval TRUE the given CTO value belongs to Range D
>
> - FALSE the given value does not belong to Range D
>
> -**/
>
> -BOOLEAN
>
> -IsCtoRangeD (
>
> - IN UINT8 CtoValue
>
> - )
>
> -{
>
> - switch (CtoValue) {
>
> - case PCIE_COMPLETION_TIMEOUT_4S_13S:
>
> - case PCIE_COMPLETION_TIMEOUT_17S_64S:
>
> - return TRUE;
>
> - }
>
> - return FALSE;
>
> -}
>
> -
>
> -/**
>
> - The main routine which setup the PCI feature Completion Timeout as per the
>
> - device-specific platform policy, as well as in complaince with the PCI Base
>
> - specification Revision 4.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE.
>
> -
>
> - @retval EFI_SUCCESS processing of PCI feature CTO is successful.
>
> -**/
>
> -EFI_STATUS
>
> -SetupCompletionTimeout (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN VOID *PciExFeatureConfiguration
>
> - )
>
> -{
>
> - PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCap2;
>
> - UINT8 CtoRangeValue;
>
> -
>
> - if (!PciDevice->SetupCTO.Override) {
>
> - //
>
> - // No override of CTO is required for this device
>
> - //
>
> - return EFI_SUCCESS;
>
> - }
>
> -
>
> - //
>
> - // determine the CTO range values as per its device capability register
>
> - //
>
> - DeviceCap2.Uint32 = PciDevice->PciExpressCapabilityStructure.DeviceCapability2.Uint32;
>
> - if (!DeviceCap2.Bits.CompletionTimeoutRanges
>
> - && !DeviceCap2.Bits.CompletionTimeoutDisable
>
> - ) {
>
> - //
>
> - // device does not support the CTO mechanism, hence no override is applicable
>
> - //
>
> - return EFI_SUCCESS;
>
> - }
>
> -
>
> - //
>
> - // override the device CTO values if applicable
>
> - //
>
> - if (PciDevice->SetupCTO.Act) {
>
> - //
>
> - // program the CTO range values
>
> - //
>
> - if (DeviceCap2.Bits.CompletionTimeoutRanges) {
>
> - CtoRangeValue = PCIE_COMPLETION_TIMEOUT_50US_50MS;
>
> - //
>
> - // in case if the supported CTO range and the requirement from platform
>
> - // policy does not match, than the CTO range setting would be based on
>
> - // this driver's implementation specific, and its rules are as follows:-
>
> - //
>
> - // if device is capable of Range A only and if platform ask for any of
>
> - // ranges B, C, D; than this implementation will only program the default
>
> - // range value for the duration of 50us to 50ms.
>
> - //
>
> - // if device is capable of Range B, or range B & C, or Ranges B, C & D only
>
> - // and if the platform ask for the Range A; than this implementation will
>
> - // only program the default range value for the duration of 50us to 50ms.
>
> - //
>
> - // if the device is capable of Range B only, or the ranges A & B; and the
>
> - // platform ask for Range C, or Range D values, than this implementation
>
> - // will only program the Range B value for the duration of 65ms to 210ms.
>
> - //
>
> - // if the device is capable of Ranges B & C, or Ranges A, B, and C; and
>
> - // if the platform ask for Range D values; than this implementation will
>
> - // only program the Range C for the duration of 1s to 3.5s.
>
> - //
>
> -
>
> - switch (DeviceCap2.Bits.CompletionTimeoutRanges) {
>
> - case PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED:
>
> - if (IsCtoRangeA (PciDevice->SetupCTO.Support)) {
>
> - CtoRangeValue = PciDevice->SetupCTO.Support;
>
> - }
>
> - //
>
> - // if device is capable of Range A only and if platform ask for any of
>
> - // ranges B, C, D; than this implementation will only program the default
>
> - // range value for the duration of 50us to 50ms.
>
> - //
>
> - if (IsCtoRangeB (PciDevice->SetupCTO.Support)
>
> - || IsCtoRangeC (PciDevice->SetupCTO.Support)
>
> - || IsCtoRangeD (PciDevice->SetupCTO.Support)
>
> - ) {
>
> - CtoRangeValue = PCIE_COMPLETION_TIMEOUT_50US_50MS;
>
> - }
>
> - break;
>
> -
>
> - case PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED:
>
> - //
>
> - // if device is capable of Range B, or range B & C, or Ranges B, C & D only
>
> - // and if the platform ask for the Range A; than this implementation will
>
> - // only program the default range value for the duration of 50us to 50ms.
>
> - //
>
> - if (IsCtoRangeA (PciDevice->SetupCTO.Support)) {
>
> - CtoRangeValue = PCIE_COMPLETION_TIMEOUT_50US_50MS;
>
> - }
>
> -
>
> - if (IsCtoRangeB (PciDevice->SetupCTO.Support)) {
>
> - CtoRangeValue = PciDevice->SetupCTO.Support;
>
> - }
>
> - //
>
> - // if the device is capable of Range B only, or the ranges A & B; and the
>
> - // platform ask for Range C, or Range D values, than this implementation
>
> - // will only program the Range B value for the duration of 65ms to 210ms.
>
> - //
>
> - if (IsCtoRangeC (PciDevice->SetupCTO.Support)
>
> - || IsCtoRangeD (PciDevice->SetupCTO.Support)
>
> - ) {
>
> - CtoRangeValue = PCIE_COMPLETION_TIMEOUT_65MS_210MS;
>
> - }
>
> - break;
>
> -
>
> - case PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED:
>
> - if (IsCtoRangeA (PciDevice->SetupCTO.Support)) {
>
> - CtoRangeValue = PCIE_COMPLETION_TIMEOUT_50US_50MS;
>
> - }
>
> -
>
> - if (IsCtoRangeB (PciDevice->SetupCTO.Support)
>
> - || IsCtoRangeC (PciDevice->SetupCTO.Support)
>
> - ) {
>
> - CtoRangeValue = PciDevice->SetupCTO.Support;
>
> - }
>
> - //
>
> - // if the device is capable of Ranges B & C, or Ranges A, B, and C; and
>
> - // if the platform ask for Range D values; than this implementation will
>
> - // only program the Range C for the duration of 1s to 3.5s.
>
> - //
>
> - if (IsCtoRangeD (PciDevice->SetupCTO.Support)) {
>
> - CtoRangeValue = PCIE_COMPLETION_TIMEOUT_1S_3_5S;
>
> - }
>
> - break;
>
> -
>
> - case PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED:
>
> - if (IsCtoRangeA (PciDevice->SetupCTO.Support)) {
>
> - CtoRangeValue = PCIE_COMPLETION_TIMEOUT_50US_50MS;
>
> - }
>
> - if (IsCtoRangeB (PciDevice->SetupCTO.Support)
>
> - || IsCtoRangeC (PciDevice->SetupCTO.Support)
>
> - || IsCtoRangeD (PciDevice->SetupCTO.Support)
>
> - ) {
>
> - CtoRangeValue = PciDevice->SetupCTO.Support;
>
> - }
>
> - break;
>
> -
>
> - case PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED:
>
> - if (IsCtoRangeA (PciDevice->SetupCTO.Support)
>
> - || IsCtoRangeB (PciDevice->SetupCTO.Support)
>
> - ) {
>
> - CtoRangeValue = PciDevice->SetupCTO.Support;
>
> - }
>
> - if (IsCtoRangeC (PciDevice->SetupCTO.Support)
>
> - || IsCtoRangeD (PciDevice->SetupCTO.Support)
>
> - ) {
>
> - CtoRangeValue = PCIE_COMPLETION_TIMEOUT_65MS_210MS;
>
> - }
>
> - break;
>
> -
>
> - case PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED:
>
> - if (IsCtoRangeA (PciDevice->SetupCTO.Support)
>
> - || IsCtoRangeB (PciDevice->SetupCTO.Support)
>
> - || IsCtoRangeC (PciDevice->SetupCTO.Support)
>
> - ) {
>
> - CtoRangeValue = PciDevice->SetupCTO.Support;
>
> - }
>
> - if (IsCtoRangeD (PciDevice->SetupCTO.Support)) {
>
> - CtoRangeValue = PCIE_COMPLETION_TIMEOUT_1S_3_5S;
>
> - }
>
> - break;
>
> -
>
> - case PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED:
>
> - if (IsCtoRangeA (PciDevice->SetupCTO.Support)
>
> - || IsCtoRangeB (PciDevice->SetupCTO.Support)
>
> - || IsCtoRangeC (PciDevice->SetupCTO.Support)
>
> - || IsCtoRangeD (PciDevice->SetupCTO.Support)
>
> - ) {
>
> - CtoRangeValue = PciDevice->SetupCTO.Support;
>
> - }
>
> - break;
>
> -
>
> - default:
>
> - DEBUG ((
>
> - DEBUG_ERROR,
>
> - "Invalid CTO range: %d\n",
>
> - DeviceCap2.Bits.CompletionTimeoutRanges
>
> - ));
>
> - return EFI_INVALID_PARAMETER;
>
> - }
>
> -
>
> - if (PciDevice->SetupCTO.Support != CtoRangeValue) {
>
> - PciDevice->SetupCTO.Support = CtoRangeValue;
>
> - }
>
> - }
>
> - DEBUG (( DEBUG_INFO, "CTO enable: %d, CTO range: 0x%x,",
>
> - PciDevice->SetupCTO.Act,
>
> - PciDevice->SetupCTO.Support
>
> - ));
>
> - }
>
> - return EFI_SUCCESS;
>
> -}
>
> -
>
> -/**
>
> - Overrides the PCI Device Control2 register Completion Timeout range; if
>
> - the hardware value is different than the intended value.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE instance.
>
> -
>
> - @retval EFI_SUCCESS The data was read from or written to the PCI device.
>
> - @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
>
> - valid for the PCI configuration header of the PCI controller.
>
> - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
>
> -
>
> -**/
>
> -EFI_STATUS
>
> -ProgramCompletionTimeout (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN VOID *PciExFeatureConfiguration
>
> - )
>
> -{
>
> - PCI_REG_PCIE_DEVICE_CONTROL2 DeviceCtl2;
>
> - PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCap2;
>
> - UINT32 Offset;
>
> - EFI_STATUS Status;
>
> - EFI_TPL OldTpl;
>
> -
>
> - if (!PciDevice->SetupCTO.Override) {
>
> - //
>
> - // No override of CTO is required for this device
>
> - //
>
> - DEBUG (( DEBUG_INFO, "CTO skipped,"));
>
> - return EFI_SUCCESS;
>
> - }
>
> -
>
> - //
>
> - // to program the CTO range values, determine in its device capability register
>
> - //
>
> - DeviceCap2.Uint32 = PciDevice->PciExpressCapabilityStructure.DeviceCapability2.Uint32;
>
> - if (DeviceCap2.Bits.CompletionTimeoutRanges
>
> - || DeviceCap2.Bits.CompletionTimeoutDisable) {
>
> - //
>
> - // device supports the CTO mechanism
>
> - //
>
> - DeviceCtl2.Uint16 = 0;
>
> - Offset = PciDevice->PciExpressCapabilityOffset +
>
> - OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl2);
>
> - Status = PciDevice->PciIo.Pci.Read (
>
> - &PciDevice->PciIo,
>
> - EfiPciIoWidthUint16,
>
> - Offset,
>
> - 1,
>
> - &DeviceCtl2.Uint16
>
> - );
>
> - ASSERT (Status == EFI_SUCCESS);
>
> - } else {
>
> - //
>
> - // device does not support the CTO mechanism, hence no override performed
>
> - //
>
> - DEBUG (( DEBUG_INFO, "CTO n/a,"));
>
> - return EFI_SUCCESS;
>
> - }
>
> -
>
> - //
>
> - // override the device CTO values if applicable
>
> - //
>
> - if (PciDevice->SetupCTO.Act) {
>
> - //
>
> - // program the CTO range values
>
> - //
>
> - if (PciDevice->SetupCTO.Support != DeviceCtl2.Bits.CompletionTimeoutValue) {
>
> - DeviceCtl2.Bits.CompletionTimeoutValue = PciDevice->SetupCTO.Support;
>
> - }
>
> - } else {
>
> - //
>
> - // disable the CTO mechanism in device
>
> - //
>
> - DeviceCtl2.Bits.CompletionTimeoutValue = 0;
>
> - DeviceCtl2.Bits.CompletionTimeoutDisable = 1;
>
> - }
>
> - DEBUG (( DEBUG_INFO, "CTO disable: %d, CTO range: 0x%x,",
>
> - DeviceCtl2.Bits.CompletionTimeoutDisable,
>
> - DeviceCtl2.Bits.CompletionTimeoutValue
>
> - ));
>
> -
>
> - //
>
> - // Raise TPL to high level to disable timer interrupt while the write operation completes
>
> - //
>
> - OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
>
> -
>
> - Status = PciDevice->PciIo.Pci.Write (
>
> - &PciDevice->PciIo,
>
> - EfiPciIoWidthUint16,
>
> - Offset,
>
> - 1,
>
> - &DeviceCtl2.Uint16
>
> - );
>
> - //
>
> - // Restore TPL to its original level
>
> - //
>
> - gBS->RestoreTPL (OldTpl);
>
> -
>
> - if (!EFI_ERROR(Status)) {
>
> - PciDevice->PciExpressCapabilityStructure.DeviceControl2.Uint16 = DeviceCtl2.Uint16;
>
> - } else {
>
> - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber, PciDevice->FunctionNumber, Offset);
>
> - }
>
> - return Status;
>
> -}
>
> -
>
> -/**
>
> - Routine to setup the AtomicOp Requester in the PCI device, verifies the routing
>
> - support in the bridge devices, to be complaint as per the PCI Base specification.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE.
>
> - @param PciExFeatureConfiguration pointer to common configuration table to
>
> - initialize the PCI Express feature
>
> -
>
> - @retval EFI_SUCCESS bridge device routing capability is successful.
>
> - EFI_INVALID_PARAMETER input parameter is NULL
>
> -**/
>
> -EFI_STATUS
>
> -SetupAtomicOpRoutingSupport (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExFeatureConfiguration
>
> - )
>
> -{
>
> - //
>
> - // to enable the AtomicOp Requester in the PCI EP device; its Root Port (bridge),
>
> - // and its PCIe switch upstream & downstream ports (if present) needs to support
>
> - // the AtomicOp Routing capability.
>
> - //
>
> - if (IS_PCI_BRIDGE (&PciDevice->Pci)) {
>
> - if (!PciDevice->PciExpressCapabilityStructure.DeviceCapability2.Bits.AtomicOpRouting) {
>
> - //
>
> - // since the AtomicOp Routing support flag is initialized as TRUE, negate
>
> - // in case if any of the PCI Bridge device in the PCI tree does not support
>
> - // the AtomicOp Routing capability
>
> - //
>
> - if (PciExFeatureConfiguration == NULL) {
>
> - return EFI_INVALID_PARAMETER;
>
> - }
>
> - PciExFeatureConfiguration->AtomicOpRoutingSupported = FALSE;
>
> - }
>
> - }
>
> -
>
> - return EFI_SUCCESS;
>
> -}
>
> -
>
> -/**
>
> - Overrides the PCI Device Control 2 register AtomicOp Requester enable field; if
>
> - the hardware value is different than the intended value.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE instance.
>
> -
>
> - @retval EFI_SUCCESS The data was read from or written to the PCI device.
>
> - @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
>
> - valid for the PCI configuration header of the PCI controller.
>
> - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
>
> -
>
> -**/
>
> -EFI_STATUS
>
> -ProgramAtomicOp (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExFeatureConfiguration
>
> - )
>
> -{
>
> - PCI_REG_PCIE_DEVICE_CONTROL2 PcieDev;
>
> - UINT32 Offset;
>
> - EFI_STATUS Status;
>
> - EFI_TPL OldTpl;
>
> -
>
> - PcieDev.Uint16 = 0;
>
> - Offset = PciDevice->PciExpressCapabilityOffset +
>
> - OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl2);
>
> - Status = PciDevice->PciIo.Pci.Read (
>
> - &PciDevice->PciIo,
>
> - EfiPciIoWidthUint16,
>
> - Offset,
>
> - 1,
>
> - &PcieDev.Uint16
>
> - );
>
> - ASSERT (Status == EFI_SUCCESS);
>
> -
>
> - if (PciDevice->SetupAtomicOp.Override) {
>
> - //
>
> - // override AtomicOp requester device control bit of the device based on the
>
> - // platform request
>
> - //
>
> - if (IS_PCI_BRIDGE (&PciDevice->Pci)) {
>
> - //
>
> - // for a bridge device as AtomicOp Requester function; only platform override
>
> - // request is used to set the device control register
>
> - //
>
> - if (PcieDev.Bits.AtomicOpRequester != PciDevice->SetupAtomicOp.Enable_AtomicOpRequester) {
>
> - PcieDev.Bits.AtomicOpRequester = PciDevice->SetupAtomicOp.Enable_AtomicOpRequester;
>
> - }
>
> - //
>
> - // if platform also request its AtomicOp Egress blocking to be enabled; set
>
> - // only if its device capability's AtomicOpRouting bit is 1.
>
> - // applicable to only the bridge devices
>
> - //
>
> - if (PciDevice->SetupAtomicOp.Enable_AtomicOpEgressBlocking) {
>
> - if (PciDevice->PciExpressCapabilityStructure.DeviceCapability2.Bits.AtomicOpRouting) {
>
> - PcieDev.Bits.AtomicOpEgressBlocking = 1;
>
> - }
>
> - }
>
> - } else {
>
> - //
>
> - // in the case of non-bridge device
>
> - //
>
> - if (PciExFeatureConfiguration) {
>
> - //
>
> - // for a device as AtomicOp Requester function; its bridge devices should
>
> - // support the AtomicOp Routing capability to enable the device's as a
>
> - // requester function
>
> - //
>
> - if (PciExFeatureConfiguration->AtomicOpRoutingSupported) {
>
> - if (PcieDev.Bits.AtomicOpRequester != PciDevice->SetupAtomicOp.Enable_AtomicOpRequester) {
>
> - PcieDev.Bits.AtomicOpRequester = PciDevice->SetupAtomicOp.Enable_AtomicOpRequester;
>
> - }
>
> - }
>
> - } else {
>
> - //
>
> - // for the RCiEP device or the bridge device without any child, setup AtomicOp
>
> - // Requester as per platform's device policy
>
> - //
>
> - if (PcieDev.Bits.AtomicOpRequester != PciDevice->SetupAtomicOp.Enable_AtomicOpRequester) {
>
> - PcieDev.Bits.AtomicOpRequester = PciDevice->SetupAtomicOp.Enable_AtomicOpRequester;
>
> - }
>
> - }
>
> - //
>
> - // the enabling of AtomicOp Egress Blocking is not applicable to a non-bridge
>
> - // device
>
> - //
>
> - }
>
> - DEBUG ((
>
> - DEBUG_INFO,
>
> - "AtomicOp=%d,",
>
> - PcieDev.Bits.AtomicOpRequester
>
> - ));
>
> -
>
> - //
>
> - // Raise TPL to high level to disable timer interrupt while the write operation completes
>
> - //
>
> - OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
>
> -
>
> - Status = PciDevice->PciIo.Pci.Write (
>
> - &PciDevice->PciIo,
>
> - EfiPciIoWidthUint16,
>
> - Offset,
>
> - 1,
>
> - &PcieDev.Uint16
>
> - );
>
> - //
>
> - // Restore TPL to its original level
>
> - //
>
> - gBS->RestoreTPL (OldTpl);
>
> -
>
> - if (!EFI_ERROR(Status)) {
>
> - PciDevice->PciExpressCapabilityStructure.DeviceControl2.Uint16 = PcieDev.Uint16;
>
> - } else {
>
> - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber, PciDevice->FunctionNumber, Offset);
>
> - }
>
> - } else {
>
> - DEBUG (( DEBUG_INFO, "No AtomicOp,"));
>
> - }
>
> -
>
> - return Status;
>
> -}
>
> -
>
> -/**
>
> - The main routine which process the PCI feature LTR enable/disable as per the
>
> - device-specific platform policy, as well as in complaince with the PCI Express
>
> - Base specification Revision 5.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE.
>
> - @param PciExpressConfigurationTable pointer to PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE
>
> -
>
> - @retval EFI_SUCCESS setup of PCI feature LTR is successful.
>
> -**/
>
> -EFI_STATUS
>
> -SetupLtr (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfigurationTable
>
> - )
>
> -{
>
> - PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCap2;
>
> - //
>
> - // as per the PCI-Express Base Specification, in order to enable LTR mechanism
>
> - // in the upstream ports, all the upstream ports and its downstream ports has
>
> - // to support the LTR mechanism reported in its Device Capability 2 register
>
> - //
>
> - DeviceCap2.Uint32 = PciDevice->PciExpressCapabilityStructure.DeviceCapability2.Uint32;
>
> -
>
> - if (PciExpressConfigurationTable) {
>
> - //
>
> - // in this phase establish 2 requirements:
>
> - // (1) all the PCI devices in the hierarchy supports the LTR mechanism
>
> - // (2) check and record any device-specific platform policy that wants to
>
> - // enable the LTR mechanism
>
> - //
>
> - if (!PciDevice->PciExpressCapabilityStructure.DeviceCapability2.Bits.LtrMechanism) {
>
> -
>
> - //
>
> - // it starts with the assumption that all the PCI devices support LTR mechanism
>
> - // and negates the flag if any PCI device Device Capability 2 register advertizes
>
> - // as not supported
>
> - //
>
> - PciExpressConfigurationTable->LtrSupported = FALSE;
>
> - }
>
> -
>
> - if (PciDevice->SetupLtr == TRUE) {
>
> - //
>
> - // it starts with the assumption that device-specific platform policy would
>
> - // be set to LTR disable, and negates the flag if any PCI device platform
>
> - // policy wants to override to enable the LTR mechanism
>
> - //
>
> - PciExpressConfigurationTable->LtrEnable = TRUE;
>
> - }
>
> - } else {
>
> - //
>
> - // in case of RCiEP device or the bridge device with out any child device,
>
> - // overrule the device policy if the device in not capable
>
> - //
>
> - if (!PciDevice->PciExpressCapabilityStructure.DeviceCapability2.Bits.LtrMechanism
>
> - && PciDevice->SetupLtr == TRUE) {
>
> - PciDevice->SetupLtr = FALSE;
>
> - }
>
> - //
>
> - // for any bridge device which is Hot-Plug capable, it is expected that platform
>
> - // will not enforce the enabling of LTR mechanism only for the bridge device
>
> - //
>
> - }
>
> -
>
> - DEBUG (( DEBUG_INFO, "LTR En: %d (LTR Cap: %d),",
>
> - PciDevice->SetupLtr ? 1 : 0,
>
> - PciDevice->PciExpressCapabilityStructure.DeviceCapability2.Bits.LtrMechanism
>
> - ));
>
> - return EFI_SUCCESS;
>
> -}
>
> -
>
> -EFI_STATUS
>
> -ReSetupLtr (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfigurationTable
>
> - )
>
> -{
>
> - //
>
> - // not applicable to RCiEP device...
>
> - // for the bridge device without any child device, the policy is already overruled
>
> - // based on capability in the above routine
>
> - //
>
> - if (PciExpressConfigurationTable) {
>
> - //
>
> - // in this phase align the device policy to enable LTR policy of any PCI device
>
> - // in the tree if all the devices are capable to support the LTR mechanism
>
> - //
>
> - if (PciExpressConfigurationTable->LtrSupported == TRUE
>
> - && PciExpressConfigurationTable->LtrEnable == TRUE
>
> - ) {
>
> - PciDevice->SetupLtr = TRUE;
>
> - } else {
>
> - PciDevice->SetupLtr = FALSE;
>
> - }
>
> - }
>
> -
>
> - DEBUG (( DEBUG_INFO, "LTR En: %d (LTR Cap: %d),",
>
> - PciDevice->SetupLtr ? 1 : 0,
>
> - PciDevice->PciExpressCapabilityStructure.DeviceCapability2.Bits.LtrMechanism
>
> - ));
>
> - return EFI_SUCCESS;
>
> -}
>
> -
>
> -/**
>
> - Program the PCI Device Control 2 register LTR mechanism field; if
>
> - the hardware value is different than the intended value.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE instance.
>
> -
>
> - @retval EFI_SUCCESS The data was read from or written to the PCI device.
>
> - @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
>
> - valid for the PCI configuration header of the PCI controller.
>
> - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
>
> -
>
> -**/
>
> -EFI_STATUS
>
> -ProgramLtr (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN VOID *PciExFeatureConfiguration
>
> - )
>
> -{
>
> - PCI_REG_PCIE_DEVICE_CONTROL2 PcieDev;
>
> - UINT32 Offset;
>
> - EFI_STATUS Status;
>
> - EFI_TPL OldTpl;
>
> -
>
> - PcieDev.Uint16 = 0;
>
> - Offset = PciDevice->PciExpressCapabilityOffset +
>
> - OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl2);
>
> - Status = PciDevice->PciIo.Pci.Read (
>
> - &PciDevice->PciIo,
>
> - EfiPciIoWidthUint16,
>
> - Offset,
>
> - 1,
>
> - &PcieDev.Uint16
>
> - );
>
> - ASSERT (Status == EFI_SUCCESS);
>
> -
>
> - if (PciDevice->SetupLtr != (BOOLEAN) PcieDev.Bits.LtrMechanism) {
>
> - PcieDev.Bits.LtrMechanism = PciDevice->SetupLtr ? 1 : 0;
>
> - DEBUG (( DEBUG_INFO, "LTR=%d,", PcieDev.Bits.LtrMechanism));
>
> -
>
> - //
>
> - // Raise TPL to high level to disable timer interrupt while the write operation completes
>
> - //
>
> - OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
>
> -
>
> - Status = PciDevice->PciIo.Pci.Write (
>
> - &PciDevice->PciIo,
>
> - EfiPciIoWidthUint16,
>
> - Offset,
>
> - 1,
>
> - &PcieDev.Uint16
>
> - );
>
> - //
>
> - // Restore TPL to its original level
>
> - //
>
> - gBS->RestoreTPL (OldTpl);
>
> -
>
> - if (!EFI_ERROR(Status)) {
>
> - PciDevice->PciExpressCapabilityStructure.DeviceControl2.Uint16 = PcieDev.Uint16;
>
> - } else {
>
> - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber, PciDevice->FunctionNumber, Offset);
>
> - }
>
> - } else {
>
> - DEBUG (( DEBUG_INFO, "no LTR,"));
>
> - }
>
> -
>
> - return Status;
>
> -}
>
> -
>
> -/**
>
> - The main routine to setup the PCI Express feature Extended Tag as per the
>
> - device-specific platform policy, as well as in complaince with the PCI Express
>
> - Base specification Revision 5.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE.
>
> - @param PciExpressConfigurationTable pointer to PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE
>
> -
>
> - @retval EFI_SUCCESS setup of PCI feature LTR is successful.
>
> -**/
>
> -EFI_STATUS
>
> -SetupExtTag (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfigurationTable
>
> - )
>
> -{
>
> - PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCap2;
>
> - PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCap;
>
> - EFI_PCI_EXPRESS_EXTENDED_TAG PciExpressExtendedTag;
>
> -
>
> - DeviceCap.Uint32 = PciDevice->PciExpressCapabilityStructure.DeviceCapability.Uint32;
>
> - DeviceCap2.Uint32 = PciDevice->PciExpressCapabilityStructure.DeviceCapability2.Uint32;
>
> - //
>
> - // The PCI Express feature Extended Tag has to be maintained common from a
>
> - // root bridge device to all its child devices.
>
> - // The Device Capability 2 register is used to determine the 10b Extended Tag
>
> - // capability of a device. The device capability register is used to determine
>
> - // 5b/8b Extended Tag capability of a device
>
> - //
>
> - if (DeviceCap2.Bits.TenBitTagCompleterSupported & DeviceCap2.Bits.TenBitTagRequesterSupported) {
>
> - //
>
> - // device supports the 10b Extended Tag capability
>
> - //
>
> - PciExpressExtendedTag = EFI_PCI_EXPRESS_EXTENDED_TAG_10BIT;
>
> - } else {
>
> - if (DeviceCap.Bits.ExtendedTagField) {
>
> - PciExpressExtendedTag = EFI_PCI_EXPRESS_EXTENDED_TAG_8BIT;
>
> - } else {
>
> - PciExpressExtendedTag = EFI_PCI_EXPRESS_EXTENDED_TAG_5BIT;
>
> - }
>
> - }
>
> - if (PciDevice->SetupExtTag == EFI_PCI_EXPRESS_EXTENDED_TAG_AUTO) {
>
> - PciDevice->SetupExtTag = PciExpressExtendedTag;
>
> - }
>
> - //
>
> - // in case of PCI Bridge and its child devices
>
> - //
>
> - if (PciExpressConfigurationTable) {
>
> - //
>
> - // align the Extended Tag value as per the device supported value
>
> - //
>
> - PciExpressConfigurationTable->ExtendedTag = MIN (
>
> - PciExpressExtendedTag,
>
> - PciExpressConfigurationTable->ExtendedTag
>
> - );
>
> - //
>
> - // check for any invalid platform policy request for the device; if true than
>
> - // align with the device capability value. Else align as per platform request
>
> - //
>
> - if (PciDevice->SetupExtTag > PciExpressConfigurationTable->ExtendedTag) {
>
> - //
>
> - // setup the device Extended Tag to common value supported by all the devices
>
> - //
>
> - PciDevice->SetupExtTag = PciExpressConfigurationTable->ExtendedTag;
>
> - }
>
> - //
>
> - // if the platform policy is to downgrade the device's Extended Tag value than
>
> - // all the other devices in the PCI tree including the root bridge will be align
>
> - // with this device override value
>
> - //
>
> - if (PciDevice->SetupExtTag < PciExpressConfigurationTable->ExtendedTag) {
>
> - PciExpressConfigurationTable->ExtendedTag = PciDevice->SetupExtTag;
>
> - }
>
> - } else {
>
> - //
>
> - // in case of RCiEP devices or the bridge device without any child, overrule
>
> - // the Extended Tag device policy if it does not match with its capability
>
> - //
>
> - PciDevice->SetupExtTag = MIN (
>
> - PciDevice->SetupExtTag,
>
> - PciExpressExtendedTag
>
> - );
>
> - }
>
> -
>
> - DEBUG ((
>
> - DEBUG_INFO,
>
> - "ExtTag: %d [cap:%d],",
>
> - PciDevice->SetupExtTag,
>
> - PciExpressExtendedTag
>
> - ));
>
> - return EFI_SUCCESS;
>
> -}
>
> -
>
> -/**
>
> - Additional routine to setup the PCI Express feature Extended Tag in complaince
>
> - with the PCI Express Base specification Revision, a common value for all the
>
> - devices in the PCI hierarchy.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE.
>
> - @param PciExpressConfigurationTable pointer to PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE
>
> -
>
> - @retval EFI_SUCCESS setup of PCI feature LTR is successful.
>
> -**/
>
> -EFI_STATUS
>
> -AlignExtTag (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfigurationTable
>
> - )
>
> -{
>
> - if (PciExpressConfigurationTable) {
>
> - //
>
> - // align the Extended Tag value to a common value among all the devices
>
> - //
>
> - PciDevice->SetupExtTag = MIN (
>
> - PciDevice->SetupExtTag,
>
> - PciExpressConfigurationTable->ExtendedTag
>
> - );
>
> - }
>
> -
>
> - DEBUG ((
>
> - DEBUG_INFO,
>
> - "ExtTag: %d,",
>
> - PciDevice->SetupExtTag
>
> - ));
>
> - return EFI_SUCCESS;
>
> -}
>
> -
>
> -/**
>
> - Program the PCI Device Control 2 register for 10b Extended Tag value, or the
>
> - Device Control register for 5b/8b Extended Tag value.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE instance.
>
> -
>
> - @retval EFI_SUCCESS The data was read from or written to the PCI device.
>
> - @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
>
> - valid for the PCI configuration header of the PCI controller.
>
> - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
>
> -
>
> -**/
>
> -EFI_STATUS
>
> -ProgramExtTag (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN VOID *PciExFeatureConfiguration
>
> - )
>
> -{
>
> - PCI_REG_PCIE_DEVICE_CONTROL DevCtl;
>
> - PCI_REG_PCIE_DEVICE_CONTROL2 DevCtl2;
>
> - UINT32 Offset;
>
> - UINT32 Offset2;
>
> - BOOLEAN OverrideDevCtl;
>
> - BOOLEAN OverrideDevCtl2;
>
> - EFI_STATUS Status;
>
> - EFI_TPL OldTpl;
>
> -
>
> - //
>
> - // read the Device Control register for the Extended Tag Field Enable
>
> - //
>
> - DevCtl.Uint16 = 0;
>
> - Offset = PciDevice->PciExpressCapabilityOffset +
>
> - OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl);
>
> - Status = PciDevice->PciIo.Pci.Read (
>
> - &PciDevice->PciIo,
>
> - EfiPciIoWidthUint16,
>
> - Offset,
>
> - 1,
>
> - &DevCtl.Uint16
>
> - );
>
> - ASSERT (Status == EFI_SUCCESS);
>
> -
>
> - OverrideDevCtl = FALSE;
>
> - //
>
> - // read the Device COntrol 2 register for the 10-Bit Tag Requester Enable
>
> - //
>
> - DevCtl2.Uint16 = 0;
>
> - Offset2 = PciDevice->PciExpressCapabilityOffset +
>
> - OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl2);
>
> - Status = PciDevice->PciIo.Pci.Read (
>
> - &PciDevice->PciIo,
>
> - EfiPciIoWidthUint16,
>
> - Offset2,
>
> - 1,
>
> - &DevCtl2.Uint16
>
> - );
>
> - ASSERT (Status == EFI_SUCCESS);
>
> -
>
> - OverrideDevCtl2 = FALSE;
>
> -
>
> - if (PciDevice->SetupExtTag == EFI_PCI_EXPRESS_EXTENDED_TAG_5BIT) {
>
> - if (DevCtl.Bits.ExtendedTagField) {
>
> - DevCtl.Bits.ExtendedTagField = 0;
>
> - OverrideDevCtl = TRUE;
>
> - }
>
> -
>
> - if (DevCtl2.Bits.TenBitTagRequesterEnable) {
>
> - DevCtl2.Bits.TenBitTagRequesterEnable = 0;
>
> - OverrideDevCtl2 = TRUE;
>
> - }
>
> - }
>
> - if (PciDevice->SetupExtTag == EFI_PCI_EXPRESS_EXTENDED_TAG_8BIT) {
>
> - if (!DevCtl.Bits.ExtendedTagField) {
>
> - DevCtl.Bits.ExtendedTagField = 1;
>
> - OverrideDevCtl = TRUE;
>
> - }
>
> - if (DevCtl2.Bits.TenBitTagRequesterEnable) {
>
> - DevCtl2.Bits.TenBitTagRequesterEnable = 0;
>
> - OverrideDevCtl2 = TRUE;
>
> - }
>
> - }
>
> - if (PciDevice->SetupExtTag == EFI_PCI_EXPRESS_EXTENDED_TAG_10BIT) {
>
> - if (!DevCtl2.Bits.TenBitTagRequesterEnable) {
>
> - DevCtl2.Bits.TenBitTagRequesterEnable = 1;
>
> - OverrideDevCtl2 = TRUE;
>
> - }
>
> - }
>
> -
>
> - if (OverrideDevCtl) {
>
> -
>
> - DEBUG (( DEBUG_INFO, "ExtTag=%d,", DevCtl.Bits.ExtendedTagField));
>
> -
>
> - //
>
> - // Raise TPL to high level to disable timer interrupt while the write operation completes
>
> - //
>
> - OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
>
> -
>
> - Status = PciDevice->PciIo.Pci.Write (
>
> - &PciDevice->PciIo,
>
> - EfiPciIoWidthUint16,
>
> - Offset,
>
> - 1,
>
> - &DevCtl.Uint16
>
> - );
>
> - //
>
> - // Restore TPL to its original level
>
> - //
>
> - gBS->RestoreTPL (OldTpl);
>
> -
>
> - if (!EFI_ERROR(Status)) {
>
> - PciDevice->PciExpressCapabilityStructure.DeviceControl.Uint16 = DevCtl.Uint16;
>
> - } else {
>
> - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber, PciDevice->FunctionNumber, Offset);
>
> - }
>
> - } else {
>
> - DEBUG (( DEBUG_INFO, "no ExtTag (%d),", DevCtl.Bits.ExtendedTagField));
>
> - }
>
> -
>
> - if (OverrideDevCtl2) {
>
> -
>
> - DEBUG (( DEBUG_INFO, "10bExtTag=%d,", DevCtl2.Bits.TenBitTagRequesterEnable));
>
> -
>
> - //
>
> - // Raise TPL to high level to disable timer interrupt while the write operation completes
>
> - //
>
> - OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
>
> -
>
> - Status = PciDevice->PciIo.Pci.Write (
>
> - &PciDevice->PciIo,
>
> - EfiPciIoWidthUint16,
>
> - Offset2,
>
> - 1,
>
> - &DevCtl2.Uint16
>
> - );
>
> - //
>
> - // Restore TPL to its original level
>
> - //
>
> - gBS->RestoreTPL (OldTpl);
>
> -
>
> - if (!EFI_ERROR(Status)) {
>
> - PciDevice->PciExpressCapabilityStructure.DeviceControl2.Uint16 = DevCtl2.Uint16;
>
> - } else {
>
> - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber, PciDevice->FunctionNumber, Offset2);
>
> - }
>
> - } else {
>
> - DEBUG (( DEBUG_INFO, "no 10bExtTag (%d),", DevCtl2.Bits.TenBitTagRequesterEnable));
>
> - }
>
> -
>
> - return Status;
>
> -}
>
> -
>
> -/**
>
> - Set the ASPM device policy as per the device's link capability.
>
> -**/
>
> -UINT8
>
> -SetAspmPolicy (
>
> - IN UINT8 PciExpressLinkCapAspm
>
> - )
>
> -{
>
> - switch (PciExpressLinkCapAspm) {
>
> - case 0:
>
> - //
>
> - // cannot support ASPM state, disable
>
> - //
>
> - return EFI_PCI_EXPRESS_ASPM_DISABLE;
>
> - case 1:
>
> - //
>
> - // supports only ASPM L0s state
>
> - //
>
> - return EFI_PCI_EXPRESS_ASPM_L0s_SUPPORT;
>
> - case 2:
>
> - //
>
> - // supports only ASPM L1 state
>
> - //
>
> - return EFI_PCI_EXPRESS_ASPM_L1_SUPPORT;
>
> - case 3:
>
> - //
>
> - // supports both L0s and L1 ASPM states
>
> - //
>
> - return EFI_PCI_EXPRESS_ASPM_L0S_L1_SUPPORT;
>
> - }
>
> - return EFI_PCI_EXPRESS_ASPM_DISABLE;
>
> -}
>
> -
>
> -/**
>
> - The main routine to setup the PCI Express feature ASPM as per the
>
> - device-specific platform policy, as well as in complaince with the PCI Express
>
> - Base specification Revision 5.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE.
>
> - @param PciExpressConfigurationTable pointer to PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE
>
> -
>
> - @retval EFI_SUCCESS setup of PCI feature LTR is successful.
>
> -**/
>
> -EFI_STATUS
>
> -SetupAspm (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfigurationTable
>
> - )
>
> -{
>
> - PCI_REG_PCIE_LINK_CAPABILITY PciExLinkCap;
>
> - PCI_REG_PCIE_DEVICE_CAPABILITY PciExpressDeviceCapability;
>
> - BOOLEAN AlignAspmPolicy;
>
> -
>
> - PciExLinkCap.Uint32 = PciDevice->PciExpressCapabilityStructure.LinkCapability.Uint32;
>
> - PciExpressDeviceCapability.Uint32 = PciDevice->PciExpressCapabilityStructure.DeviceCapability.Uint32;
>
> - //
>
> - // ASPM support is only applicable to root bridge and its child devices. Not
>
> - // applicable to empty bridge devices or RCiEP devices
>
> - //
>
> - if (PciExpressConfigurationTable) {
>
> - PciExpressConfigurationTable->L0sExitLatency = MAX (
>
> - PciExpressConfigurationTable->L0sExitLatency,
>
> - (UINT8)PciExLinkCap.Bits.L0sExitLatency
>
> - );
>
> - PciExpressConfigurationTable->L1ExitLatency = MAX (
>
> - PciExpressConfigurationTable->L1ExitLatency,
>
> - (UINT8)PciExLinkCap.Bits.L1ExitLatency
>
> - );
>
> - if (PciDevice->SetupAspm == EFI_PCI_EXPRESS_ASPM_AUTO) {
>
> - //
>
> - // set the ASPM support as per device's link capability
>
> - //
>
> - PciDevice->SetupAspm = SetAspmPolicy ((UINT8)PciExLinkCap.Bits.Aspm);
>
> - } else {
>
> - //
>
> - // Check the ASPM device policy is applicable to the link capability.
>
> - // In case of invalid device policy, there are 2 options:
>
> - // (1) ASPM disable -> platform request rightly denied, and no ASPM
>
> - // (2) set as per the device capability -> platform request rightly denied,
>
> - // but still set applicable power management
>
> - // this implementation shall take option 2 to overule invalid platform request
>
> - // and go with applicable policy as per device capability
>
> - //
>
> - switch (SetAspmPolicy ((UINT8)PciExLinkCap.Bits.Aspm)) {
>
> - case EFI_PCI_EXPRESS_ASPM_DISABLE:
>
> - PciDevice->SetupAspm = EFI_PCI_EXPRESS_ASPM_DISABLE;
>
> - break;
>
> - case EFI_PCI_EXPRESS_ASPM_L1_SUPPORT:
>
> - if (PciDevice->SetupAspm == EFI_PCI_EXPRESS_ASPM_L0s_SUPPORT) {
>
> - //
>
> - // not applicable, set as per device's link capability
>
> - //
>
> - PciDevice->SetupAspm = EFI_PCI_EXPRESS_ASPM_L1_SUPPORT;
>
> - }
>
> - break;
>
> - case EFI_PCI_EXPRESS_ASPM_L0s_SUPPORT:
>
> - if (PciDevice->SetupAspm == EFI_PCI_EXPRESS_ASPM_L1_SUPPORT) {
>
> - //
>
> - // not applicable, set as per device's link capability
>
> - //
>
> - PciDevice->SetupAspm = EFI_PCI_EXPRESS_ASPM_L0s_SUPPORT;
>
> - }
>
> - break;
>
> - }
>
> - }
>
> - //
>
> - // set the ASPM policy to minimum state among all the devices links
>
> - //
>
> - PciExpressConfigurationTable->AspmSupport = MIN (
>
> - PciExpressConfigurationTable->AspmSupport,
>
> - PciDevice->SetupAspm
>
> - );
>
> - //
>
> - // check the common ASPM value applicable as per this device capability, if
>
> - // not applicable disable the ASPM for all the devices
>
> - //
>
> - if (
>
> - (PciExpressConfigurationTable->AspmSupport == EFI_PCI_EXPRESS_ASPM_L0s_SUPPORT
>
> - && SetAspmPolicy ((UINT8)PciExLinkCap.Bits.Aspm) == EFI_PCI_EXPRESS_ASPM_L1_SUPPORT)
>
> - ||
>
> - (PciExpressConfigurationTable->AspmSupport == EFI_PCI_EXPRESS_ASPM_L1_SUPPORT
>
> - && SetAspmPolicy ((UINT8)PciExLinkCap.Bits.Aspm) == EFI_PCI_EXPRESS_ASPM_L0s_SUPPORT)
>
> - ) {
>
> - //
>
> - // disable the ASPM
>
> - //
>
> - PciExpressConfigurationTable->AspmSupport = EFI_PCI_EXPRESS_ASPM_DISABLE;
>
> - PciDevice->SetupAspm = PciExpressConfigurationTable->AspmSupport;
>
> - }
>
> -
>
> - if (PciExpressConfigurationTable->AspmSupport != EFI_PCI_EXPRESS_ASPM_DISABLE) {
>
> - //
>
> - // in case of ASPM policy is not to disable the ASPM support, check other
>
> - // condition of EP device L0s/L1 acceptance latency with the L0s/L1 exit
>
> - // latencies comprising from this endpoint all the way up to root complex
>
> - // root port, to determine whether the ASPM L0s/L1 entry can be used with
>
> - // no loss of performance
>
> - //
>
> - if (!IS_PCI_BRIDGE (&PciDevice->Pci)) {
>
> -
>
> - switch (PciExpressConfigurationTable->AspmSupport) {
>
> - case EFI_PCI_EXPRESS_ASPM_L0S_L1_SUPPORT:
>
> - if (
>
> - PciExpressDeviceCapability.Bits.EndpointL0sAcceptableLatency >= PciExpressConfigurationTable->L0sExitLatency
>
> - && PciExpressDeviceCapability.Bits.EndpointL1AcceptableLatency >= PciExpressConfigurationTable-
> >L1ExitLatency
>
> - ) {
>
> - //
>
> - // both the L0s & L1 acceptance of this endpoint device is greater
>
> - // than or equal to all of the comprised L0s & L1 exit latencies
>
> - // thus good to set the ASPM to L0s & L1 state
>
> - //
>
> - AlignAspmPolicy = TRUE;
>
> - } else {
>
> - //
>
> - // in case the EP device L0s and L1 Acceptance latency does not match
>
> - // with the comprised L0s & L1 exit latencies than disable the ASPM
>
> - // state
>
> - //
>
> - AlignAspmPolicy = FALSE;
>
> - }
>
> - break;
>
> -
>
> - case EFI_PCI_EXPRESS_ASPM_L1_SUPPORT:
>
> - if (
>
> - PciExpressDeviceCapability.Bits.EndpointL1AcceptableLatency >= PciExpressConfigurationTable->L1ExitLatency
>
> - ) {
>
> - //
>
> - // the endpoint device L1 acceptance latency meets the all the
>
> - // comprised L1 exit latencies of all the devices from the bridge
>
> - // hence ASPM L1 is applicable state for the PCI tree
>
> - //
>
> - AlignAspmPolicy = TRUE;
>
> - } else {
>
> - //
>
> - // in case the EP device L1 Acceptance latency does not match
>
> - // with the comprised L1 exit latencies than disable the ASPM
>
> - // state
>
> - //
>
> - AlignAspmPolicy = FALSE;
>
> - }
>
> - break;
>
> -
>
> - case EFI_PCI_EXPRESS_ASPM_L0s_SUPPORT:
>
> - if (
>
> - PciExpressDeviceCapability.Bits.EndpointL0sAcceptableLatency >= PciExpressConfigurationTable->L0sExitLatency
>
> - ) {
>
> - //
>
> - // the endpoint device L0s acceptance latency meets the all the
>
> - // comprised L0s exit latencies of all the devices from the bridge
>
> - // hence ASPM L0s is applicable state for the PCI tree
>
> - //
>
> - AlignAspmPolicy = TRUE;
>
> - } else {
>
> - //
>
> - // in case the EP device L0s Acceptance latency does not match
>
> - // with the comprised L0s exit latencies than disable the ASPM
>
> - // state
>
> - //
>
> - AlignAspmPolicy = FALSE;
>
> - }
>
> - break;
>
> - }
>
> - } else {
>
> - //
>
> - // align the bridge with the global common ASPM value
>
> - //
>
> - AlignAspmPolicy = TRUE;
>
> - }
>
> - } else {
>
> - //
>
> - // ASPM is disabled for all the devices
>
> - //
>
> - AlignAspmPolicy = FALSE;
>
> - }
>
> -
>
> - if (AlignAspmPolicy) {
>
> - //
>
> - // reset the device's ASPM policy to common minimum value
>
> - //
>
> - if (PciDevice->SetupAspm != PciExpressConfigurationTable->AspmSupport) {
>
> - PciDevice->SetupAspm = PciExpressConfigurationTable->AspmSupport;
>
> - }
>
> - } else {
>
> - //
>
> - // disable the ASPM
>
> - //
>
> - PciExpressConfigurationTable->AspmSupport = EFI_PCI_EXPRESS_ASPM_DISABLE;
>
> - PciDevice->SetupAspm = PciExpressConfigurationTable->AspmSupport;
>
> - }
>
> - DEBUG ((
>
> - DEBUG_INFO,
>
> - "Aspm: %d [cap:%d],",
>
> - PciDevice->SetupAspm,
>
> - (PciExLinkCap.Bits.Aspm + 1)
>
> - ));
>
> - }
>
> -
>
> - return EFI_SUCCESS;
>
> -}
>
> -
>
> -/**
>
> - Setup of PCI Express feature ASPM in the PciExpressFeatureEntendedSetupPhase
>
> -**/
>
> -EFI_STATUS
>
> -AlignAspm (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfigurationTable
>
> - )
>
> -{
>
> - //
>
> - // ASPM support is only applicable to root bridge and its child devices. Not
>
> - // applicable to empty bridge devices or RCiEP devices
>
> - //
>
> - if (PciExpressConfigurationTable) {
>
> - //
>
> - // reset the device's ASPM policy to common minimum ASPM value
>
> - //
>
> - if (PciDevice->SetupAspm != PciExpressConfigurationTable->AspmSupport) {
>
> - PciDevice->SetupAspm = PciExpressConfigurationTable->AspmSupport;
>
> - }
>
> - DEBUG ((
>
> - DEBUG_INFO,
>
> - "Aspm: %d,",
>
> - PciDevice->SetupAspm
>
> - ));
>
> - }
>
> -
>
> - return EFI_SUCCESS;
>
> -}
>
> -
>
> -
>
> -/**
>
> - Get the ASPM value from the ASPM device policy.
>
> -**/
>
> -UINT8
>
> -GetAspmValue (
>
> - IN UINT8 AspmPolicy
>
> - )
>
> -{
>
> - switch (AspmPolicy) {
>
> - case EFI_PCI_EXPRESS_ASPM_DISABLE:
>
> - //
>
> - // ASPM disable
>
> - //
>
> - return 0;
>
> - case EFI_PCI_EXPRESS_ASPM_L0s_SUPPORT:
>
> - //
>
> - // ASPM L0s state
>
> - //
>
> - return 1;
>
> - case EFI_PCI_EXPRESS_ASPM_L1_SUPPORT:
>
> - //
>
> - // ASPM L1 state
>
> - //
>
> - return 2;
>
> - case EFI_PCI_EXPRESS_ASPM_L0S_L1_SUPPORT:
>
> - //
>
> - // L0s and L1 ASPM states
>
> - //
>
> - return 3;
>
> - }
>
> - return 0;
>
> -}
>
> -
>
> -/**
>
> - Program the PCIe Link Control register ASPM Control field; if
>
> - the hardware value is different than the intended value.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE instance.
>
> -
>
> - @retval EFI_SUCCESS The data was read from or written to the PCI device.
>
> - @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
>
> - valid for the PCI configuration header of the PCI controller.
>
> - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
>
> -
>
> -**/
>
> -EFI_STATUS
>
> -ProgramAspm (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN VOID *PciExFeatureConfiguration
>
> - )
>
> -{
>
> - PCI_REG_PCIE_LINK_CONTROL LinkCtl;
>
> - UINT32 Offset;
>
> - EFI_STATUS Status;
>
> - EFI_TPL OldTpl;
>
> - UINT8 AspmValue;
>
> -
>
> - //
>
> - // ASPM support is only applicable to root bridge and its child devices. Not
>
> - // applicable to empty bridge devices or RCiEP devices
>
> - //
>
> - if (!PciExFeatureConfiguration) {
>
> - return EFI_SUCCESS;
>
> - }
>
> -
>
> - //
>
> - // read the link Control register for the ASPM Control
>
> - //
>
> - LinkCtl.Uint16 = 0;
>
> - Offset = PciDevice->PciExpressCapabilityOffset +
>
> - OFFSET_OF (PCI_CAPABILITY_PCIEXP, LinkControl);
>
> - Status = PciDevice->PciIo.Pci.Read (
>
> - &PciDevice->PciIo,
>
> - EfiPciIoWidthUint16,
>
> - Offset,
>
> - 1,
>
> - &LinkCtl.Uint16
>
> - );
>
> - ASSERT (Status == EFI_SUCCESS);
>
> -
>
> - AspmValue = GetAspmValue (PciDevice->SetupAspm);
>
> - if (AspmValue != LinkCtl.Bits.AspmControl) {
>
> - DEBUG ((
>
> - DEBUG_INFO,
>
> - "Aspm: %d,",
>
> - AspmValue
>
> - ));
>
> - //
>
> - // Raise TPL to high level to disable timer interrupt while the write operation completes
>
> - //
>
> - OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
>
> -
>
> - Status = PciDevice->PciIo.Pci.Write (
>
> - &PciDevice->PciIo,
>
> - EfiPciIoWidthUint16,
>
> - Offset,
>
> - 1,
>
> - &LinkCtl.Uint16
>
> - );
>
> - //
>
> - // Restore TPL to its original level
>
> - //
>
> - gBS->RestoreTPL (OldTpl);
>
> -
>
> - if (!EFI_ERROR (Status)) {
>
> - PciDevice->PciExpressCapabilityStructure.LinkControl.Uint16 = LinkCtl.Uint16;
>
> - } else {
>
> - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber, PciDevice->FunctionNumber, Offset);
>
> - return Status;
>
> - }
>
> - } else {
>
> - DEBUG ((
>
> - DEBUG_INFO,
>
> - "No Aspm (%d),",
>
> - AspmValue
>
> - ));
>
> - }
>
> - return EFI_SUCCESS;
>
> -}
>
> -
>
> -/**
>
> - The main routine to setup the PCI Express feature Common Clock configuration
>
> - as per the device-specific platform policy, as well as in complaince with the
>
> - PCI Express Base specification Revision 5.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE.
>
> - @param PciExpressConfigurationTable pointer to PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE
>
> -
>
> - @retval EFI_SUCCESS setup of PCI feature LTR is successful.
>
> -**/
>
> -EFI_STATUS
>
> -SetupCommonClkCfg (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfigurationTable
>
> - )
>
> -{
>
> - PCI_REG_PCIE_LINK_STATUS LinkSts;
>
> -
>
> - LinkSts.Uint16 = PciDevice->PciExpressCapabilityStructure.LinkStatus.Uint16;
>
> -
>
> - //
>
> - // Common Clock Configuration is only applicable to root bridge and its child
>
> - // devices. Not applicable to empty bridge devices or RCiEP devices
>
> - //
>
> - if (PciExpressConfigurationTable) {
>
> - if (PciDevice->SetupCcc == EFI_PCI_EXPRESS_CLK_CFG_AUTO) {
>
> - //
>
> - // as per the PCI Express Base Specification, the link status register
>
> - // slot clock configuration of the opposing side of link devices indicate
>
> - // the clock configuration properly; hence rely on this data to configure
>
> - // the link's clock configuration
>
> - //
>
> - if (LinkSts.Bits.SlotClockConfiguration) {
>
> - PciExpressConfigurationTable->CommonClockConfiguration = TRUE;
>
> - } else {
>
> - PciExpressConfigurationTable->CommonClockConfiguration = FALSE;
>
> - }
>
> - } else if (PciDevice->SetupCcc == EFI_PCI_EXPRESS_CLK_CFG_ASYNCH) {
>
> - //
>
> - // platform override to any device shall change for other device on the
>
> - // link, the clock configuration has to be maintained common across all
>
> - // the devices
>
> - //
>
> - PciExpressConfigurationTable->CommonClockConfiguration = FALSE;
>
> - } else {
>
> - PciExpressConfigurationTable->CommonClockConfiguration = TRUE;
>
> - }
>
> - }
>
> - return EFI_SUCCESS;
>
> -}
>
> -
>
> -/**
>
> - Program the PCIe Link Control register Coomon Clock Configuration field; if
>
> - the hardware value is different than the intended value.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE instance.
>
> -
>
> - @retval EFI_SUCCESS The data was read from or written to the PCI device.
>
> - @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
>
> - valid for the PCI configuration header of the PCI controller.
>
> - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
>
> -
>
> -**/
>
> -EFI_STATUS
>
> -ProgramCcc (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExFeatureConfiguration
>
> - )
>
> -{
>
> - PCI_REG_PCIE_LINK_CONTROL LinkCtl;
>
> - UINT32 Offset;
>
> - EFI_STATUS Status;
>
> - EFI_TPL OldTpl;
>
> -
>
> - //
>
> - // Common Clock Configuration is only applicable to root bridge and its child
>
> - // devices. Not applicable to empty bridge devices or RCiEP devices
>
> - //
>
> - if (!PciExFeatureConfiguration) {
>
> - return EFI_SUCCESS;
>
> - }
>
> -
>
> - //
>
> - // read the link Control register for the ASPM Control
>
> - //
>
> - LinkCtl.Uint16 = 0;
>
> - Offset = PciDevice->PciExpressCapabilityOffset +
>
> - OFFSET_OF (PCI_CAPABILITY_PCIEXP, LinkControl);
>
> - Status = PciDevice->PciIo.Pci.Read (
>
> - &PciDevice->PciIo,
>
> - EfiPciIoWidthUint16,
>
> - Offset,
>
> - 1,
>
> - &LinkCtl.Uint16
>
> - );
>
> - ASSERT (Status == EFI_SUCCESS);
>
> -
>
> - //
>
> - // in case Common Clock Configuration is required to be programmed in the
>
> - // downstream ports from the root bridge devices in the heirarchy
>
> - //
>
> - if (PciExFeatureConfiguration->CommonClockConfiguration == TRUE) {
>
> - if (LinkCtl.Bits.CommonClockConfiguration == 0) {
>
> - LinkCtl.Bits.CommonClockConfiguration = 1;
>
> - //
>
> - // current clock mode does not match hence retrain of the link at bridge device
>
> - // is required
>
> - //
>
> - PciExFeatureConfiguration->LinkReTrain = TRUE;
>
> - }
>
> - } else {
>
> - //
>
> - // in case the opposing devices of the PCI link have different reference clock
>
> - // set the link control register CCC field accordingly
>
> - //
>
> - if (LinkCtl.Bits.CommonClockConfiguration) {
>
> - LinkCtl.Bits.CommonClockConfiguration = 0;
>
> - //
>
> - // current clock mode does not match hence retrain of the link at bridge device
>
> - // is required
>
> - //
>
> - PciExFeatureConfiguration->LinkReTrain = TRUE;
>
> - }
>
> - }
>
> - //
>
> - // use the retrain flag as a sigm to also update the CCC of the link register
>
> - //
>
> - if (PciExFeatureConfiguration->LinkReTrain == TRUE) {
>
> - DEBUG ((
>
> - DEBUG_INFO,
>
> - "CCC: %d,",
>
> - LinkCtl.Bits.CommonClockConfiguration
>
> - ));
>
> - //
>
> - // Raise TPL to high level to disable timer interrupt while the write operation completes
>
> - //
>
> - OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
>
> -
>
> - Status = PciDevice->PciIo.Pci.Write (
>
> - &PciDevice->PciIo,
>
> - EfiPciIoWidthUint16,
>
> - Offset,
>
> - 1,
>
> - &LinkCtl.Uint16
>
> - );
>
> - //
>
> - // Restore TPL to its original level
>
> - //
>
> - gBS->RestoreTPL (OldTpl);
>
> -
>
> - if (!EFI_ERROR (Status)) {
>
> - PciDevice->PciExpressCapabilityStructure.LinkControl.Uint16 = LinkCtl.Uint16;
>
> - } else {
>
> - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber, PciDevice->FunctionNumber, Offset);
>
> - return Status;
>
> - }
>
> - } else {
>
> - PciDevice->PciExpressCapabilityStructure.LinkControl.Uint16 = LinkCtl.Uint16;
>
> - DEBUG ((
>
> - DEBUG_INFO,
>
> - "No CCC (%d),",
>
> - LinkCtl.Bits.CommonClockConfiguration
>
> - ));
>
> - }
>
> - return EFI_SUCCESS;
>
> -}
>
> -
>
> -/**
>
> - Second phase of programming for Common Clock COnfiguration, conditoonally done
>
> - only on the downstream ports (bridge devices only).
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE instance.
>
> -
>
> - @retval EFI_SUCCESS The data was read from or written to the PCI device.
>
> - @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
>
> - valid for the PCI configuration header of the PCI controller.
>
> - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
>
> -
>
> -**/
>
> -EFI_STATUS
>
> -EnforceCcc (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExFeatureConfiguration
>
> - )
>
> -{
>
> - PCI_REG_PCIE_LINK_CONTROL LinkCtl;
>
> - PCI_REG_PCIE_LINK_STATUS LinkSts;
>
> - PCI_REG_PCIE_CAPABILITY PciExCap;
>
> - UINT32 Offset;
>
> - EFI_STATUS Status;
>
> - EFI_TPL OldTpl;
>
> -
>
> - //
>
> - // Common Clock Configuration is only applicable to root bridge and its child
>
> - // devices. Not applicable to empty bridge devices or RCiEP devices
>
> - //
>
> - if (!PciExFeatureConfiguration) {
>
> - return EFI_SUCCESS;
>
> - }
>
> - PciExCap.Uint16 = PciDevice->PciExpressCapabilityStructure.Capability.Uint16;
>
> - LinkCtl.Uint16 = PciDevice->PciExpressCapabilityStructure.LinkControl.Uint16;
>
> -
>
> - //
>
> - // retrain the bridge device (downstream ports including the root port)
>
> - //
>
> - if (PciExFeatureConfiguration->LinkReTrain == TRUE) {
>
> - if (IS_PCI_BRIDGE (&PciDevice->Pci)) {
>
> - //
>
> - // retrain of the PCI link happens for CCC change only on the downstream
>
> - // ports
>
> - //
>
> - if (
>
> - PciExCap.Bits.DevicePortType == PCIE_DEVICE_PORT_TYPE_ROOT_PORT
>
> - || PciExCap.Bits.DevicePortType == PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT
>
> - ) {
>
> - LinkCtl.Bits.RetrainLink = 1;
>
> - Offset = PciDevice->PciExpressCapabilityOffset +
>
> - OFFSET_OF (PCI_CAPABILITY_PCIEXP, LinkControl);
>
> - //
>
> - // Raise TPL to high level to disable timer interrupt while the write operation completes
>
> - //
>
> - OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
>
> -
>
> - Status = PciDevice->PciIo.Pci.Write (
>
> - &PciDevice->PciIo,
>
> - EfiPciIoWidthUint16,
>
> - Offset,
>
> - 1,
>
> - &LinkCtl.Uint16
>
> - );
>
> - //
>
> - // Restore TPL to its original level
>
> - //
>
> - gBS->RestoreTPL (OldTpl);
>
> -
>
> - if (!EFI_ERROR (Status)) {
>
> - //
>
> - // poll the link status register for the link retrain to be complete
>
> - //
>
> - Offset = PciDevice->PciExpressCapabilityOffset +
>
> - OFFSET_OF (PCI_CAPABILITY_PCIEXP, LinkStatus);
>
> - do {
>
> - Status = PciDevice->PciIo.Pci.Read (
>
> - &PciDevice->PciIo,
>
> - EfiPciIoWidthUint16,
>
> - Offset,
>
> - 1,
>
> - &LinkSts.Uint16
>
> - );
>
> - ASSERT (Status == EFI_SUCCESS);
>
> - } while (LinkSts.Bits.LinkTraining);
>
> - } else {
>
> - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber, PciDevice->FunctionNumber, Offset);
>
> - return Status;
>
> - }
>
> - }
>
> - //
>
> - // ignore the upstream bridge devices
>
> - //
>
> - }
>
> - //
>
> - // not applicable to endpoint devices
>
> - //
>
> - }
>
> - return EFI_SUCCESS;
>
> -}
>
> -
>
> diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h
> b/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h
> deleted file mode 100644
> index 33df337..0000000
> --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h
> +++ /dev/null
> @@ -1,399 +0,0 @@
> -/** @file
>
> - PCI standard feature support functions implementation for PCI Bus module..
>
> -
>
> -Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
>
> -
>
> -**/
>
> -
>
> -#ifndef _EFI_PCI_EXPRESS_FEATURES_H_
>
> -#define _EFI_PCI_EXPRESS_FEATURES_H_
>
> -
>
> -//
>
> -// PCIe L0s Exit Latencies declarations
>
> -//
>
> -#define PCIE_LINK_CAPABILITY_L0S_EXIT_LATENCY_64NS 0 // less than 64ns
>
> -
>
> -//
>
> -// PCIe L1 Exit latencies declarations
>
> -//
>
> -#define PCIE_LINK_CAPABILITY_L1_EXIT_LATENCY_1US 0 // less than 1us
>
> -
>
> -/**
>
> - The main routine which process the PCI feature Max_Payload_Size as per the
>
> - device-specific platform policy, as well as in complaince with the PCI Base
>
> - specification Revision 4, that aligns the value for the entire PCI heirarchy
>
> - starting from its physical PCI Root port / Bridge device.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE.
>
> - @param PciFeaturesConfigurationTable pointer to PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE
>
> -
>
> - @retval EFI_SUCCESS processing of PCI feature Max_Payload_Size
>
> - is successful.
>
> -**/
>
> -EFI_STATUS
>
> -SetupMaxPayloadSize (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfigurationTable
>
> - );
>
> -
>
> -EFI_STATUS
>
> -CasMaxPayloadSize (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfigurationTable
>
> - );
>
> -
>
> -/**
>
> - Overrides the PCI Device Control register Max_Read_Req_Size register field; if
>
> - the hardware value is different than the intended value.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE instance.
>
> -
>
> - @retval EFI_SUCCESS The data was read from or written to the PCI controller.
>
> - @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
>
> - valid for the PCI configuration header of the PCI controller.
>
> - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
>
> -
>
> -**/
>
> -EFI_STATUS
>
> -ProgramMaxPayloadSize (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN VOID *PciExFeatureConfiguration
>
> - );
>
> -
>
> -
>
> -EFI_STATUS
>
> -ConditionalCasMaxReadReqSize (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfigurationTable
>
> - );
>
> -
>
> -/**
>
> - The main routine which process the PCI feature Max_Read_Req_Size as per the
>
> - device-specific platform policy, as well as in complaince with the PCI Base
>
> - specification Revision 4, that aligns the value for the entire PCI heirarchy
>
> - starting from its physical PCI Root port / Bridge device.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE.
>
> - @param PciConfigPhase for the PCI feature configuration phases:
>
> - PciExpressFeatureSetupPhase & PciExpressFeatureEntendedSetupPhase
>
> - @param PciFeaturesConfigurationTable pointer to PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE
>
> -
>
> - @retval EFI_SUCCESS processing of PCI feature Max_Read_Req_Size
>
> - is successful.
>
> -**/
>
> -EFI_STATUS
>
> -SetupMaxReadReqSize (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfigurationTable
>
> - );
>
> -
>
> -/**
>
> - Overrides the PCI Device Control register Max_Read_Req_Size register field; if
>
> - the hardware value is different than the intended value.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE instance.
>
> -
>
> - @retval EFI_SUCCESS The data was read from or written to the PCI controller.
>
> - @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
>
> - valid for the PCI configuration header of the PCI controller.
>
> - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
>
> -
>
> -**/
>
> -EFI_STATUS
>
> -ProgramMaxReadReqSize (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN VOID *PciExFeatureConfiguration
>
> - );
>
> -
>
> -/**
>
> - Overrides the PCI Device Control register Relax Order register field; if
>
> - the hardware value is different than the intended value.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE instance.
>
> -
>
> - @retval EFI_SUCCESS The data was read from or written to the PCI device.
>
> - @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
>
> - valid for the PCI configuration header of the PCI controller.
>
> - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
>
> -
>
> -**/
>
> -EFI_STATUS
>
> -ProgramRelaxOrder (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN VOID *PciExFeatureConfiguration
>
> - );
>
> -
>
> -/**
>
> - Overrides the PCI Device Control register No-Snoop register field; if
>
> - the hardware value is different than the intended value.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE instance.
>
> -
>
> - @retval EFI_SUCCESS The data was read from or written to the PCI device.
>
> - @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
>
> - valid for the PCI configuration header of the PCI controller.
>
> - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
>
> -
>
> -**/
>
> -EFI_STATUS
>
> -ProgramNoSnoop (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN VOID *PciExFeatureConfiguration
>
> - );
>
> -
>
> -/**
>
> - The main routine which process the PCI feature Completion Timeout as per the
>
> - device-specific platform policy, as well as in complaince with the PCI Base
>
> - specification Revision 4.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE.
>
> - @param PciConfigPhase for the PCI feature configuration phases:
>
> - PciExpressFeatureSetupPhase & PciExpressFeatureEntendedSetupPhase
>
> -
>
> - @retval EFI_SUCCESS processing of PCI feature CTO is successful.
>
> -**/
>
> -EFI_STATUS
>
> -SetupCompletionTimeout (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN VOID *PciExFeatureConfiguration
>
> - );
>
> -
>
> -/**
>
> - Overrides the PCI Device Control2 register Completion Timeout range; if
>
> - the hardware value is different than the intended value.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE instance.
>
> -
>
> - @retval EFI_SUCCESS The data was read from or written to the PCI device.
>
> - @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
>
> - valid for the PCI configuration header of the PCI controller.
>
> - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
>
> -
>
> -**/
>
> -EFI_STATUS
>
> -ProgramCompletionTimeout (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN VOID *PciExFeatureConfiguration
>
> - );
>
> -
>
> -/**
>
> - Routine to setup the AtomicOp Requester in the PCI device, verifies the routing
>
> - support in the bridge devices, to be complaint as per the PCI Base specification.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE.
>
> - @param PciExFeatureConfiguration pointer to common configuration table to
>
> - initialize the PCI Express feature
>
> -
>
> - @retval EFI_SUCCESS bridge device routing capability is successful.
>
> - EFI_INVALID_PARAMETER input parameter is NULL
>
> -**/
>
> -EFI_STATUS
>
> -SetupAtomicOpRoutingSupport (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExFeatureConfiguration
>
> - );
>
> -
>
> -/**
>
> - Overrides the PCI Device Control 2 register AtomicOp Requester enable field; if
>
> - the hardware value is different than the intended value.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE instance.
>
> -
>
> - @retval EFI_SUCCESS The data was read from or written to the PCI device.
>
> - @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
>
> - valid for the PCI configuration header of the PCI controller.
>
> - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
>
> -
>
> -**/
>
> -EFI_STATUS
>
> -ProgramAtomicOp (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN VOID *PciExFeatureConfiguration
>
> - );
>
> -
>
> -/**
>
> - The main routine which process the PCI feature LTR enable/disable as per the
>
> - device-specific platform policy, as well as in complaince with the PCI Express
>
> - Base specification Revision 5.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE.
>
> - @param PciFeaturesConfigurationTable pointer to PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE
>
> -
>
> - @retval EFI_SUCCESS setup of PCI feature LTR is successful.
>
> -**/
>
> -EFI_STATUS
>
> -SetupLtr (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfigurationTable
>
> - );
>
> -
>
> -EFI_STATUS
>
> -ReSetupLtr (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfigurationTable
>
> - );
>
> -
>
> -/**
>
> - Program the PCI Device Control 2 register LTR mechanism field; if
>
> - the hardware value is different than the intended value.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE instance.
>
> -
>
> - @retval EFI_SUCCESS The data was read from or written to the PCI device.
>
> - @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
>
> - valid for the PCI configuration header of the PCI controller.
>
> - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
>
> -
>
> -**/
>
> -EFI_STATUS
>
> -ProgramLtr (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN VOID *PciExFeatureConfiguration
>
> - );
>
> -
>
> -/**
>
> - The main routine to setup the PCI Express feature Extended Tag as per the
>
> - device-specific platform policy, as well as in complaince with the PCI Express
>
> - Base specification Revision 5.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE.
>
> - @param PciFeaturesConfigurationTable pointer to PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE
>
> -
>
> - @retval EFI_SUCCESS setup of PCI feature LTR is successful.
>
> -**/
>
> -EFI_STATUS
>
> -SetupExtTag (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfigurationTable
>
> - );
>
> -
>
> -/**
>
> - Additional routine to setup the PCI Express feature Extended Tag in complaince
>
> - with the PCI Express Base specification Revision, a common value for all the
>
> - devices in the PCI hierarchy.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE.
>
> - @param PciFeaturesConfigurationTable pointer to PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE
>
> -
>
> - @retval EFI_SUCCESS setup of PCI feature LTR is successful.
>
> -**/
>
> -EFI_STATUS
>
> -AlignExtTag (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfigurationTable
>
> - );
>
> -
>
> -/**
>
> - Program the PCI Device Control 2 register for 10b Extended Tag value, or the
>
> - Device Control register for 5b/8b Extended Tag value.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE instance.
>
> -
>
> - @retval EFI_SUCCESS The data was read from or written to the PCI device.
>
> - @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
>
> - valid for the PCI configuration header of the PCI controller.
>
> - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
>
> -
>
> -**/
>
> -EFI_STATUS
>
> -ProgramExtTag (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN VOID *PciExFeatureConfiguration
>
> - );
>
> -
>
> -/**
>
> - The main routine to setup the PCI Express feature ASPM as per the
>
> - device-specific platform policy, as well as in complaince with the PCI Express
>
> - Base specification Revision 5.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE.
>
> - @param PciFeaturesConfigurationTable pointer to PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE
>
> -
>
> - @retval EFI_SUCCESS setup of PCI feature LTR is successful.
>
> -**/
>
> -EFI_STATUS
>
> -SetupAspm (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfigurationTable
>
> - );
>
> -
>
> -/**
>
> - Setup of PCI Express feature ASPM in the PciExpressFeatureEntendedSetupPhase
>
> -**/
>
> -EFI_STATUS
>
> -AlignAspm (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfigurationTable
>
> - );
>
> -
>
> -/**
>
> - Program the PCIe Link Control register ASPM Control field; if
>
> - the hardware value is different than the intended value.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE instance.
>
> -
>
> - @retval EFI_SUCCESS The data was read from or written to the PCI device.
>
> - @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
>
> - valid for the PCI configuration header of the PCI controller.
>
> - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
>
> -
>
> -**/
>
> -EFI_STATUS
>
> -ProgramAspm (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN VOID *PciExFeatureConfiguration
>
> - );
>
> -
>
> -/**
>
> - The main routine to setup the PCI Express feature Common Clock configuration
>
> - as per the device-specific platform policy, as well as in complaince with the
>
> - PCI Express Base specification Revision 5.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE.
>
> - @param PciExpressConfigurationTable pointer to PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE
>
> -
>
> - @retval EFI_SUCCESS setup of PCI feature LTR is successful.
>
> -**/
>
> -EFI_STATUS
>
> -SetupCommonClkCfg (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfigurationTable
>
> - );
>
> -
>
> -/**
>
> - Program the PCIe Link Control register Coomon Clock Configuration field; if
>
> - the hardware value is different than the intended value.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE instance.
>
> -
>
> - @retval EFI_SUCCESS The data was read from or written to the PCI device.
>
> - @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
>
> - valid for the PCI configuration header of the PCI controller.
>
> - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
>
> -
>
> -**/
>
> -EFI_STATUS
>
> -ProgramCcc (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExFeatureConfiguration
>
> - );
>
> -
>
> -/**
>
> - Second phase of programming for Common Clock COnfiguration, conditoonally done
>
> - only on the downstream ports (bridge devices only).
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE instance.
>
> -
>
> - @retval EFI_SUCCESS The data was read from or written to the PCI device.
>
> - @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
>
> - valid for the PCI configuration header of the PCI controller.
>
> - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
>
> -
>
> -**/
>
> -EFI_STATUS
>
> -EnforceCcc (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExFeatureConfiguration
>
> - );
>
> -#endif
>
> diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c
> b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c
> deleted file mode 100644
> index 4d3641c..0000000
> --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c
> +++ /dev/null
> @@ -1,1019 +0,0 @@
> -/** @file
>
> - PCI standard feature support functions implementation for PCI Bus module..
>
> -
>
> -Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
>
> -
>
> -**/
>
> -
>
> -#include "PciBus.h"
>
> -#include "PciFeatureSupport.h"
>
> -#include "PciExpressFeatures.h"
>
> -
>
> -/**
>
> - Hold the current instance of Root Bridge IO protocol Handle
>
> -**/
>
> -EFI_HANDLE mRootBridgeHandle;
>
> -
>
> -/**
>
> - A gobal pointer to BRIDGE_DEVICE_NODE buffer to track all the primary physical
>
> - PCI Root Ports (PCI Controllers) for a given PCI Root Bridge instance while
>
> - enumerating to configure the PCI features
>
> -**/
>
> -LIST_ENTRY mRootBridgeDeviceList;
>
> -
>
> -/**
>
> - global list to indicate the supported PCI Express features of this driver, it
>
> - is expected to be overridden based on the platform request
>
> -**/
>
> -EFI_PCI_EXPRESS_PLATFORM_POLICY mPciExpressPlatformPolicy = {
>
> - //
>
> - // support for PCI Express feature - Max. Payload Size
>
> - //
>
> - TRUE,
>
> - //
>
> - // support for PCI Express feature - Max. Read Request Size
>
> - //
>
> - TRUE,
>
> - //
>
> - // support for PCI Express feature - Extended Tag
>
> - //
>
> - TRUE,
>
> - //
>
> - // support for PCI Express feature - Relax Order
>
> - //
>
> - TRUE,
>
> - //
>
> - // support for PCI Express feature - No-Snoop
>
> - //
>
> - TRUE,
>
> - //
>
> - // support for PCI Express feature - ASPM state
>
> - //
>
> - TRUE,
>
> - //
>
> - // support for PCI Express feature - Common Clock Configuration
>
> - //
>
> - TRUE,
>
> - //
>
> - // support for PCI Express feature - Extended Sync
>
> - //
>
> - FALSE,
>
> - //
>
> - // support for PCI Express feature - Atomic Op
>
> - //
>
> - TRUE,
>
> - //
>
> - // support for PCI Express feature - LTR
>
> - //
>
> - TRUE,
>
> - //
>
> - // support for PCI Express feature - PTM
>
> - //
>
> - FALSE,
>
> - //
>
> - // support for PCI Express feature - Completion Timeout
>
> - //
>
> - TRUE,
>
> - //
>
> - // support for PCI Express feature - Clock Power Management
>
> - //
>
> - FALSE,
>
> - //
>
> - // support for PCI Express feature - L1 PM Substates
>
> - //
>
> - FALSE
>
> -};
>
> -
>
> -//
>
> -// indicates the driver has completed query to platform on the list of supported
>
> -// PCI features to be configured
>
> -//
>
> -BOOLEAN mPciExpressGetPlatformPolicyComplete = FALSE;
>
> -
>
> -//
>
> -// PCI Express feature initialization phase handle routines
>
> -//
>
> -PCI_EXPRESS_FEATURE_INITIALIZATION_POINT mPciExpressFeatureInitializationList[] = {
>
> - {
>
> - PciExpressFeatureSetupPhase, PciExpressCcc, SetupCommonClkCfg
>
> - },
>
> - {
>
> - PciExpressFeatureEntendedSetupPhase, PciExpressCcc, ProgramCcc
>
> - },
>
> - {
>
> - PciExpressFeatureProgramPhase, PciExpressCcc, EnforceCcc
>
> - },
>
> - {
>
> - PciExpressFeatureSetupPhase, PciExpressAspm, SetupAspm
>
> - },
>
> - {
>
> - PciExpressFeatureEntendedSetupPhase, PciExpressAspm, AlignAspm
>
> - },
>
> - {
>
> - PciExpressFeatureProgramPhase, PciExpressAspm, ProgramAspm
>
> - },
>
> - {
>
> - PciExpressFeatureSetupPhase, PciExpressMps, SetupMaxPayloadSize
>
> - },
>
> - {
>
> - PciExpressFeatureEntendedSetupPhase, PciExpressMps, CasMaxPayloadSize
>
> - },
>
> - {
>
> - PciExpressFeatureProgramPhase, PciExpressMps, ProgramMaxPayloadSize
>
> - },
>
> - {
>
> - PciExpressFeatureSetupPhase, PciExpressMrrs, SetupMaxReadReqSize
>
> - },
>
> - {
>
> - PciExpressFeatureEntendedSetupPhase, PciExpressMrrs, ConditionalCasMaxReadReqSize
>
> - },
>
> - {
>
> - PciExpressFeatureProgramPhase, PciExpressMrrs, ProgramMaxReadReqSize
>
> - },
>
> - {
>
> - PciExpressFeatureProgramPhase, PciExpressRelaxOrder, ProgramRelaxOrder
>
> - },
>
> - {
>
> - PciExpressFeatureProgramPhase, PciExpressNoSnoop, ProgramNoSnoop
>
> - },
>
> - {
>
> - PciExpressFeatureSetupPhase, PciExpressCto, SetupCompletionTimeout
>
> - },
>
> - {
>
> - PciExpressFeatureProgramPhase, PciExpressCto, ProgramCompletionTimeout
>
> - },
>
> - {
>
> - PciExpressFeatureSetupPhase, PciExpressAtomicOp, SetupAtomicOpRoutingSupport
>
> - },
>
> - {
>
> - PciExpressFeatureProgramPhase, PciExpressAtomicOp, ProgramAtomicOp
>
> - },
>
> - {
>
> - PciExpressFeatureSetupPhase, PciExpressLtr, SetupLtr
>
> - },
>
> - {
>
> - PciExpressFeatureEntendedSetupPhase, PciExpressLtr, ReSetupLtr
>
> - },
>
> - {
>
> - PciExpressFeatureProgramPhase, PciExpressLtr, ProgramLtr
>
> - },
>
> - {
>
> - PciExpressFeatureSetupPhase, PciExpressExtTag, SetupExtTag
>
> - },
>
> - {
>
> - PciExpressFeatureEntendedSetupPhase, PciExpressExtTag, AlignExtTag
>
> - },
>
> - {
>
> - PciExpressFeatureProgramPhase, PciExpressExtTag, ProgramExtTag
>
> - }
>
> -};
>
> -
>
> -/**
>
> - Routine to serially dispatch the designated the PCI Express feature specific
>
> - functions defined for each of the configuration phase. The order for each phase
>
> - would be based entirely on the table mPciExpressFeatureInitializationList.
>
> -
>
> - @param PciDevice pointer to PCI_IO_DEVICE to identify device
>
> - @param PciExFeatureConfigPhase input configuration phase
>
> - @param PciExpressFeatureConfiguration used pointer to void to accomodate any PCI
>
> - Express feature specific data type
>
> - @retval EFI_STATUS output only from feature specific function
>
> - defined in the table mPciExpressFeatureInitializationList
>
> -**/
>
> -EFI_STATUS
>
> -DispatchPciExpressInitializationFunctions (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURE_CONFIGURATION_PHASE PciExFeatureConfigPhase,
>
> - IN VOID *PciExpressFeatureConfiguration
>
> - )
>
> -{
>
> - UINTN idx;
>
> - EFI_STATUS Status;
>
> - UINT8 *PciExpressPolicy;
>
> -
>
> - for (
>
> - idx = 0, PciExpressPolicy = (UINT8*)&mPciExpressPlatformPolicy
>
> - ; idx < sizeof (mPciExpressFeatureInitializationList) / sizeof (PCI_EXPRESS_FEATURE_INITIALIZATION_POINT)
>
> - ; idx++
>
> - ){
>
> - if (
>
> - //
>
> - // match the configuration phase
>
> - //
>
> - mPciExpressFeatureInitializationList[idx].PciExpressFeatureConfigurationPhase == PciExFeatureConfigPhase
>
> - //
>
> - // check whether the PCI Express features is enabled
>
> - //
>
> - && PciExpressPolicy[mPciExpressFeatureInitializationList[idx].PciExpressFeatureId] == TRUE
>
> - ) {
>
> - Status = mPciExpressFeatureInitializationList[idx].PciExpressFeatureConfigurationRoutine (
>
> - PciDevice,
>
> - PciExpressFeatureConfiguration
>
> - );
>
> - }
>
> - }
>
> - return Status;
>
> -}
>
> -
>
> -/**
>
> - Main routine to indicate platform selection of any of the other PCI features
>
> - to be configured by this driver
>
> -
>
> - @retval TRUE platform has selected the other PCI features to be configured
>
> - FALSE platform has not selected any of the other PCI features
>
> -**/
>
> -BOOLEAN
>
> -CheckPciExpressFeatureList (
>
> - )
>
> -{
>
> - UINTN length;
>
> - UINT8 *list;
>
> -
>
> - for (
>
> - length = 0, list = (UINT8*)&mPciExpressPlatformPolicy
>
> - ; length < sizeof (EFI_PCI_EXPRESS_PLATFORM_POLICY)
>
> - ; length++
>
> - ) {
>
> - if (list[length]) {
>
> - return TRUE;
>
> - }
>
> - }
>
> - return FALSE;
>
> -}
>
> -
>
> -/**
>
> - helper routine to wipe out the global PCI Express feature list
>
> -**/
>
> -VOID
>
> -NegatePciExpressFeatureList (
>
> - )
>
> -{
>
> - UINTN length;
>
> - UINT8 *list;
>
> -
>
> - for (
>
> - length = 0, list = (UINT8*)&mPciExpressPlatformPolicy
>
> - ; length < sizeof (EFI_PCI_EXPRESS_PLATFORM_POLICY)
>
> - ; length++
>
> - ) {
>
> - if (list[length]) {
>
> - list[length] = FALSE;
>
> - }
>
> - }
>
> -}
>
> -
>
> -/**
>
> - Main routine to indicate whether the PCI Express feature initialization is
>
> - required or not
>
> -
>
> - @retval TRUE PCI Express feature initialization required
>
> - FALSE PCI Express feature not required
>
> -**/
>
> -BOOLEAN
>
> -IsPciExpressFeatureConfigurationRequired (
>
> - )
>
> -{
>
> - EFI_STATUS Status;
>
> -
>
> - if (mPciExpressGetPlatformPolicyComplete) {
>
> - return CheckPciExpressFeatureList ();
>
> - }
>
> - //
>
> - // initialize the PCI Express feature data members
>
> - //
>
> - InitializeListHead (&mRootBridgeDeviceList);
>
> - //
>
> - // check the platform to configure the PCI Express features
>
> - //
>
> - mPciExpressGetPlatformPolicyComplete = TRUE;
>
> -
>
> - Status = PciExpressPlatformGetPolicy ();
>
> - if (EFI_ERROR (Status)) {
>
> - //
>
> - // fail to obtain the PCI Express feature configuration from platform,
>
> - // negate the list to avoid any unwanted configuration
>
> - //
>
> - NegatePciExpressFeatureList ();
>
> - return FALSE;
>
> - }
>
> - //
>
> - // PCI Express feature configuration list is ready from platform
>
> - //
>
> - return TRUE;
>
> -}
>
> -
>
> -
>
> -/**
>
> - Indicates whether the set of PCI Express features selected by platform requires
>
> - extended setup, that has additional resources that would be allocated to align
>
> - all the devices in the PCI tree, and free the resources later.
>
> -
>
> - @retval TRUE PCI Express feature requires extended setup
>
> - FALSE PCI Express feature does not require extended setup
>
> -**/
>
> -BOOLEAN
>
> -IsPciExpressFeatureExtendedSetupRequired (
>
> - )
>
> -{
>
> - UINTN idx;
>
> - UINT8 *PciExpressPolicy;
>
> - //
>
> - // return TRUE only for those features which are required to be aligned with
>
> - // common values among all the devices in the PCI tree
>
> - //
>
> - for (
>
> - idx = 0, PciExpressPolicy = (UINT8*)&mPciExpressPlatformPolicy
>
> - ; idx < sizeof (mPciExpressFeatureInitializationList) / sizeof (PCI_EXPRESS_FEATURE_INITIALIZATION_POINT)
>
> - ; idx++
>
> - ){
>
> - if (
>
> - //
>
> - // match the configuration phase to extended setup phase
>
> - //
>
> - mPciExpressFeatureInitializationList[idx].PciExpressFeatureConfigurationPhase ==
> PciExpressFeatureEntendedSetupPhase
>
> - //
>
> - // check whether the PCI Express features is enabled
>
> - //
>
> - && PciExpressPolicy[mPciExpressFeatureInitializationList[idx].PciExpressFeatureId] == TRUE
>
> - ) {
>
> - return TRUE;
>
> - } else if (
>
> - //
>
> - // the PCI Express feature does not require extended setup phase but it
>
> - // does require global flag to track the AtomicOpRouting caoability to
>
> - // be tracked for all its bridge devices
>
> - //
>
> - idx == PciExpressAtomicOp
>
> - && PciExpressPolicy[idx] == TRUE
>
> - ) {
>
> - return TRUE;
>
> - }
>
> - }
>
> -
>
> - return FALSE;
>
> -}
>
> -
>
> -/**
>
> - Helper routine to determine the existence of previously enumerated PCI device
>
> -
>
> - @retval TRUE PCI device exist
>
> - FALSE does not exist
>
> -**/
>
> -BOOLEAN
>
> -DeviceExist (
>
> - PCI_IO_DEVICE *PciDevice
>
> - )
>
> -{
>
> - EFI_PCI_IO_PROTOCOL *PciIoProtocol = &PciDevice->PciIo;
>
> - UINT16 VendorId = 0xFFFF;
>
> -
>
> - PciIoProtocol->Pci.Read (
>
> - PciIoProtocol,
>
> - EfiPciIoWidthUint16,
>
> - PCI_VENDOR_ID_OFFSET,
>
> - 1,
>
> - &VendorId
>
> - );
>
> - if (VendorId == 0 || VendorId == 0xFFFF) {
>
> - return FALSE;
>
> - } else {
>
> - return TRUE;
>
> - }
>
> -}
>
> -
>
> -/**
>
> - Free up memory alloted for the primary physical PCI Root ports of the PCI Root
>
> - Bridge instance. Free up all the nodes of type BRIDGE_DEVICE_NODE.
>
> -**/
>
> -VOID
>
> -DestroyRootBridgeDeviceNodes ()
>
> -{
>
> - LIST_ENTRY *Link;
>
> - BRIDGE_DEVICE_NODE *Temp;
>
> -
>
> - Link = mRootBridgeDeviceList.ForwardLink;
>
> - while (Link != NULL && Link != &mRootBridgeDeviceList) {
>
> - Temp = ROOT_BRIDGE_DEVICE_NODE_FROM_LINK (Link);
>
> - Link = RemoveEntryList (Link);
>
> - FreePool (Temp->PciExFeaturesConfigurationTable);
>
> - FreePool (Temp);
>
> - }
>
> -}
>
> -
>
> -/**
>
> - Main routine to determine the child PCI devices of a PCI bridge device
>
> - and group them under a common internal PCI features Configuration table.
>
> -
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE.
>
> - @param PciFeaturesConfigTable A pointer to a pointer to the
>
> - PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE.
>
> - Returns NULL in case of RCiEP or the PCI
>
> - device does match with any of the physical
>
> - Root ports, or it does not belong to any
>
> - Root port's PCI bus range (not a child)
>
> -
>
> - @retval EFI_SUCCESS able to determine the PCI feature
>
> - configuration table. For RCiEP since
>
> - since it is not prepared.
>
> - EFI_DEVICE_ERROR the PCI device has invalid EFI device
>
> - path
>
> -**/
>
> -EFI_STATUS
>
> -GetPciExpressFeaturesConfigurationTable (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - OUT PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE **PciFeaturesConfigTable
>
> - )
>
> -{
>
> - LIST_ENTRY *Link;
>
> - BRIDGE_DEVICE_NODE *Temp;
>
> - BOOLEAN NodeMatch;
>
> - EFI_DEVICE_PATH_PROTOCOL *RootPortPath;
>
> - EFI_DEVICE_PATH_PROTOCOL *PciDevicePath;
>
> -
>
> - if (IsListEmpty (&mRootBridgeDeviceList)) {
>
> - //
>
> - // no populated PCI primary root ports to parse and match the PCI features
>
> - // configuration table
>
> - //
>
> - *PciFeaturesConfigTable = NULL;
>
> - return EFI_SUCCESS;
>
> - }
>
> -
>
> - //
>
> - // The PCI features configuration table is not built for RCiEP, return NULL
>
> - //
>
> - if (PciDevice->PciExpressCapabilityStructure.Capability.Bits.DevicePortType == \
>
> - PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT) {
>
> - *PciFeaturesConfigTable = NULL;
>
> - return EFI_SUCCESS;
>
> - }
>
> -
>
> - if (IsDevicePathEnd (PciDevice->DevicePath)){
>
> - //
>
> - // the given PCI device does not have a valid device path
>
> - //
>
> - *PciFeaturesConfigTable = NULL;
>
> - return EFI_DEVICE_ERROR;
>
> - }
>
> -
>
> -
>
> - Link = mRootBridgeDeviceList.ForwardLink;
>
> - do {
>
> - Temp = ROOT_BRIDGE_DEVICE_NODE_FROM_LINK (Link);
>
> - RootPortPath = Temp->RootBridgeDevicePath;
>
> - PciDevicePath = PciDevice->DevicePath;
>
> - NodeMatch = FALSE;
>
> - //
>
> - // match the device path from the list of primary Root Ports with the given
>
> - // device; the initial nodes matching in sequence indicate that the given PCI
>
> - // device belongs to that PCI tree from the root port
>
> - //
>
> - if (IsDevicePathEnd (RootPortPath)) {
>
> - //
>
> - // critical error as no device path available in root
>
> - //
>
> - *PciFeaturesConfigTable = NULL;
>
> - return EFI_DEVICE_ERROR;
>
> - }
>
> -
>
> - if (EfiCompareDevicePath (RootPortPath, PciDevicePath)) {
>
> - //
>
> - // the given PCI device is the primary root port itself
>
> - //
>
> - *PciFeaturesConfigTable = Temp->PciExFeaturesConfigurationTable;
>
> - return EFI_SUCCESS;
>
> - }
>
> - //
>
> - // check this PCI device belongs to the primary root port of the root bridge
>
> - // any child PCI device will have the same initial device path nodes as
>
> - // its parent root port
>
> - //
>
> - while (!IsDevicePathEnd (RootPortPath)){
>
> -
>
> - if (DevicePathNodeLength (RootPortPath) != DevicePathNodeLength (PciDevicePath)) {
>
> - //
>
> - // break to check the next primary root port nodes as does not match
>
> - //
>
> - NodeMatch = FALSE;
>
> - break;
>
> - }
>
> - if (CompareMem (RootPortPath, PciDevicePath, DevicePathNodeLength (RootPortPath)) != 0) {
>
> - //
>
> - // node does not match, break to check next node
>
> - //
>
> - NodeMatch = FALSE;
>
> - break;
>
> - }
>
> - NodeMatch = TRUE;
>
> - //
>
> - // advance to next node
>
> - //
>
> - RootPortPath = NextDevicePathNode (RootPortPath);
>
> - PciDevicePath = NextDevicePathNode (PciDevicePath);
>
> - }
>
> -
>
> - if (NodeMatch == TRUE) {
>
> - //
>
> - // device belongs to primary root port, return its PCI feature configuration
>
> - // table
>
> - //
>
> - *PciFeaturesConfigTable = Temp->PciExFeaturesConfigurationTable;
>
> - return EFI_SUCCESS;
>
> - }
>
> -
>
> - //
>
> - // advance to next Root port node
>
> - //
>
> - Link = Link->ForwardLink;
>
> - } while (Link != &mRootBridgeDeviceList && Link != NULL);
>
> - //
>
> - // the PCI device must be RCiEP, does not belong to any primary root port
>
> - //
>
> - *PciFeaturesConfigTable = NULL;
>
> - return EFI_SUCCESS;
>
> -}
>
> -
>
> -/**
>
> - helper routine to dump the PCIe Device Port Type
>
> -**/
>
> -VOID
>
> -DumpDevicePortType (
>
> - IN UINT8 DevicePortType
>
> - )
>
> -{
>
> - switch (DevicePortType){
>
> - case PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT:
>
> - DEBUG (( DEBUG_INFO, "PCIe endpoint found\n"));
>
> - break;
>
> - case PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT:
>
> - DEBUG (( DEBUG_INFO, "legacy PCI endpoint found\n"));
>
> - break;
>
> - case PCIE_DEVICE_PORT_TYPE_ROOT_PORT:
>
> - DEBUG (( DEBUG_INFO, "PCIe Root Port found\n"));
>
> - break;
>
> - case PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT:
>
> - DEBUG (( DEBUG_INFO, "PCI switch upstream port found\n"));
>
> - break;
>
> - case PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT:
>
> - DEBUG (( DEBUG_INFO, "PCI switch downstream port found\n"));
>
> - break;
>
> - case PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE:
>
> - DEBUG (( DEBUG_INFO, "PCIe-PCI bridge found\n"));
>
> - break;
>
> - case PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE:
>
> - DEBUG (( DEBUG_INFO, "PCI-PCIe bridge found\n"));
>
> - break;
>
> - case PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT:
>
> - DEBUG (( DEBUG_INFO, "RCiEP found\n"));
>
> - break;
>
> - case PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR:
>
> - DEBUG (( DEBUG_INFO, "RC Event Collector found\n"));
>
> - break;
>
> - }
>
> -}
>
> -
>
> -/**
>
> - Setup each PCI device as per the pltaform's device-specific policy, in accordance
>
> - with PCI Express Base specification.
>
> -
>
> - @param RootBridge A pointer to the PCI_IO_DEVICE.
>
> -
>
> - @retval EFI_SUCCESS processing each PCI feature as per policy defined
>
> - was successful.
>
> - **/
>
> -EFI_STATUS
>
> -SetupDevicePciExpressFeatures (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURE_CONFIGURATION_PHASE PciConfigPhase
>
> - )
>
> -{
>
> - EFI_STATUS Status;
>
> - PCI_REG_PCIE_CAPABILITY PcieCap;
>
> - PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressFeaturesConfigTable;
>
> -
>
> - PciExpressFeaturesConfigTable = NULL;
>
> - Status = GetPciExpressFeaturesConfigurationTable (PciDevice, &PciExpressFeaturesConfigTable);
>
> -
>
> - if (PciConfigPhase == PciExpressFeatureSetupPhase) {
>
> - DEBUG_CODE (
>
> - if (EFI_ERROR( Status)) {
>
> - DEBUG ((
>
> - DEBUG_WARN,
>
> - "[Cfg group: 0 {error in dev path}]"
>
> - ));
>
> - } else if (PciExpressFeaturesConfigTable == NULL) {
>
> - DEBUG ((
>
> - DEBUG_INFO,
>
> - "[Cfg group: 0]"
>
> - ));
>
> - } else {
>
> - DEBUG ((
>
> - DEBUG_INFO,
>
> - "[Cfg group: %d]",
>
> - PciExpressFeaturesConfigTable->ID
>
> - ));
>
> - }
>
> - PcieCap.Uint16 = PciDevice->PciExpressCapabilityStructure.Capability.Uint16;
>
> - DumpDevicePortType ((UINT8)PcieCap.Bits.DevicePortType);
>
> - );
>
> -
>
> - //
>
> - // get the device-specific platform policy for the PCI Express features
>
> - //
>
> - Status = PciExpressPlatformGetDevicePolicy (PciDevice);
>
> - if (EFI_ERROR(Status)) {
>
> - DEBUG ((
>
> - DEBUG_ERROR,
>
> - "Error in obtaining PCI device policy!!!\n"
>
> - ));
>
> - }
>
> - }
>
> -
>
> - DEBUG ((DEBUG_INFO, "["));
>
> -
>
> - Status = DispatchPciExpressInitializationFunctions (
>
> - PciDevice,
>
> - PciConfigPhase,
>
> - PciExpressFeaturesConfigTable
>
> - );
>
> -
>
> - DEBUG ((DEBUG_INFO, "]\n"));
>
> - return Status;
>
> -}
>
> -
>
> -/**
>
> - Create and append a node of type BRIDGE_DEVICE_NODE in the list for the primary
>
> - Root Port so that all its child PCI devices can be identified against the PCI
>
> - features configuration table group ID, of type PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE.
>
> -
>
> - @param BridgePort A pointer to the PCI_IO_DEVICE
>
> - @param PortNumber A UINTN value to identify the PCI feature configuration
>
> - table group
>
> -
>
> - @retval EFI_SUCCESS success in adding a node of BRIDGE_DEVICE_NODE
>
> - to the list
>
> - EFI_OUT_OF_RESOURCES unable to get memory for creating the node
>
> -**/
>
> -EFI_STATUS
>
> -CreatePciRootBridgeDeviceNode (
>
> - IN PCI_IO_DEVICE *BridgePort,
>
> - IN UINTN PortNumber
>
> - )
>
> -{
>
> - BRIDGE_DEVICE_NODE *RootBridgeNode = NULL;
>
> - PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciConfigTable = NULL;
>
> -
>
> - RootBridgeNode = AllocateZeroPool (sizeof (BRIDGE_DEVICE_NODE));
>
> - if (RootBridgeNode == NULL) {
>
> - return EFI_OUT_OF_RESOURCES;
>
> - }
>
> - RootBridgeNode->Signature = PCI_ROOT_BRIDGE_DEVICE_SIGNATURE;
>
> - RootBridgeNode->RootBridgeDevicePath = BridgePort->DevicePath;
>
> - PciConfigTable = AllocateZeroPool (
>
> - sizeof (PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE)
>
> - );
>
> - if (PciConfigTable) {
>
> - PciConfigTable->ID = PortNumber;
>
> - //
>
> - // start by assuming 4096B as the default value for the Max. Payload Size
>
> - //
>
> - PciConfigTable->Max_Payload_Size = PCIE_MAX_PAYLOAD_SIZE_4096B;
>
> - //
>
> - // start by assuming 4096B as the default value for the Max. Read Request Size
>
> - //
>
> - PciConfigTable->Max_Read_Request_Size = PCIE_MAX_READ_REQ_SIZE_4096B;
>
> - //
>
> - // start by assuming the Max. Read Request Size need not be common for all
>
> - // the devices in the PCI tree
>
> - //
>
> - PciConfigTable->Lock_Max_Read_Request_Size = FALSE;
>
> - //
>
> - // start by assuming the LTR mechanism is supported in a PCI tree
>
> - //
>
> - PciConfigTable->LtrSupported = TRUE;
>
> - //
>
> - // the default LTR mechanism is disabled as per the PCI Base specification
>
> - //
>
> - PciConfigTable->LtrEnable = FALSE;
>
> - //
>
> - // start by assuming the AtomicOp Routing capability is supported in the PCI
>
> - // tree
>
> - //
>
> - PciConfigTable->AtomicOpRoutingSupported = TRUE;
>
> - //
>
> - // start by assuming the Extended Tag is 10b Requester capable
>
> - //
>
> - PciConfigTable->ExtendedTag = EFI_PCI_EXPRESS_EXTENDED_TAG_10BIT;
>
> - //
>
> - // initial state set to ASPM L0s and L1 both
>
> - //
>
> - PciConfigTable->AspmSupport = EFI_PCI_EXPRESS_ASPM_L0S_L1_SUPPORT;
>
> - //
>
> - // start by assuming less than 64ns of L0s Exit Latency
>
> - //
>
> - PciConfigTable->L0sExitLatency = PCIE_LINK_CAPABILITY_L0S_EXIT_LATENCY_64NS;
>
> - //
>
> - // start by assuming less than 1us of L1 Exit Latency
>
> - //
>
> - PciConfigTable->L1ExitLatency = PCIE_LINK_CAPABILITY_L1_EXIT_LATENCY_1US;
>
> - //
>
> - // default link retrain is not required
>
> - //
>
> - PciConfigTable->LinkReTrain = FALSE;
>
> - //
>
> - // start by assuming no common clock configuration mode for the device's link
>
> - //
>
> - PciConfigTable->CommonClockConfiguration = FALSE;
>
> - }
>
> -
>
> - RootBridgeNode->PciExFeaturesConfigurationTable = PciConfigTable;
>
> -
>
> - InsertTailList (&mRootBridgeDeviceList, &RootBridgeNode->NextRootBridgeDevice);
>
> -
>
> - if (PciConfigTable == NULL) {
>
> - return EFI_OUT_OF_RESOURCES;
>
> - }
>
> - return EFI_SUCCESS;
>
> -}
>
> -
>
> -/**
>
> - Scan all the nodes of the RootBridge to identify and create a separate list
>
> - of all primary physical PCI root ports and link each with its own instance of
>
> - the PCI Feature Configuration Table.
>
> -
>
> - @param RootBridge A pointer to the PCI_IO_DEVICE of the PCI Root Bridge
>
> -
>
> - @retval EFI_OUT_OF_RESOURCES unable to allocate buffer to store PCI feature
>
> - configuration table for all the physical PCI root
>
> - ports given
>
> - EFI_NOT_FOUND No PCI Bridge device found
>
> - EFI_SUCCESS PCI Feature COnfiguration table created for all
>
> - the PCI Rooot ports found
>
> - EFI_INVALID_PARAMETER invalid parameter passed to the routine which
>
> - creates the PCI controller node for the primary
>
> - Root post list
>
> -**/
>
> -EFI_STATUS
>
> -CreatePciRootBridgeDeviceList (
>
> - IN PCI_IO_DEVICE *RootBridge
>
> - )
>
> -{
>
> - EFI_STATUS Status = EFI_NOT_FOUND;
>
> - LIST_ENTRY *Link;
>
> - PCI_IO_DEVICE *Device;
>
> - UINTN BridgeDeviceCount;
>
> -
>
> - BridgeDeviceCount = 0;
>
> - for ( Link = RootBridge->ChildList.ForwardLink
>
> - ; Link != &RootBridge->ChildList
>
> - ; Link = Link->ForwardLink
>
> - ) {
>
> - Device = PCI_IO_DEVICE_FROM_LINK (Link);
>
> - if (!DeviceExist (Device)) {
>
> - continue;
>
> - }
>
> - if (IS_PCI_BRIDGE (&Device->Pci)) {
>
> - BridgeDeviceCount++;
>
> - DEBUG ((
>
> - DEBUG_INFO,
>
> - "#%d ::Bridge [%02x|%02x|%02x]",
>
> - BridgeDeviceCount, Device->BusNumber, Device->DeviceNumber, Device->FunctionNumber
>
> - ));
>
> - //
>
> - // create a list of bridge devices if that is connected to any other device
>
> - //
>
> - if (!IsListEmpty (&Device->ChildList)) {
>
> - DEBUG ((
>
> - DEBUG_INFO,
>
> - "- has downstream device!\n"
>
> - ));
>
> - Status = CreatePciRootBridgeDeviceNode (Device, BridgeDeviceCount);
>
> - if (EFI_ERROR (Status)) {
>
> - DEBUG ((
>
> - DEBUG_ERROR,
>
> - "PCI configuration table allocation failure for #%d ::Bridge [%02x|%02x|%02x]\n",
>
> - BridgeDeviceCount, Device->BusNumber, Device->DeviceNumber, Device->FunctionNumber
>
> - ));
>
> - }
>
> - } else {
>
> - DEBUG ((
>
> - DEBUG_INFO,
>
> - "- no downstream device!\n"
>
> - ));
>
> - }
>
> - }
>
> - }
>
> -
>
> - return Status;
>
> -}
>
> -
>
> -/**
>
> - Initialize the device's PCI Express features, in a staged manner
>
> - @param PciDevice A pointer to the PCI_IO_DEVICE.
>
> -
>
> - @retval EFI_SUCCESS initializing all the nodes of the root bridge
>
> - instances were successfull.
>
> -**/
>
> -EFI_STATUS
>
> -InitializeDevicePciExpressFeatures (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN PCI_EXPRESS_FEATURE_CONFIGURATION_PHASE PciConfigPhase
>
> - )
>
> -{
>
> - EFI_STATUS Status;
>
> -
>
> - switch (PciConfigPhase) {
>
> - case PciExpressFeatureSetupPhase:
>
> - case PciExpressFeatureEntendedSetupPhase:
>
> - case PciExpressFeatureProgramPhase:
>
> - Status = SetupDevicePciExpressFeatures (PciDevice, PciConfigPhase);
>
> - break;
>
> - case PciExpressFeatureEndPhase:
>
> - Status = PciExpressPlatformNotifyDeviceState (PciDevice);
>
> - break;
>
> - }
>
> - return Status;
>
> -}
>
> -
>
> -/**
>
> - Traverse all the nodes from the root bridge or PCI-PCI bridge instance, to
>
> - configure the PCI Express features as per the PCI Express Base Secification
>
> - by considering its device-specific platform policy, and its device capability,
>
> - as applicable.
>
> -
>
> - @param RootBridge A pointer to the PCI_IO_DEVICE.
>
> -
>
> - @retval EFI_SUCCESS Traversing all the nodes of the root bridge
>
> - instances were successfull.
>
> -**/
>
> -EFI_STATUS
>
> -InitializePciExpressFeatures (
>
> - IN PCI_IO_DEVICE *RootBridge,
>
> - IN PCI_EXPRESS_FEATURE_CONFIGURATION_PHASE PciConfigPhase
>
> - )
>
> -{
>
> - EFI_STATUS Status;
>
> - LIST_ENTRY *Link;
>
> - PCI_IO_DEVICE *Device;
>
> -
>
> - for ( Link = RootBridge->ChildList.ForwardLink
>
> - ; Link != &RootBridge->ChildList
>
> - ; Link = Link->ForwardLink
>
> - ) {
>
> - Device = PCI_IO_DEVICE_FROM_LINK (Link);
>
> - if (!DeviceExist (Device)) {
>
> - DEBUG ((
>
> - DEBUG_ERROR,
>
> - "::Device [%02x|%02x|%02x] - does not exist!!!\n",
>
> - Device->BusNumber, Device->DeviceNumber, Device->FunctionNumber
>
> - ));
>
> - continue;
>
> - }
>
> - if (IS_PCI_BRIDGE (&Device->Pci)) {
>
> - DEBUG ((
>
> - DEBUG_INFO,
>
> - "::Bridge [%02x|%02x|%02x] -",
>
> - Device->BusNumber, Device->DeviceNumber, Device->FunctionNumber
>
> - ));
>
> - if (Device->IsPciExp) {
>
> - Status = InitializeDevicePciExpressFeatures (
>
> - Device,
>
> - PciConfigPhase
>
> - );
>
> - } else {
>
> - DEBUG ((
>
> - DEBUG_INFO,
>
> - "Not a PCIe capable device!\n"
>
> - ));
>
> - //
>
> - // PCI Bridge which does not have PCI Express Capability structure
>
> - // cannot process this kind of PCI Bridge device
>
> - //
>
> - }
>
> -
>
> - InitializePciExpressFeatures (Device, PciConfigPhase);
>
> - } else {
>
> - DEBUG ((
>
> - DEBUG_INFO,
>
> - "::Device [%02x|%02x|%02x] -",
>
> - Device->BusNumber, Device->DeviceNumber, Device->FunctionNumber
>
> - ));
>
> - if (Device->IsPciExp) {
>
> - Status = InitializeDevicePciExpressFeatures (
>
> - Device,
>
> - PciConfigPhase
>
> - );
>
> - } else {
>
> - DEBUG ((
>
> - DEBUG_INFO,
>
> - "Not a PCIe capable device!\n"
>
> - ));
>
> - //
>
> - // PCI Device which does not have PCI Express Capability structure
>
> - // cannot process this kind of PCI device
>
> - //
>
> - }
>
> - }
>
> - }
>
> -
>
> - return EFI_SUCCESS;
>
> -}
>
> -
>
> -/**
>
> - Enumerate all the nodes of the specified root bridge or PCI-PCI Bridge, to
>
> - configure the other PCI features.
>
> -
>
> - @param RootBridge A pointer to the PCI_IO_DEVICE.
>
> -
>
> - @retval EFI_SUCCESS The other PCI features configuration during enumeration
>
> - of all the nodes of the PCI root bridge instance were
>
> - programmed in PCI-compliance pattern along with the
>
> - device-specific policy, as applicable.
>
> - @retval EFI_UNSUPPORTED One of the override operation maong the nodes of
>
> - the PCI hierarchy resulted in a incompatible address
>
> - range.
>
> - @retval EFI_INVALID_PARAMETER The override operation is performed with invalid input
>
> - parameters.
>
> -**/
>
> -EFI_STATUS
>
> -EnumeratePciExpressFeatures (
>
> - IN EFI_HANDLE Controller,
>
> - IN PCI_IO_DEVICE *RootBridge
>
> - )
>
> -{
>
> - EFI_STATUS Status;
>
> - UINTN PciExpressFeatureConfigPhase;
>
> -
>
> - if (!IsPciExpressFeatureConfigurationRequired ()) {
>
> - //
>
> - // exit as agreement is not reached with platform to configure the PCI
>
> - // Express features
>
> - //
>
> - return EFI_SUCCESS;
>
> - }
>
> - mRootBridgeHandle = Controller;
>
> -
>
> - DEBUG_CODE (
>
> - CHAR16 *Str;
>
> - Str = ConvertDevicePathToText (
>
> - DevicePathFromHandle (RootBridge->Handle),
>
> - FALSE,
>
> - FALSE
>
> - );
>
> - DEBUG ((
>
> - DEBUG_INFO,
>
> - "Enumerating PCI features for Root Bridge %s\n",
>
> - Str != NULL ? Str : L""
>
> - ));
>
> -
>
> - if (Str != NULL) {
>
> - FreePool (Str);
>
> - }
>
> - );
>
> -
>
> - for ( PciExpressFeatureConfigPhase = PciExpressFeaturePreProcessPhase
>
> - ; PciExpressFeatureConfigPhase <= PciExpressFeatureEndPhase
>
> - ; PciExpressFeatureConfigPhase++
>
> - ) {
>
> - DEBUG ((
>
> - DEBUG_INFO,
>
> - "<<********** Phase [%d]**********>>\n",
>
> - PciExpressFeatureConfigPhase
>
> - ));
>
> - if (PciExpressFeatureConfigPhase == PciExpressFeaturePreProcessPhase) {
>
> - //
>
> - // create a list of root bridge devices (root ports) of the root complex
>
> - // if extra setup phase required
>
> - //
>
> - if (IsPciExpressFeatureExtendedSetupRequired ()) {
>
> - CreatePciRootBridgeDeviceList (RootBridge);
>
> - }
>
> - continue;
>
> - }
>
> - if (PciExpressFeatureConfigPhase == PciExpressFeatureEntendedSetupPhase) {
>
> - if (!IsPciExpressFeatureExtendedSetupRequired ()) {
>
> - //
>
> - // since the PCI Express features require no extra initialization steps
>
> - // skip this phase
>
> - //
>
> - continue;
>
> - }
>
> - }
>
> - //
>
> - // setup the PCI Express features
>
> - //
>
> - Status = InitializePciExpressFeatures (RootBridge, PciExpressFeatureConfigPhase);
>
> -
>
> - if (PciExpressFeatureConfigPhase == PciExpressFeatureEndPhase) {
>
> - //
>
> - // clean up the temporary resource nodes created for this root bridge
>
> - //
>
> - if (IsPciExpressFeatureExtendedSetupRequired ()) {
>
> - DestroyRootBridgeDeviceNodes ();
>
> - }
>
> - }
>
> - }
>
> -
>
> - return Status;
>
> -}
>
> diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h
> b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h
> deleted file mode 100644
> index 481bd90..0000000
> --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h
> +++ /dev/null
> @@ -1,304 +0,0 @@
> -/** @file
>
> - PCI standard feature support functions implementation for PCI Bus module..
>
> -
>
> -Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
>
> -
>
> -**/
>
> -
>
> -#ifndef _EFI_PCI_FEATURES_SUPPORT_H_
>
> -#define _EFI_PCI_FEATURES_SUPPORT_H_
>
> -
>
> -extern EFI_HANDLE mRootBridgeHandle;
>
> -extern EFI_PCI_EXPRESS_PLATFORM_POLICY mPciExpressPlatformPolicy;
>
> -//
>
> -// defines the data structure to hold the details of the PCI Root port devices
>
> -//
>
> -typedef struct _BRIDGE_DEVICE_NODE BRIDGE_DEVICE_NODE;
>
> -
>
> -//
>
> -// defines the data structure to hold the configuration data for the other PCI
>
> -// features
>
> -//
>
> -typedef struct _PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE;
>
> -
>
> -//
>
> -// define the data type for the PCI feature policy support
>
> -//
>
> -typedef struct _PCI_FEATURE_POLICY PCI_FEATURE_POLICY;
>
> -
>
> -//
>
> -// Signature value for the PCI Root Port node
>
> -//
>
> -#define PCI_ROOT_BRIDGE_DEVICE_SIGNATURE SIGNATURE_32 ('p', 'c', 'i', 'p')
>
> -
>
> -//
>
> -// Definitions of the PCI Root Port data structure members
>
> -//
>
> -struct _BRIDGE_DEVICE_NODE {
>
> - //
>
> - // Signature header
>
> - //
>
> - UINT32 Signature;
>
> - //
>
> - // linked list pointers to next node
>
> - //
>
> - LIST_ENTRY NextRootBridgeDevice;
>
> - //
>
> - // pointer to PCI_IO_DEVICE of the primary PCI Controller device
>
> - //
>
> - EFI_DEVICE_PATH_PROTOCOL *RootBridgeDevicePath;
>
> - //
>
> - // pointer to the corresponding PCI Express feature configuration Table node
>
> - // all the child PCI devices of the controller are aligned based on this table
>
> - //
>
> - PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExFeaturesConfigurationTable;
>
> -};
>
> -
>
> -#define ROOT_BRIDGE_DEVICE_NODE_FROM_LINK(a) \
>
> - CR (a, BRIDGE_DEVICE_NODE, NextRootBridgeDevice, PCI_ROOT_BRIDGE_DEVICE_SIGNATURE)
>
> -
>
> -//
>
> -// Definition of the PCI Feature configuration Table members
>
> -//
>
> -struct _PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE {
>
> - //
>
> - // Configuration Table ID
>
> - //
>
> - UINTN ID;
>
> - //
>
> - // to configure the PCI feature Maximum payload size to maintain the data packet
>
> - // size among all the PCI devices in the PCI hierarchy
>
> - //
>
> - UINT8 Max_Payload_Size;
>
> - //
>
> - // to configure the PCI feature maximum read request size to maintain the memory
>
> - // requester size among all the PCI devices in the PCI hierarchy
>
> - //
>
> - UINT8 Max_Read_Request_Size;
>
> - //
>
> - // lock the Max_Read_Request_Size for the entire PCI tree of a root port
>
> - //
>
> - BOOLEAN Lock_Max_Read_Request_Size;
>
> - //
>
> - // to record the adversity in LTR mechanism support capability among the PCI
>
> - // device of an heirarchy
>
> - //
>
> - BOOLEAN LtrSupported;
>
> - //
>
> - // to enable the LTR mechansim for the entire PCI tree from a root port
>
> - //
>
> - BOOLEAN LtrEnable;
>
> - //
>
> - // to record the AtomicOp Routing capability of the PCI Heirarchy to enable
>
> - // the AtomicOp of the EP device
>
> - //
>
> - BOOLEAN AtomicOpRoutingSupported;
>
> - //
>
> - // to configure a common extended tag size for all the childs of a root port
>
> - //
>
> - UINT8 ExtendedTag;
>
> - //
>
> - // to configure common ASPM state for all the devices link
>
> - //
>
> - UINT8 AspmSupport;
>
> - //
>
> - // to record maximum L0s Exit Latency among all the devices starting from root
>
> - // bridge device to its downstream bridge and its endpoint device
>
> - //
>
> - UINT8 L0sExitLatency;
>
> - //
>
> - // to record maximum L1 Exit Latency among all the devices starting from root
>
> - // bridge device to its downstream bridge and its endpoint device
>
> - //
>
> - UINT8 L1ExitLatency;
>
> - //
>
> - // flag to indicate the link training is required in the devices of downstream
>
> - // ports
>
> - //
>
> - BOOLEAN LinkReTrain;
>
> - //
>
> - // link status slot clock configuration
>
> - //
>
> - BOOLEAN CommonClockConfiguration;
>
> -};
>
> -
>
> -//
>
> -// Declaration of the internal sub-phases during enumeration to configure the PCI
>
> -// Express features
>
> -//
>
> -typedef enum {
>
> - //
>
> - // preprocessing applicable only to few PCI Express features to bind all devices
>
> - // under the common root bridge device (root port), that would be useful to align
>
> - // all devices with a common value. This would be optional phase based on the
>
> - // type of the PCI Express feature to be programmed based on platform policy
>
> - //
>
> - PciExpressFeaturePreProcessPhase,
>
> -
>
> - //
>
> - // mandatory phase to setup the PCI Express feature to its applicable attribute,
>
> - // based on its device-specific platform policies, matching with its device capabilities
>
> - //
>
> - PciExpressFeatureSetupPhase,
>
> -
>
> - //
>
> - // optional phase primarily to align all devices, specially required when PCI
>
> - // switch is present in the hierarchy, applicable to certain few PCI Express
>
> - // features only
>
> - //
>
> - PciExpressFeatureEntendedSetupPhase,
>
> -
>
> - //
>
> - // mandatory programming phase to complete the configuration of the PCI Express
>
> - // features
>
> - //
>
> - PciExpressFeatureProgramPhase,
>
> -
>
> - //
>
> - // optional phase to clean up temporary buffers, like those that were prepared
>
> - // during the preprocessing phase above
>
> - //
>
> - PciExpressFeatureEndPhase
>
> -
>
> -}PCI_EXPRESS_FEATURE_CONFIGURATION_PHASE;
>
> -
>
> -//
>
> -// declaration for the data type to harbor the PCI feature policies
>
> -//
>
> -struct _PCI_FEATURE_POLICY {
>
> - //
>
> - // if set, it indicates the feature should be enabled
>
> - // if clear, it indicates the feature should be disabled
>
> - //
>
> - UINT8 Act : 1;
>
> - //
>
> - // this field will be specific to feature, it can be implementation specific
>
> - // or it can be reserved and remain unused
>
> - //
>
> - UINT8 Support : 6;
>
> - //
>
> - // if set indicates override the feature policy defined by the members above
>
> - // if clear it indicates that this feature policy should be ignored completely
>
> - // this means the above two members should not be used
>
> - //
>
> - UINT8 Override : 1;
>
> -};
>
> -
>
> -//
>
> -// Declaration of the PCI Express features unique Id
>
> -//
>
> -typedef enum {
>
> - //
>
> - // support for PCI Express feature - Max. Payload Size
>
> - //
>
> - PciExpressMps,
>
> - //
>
> - // support for PCI Express feature - Max. Read Request Size
>
> - //
>
> - PciExpressMrrs,
>
> - //
>
> - // support for PCI Express feature - Extended Tag
>
> - //
>
> - PciExpressExtTag,
>
> - //
>
> - // support for PCI Express feature - Relax Order
>
> - //
>
> - PciExpressRelaxOrder,
>
> - //
>
> - // support for PCI Express feature - No-Snoop
>
> - //
>
> - PciExpressNoSnoop,
>
> - //
>
> - // support for PCI Express feature - ASPM state
>
> - //
>
> - PciExpressAspm,
>
> - //
>
> - // support for PCI Express feature - Common Clock Configuration
>
> - //
>
> - PciExpressCcc,
>
> - //
>
> - // support for PCI Express feature - Extended Sync
>
> - //
>
> - PciExpressExtSync,
>
> - //
>
> - // support for PCI Express feature - Atomic Op
>
> - //
>
> - PciExpressAtomicOp,
>
> - //
>
> - // support for PCI Express feature - LTR
>
> - //
>
> - PciExpressLtr,
>
> - //
>
> - // support for PCI Express feature - PTM
>
> - //
>
> - PciExpressPtm,
>
> - //
>
> - // support for PCI Express feature - Completion Timeout
>
> - //
>
> - PciExpressCto,
>
> - //
>
> - // support for PCI Express feature - Clock Power Management
>
> - //
>
> - PciExpressCpm,
>
> - //
>
> - // support for PCI Express feature - L1 PM Substates
>
> - //
>
> - PciExpressL1PmSubstates
>
> -
>
> -} PCI_EXPRESS_FEATURE_ID;
>
> -
>
> -//
>
> -// PCI Express feature configuration routine during initialization phases
>
> -//
>
> -typedef
>
> -EFI_STATUS
>
> -(*PCI_EXPRESS_FEATURE_CONFIGURATION_ROUTINE) (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN VOID *PciExpressFeatureConfiguration
>
> - );
>
> -
>
> -//
>
> -// data type for the PCI Express feature initialization phases
>
> -//
>
> -typedef struct {
>
> - //
>
> - // Pci Express feature configuration phase
>
> - //
>
> - PCI_EXPRESS_FEATURE_CONFIGURATION_PHASE PciExpressFeatureConfigurationPhase;
>
> - //
>
> - // PCI Express feature Id
>
> - //
>
> - PCI_EXPRESS_FEATURE_ID PciExpressFeatureId;
>
> - //
>
> - // PCI Express feature configuration routine
>
> - //
>
> - PCI_EXPRESS_FEATURE_CONFIGURATION_ROUTINE PciExpressFeatureConfigurationRoutine;
>
> -
>
> -}PCI_EXPRESS_FEATURE_INITIALIZATION_POINT;
>
> -
>
> -
>
> -
>
> -/**
>
> - Enumerate all the nodes of the specified root bridge or PCI-PCI Bridge, to
>
> - configure the other PCI features.
>
> -
>
> - @param RootBridge A pointer to the PCI_IO_DEVICE.
>
> -
>
> - @retval EFI_SUCCESS The other PCI features configuration during enumeration
>
> - of all the nodes of the PCI root bridge instance were
>
> - programmed in PCI-compliance pattern along with the
>
> - device-specific policy, as applicable.
>
> - @retval EFI_UNSUPPORTED One of the override operation maong the nodes of
>
> - the PCI hierarchy resulted in a incompatible address
>
> - range.
>
> - @retval EFI_INVALID_PARAMETER The override operation is performed with invalid input
>
> - parameters.
>
> -**/
>
> -EFI_STATUS
>
> -EnumeratePciExpressFeatures (
>
> - IN EFI_HANDLE Controller,
>
> - IN PCI_IO_DEVICE *RootBridge
>
> - );
>
> -
>
> -#endif
>
> diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c
> b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c
> deleted file mode 100644
> index bf380ab..0000000
> --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c
> +++ /dev/null
> @@ -1,902 +0,0 @@
> -/** @file
>
> - This file encapsulate the usage of PCI Platform Protocol
>
> -
>
> - This file define the necessary hooks used to obtain the platform
>
> - level data and policies which could be used in the PCI Enumeration phases
>
> -
>
> -Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
>
> -
>
> -**/
>
> -
>
> -#include "PciBus.h"
>
> -
>
> -
>
> -EFI_PCI_EXPRESS_PLATFORM_PROTOCOL *mPciExPlatformProtocol;
>
> -EFI_PCI_EXPRESS_OVERRIDE_PROTOCOL *mPciExOverrideProtocol;
>
> -
>
> -
>
> -/**
>
> - This function retrieves the PCI Express Platform Protocols published by platform
>
> - @retval EFI_STATUS direct return status from the LocateProtocol ()
>
> - boot service for the PCI Express Override Protocol
>
> - EFI_SUCCESS The PCI Express Platform Protocol is found
>
> -**/
>
> -EFI_STATUS
>
> -GetPciExpressProtocol (
>
> - )
>
> -{
>
> - EFI_STATUS Status;
>
> -
>
> - if (mPciExPlatformProtocol) {
>
> - //
>
> - // the PCI Express Platform Protocol is already initialized
>
> - //
>
> - return EFI_SUCCESS;
>
> - }
>
> - if (mPciExOverrideProtocol) {
>
> - //
>
> - // the PCI Express Override Protocol is already initialized
>
> - //
>
> - return EFI_SUCCESS;
>
> - }
>
> - //
>
> - // locate the PCI Express Platform Protocol
>
> - //
>
> - Status = gBS->LocateProtocol (
>
> - &gEfiPciExpressPlatformProtocolGuid,
>
> - NULL,
>
> - (VOID **) &mPciExPlatformProtocol
>
> - );
>
> - if (!EFI_ERROR (Status)) {
>
> - return Status;
>
> - }
>
> - //
>
> - // If PCI Express Platform protocol doesn't exist, try to get the Pci Express
>
> - // Override Protocol.
>
> - //
>
> - return gBS->LocateProtocol (
>
> - &gEfiPciExpressOverrideProtocolGuid,
>
> - NULL,
>
> - (VOID **) &mPciExOverrideProtocol
>
> - );
>
> -}
>
> -
>
> -/**
>
> - This function indicates that the platform has published the PCI Express Platform
>
> - Protocol (or PCI Express Override Protocol) to indicate that this driver can
>
> - initialize the PCI Express features.
>
> - @retval TRUE or FALSE
>
> -**/
>
> -BOOLEAN
>
> -IsPciExpressProtocolPresent (
>
> - )
>
> -{
>
> - if (
>
> - mPciExPlatformProtocol == NULL
>
> - && mPciExOverrideProtocol == NULL
>
> - ) {
>
> - return FALSE;
>
> - }
>
> - return TRUE;
>
> -}
>
> -
>
> -/**
>
> - Routine to translate the given device-specific platform policy from type
>
> - EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE to HW-specific value, as per PCI Base Specification
>
> - Revision 4.0; for the PCI feature Max_Payload_Size.
>
> -
>
> - @param MPS Input device-specific policy should be in terms of type
>
> - EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE
>
> -
>
> - @retval Range values for the Max_Payload_Size as defined in the PCI
>
> - Base Specification 4.0
>
> -**/
>
> -UINT8
>
> -SetDevicePolicyPciExpressMps (
>
> - IN UINT8 MPS
>
> -)
>
> -{
>
> - switch (MPS) {
>
> - case EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_128B:
>
> - return PCIE_MAX_PAYLOAD_SIZE_128B;
>
> - case EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_256B:
>
> - return PCIE_MAX_PAYLOAD_SIZE_256B;
>
> - case EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_512B:
>
> - return PCIE_MAX_PAYLOAD_SIZE_512B;
>
> - case EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_1024B:
>
> - return PCIE_MAX_PAYLOAD_SIZE_1024B;
>
> - case EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_2048B:
>
> - return PCIE_MAX_PAYLOAD_SIZE_2048B;
>
> - case EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_4096B:
>
> - return PCIE_MAX_PAYLOAD_SIZE_4096B;
>
> - default:
>
> - return PCIE_MAX_PAYLOAD_SIZE_128B;
>
> - }
>
> -}
>
> -
>
> -/**
>
> - Routine to translate the given device-specific platform policy from type
>
> - EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE to HW-specific value, as per PCI Base Specification
>
> - Revision 4.0; for the PCI feature Max_Read_Req_Size.
>
> -
>
> - @param MRRS Input device-specific policy should be in terms of type
>
> - EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE
>
> -
>
> - @retval Range values for the Max_Read_Req_Size as defined in the PCI
>
> - Base Specification 4.0
>
> -**/
>
> -UINT8
>
> -SetDevicePolicyPciExpressMrrs (
>
> - IN UINT8 MRRS
>
> -)
>
> -{
>
> - switch (MRRS) {
>
> - case EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_128B:
>
> - return PCIE_MAX_READ_REQ_SIZE_128B;
>
> - case EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_256B:
>
> - return PCIE_MAX_READ_REQ_SIZE_256B;
>
> - case EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_512B:
>
> - return PCIE_MAX_READ_REQ_SIZE_512B;
>
> - case EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_1024B:
>
> - return PCIE_MAX_READ_REQ_SIZE_1024B;
>
> - case EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_2048B:
>
> - return PCIE_MAX_READ_REQ_SIZE_2048B;
>
> - case EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_4096B:
>
> - return PCIE_MAX_READ_REQ_SIZE_4096B;
>
> - default:
>
> - return PCIE_MAX_READ_REQ_SIZE_128B;
>
> - }
>
> -}
>
> -
>
> -/**
>
> - Routine to set the device-specific policy for the PCI feature Relax Ordering
>
> -
>
> - @param RelaxOrder value corresponding to data type EFI_PCI_EXPRESS_RELAX_ORDER
>
> - @param PciDevice A pointer to PCI_IO_DEVICE
>
> -**/
>
> -VOID
>
> -SetDevicePolicyPciExpressRo (
>
> - IN EFI_PCI_EXPRESS_RELAX_ORDER RelaxOrder,
>
> - OUT PCI_IO_DEVICE *PciDevice
>
> - )
>
> -{
>
> - //
>
> - // implementation specific rules for the usage of PCI_FEATURE_POLICY members
>
> - // exclusively for the PCI Feature Relax Ordering (RO)
>
> - //
>
> - // .Override = 0 to skip this PCI feature RO for the PCI device
>
> - // .Override = 1 to program this RO PCI feature
>
> - // .Act = 1 to enable the RO in the PCI device
>
> - // .Act = 0 to disable the RO in the PCI device
>
> - //
>
> - switch (RelaxOrder) {
>
> - case EFI_PCI_EXPRESS_RO_AUTO:
>
> - PciDevice->SetupRO.Override = 0;
>
> - break;
>
> - case EFI_PCI_EXPRESS_RO_DISABLE:
>
> - PciDevice->SetupRO.Override = 1;
>
> - PciDevice->SetupRO.Act = 0;
>
> - break;
>
> - case EFI_PCI_EXPRESS_RO_ENABLE:
>
> - PciDevice->SetupRO.Override = 1;
>
> - PciDevice->SetupRO.Act = 1;
>
> - break;
>
> - default:
>
> - PciDevice->SetupRO.Override = 0;
>
> - break;
>
> - }
>
> -}
>
> -
>
> -/**
>
> - Routine to set the device-specific policy for the PCI feature No-Snoop enable
>
> - or disable
>
> -
>
> - @param NoSnoop value corresponding to data type EFI_PCI_EXPRESS_NO_SNOOP
>
> - @param PciDevice A pointer to PCI_IO_DEVICE
>
> -**/
>
> -VOID
>
> -SetDevicePolicyPciExpressNs (
>
> - IN EFI_PCI_EXPRESS_NO_SNOOP NoSnoop,
>
> - OUT PCI_IO_DEVICE *PciDevice
>
> - )
>
> -{
>
> - //
>
> - // implementation specific rules for the usage of PCI_FEATURE_POLICY members
>
> - // exclusively for the PCI Feature No-Snoop
>
> - //
>
> - // .Override = 0 to skip this PCI feature No-Snoop for the PCI device
>
> - // .Override = 1 to program this No-Snoop PCI feature
>
> - // .Act = 1 to enable the No-Snoop in the PCI device
>
> - // .Act = 0 to disable the No-Snoop in the PCI device
>
> - //
>
> - switch (NoSnoop) {
>
> - case EFI_PCI_EXPRESS_NS_AUTO:
>
> - PciDevice->SetupNS.Override = 0;
>
> - break;
>
> - case EFI_PCI_EXPRESS_NS_DISABLE:
>
> - PciDevice->SetupNS.Override = 1;
>
> - PciDevice->SetupNS.Act = 0;
>
> - break;
>
> - case EFI_PCI_EXPRESS_NS_ENABLE:
>
> - PciDevice->SetupNS.Override = 1;
>
> - PciDevice->SetupNS.Act = 1;
>
> - break;
>
> - default:
>
> - PciDevice->SetupNS.Override = 0;
>
> - break;
>
> - }
>
> -}
>
> -
>
> -/**
>
> - Routine to set the device-specific policy for the PCI feature CTO value range
>
> - or disable
>
> -
>
> - @param CtoSupport value corresponding to data type EFI_PCI_EXPRESS_CTO_SUPPORT
>
> - @param PciDevice A pointer to PCI_IO_DEVICE
>
> -**/
>
> -VOID
>
> -SetDevicePolicyPciExpressCto (
>
> - IN EFI_PCI_EXPRESS_CTO_SUPPORT CtoSupport,
>
> - OUT PCI_IO_DEVICE *PciDevice
>
> -)
>
> -{
>
> - //
>
> - // implementation specific rules for the usage of PCI_FEATURE_POLICY members
>
> - // exclusively for the PCI Feature CTO
>
> - //
>
> - // .Override = 0 to skip this PCI feature CTO for the PCI device
>
> - // .Override = 1 to program this CTO PCI feature
>
> - // .Act = 1 to program the CTO range as per given device policy in .Support
>
> - // .Act = 0 to disable the CTO mechanism in the PCI device, CTO set to default range
>
> - //
>
> - switch (CtoSupport) {
>
> - case EFI_PCI_EXPRESS_CTO_AUTO:
>
> - PciDevice->SetupCTO.Override = 0;
>
> - break;
>
> - case EFI_PCI_EXPRESS_CTO_DEFAULT:
>
> - PciDevice->SetupCTO.Override = 1;
>
> - PciDevice->SetupCTO.Act = 1;
>
> - PciDevice->SetupCTO.Support = PCIE_COMPLETION_TIMEOUT_50US_50MS;
>
> - break;
>
> - case EFI_PCI_EXPRESS_CTO_RANGE_A1:
>
> - PciDevice->SetupCTO.Override = 1;
>
> - PciDevice->SetupCTO.Act = 1;
>
> - PciDevice->SetupCTO.Support = PCIE_COMPLETION_TIMEOUT_50US_100US;
>
> - break;
>
> - case EFI_PCI_EXPRESS_CTO_RANGE_A2:
>
> - PciDevice->SetupCTO.Override = 1;
>
> - PciDevice->SetupCTO.Act = 1;
>
> - PciDevice->SetupCTO.Support = PCIE_COMPLETION_TIMEOUT_1MS_10MS;
>
> - break;
>
> - case EFI_PCI_EXPRESS_CTO_RANGE_B1:
>
> - PciDevice->SetupCTO.Override = 1;
>
> - PciDevice->SetupCTO.Act = 1;
>
> - PciDevice->SetupCTO.Support = PCIE_COMPLETION_TIMEOUT_16MS_55MS;
>
> - break;
>
> - case EFI_PCI_EXPRESS_CTO_RANGE_B2:
>
> - PciDevice->SetupCTO.Override = 1;
>
> - PciDevice->SetupCTO.Act = 1;
>
> - PciDevice->SetupCTO.Support = PCIE_COMPLETION_TIMEOUT_65MS_210MS;
>
> - break;
>
> - case EFI_PCI_EXPRESS_CTO_RANGE_C1:
>
> - PciDevice->SetupCTO.Override = 1;
>
> - PciDevice->SetupCTO.Act = 1;
>
> - PciDevice->SetupCTO.Support = PCIE_COMPLETION_TIMEOUT_260MS_900MS;
>
> - break;
>
> - case EFI_PCI_EXPRESS_CTO_RANGE_C2:
>
> - PciDevice->SetupCTO.Override = 1;
>
> - PciDevice->SetupCTO.Act = 1;
>
> - PciDevice->SetupCTO.Support = PCIE_COMPLETION_TIMEOUT_1S_3_5S;
>
> - break;
>
> - case EFI_PCI_EXPRESS_CTO_RANGE_D1:
>
> - PciDevice->SetupCTO.Override = 1;
>
> - PciDevice->SetupCTO.Act = 1;
>
> - PciDevice->SetupCTO.Support = PCIE_COMPLETION_TIMEOUT_4S_13S;
>
> - break;
>
> - case EFI_PCI_EXPRESS_CTO_RANGE_D2:
>
> - PciDevice->SetupCTO.Override = 1;
>
> - PciDevice->SetupCTO.Act = 1;
>
> - PciDevice->SetupCTO.Support = PCIE_COMPLETION_TIMEOUT_17S_64S;
>
> - break;
>
> - case EFI_PCI_EXPRESS_CTO_DET_DISABLE:
>
> - PciDevice->SetupCTO.Override = 1;
>
> - PciDevice->SetupCTO.Act = 0;
>
> - PciDevice->SetupCTO.Support = PCIE_COMPLETION_TIMEOUT_50US_50MS;
>
> - break;
>
> - }
>
> -}
>
> -
>
> -/**
>
> - Routine to set the device-specific policy for the PCI feature LTR enable/disable
>
> -
>
> - @param AtomicOp value corresponding to data type EFI_PCI_EXPRESS_ATOMIC_OP
>
> - @param PciDevice A pointer to PCI_IO_DEVICE
>
> -
>
> -**/
>
> -VOID
>
> -SetDevicePolicyPciExpressLtr (
>
> - IN EFI_PCI_EXPRESS_LTR Ltr,
>
> - OUT PCI_IO_DEVICE *PciDevice
>
> - )
>
> -{
>
> - switch (Ltr){
>
> - case EFI_PCI_EXPRESS_LTR_AUTO:
>
> - case EFI_PCI_EXPRESS_LTR_DISABLE:
>
> - //
>
> - // leave the LTR mechanism disable or restore to its default state
>
> - //
>
> - PciDevice->SetupLtr = FALSE;
>
> - break;
>
> - case EFI_PCI_EXPRESS_LTR_ENABLE:
>
> - //
>
> - // LTR mechanism enable
>
> - //
>
> - PciDevice->SetupLtr = TRUE;
>
> - break;
>
> - }
>
> -}
>
> -
>
> -/**
>
> - Generic routine to setup the PCI features as per its predetermined defaults.
>
> -**/
>
> -VOID
>
> -SetupDefaultPciExpressDevicePolicy (
>
> - IN PCI_IO_DEVICE *PciDevice
>
> - )
>
> -{
>
> -
>
> - if (mPciExpressPlatformPolicy.Mps) {
>
> - PciDevice->SetupMPS = EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_AUTO;
>
> - } else {
>
> - PciDevice->SetupMPS = EFI_PCI_EXPRESS_NOT_APPLICABLE;
>
> - }
>
> -
>
> - if (mPciExpressPlatformPolicy.Mrrs) {
>
> - PciDevice->SetupMRRS = EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_AUTO;
>
> - } else {
>
> - PciDevice->SetupMRRS = EFI_PCI_EXPRESS_NOT_APPLICABLE;
>
> - }
>
> -
>
> - PciDevice->SetupRO.Override = 0;
>
> -
>
> - PciDevice->SetupNS.Override = 0;
>
> -
>
> - PciDevice->SetupCTO.Override = 0;
>
> -
>
> - PciDevice->SetupAtomicOp.Override = 0;
>
> -
>
> - PciDevice->SetupLtr = FALSE;
>
> -
>
> - if (mPciExpressPlatformPolicy.ExtTag) {
>
> - PciDevice->SetupExtTag = EFI_PCI_EXPRESS_EXTENDED_TAG_AUTO;
>
> - } else {
>
> - PciDevice->SetupExtTag = EFI_PCI_EXPRESS_NOT_APPLICABLE;
>
> - }
>
> -
>
> - //
>
> - // default device policy for device's link ASPM
>
> - //
>
> - if (mPciExpressPlatformPolicy.Aspm) {
>
> - PciDevice->SetupAspm = EFI_PCI_EXPRESS_ASPM_AUTO;
>
> - } else {
>
> - PciDevice->SetupAspm = EFI_PCI_EXPRESS_NOT_APPLICABLE;
>
> - }
>
> -
>
> - //
>
> - // default device policy for the device's link clock configuration
>
> - //
>
> - if (mPciExpressPlatformPolicy.Ccc) {
>
> - PciDevice->SetupCcc = EFI_PCI_EXPRESS_CLK_CFG_AUTO;
>
> - } else {
>
> - PciDevice->SetupCcc = EFI_PCI_EXPRESS_NOT_APPLICABLE;
>
> - }
>
> -
>
> -}
>
> -
>
> -/**
>
> - initialize the device policy data members
>
> -**/
>
> -VOID
>
> -InitializeDevicePolicyData (
>
> - IN EFI_PCI_EXPRESS_DEVICE_POLICY *PciExpressDevicePolicy
>
> - )
>
> -{
>
> - UINTN length;
>
> - UINT8 *PciExpressPolicy;
>
> - UINT8 *PciExDevicePolicy;
>
> -
>
> -
>
> - ZeroMem (PciExpressDevicePolicy, sizeof (EFI_PCI_EXPRESS_DEVICE_POLICY));
>
> -
>
> - for (
>
> - length = 0
>
> - , PciExpressPolicy = (UINT8*)&mPciExpressPlatformPolicy
>
> - , PciExDevicePolicy = (UINT8*)PciExpressDevicePolicy
>
> - ; length < sizeof (EFI_PCI_EXPRESS_PLATFORM_POLICY)
>
> - ; length++
>
> - ) {
>
> - if (!PciExpressPolicy[length]) {
>
> - PciExDevicePolicy[length] = EFI_PCI_EXPRESS_NOT_APPLICABLE;
>
> - }
>
> - }
>
> -}
>
> -
>
> -/**
>
> - Intermediate routine to either get the PCI device specific platform policies
>
> - through the PCI Platform Protocol, or its alias the PCI Override Protocol.
>
> -
>
> - @param PciDevice A pointer to PCI_IO_DEVICE
>
> - @param PciPlatformProtocol A pointer to EFI_PCI_EXPRESS_PLATFORM_PROTOCOL
>
> -
>
> - @retval EFI_STATUS The direct status from the PCI Platform Protocol
>
> - @retval EFI_SUCCESS if on returning predetermined PCI features defaults,
>
> - for the case when protocol returns as EFI_UNSUPPORTED
>
> - to indicate PCI device exist and it has no platform
>
> - policy defined.
>
> -**/
>
> -EFI_STATUS
>
> -GetPciExpressDevicePolicy (
>
> - IN PCI_IO_DEVICE *PciDevice,
>
> - IN EFI_PCI_EXPRESS_PLATFORM_PROTOCOL *PciPlatformProtocol
>
> - )
>
> -{
>
> - EFI_PCI_EXPRESS_DEVICE_POLICY PciExpressDevicePolicy;
>
> - EFI_STATUS Status;
>
> - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress;
>
> -
>
> - PciAddress.Bus = PciDevice->BusNumber;
>
> - PciAddress.Device = PciDevice->DeviceNumber;
>
> - PciAddress.Function = PciDevice->FunctionNumber;
>
> - PciAddress.Register = 0;
>
> - PciAddress.ExtendedRegister = 0;
>
> -
>
> - InitializeDevicePolicyData (&PciExpressDevicePolicy);
>
> - Status = PciPlatformProtocol->GetDevicePolicy (
>
> - PciPlatformProtocol,
>
> - mRootBridgeHandle,
>
> - PciAddress,
>
> - sizeof (EFI_PCI_EXPRESS_DEVICE_POLICY),
>
> - &PciExpressDevicePolicy
>
> - );
>
> - if (!EFI_ERROR(Status)) {
>
> - //
>
> - // platform chipset policies are returned for this PCI device
>
> - //
>
> -
>
> - //
>
> - // set device specific policy for the Max_Payload_Size
>
> - //
>
> - if (mPciExpressPlatformPolicy.Mps) {
>
> - PciDevice->SetupMPS = PciExpressDevicePolicy.DeviceCtlMPS;
>
> - } else {
>
> - PciDevice->SetupMPS = EFI_PCI_EXPRESS_NOT_APPLICABLE;
>
> - }
>
> -
>
> - //
>
> - // set device specific policy for Max_Read_Req_Size
>
> - //
>
> - if (mPciExpressPlatformPolicy.Mrrs) {
>
> - PciDevice->SetupMRRS = PciExpressDevicePolicy.DeviceCtlMRRS;
>
> - } else {
>
> - PciDevice->SetupMRRS = EFI_PCI_EXPRESS_NOT_APPLICABLE;
>
> - }
>
> - //
>
> - // set device specific policy for Relax Ordering
>
> - //
>
> - if (mPciExpressPlatformPolicy.RelaxOrder) {
>
> - SetDevicePolicyPciExpressRo (PciExpressDevicePolicy.DeviceCtlRelaxOrder, PciDevice);
>
> - } else {
>
> - PciDevice->SetupRO.Override = 0;
>
> - }
>
> -
>
> - //
>
> - // set the device specific policy for No-Snoop
>
> - //
>
> - if (mPciExpressPlatformPolicy.NoSnoop) {
>
> - SetDevicePolicyPciExpressNs (PciExpressDevicePolicy.DeviceCtlNoSnoop, PciDevice);
>
> - } else {
>
> - PciDevice->SetupNS.Override = 0;
>
> - }
>
> -
>
> - //
>
> - // set the device specific policy for Completion Timeout (CTO)
>
> - //
>
> - if (mPciExpressPlatformPolicy.Cto) {
>
> - SetDevicePolicyPciExpressCto (PciExpressDevicePolicy.CTOsupport, PciDevice);
>
> - } else {
>
> - PciDevice->SetupCTO.Override = 0;
>
> - }
>
> -
>
> - //
>
> - // set the device-specific policy for AtomicOp
>
> - //
>
> - if (mPciExpressPlatformPolicy.AtomicOp) {
>
> - PciDevice->SetupAtomicOp = PciExpressDevicePolicy.DeviceCtl2AtomicOp;
>
> - } else {
>
> - PciDevice->SetupAtomicOp.Override = 0;
>
> - }
>
> -
>
> - //
>
> - // set the device-specific policy for LTR mechanism in the function
>
> - //
>
> - if (mPciExpressPlatformPolicy.Ltr) {
>
> - SetDevicePolicyPciExpressLtr (PciExpressDevicePolicy.DeviceCtl2LTR, PciDevice);
>
> - } else {
>
> - PciDevice->SetupLtr = FALSE;
>
> - }
>
> -
>
> - //
>
> - // set the device-specifci policy for the PCI Express feature Extended Tag
>
> - //
>
> - if (mPciExpressPlatformPolicy.ExtTag) {
>
> - PciDevice->SetupExtTag = PciExpressDevicePolicy.DeviceCtlExtTag;
>
> - } else {
>
> - PciDevice->SetupExtTag = EFI_PCI_EXPRESS_NOT_APPLICABLE;
>
> - }
>
> -
>
> - //
>
> - // set the device-specific policy for the PCI Express feature ASPM
>
> - //
>
> - if (mPciExpressPlatformPolicy.Aspm) {
>
> - PciDevice->SetupAspm = PciExpressDevicePolicy.LinkCtlASPMState;
>
> - } else {
>
> - PciDevice->SetupAspm = EFI_PCI_EXPRESS_NOT_APPLICABLE;
>
> - }
>
> -
>
> - //
>
> - // set the device policy for the PCI Express feature Common Clock Configuration
>
> - //
>
> - if (mPciExpressPlatformPolicy.Ccc) {
>
> - PciDevice->SetupCcc = PciExpressDevicePolicy.LinkCtlCommonClkCfg;
>
> - } else {
>
> - PciDevice->SetupCcc = EFI_PCI_EXPRESS_NOT_APPLICABLE;
>
> - }
>
> -
>
> - DEBUG ((
>
> - DEBUG_INFO,
>
> - "[device policy: platform]"
>
> - ));
>
> - return Status;
>
> - } else if (Status == EFI_UNSUPPORTED) {
>
> - //
>
> - // platform chipset policies are not provided for this PCI device
>
> - // let the enumeration happen as per the PCI standard way
>
> - //
>
> - SetupDefaultPciExpressDevicePolicy (PciDevice);
>
> - DEBUG ((
>
> - DEBUG_INFO,
>
> - "[device policy: default]"
>
> - ));
>
> - return EFI_SUCCESS;
>
> - }
>
> - DEBUG ((
>
> - DEBUG_ERROR,
>
> - "[device policy: none (error)]"
>
> - ));
>
> - return Status;
>
> -}
>
> -
>
> -/**
>
> - Gets the PCI device-specific platform policy from the PCI Express Platform Protocol.
>
> - If no PCI Platform protocol is published than setup the PCI feature to predetermined
>
> - defaults, in order to align all the PCI devices in the PCI hierarchy, as applicable.
>
> -
>
> - @param PciDevice A pointer to PCI_IO_DEVICE
>
> -
>
> - @retval EFI_STATUS The direct status from the PCI Platform Protocol
>
> - @retval EFI_SUCCESS On return of predetermined PCI features defaults, for
>
> - the case when protocol returns as EFI_UNSUPPORTED to
>
> - indicate PCI device exist and it has no platform policy
>
> - defined. Also, on returns when no PCI Platform Protocol
>
> - exist.
>
> -**/
>
> -EFI_STATUS
>
> -PciExpressPlatformGetDevicePolicy (
>
> - IN PCI_IO_DEVICE *PciDevice
>
> - )
>
> -{
>
> - if (mPciExPlatformProtocol != NULL) {
>
> - return GetPciExpressDevicePolicy (PciDevice, mPciExPlatformProtocol);
>
> - } else if (mPciExOverrideProtocol != NULL) {
>
> - return GetPciExpressDevicePolicy (PciDevice, mPciExOverrideProtocol);
>
> - } else {
>
> - //
>
> - // no protocol found, platform does not require the PCI Express initialization
>
> - //
>
> - return EFI_UNSUPPORTED;
>
> - }
>
> -}
>
> -
>
> -/**
>
> - This function gets the platform requirement to initialize the list of PCI Express
>
> - features from the protocol definition supported.
>
> - This function should be called after the LocatePciPlatformProtocol.
>
> - @retval EFI_SUCCESS return by platform to acknowledge the list of
>
> - PCI Express feature to be configured
>
> - (in mPciExpressPlatformPolicy)
>
> - EFI_INVALID_PARAMETER platform does not support the protocol arguements
>
> - passed
>
> - EFI_UNSUPPORTED platform did not published the protocol
>
> -**/
>
> -EFI_STATUS
>
> -PciExpressPlatformGetPolicy (
>
> - )
>
> -{
>
> - EFI_STATUS Status;
>
> -
>
> - if (mPciExPlatformProtocol) {
>
> - Status = mPciExPlatformProtocol->GetPolicy (
>
> - mPciExPlatformProtocol,
>
> - sizeof (EFI_PCI_EXPRESS_PLATFORM_POLICY),
>
> - &mPciExpressPlatformPolicy
>
> - );
>
> - } else if (mPciExOverrideProtocol) {
>
> - Status = mPciExOverrideProtocol->GetPolicy (
>
> - mPciExOverrideProtocol,
>
> - sizeof (EFI_PCI_EXPRESS_PLATFORM_POLICY),
>
> - &mPciExpressPlatformPolicy
>
> - );
>
> - } else {
>
> - //
>
> - // no protocol found, platform does not require the PCI Express initialization
>
> - //
>
> - return EFI_UNSUPPORTED;
>
> - }
>
> - return Status;
>
> -}
>
> -
>
> -EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE
>
> -GetPciExpressMps (
>
> - IN UINT8 Mps
>
> - )
>
> -{
>
> - switch (Mps) {
>
> - case PCIE_MAX_PAYLOAD_SIZE_128B:
>
> - return EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_128B;
>
> - case PCIE_MAX_PAYLOAD_SIZE_256B:
>
> - return EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_256B;
>
> - case PCIE_MAX_PAYLOAD_SIZE_512B:
>
> - return EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_512B;
>
> - case PCIE_MAX_PAYLOAD_SIZE_1024B:
>
> - return EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_1024B;
>
> - case PCIE_MAX_PAYLOAD_SIZE_2048B:
>
> - return EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_2048B;
>
> - case PCIE_MAX_PAYLOAD_SIZE_4096B:
>
> - return EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_4096B;
>
> - }
>
> - return EFI_PCI_EXPRESS_NOT_APPLICABLE;
>
> -}
>
> -
>
> -EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE
>
> -GetPciExpressMrrs (
>
> - IN UINT8 Mrrs
>
> - )
>
> -{
>
> - switch (Mrrs) {
>
> - case PCIE_MAX_READ_REQ_SIZE_128B:
>
> - return EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_128B;
>
> - case PCIE_MAX_READ_REQ_SIZE_256B:
>
> - return EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_256B;
>
> - case PCIE_MAX_READ_REQ_SIZE_512B:
>
> - return EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_512B;
>
> - case PCIE_MAX_READ_REQ_SIZE_1024B:
>
> - return EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_1024B;
>
> - case PCIE_MAX_READ_REQ_SIZE_2048B:
>
> - return EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_2048B;
>
> - case PCIE_MAX_READ_REQ_SIZE_4096B:
>
> - return EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_4096B;
>
> - }
>
> - return EFI_PCI_EXPRESS_NOT_APPLICABLE;
>
> -}
>
> -
>
> -EFI_PCI_EXPRESS_CTO_SUPPORT
>
> -GetPciExpressCto (
>
> - IN UINT8 Cto
>
> - )
>
> -{
>
> - switch (Cto) {
>
> - case PCIE_COMPLETION_TIMEOUT_50US_50MS:
>
> - return EFI_PCI_EXPRESS_CTO_DEFAULT;
>
> - case PCIE_COMPLETION_TIMEOUT_50US_100US:
>
> - return EFI_PCI_EXPRESS_CTO_RANGE_A1;
>
> - case PCIE_COMPLETION_TIMEOUT_1MS_10MS:
>
> - return EFI_PCI_EXPRESS_CTO_RANGE_A2;
>
> - case PCIE_COMPLETION_TIMEOUT_16MS_55MS:
>
> - return EFI_PCI_EXPRESS_CTO_RANGE_B1;
>
> - case PCIE_COMPLETION_TIMEOUT_65MS_210MS:
>
> - return EFI_PCI_EXPRESS_CTO_RANGE_B2;
>
> - case PCIE_COMPLETION_TIMEOUT_260MS_900MS:
>
> - return EFI_PCI_EXPRESS_CTO_RANGE_C1;
>
> - case PCIE_COMPLETION_TIMEOUT_1S_3_5S:
>
> - return EFI_PCI_EXPRESS_CTO_RANGE_C2;
>
> - case PCIE_COMPLETION_TIMEOUT_4S_13S:
>
> - return EFI_PCI_EXPRESS_CTO_RANGE_D1;
>
> - case PCIE_COMPLETION_TIMEOUT_17S_64S:
>
> - return EFI_PCI_EXPRESS_CTO_RANGE_D2;
>
> - }
>
> - return EFI_PCI_EXPRESS_NOT_APPLICABLE;
>
> -}
>
> -
>
> -EFI_PCI_EXPRESS_EXTENDED_TAG
>
> -GetPciExpressExtTag (
>
> - IN PCI_IO_DEVICE *PciDevice
>
> - )
>
> -{
>
> - if (PciDevice->PciExpressCapabilityStructure.DeviceControl2.Bits.TenBitTagRequesterEnable) {
>
> - return EFI_PCI_EXPRESS_EXTENDED_TAG_10BIT;
>
> - } else if (PciDevice->PciExpressCapabilityStructure.DeviceControl.Bits.ExtendedTagField) {
>
> - return EFI_PCI_EXPRESS_EXTENDED_TAG_8BIT;
>
> - } else {
>
> - return EFI_PCI_EXPRESS_EXTENDED_TAG_5BIT;
>
> - }
>
> -}
>
> -
>
> -EFI_PCI_EXPRESS_ASPM_SUPPORT
>
> -GetPciExpressAspmState (
>
> - IN PCI_IO_DEVICE *PciDevice
>
> - )
>
> -{
>
> - switch (PciDevice->PciExpressCapabilityStructure.LinkControl.Bits.AspmControl) {
>
> - case 0:
>
> - return EFI_PCI_EXPRESS_ASPM_DISABLE;
>
> - case 1:
>
> - return EFI_PCI_EXPRESS_ASPM_L0s_SUPPORT;
>
> - case 2:
>
> - return EFI_PCI_EXPRESS_ASPM_L1_SUPPORT;
>
> - case 3:
>
> - return EFI_PCI_EXPRESS_ASPM_L0S_L1_SUPPORT;
>
> - }
>
> - return EFI_PCI_EXPRESS_NOT_APPLICABLE;
>
> -}
>
> -
>
> -/**
>
> - Notifies the platform about the current PCI Express state of the device.
>
> -
>
> - @param PciDevice A pointer to PCI_IO_DEVICE
>
> - @param PciExDeviceConfiguration Pointer to EFI_PCI_EXPRESS_DEVICE_CONFIGURATION.
>
> - Used to pass the current state of device to
>
> - platform.
>
> -
>
> - @retval EFI_STATUS The direct status from the PCI Express Platform Protocol
>
> - @retval EFI_UNSUPPORTED returns when the PCI Express Platform Protocol or its
>
> - alias PCI Express OVerride Protocol is not present.
>
> -**/
>
> -EFI_STATUS
>
> -PciExpressPlatformNotifyDeviceState (
>
> - IN PCI_IO_DEVICE *PciDevice
>
> - )
>
> -{
>
> - EFI_PCI_EXPRESS_DEVICE_CONFIGURATION PciExDeviceConfiguration;
>
> -
>
> - //
>
> - // get the device-specific state for the PCIe Max_Payload_Size feature
>
> - //
>
> - if (mPciExpressPlatformPolicy.Mps) {
>
> - PciExDeviceConfiguration.DeviceCtlMPS = GetPciExpressMps (
>
> - (UINT8)PciDevice->PciExpressCapabilityStructure.DeviceControl.Bits.MaxPayloadSize
>
> - );
>
> - } else {
>
> - PciExDeviceConfiguration.DeviceCtlMPS = EFI_PCI_EXPRESS_NOT_APPLICABLE;
>
> - }
>
> -
>
> - //
>
> - // get the device-specific state for the PCIe Max_Read_Req_Size feature
>
> - //
>
> - if (mPciExpressPlatformPolicy.Mrrs) {
>
> - PciExDeviceConfiguration.DeviceCtlMRRS = GetPciExpressMrrs (
>
> - (UINT8)PciDevice->PciExpressCapabilityStructure.DeviceControl.Bits.MaxReadRequestSize
>
> - );
>
> - } else {
>
> - PciExDeviceConfiguration.DeviceCtlMRRS = EFI_PCI_EXPRESS_NOT_APPLICABLE;
>
> - }
>
> - //
>
> - // get the device-specific state for the PCIe Relax Order feature
>
> - //
>
> - if (mPciExpressPlatformPolicy.RelaxOrder) {
>
> - PciExDeviceConfiguration.DeviceCtlRelaxOrder = PciDevice-
> >PciExpressCapabilityStructure.DeviceControl.Bits.RelaxedOrdering
>
> - ? EFI_PCI_EXPRESS_RO_ENABLE
>
> - : EFI_PCI_EXPRESS_RO_DISABLE;
>
> - } else {
>
> - PciExDeviceConfiguration.DeviceCtlRelaxOrder = EFI_PCI_EXPRESS_NOT_APPLICABLE;
>
> - }
>
> -
>
> - //
>
> - // get the device-specific state for the PCIe NoSnoop feature
>
> - //
>
> - if (mPciExpressPlatformPolicy.NoSnoop) {
>
> - PciExDeviceConfiguration.DeviceCtlNoSnoop = PciDevice->PciExpressCapabilityStructure.DeviceControl.Bits.NoSnoop
>
> - ? EFI_PCI_EXPRESS_NS_ENABLE
>
> - : EFI_PCI_EXPRESS_NS_DISABLE;
>
> - } else {
>
> - PciExDeviceConfiguration.DeviceCtlNoSnoop = EFI_PCI_EXPRESS_NOT_APPLICABLE;
>
> - }
>
> -
>
> - //
>
> - // get the device-specific state for the PCIe CTO feature
>
> - //
>
> - if (mPciExpressPlatformPolicy.Cto) {
>
> - PciExDeviceConfiguration.CTOsupport = PciDevice-
> >PciExpressCapabilityStructure.DeviceControl2.Bits.CompletionTimeoutDisable
>
> - ? EFI_PCI_EXPRESS_CTO_DET_DISABLE
>
> - : GetPciExpressCto (
>
> - (UINT8)PciDevice->PciExpressCapabilityStructure.DeviceControl2.Bits.CompletionTimeoutValue
>
> - );
>
> - } else {
>
> - PciExDeviceConfiguration.CTOsupport = EFI_PCI_EXPRESS_NOT_APPLICABLE;
>
> - }
>
> -
>
> - //
>
> - // get the device-specific state for the PCIe AtomicOp feature
>
> - //
>
> - if (mPciExpressPlatformPolicy.AtomicOp) {
>
> - PciExDeviceConfiguration.DeviceCtl2AtomicOp.Enable_AtomicOpRequester
>
> - = (UINT8)PciDevice->PciExpressCapabilityStructure.DeviceControl2.Bits.AtomicOpRequester;
>
> - PciExDeviceConfiguration.DeviceCtl2AtomicOp.Enable_AtomicOpEgressBlocking
>
> - = (UINT8)PciDevice->PciExpressCapabilityStructure.DeviceControl2.Bits.AtomicOpEgressBlocking;
>
> - } else {
>
> - PciExDeviceConfiguration.DeviceCtl2AtomicOp.Override = 0;
>
> - PciExDeviceConfiguration.DeviceCtl2AtomicOp.Enable_AtomicOpRequester = 0;
>
> - PciExDeviceConfiguration.DeviceCtl2AtomicOp.Enable_AtomicOpEgressBlocking = 0;
>
> - }
>
> - //
>
> - // get the device-specific state for LTR mechanism in the function
>
> - //
>
> - if (mPciExpressPlatformPolicy.Ltr) {
>
> - PciExDeviceConfiguration.DeviceCtl2LTR = PciDevice->PciExpressCapabilityStructure.DeviceControl2.Bits.LtrMechanism
>
> - ? EFI_PCI_EXPRESS_LTR_ENABLE
>
> - : EFI_PCI_EXPRESS_LTR_DISABLE;
>
> - } else {
>
> - PciExDeviceConfiguration.DeviceCtl2LTR = EFI_PCI_EXPRESS_NOT_APPLICABLE;
>
> - }
>
> -
>
> - //
>
> - // get the device-specific state for the PCie Extended Tag in the function
>
> - //
>
> - if (mPciExpressPlatformPolicy.ExtTag) {
>
> - PciExDeviceConfiguration.DeviceCtlExtTag = GetPciExpressExtTag (PciDevice);
>
> - } else {
>
> - PciExDeviceConfiguration.DeviceCtlExtTag = EFI_PCI_EXPRESS_NOT_APPLICABLE;
>
> - }
>
> -
>
> - //
>
> - // get the device-specific state for PCIe ASPM state
>
> - //
>
> - if (mPciExpressPlatformPolicy.Aspm) {
>
> - PciExDeviceConfiguration.LinkCtlASPMState = GetPciExpressAspmState (PciDevice);
>
> - } else {
>
> - PciExDeviceConfiguration.LinkCtlASPMState = EFI_PCI_EXPRESS_NOT_APPLICABLE;
>
> - }
>
> -
>
> - //
>
> - // get the device-specific Common CLock Configuration value
>
> - //
>
> - if (mPciExpressPlatformPolicy.Ccc) {
>
> - PciExDeviceConfiguration.LinkCtlCommonClkCfg =
>
> - PciDevice->PciExpressCapabilityStructure.LinkControl.Bits.CommonClockConfiguration ?
>
> - EFI_PCI_EXPRESS_CLK_CFG_COMMON : EFI_PCI_EXPRESS_CLK_CFG_ASYNCH;
>
> - } else {
>
> - PciExDeviceConfiguration.LinkCtlCommonClkCfg = EFI_PCI_EXPRESS_NOT_APPLICABLE;
>
> - }
>
> -
>
> - if (mPciExPlatformProtocol != NULL) {
>
> - return mPciExPlatformProtocol->NotifyDeviceState (
>
> - mPciExPlatformProtocol,
>
> - PciDevice->Handle,
>
> - sizeof (EFI_PCI_EXPRESS_DEVICE_CONFIGURATION),
>
> - &PciExDeviceConfiguration
>
> - );
>
> - } else if (mPciExOverrideProtocol != NULL) {
>
> - return mPciExOverrideProtocol->NotifyDeviceState (
>
> - mPciExOverrideProtocol,
>
> - PciDevice->Handle,
>
> - sizeof (EFI_PCI_EXPRESS_DEVICE_CONFIGURATION),
>
> - &PciExDeviceConfiguration
>
> - );
>
> - } else {
>
> - //
>
> - // unexpected error
>
> - //
>
> - return EFI_UNSUPPORTED;
>
> - }
>
> -}
>
> -
>
> diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h
> b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h
> deleted file mode 100644
> index 4653c79..0000000
> --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h
> +++ /dev/null
> @@ -1,119 +0,0 @@
> -/** @file
>
> - This file encapsulate the usage of PCI Platform Protocol
>
> -
>
> - This file define the necessary hooks used to obtain the platform
>
> - level data and policies which could be used in the PCI Enumeration phases
>
> -
>
> -Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
>
> -
>
> -**/
>
> -
>
> -
>
> -#ifndef _EFI_PCI_PLATFORM_SUPPORT_H_
>
> -#define _EFI_PCI_PLATFORM_SUPPORT_H_
>
> -
>
> -
>
> -/**
>
> - This function retrieves the PCI Express Platform Protocols published by platform
>
> - @retval EFI_STATUS direct return status from the LocateProtocol ()
>
> - boot service for the PCI Express Override Protocol
>
> - EFI_SUCCESS The PCI Express Platform Protocol is found
>
> -**/
>
> -EFI_STATUS
>
> -GetPciExpressProtocol (
>
> - );
>
> -
>
> -/**
>
> - This function indicates that the platform has published the PCI Express Platform
>
> - Protocol (or PCI Express Override Protocol) to indicate that this driver can
>
> - initialize the PCI Express features.
>
> - @retval TRUE or FALSE
>
> -**/
>
> -BOOLEAN
>
> -IsPciExpressProtocolPresent (
>
> - );
>
> -
>
> -/**
>
> - This function gets the platform requirement to initialize the list of PCI Express
>
> - features from the protocol definition supported.
>
> - This function should be called after the LocatePciPlatformProtocol.
>
> - @retval EFI_SUCCESS return by platform to acknowledge the list of
>
> - PCI Express feature to be configured
>
> - (in mPciExpressPlatformPolicy)
>
> - EFI_INVALID_PARAMETER platform does not support the protocol arguements
>
> - passed
>
> - EFI_UNSUPPORTED platform did not published the protocol
>
> -**/
>
> -EFI_STATUS
>
> -PciExpressPlatformGetPolicy (
>
> - );
>
> -
>
> -/**
>
> - Gets the PCI device-specific platform policy from the PCI Platform Protocol.
>
> - If no PCI Platform protocol is published than setup the PCI feature to predetermined
>
> - defaults, in order to align all the PCI devices in the PCI hierarchy, as applicable.
>
> -
>
> - @param PciDevice A pointer to PCI_IO_DEVICE
>
> -
>
> - @retval EFI_STATUS The direct status from the PCI Platform Protocol
>
> - @retval EFI_SUCCESS On return of predetermined PCI features defaults, for
>
> - the case when protocol returns as EFI_UNSUPPORTED to
>
> - indicate PCI device exist and it has no platform policy
>
> - defined. Also, on returns when no PCI Platform Protocol
>
> - exist.
>
> -**/
>
> -EFI_STATUS
>
> -PciExpressPlatformGetDevicePolicy (
>
> - IN PCI_IO_DEVICE *PciDevice
>
> - );
>
> -
>
> -/**
>
> - Notifies the platform about the current PCI Express state of the device.
>
> -
>
> - @param PciDevice A pointer to PCI_IO_DEVICE
>
> - @param PciExDeviceConfiguration Pointer to EFI_PCI_EXPRESS_DEVICE_CONFIGURATION.
>
> - Used to pass the current state of device to
>
> - platform.
>
> -
>
> - @retval EFI_STATUS The direct status from the PCI Express Platform Protocol
>
> - @retval EFI_UNSUPPORTED returns when the PCI Express Platform Protocol or its
>
> - alias PCI Express OVerride Protocol is not present.
>
> -**/
>
> -EFI_STATUS
>
> -PciExpressPlatformNotifyDeviceState (
>
> - IN PCI_IO_DEVICE *PciDevice
>
> - );
>
> -
>
> -/**
>
> - Routine to translate the given device-specific platform policy from type
>
> - EFI_PCI_CONF_MAX_PAYLOAD_SIZE to HW-specific value, as per PCI Base Specification
>
> - Revision 4.0; for the PCI feature Max_Payload_Size.
>
> -
>
> - @param MPS Input device-specific policy should be in terms of type
>
> - EFI_PCI_CONF_MAX_PAYLOAD_SIZE
>
> -
>
> - @retval Range values for the Max_Payload_Size as defined in the PCI
>
> - Base Specification 4.0
>
> -**/
>
> -UINT8
>
> -SetDevicePolicyPciExpressMps (
>
> - IN UINT8 MPS
>
> -);
>
> -
>
> -/**
>
> - Routine to translate the given device-specific platform policy from type
>
> - EFI_PCI_CONF_MAX_READ_REQ_SIZE to HW-specific value, as per PCI Base Specification
>
> - Revision 4.0; for the PCI feature Max_Read_Req_Size.
>
> -
>
> - @param MRRS Input device-specific policy should be in terms of type
>
> - EFI_PCI_CONF_MAX_READ_REQ_SIZE
>
> -
>
> - @retval Range values for the Max_Read_Req_Size as defined in the PCI
>
> - Base Specification 4.0
>
> -**/
>
> -UINT8
>
> -SetDevicePolicyPciExpressMrrs (
>
> - IN UINT8 MRRS
>
> -);
>
> -#endif
>
> --
> 2.21.0.windows.1
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