[edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 15/15] MdeModulePkg/PciBusDxe: Enable CommonClockConfiguration feature

[Ni, Ray]

> +    //
> +    // retrain the link at Root Port level, if its link is active
> +    //
> +    if (Level == 1 && PciIoDevice->PciExpressCapability.LinkStatus.Bits.DataLinkLayerLinkActive) {
Should use "PciIoDevice->PciExpressCapability.LinkStatus.Bits.DataLinkLayerLinkActive != 0" to following EDK II coding style.
Do you want to retrain the link from the root port? Then we need compare the Level against 0 instead of 1.

> +    //
> +    if (Level == 1 && PciIoDevice->PciExpressCapability.LinkStatus.Bits.DataLinkLayerLinkActive) {
Similar comments to above line.

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