[edk2-devel] [PATCH edk2-platforms v2 04/16] Silicon/NXP: PciHostBridgeLib: CFG Shift feature support for PCIeLS Ctrl

[Wasim Khan]

From: Wasim Khan <wasim.khan at nxp.com>

PCIe layerscape controller supports CFG Shift feature. It can be
enabled by setting BIT[28] of iATU Control 2 Register.
Check PcdPciCfgShiftEnable to enable 'CFG Shift feature' in
PCIe controller.
if enable, PCIe layerscape controller shifts BDF from bits[27:12] to
bits[31:16] and supports Enhanced Configuration Address Mapping (ECAM)
mechanism.

PCIe layerscape controller is ECAM complaint for bus[0x1-0xff].
So create outbound CFG windows from 1MB-256MB (255 buses) for
type0/type1 configuration access.
PCIe layerscape controller is Non-ECAM complaint for bus 0.It does
not support device > 0 on bus 0. PciSegmentLib should handles this
limitation.

Co-authored-by: Vabhav Sharma <vabhav.sharma at nxp.com>
Co-authored-by: Wasim Khan <wasim.khan at nxp.com>
Signed-off-by: Wasim Khan <wasim.khan at nxp.com>
---

Notes:
    V2:
    - Removed Signed-off and added Co-authored-by for co-author
    - Introduced ECAM_BUS_SIZE and ECAM_CFG_REGION_SIZE for CFG
      region size and added comments for same.

 Silicon/NXP/NxpQoriqLs.dec                                |  3 ++
 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf |  3 ++
 Silicon/NXP/Include/Pcie.h                                |  5 +++
 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c   | 37 +++++++++++++++-----
 4 files changed, 40 insertions(+), 8 deletions(-)

diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index 9ff5ce8a1c6e..5358aaeb037e 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -35,3 +35,6 @@ [PcdsFixedAtBuild.common]
   gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|0|UINT32|0x00000501
   gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x0|UINT32|0x00000502
   gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x0|UINT32|0x00000503
+
+[PcdsDynamic.common]
+  gNxpQoriqLsTokenSpaceGuid.PcdPciCfgShiftEnable|FALSE|BOOLEAN|0x00000600
diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
index aa4802b019f6..99807d5beb1f 100644
--- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
@@ -37,3 +37,6 @@ [FixedPcd]
   gNxpQoriqLsTokenSpaceGuid.PcdNumPciController
   gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase
   gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg
+
+[Pcd]
+  gNxpQoriqLsTokenSpaceGuid.PcdPciCfgShiftEnable
diff --git a/Silicon/NXP/Include/Pcie.h b/Silicon/NXP/Include/Pcie.h
index 9dbe876b9c1a..f7c18c3aa094 100755
--- a/Silicon/NXP/Include/Pcie.h
+++ b/Silicon/NXP/Include/Pcie.h
@@ -27,6 +27,8 @@
 #define PCI_SEG_PORTIO_MIN        0x0
 #define PCI_SEG_PORTIO_MAX        0xffff
 #define SEG_CFG_SIZE              0x00001000
+#define ECAM_BUS_SIZE             SIZE_1MB
+#define ECAM_CFG_REGION_SIZE      SIZE_256MB
 #define SEG_MEM_BASE              0x40000000
 #define SEG_MEM_SIZE              0xC0000000
 #define SEG_MEM_LIMIT             SEG_MEM_BASE + (SEG_MEM_SIZE -1)
@@ -64,6 +66,7 @@
 #define IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0        0x91C
 #define IATU_VIEWPORT_OUTBOUND                       0x0
 #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN  BIT31
+#define IATU_ENABLE_CFG_SHIFT_FEATURE                BIT28
 
 // ATU Programming
 #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM   0x0
@@ -77,4 +80,6 @@
 #define SEG_IO_SIZE               0x10000
 #define SEG_IO_BUS                0x0
 
+#define CFG_SHIFT_ENABLE          (PcdGetBool (PcdPciCfgShiftEnable))
+
 #endif
diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
index 230fcf57690e..9fae19095cba 100644
--- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
+++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
@@ -259,8 +259,17 @@ PcieOutboundSet (
   MmioWrite32 (Dbi + IATU_REGION_CTRL_1_OFF_OUTBOUND_0,
                 (UINT32)Type);
 
-  MmioWrite32 (Dbi + IATU_REGION_CTRL_2_OFF_OUTBOUND_0,
-                IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN);
+  if (CFG_SHIFT_ENABLE &&
+     ((Type == IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0) ||
+     (Type == IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1))) {
+       MmioWrite32 (Dbi + IATU_REGION_CTRL_2_OFF_OUTBOUND_0,
+         (IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN |
+         IATU_ENABLE_CFG_SHIFT_FEATURE)
+         );
+  } else {
+    MmioWrite32 (Dbi + IATU_REGION_CTRL_2_OFF_OUTBOUND_0,
+                  IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN);
+  }
 }
 
 /**
@@ -293,12 +302,24 @@ PcieLsSetupAtu (
   UINT64 Mem64End;
   UINT32 Index;
 
-  Cfg0BaseAddr = Cfg0Base;
-  Cfg1BaseAddr = Cfg1Base;
-  Cfg0BusAddress = SEG_CFG_BUS;
-  Cfg1BusAddress = SEG_CFG_BUS;
-  Cfg0Size = SEG_CFG_SIZE;
-  Cfg1Size = SEG_CFG_SIZE;
+  if (CFG_SHIFT_ENABLE) {
+    DEBUG ((DEBUG_INFO, "PCIe: CFG Shift Method Enabled \n"));
+    Cfg0BaseAddr = Cfg0Base + SIZE_1MB;
+    Cfg1BaseAddr = Cfg0Base + SIZE_2MB;
+    Cfg0BusAddress = SIZE_1MB;
+    Cfg1BusAddress = SIZE_2MB;
+    // Region for type0 CFG transactions (only for bus1)
+    Cfg0Size = ECAM_BUS_SIZE;
+    // Region for type1 CFG transactions (for bus > 1)
+    Cfg1Size = (ECAM_CFG_REGION_SIZE - ECAM_BUS_SIZE); // 255MB
+  } else {
+    Cfg0BaseAddr = Cfg0Base;
+    Cfg1BaseAddr = Cfg1Base;
+    Cfg0BusAddress = SEG_CFG_BUS;
+    Cfg1BusAddress = SEG_CFG_BUS;
+    Cfg0Size = SEG_CFG_SIZE;
+    Cfg1Size = SEG_CFG_SIZE;
+  }
 
   Index = 0;
   // iATU : OUTBOUND WINDOW 1 : CFG0
-- 
2.7.4


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