[edk2-devel] [edk2-platforms v2 3/6] Silicon/NXP: Add SCFG support for Chassis2
Leif Lindholm
leif at nuviainc.com
Thu Oct 8 12:15:47 UTC 2020
On Wed, Oct 07, 2020 at 21:40:38 +0530, Meenakshi Aggarwal wrote:
> Add support for SCFG (Supplemental Configuration Unit)
> register space and helper functions to R/W SCFG registers
>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal at nxp.com>
Reviewed-by: Leif Lindholm <leif at nuviainc.com>
> ---
> Silicon/NXP/NxpQoriqLs.dec | 1 +
> Silicon/NXP/Chassis2/Include/Chassis.h | 108 +++++++++++++++++++++
> Silicon/NXP/Include/Library/ChassisLib.h | 42 ++++++++
> .../NXP/Chassis2/Library/ChassisLib/ChassisLib.c | 63 ++++++++++++
> 4 files changed, 214 insertions(+)
>
> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> index 3a568c0437e7..90dce69fd472 100644
> --- a/Silicon/NXP/NxpQoriqLs.dec
> +++ b/Silicon/NXP/NxpQoriqLs.dec
> @@ -30,6 +30,7 @@ [PcdsFeatureFlag]
> gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000317
> gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185|FALSE|BOOLEAN|0x00000318
> gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian|FALSE|BOOLEAN|0x00000319
> + gNxpQoriqLsTokenSpaceGuid.PcdScfgBigEndian|FALSE|BOOLEAN|0x00000320
>
> [PcdsFixedAtBuild.common]
> # Pcds for PCI Express
> diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h b/Silicon/NXP/Chassis2/Include/Chassis.h
> index 7e8bf224884b..6dfce425a0b0 100644
> --- a/Silicon/NXP/Chassis2/Include/Chassis.h
> +++ b/Silicon/NXP/Chassis2/Include/Chassis.h
> @@ -11,6 +11,7 @@
> #include <Uefi.h>
>
> #define NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS 0x1EE0000
> +#define NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS 0x1570000
>
> #define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFE)
> #define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
> @@ -45,4 +46,111 @@ typedef struct {
> } NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG;
> #pragma pack()
>
> +/* Supplemental Configuration Unit (SCFG) */
> +typedef struct {
> + UINT8 Res000[0x070-0x000];
> + UINT32 Usb1Prm1Cr;
> + UINT32 Usb1Prm2Cr;
> + UINT32 Usb1Prm3Cr;
> + UINT32 Usb2Prm1Cr;
> + UINT32 Usb2Prm2Cr;
> + UINT32 Usb2Prm3Cr;
> + UINT32 Usb3Prm1Cr;
> + UINT32 Usb3Prm2Cr;
> + UINT32 Usb3Prm3Cr;
> + UINT8 Res094[0x100-0x094];
> + UINT32 Usb2Icid;
> + UINT32 Usb3Icid;
> + UINT8 Res108[0x114-0x108];
> + UINT32 DmaIcid;
> + UINT32 SataIcid;
> + UINT32 Usb1Icid;
> + UINT32 QeIcid;
> + UINT32 SdhcIcid;
> + UINT32 EdmaIcid;
> + UINT32 EtrIcid;
> + UINT32 Core0SftRst;
> + UINT32 Core1SftRst;
> + UINT32 Core2SftRst;
> + UINT32 Core3SftRst;
> + UINT8 Res140[0x158-0x140];
> + UINT32 AltCBar;
> + UINT32 QspiCfg;
> + UINT8 Res160[0x180-0x160];
> + UINT32 DmaMcr;
> + UINT8 Res184[0x188-0x184];
> + UINT32 GicAlign;
> + UINT32 DebugIcid;
> + UINT8 Res190[0x1a4-0x190];
> + UINT32 SnpCnfgCr;
> +#define SCFG_SNPCNFGCR_SECRDSNP BIT31
> +#define SCFG_SNPCNFGCR_SECWRSNP BIT30
> +#define SCFG_SNPCNFGCR_SATARDSNP BIT23
> +#define SCFG_SNPCNFGCR_SATAWRSNP BIT22
> +#define SCFG_SNPCNFGCR_USB1RDSNP BIT21
> +#define SCFG_SNPCNFGCR_USB1WRSNP BIT20
> +#define SCFG_SNPCNFGCR_USB2RDSNP BIT15
> +#define SCFG_SNPCNFGCR_USB2WRSNP BIT16
> +#define SCFG_SNPCNFGCR_USB3RDSNP BIT13
> +#define SCFG_SNPCNFGCR_USB3WRSNP BIT14
> + UINT8 Res1a8[0x1ac-0x1a8];
> + UINT32 IntpCr;
> + UINT8 Res1b0[0x204-0x1b0];
> + UINT32 CoreSrEnCr;
> + UINT8 Res208[0x220-0x208];
> + UINT32 RvBar00;
> + UINT32 RvBar01;
> + UINT32 RvBar10;
> + UINT32 RvBar11;
> + UINT32 RvBar20;
> + UINT32 RvBar21;
> + UINT32 RvBar30;
> + UINT32 RvBar31;
> + UINT32 LpmCsr;
> + UINT8 Res244[0x400-0x244];
> + UINT32 QspIdQScr;
> + UINT32 EcgTxcMcr;
> + UINT32 SdhcIoVSelCr;
> + UINT32 RcwPMuxCr0;
> + /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
> + Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
> + Setting RCW PinMux Register bits 25-27 to select USB3_DRVVBUS
> + Setting RCW PinMux Register bits 29-31 to select USB3_DRVVBUS
> + **/
> +#define SCFG_RCWPMUXCRO_SELCR_USB 0x3333
> + /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
> + Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
> + Setting RCW PinMux Register bits 25-27 to select IIC4_SCL
> + Setting RCW PinMux Register bits 29-31 to select IIC4_SDA
> + **/
> +#define SCFG_RCWPMUXCRO_NOT_SELCR_USB 0x3300
> + UINT32 UsbDrvVBusSelCr;
> +#define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
> +#define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
> +#define SCFG_USBDRVVBUS_SELCR_USB3 0x00000003
> + UINT32 UsbPwrFaultSelCr;
> +#define SCFG_USBPWRFAULT_INACTIVE 0x00000000
> +#define SCFG_USBPWRFAULT_SHARED 0x00000001
> +#define SCFG_USBPWRFAULT_DEDICATED 0x00000002
> +#define SCFG_USBPWRFAULT_USB3_SHIFT 4
> +#define SCFG_USBPWRFAULT_USB2_SHIFT 2
> +#define SCFG_USBPWRFAULT_USB1_SHIFT 0
> + UINT32 UsbRefclkSelcr1;
> + UINT32 UsbRefclkSelcr2;
> + UINT32 UsbRefclkSelcr3;
> + UINT8 Res424[0x600-0x424];
> + UINT32 ScratchRw[4];
> + UINT8 Res610[0x680-0x610];
> + UINT32 CoreBCr;
> + UINT8 Res684[0x1000-0x684];
> + UINT32 Pex1MsiIr;
> + UINT32 Pex1MsiR;
> + UINT8 Res1008[0x2000-0x1008];
> + UINT32 Pex2;
> + UINT32 Pex2MsiR;
> + UINT8 Res2008[0x3000-0x2008];
> + UINT32 Pex3MsiIr;
> + UINT32 Pex3MsiR;
> +} NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG;
> +
> #endif // CHASSIS_H__
> diff --git a/Silicon/NXP/Include/Library/ChassisLib.h b/Silicon/NXP/Include/Library/ChassisLib.h
> index 89992a4b6fd5..a038d8e5ce31 100644
> --- a/Silicon/NXP/Include/Library/ChassisLib.h
> +++ b/Silicon/NXP/Include/Library/ChassisLib.h
> @@ -13,6 +13,48 @@
> #include <Chassis.h>
>
> /**
> + Or Scfg register
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +**/
> +UINT32
> +EFIAPI
> +ScfgOr32 (
> + IN UINTN Address,
> + IN UINT32 Value
> + );
> +
> +/**
> + Read Scfg register
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +**/
> +UINT32
> +EFIAPI
> +ScfgRead32 (
> + IN UINTN Address
> + );
> +
> +/**
> + Write Scfg register
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> + @return Value.
> +**/
> +UINT32
> +EFIAPI
> +ScfgWrite32 (
> + IN UINTN Address,
> + IN UINT32 Value
> + );
> +
> +/**
> Read Dcfg register
>
> @param Address The MMIO register to read.
> diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> index 91b19f832f00..e6410a53f480 100644
> --- a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> +++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> @@ -15,6 +15,69 @@
> #include <Library/SerialPortLib.h>
>
> /**
> + Or Scfg register
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +**/
> +UINT32
> +EFIAPI
> +ScfgOr32 (
> + IN UINTN Address,
> + IN UINT32 Value
> + )
> +{
> + MMIO_OPERATIONS *ScfgOps;
> +
> + ScfgOps = GetMmioOperations (FeaturePcdGet (PcdScfgBigEndian));
> +
> + return ScfgOps->Or32 (Address, Value);
> +}
> +
> +/**
> + Read Scfg register
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +**/
> +UINT32
> +EFIAPI
> +ScfgRead32 (
> + IN UINTN Address
> + )
> +{
> + MMIO_OPERATIONS *ScfgOps;
> +
> + ScfgOps = GetMmioOperations (FeaturePcdGet (PcdScfgBigEndian));
> +
> + return ScfgOps->Read32 (Address);
> +}
> +
> +/**
> + Write Scfg register
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> + @return Value.
> +**/
> +UINT32
> +EFIAPI
> +ScfgWrite32 (
> + IN UINTN Address,
> + IN UINT32 Value
> + )
> +{
> + MMIO_OPERATIONS *ScfgOps;
> +
> + ScfgOps = GetMmioOperations (FeaturePcdGet (PcdScfgBigEndian));
> +
> + return ScfgOps->Write32 (Address, Value);
> +}
> +
> +/**
> Read Dcfg register
>
> @param Address The MMIO register to read.
> --
> 1.9.1
>
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