[edk2-devel] [edk2-platforms 3/4] Silicon/NXP: Implement USB Errata
Leif Lindholm
leif at nuviainc.com
Fri Sep 25 11:47:01 UTC 2020
On Tue, Sep 15, 2020 at 21:59:02 +0530, Meenakshi Aggarwal wrote:
> Implement USB errata A009008, A009798, A008997, A009007
> Make USB,SEC and SATA snoopable
Somewhat nitpicking, but for both subject and message - can you say
"errata workarounds" rather than "errata"?
Ideally, I would like to see the addition of the SCFG as a separate
patch from the one that implements the workarounds.
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal at nxp.com>
> ---
> Silicon/NXP/NxpQoriqLs.dec | 1 +
> Silicon/NXP/LS1046A/LS1046A.dsc.inc | 1 +
> .../NXP/Chassis2/Library/ChassisLib/ChassisLib.inf | 2 +
> Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf | 2 +
> Silicon/NXP/Chassis2/Include/Chassis.h | 112 +++++++++++++++
> Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h | 23 +++
> Silicon/NXP/Include/Library/ChassisLib.h | 62 ++++++++
> Silicon/NXP/LS1046A/Include/Soc.h | 2 +
> .../NXP/Chassis2/Library/ChassisLib/ChassisLib.c | 63 ++++++++
> Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c | 159 +++++++++++++++++++++
> Silicon/NXP/LS1046A/Library/SocLib/SocLib.c | 66 +++++++++
> 11 files changed, 493 insertions(+)
> create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h
> create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c
>
> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> index 3a568c0437e7..90dce69fd472 100644
> --- a/Silicon/NXP/NxpQoriqLs.dec
> +++ b/Silicon/NXP/NxpQoriqLs.dec
> @@ -30,6 +30,7 @@ [PcdsFeatureFlag]
> gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000317
> gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185|FALSE|BOOLEAN|0x00000318
> gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian|FALSE|BOOLEAN|0x00000319
> + gNxpQoriqLsTokenSpaceGuid.PcdScfgBigEndian|FALSE|BOOLEAN|0x00000320
>
> [PcdsFixedAtBuild.common]
> # Pcds for PCI Express
> diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
> index db110553605f..4e1d6a7ae7a2 100644
> --- a/Silicon/NXP/LS1046A/LS1046A.dsc.inc
> +++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
> @@ -34,6 +34,7 @@ [PcdsFixedAtBuild.common]
>
> [PcdsFeatureFlag]
> gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
> + gNxpQoriqLsTokenSpaceGuid.PcdScfgBigEndian|TRUE
> gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian|TRUE
>
> ################################################################################
> diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
> index f5dbd1349dc5..d64286b199c6 100644
> --- a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
> +++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
> @@ -28,6 +28,8 @@ [LibraryClasses]
>
> [Sources.common]
> ChassisLib.c
> + Erratum.c
>
> [FeaturePcd]
> gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian
> + gNxpQoriqLsTokenSpaceGuid.PcdScfgBigEndian
> diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
> index 01ed0f6592d2..e2336bb18f29 100644
> --- a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
> +++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
> @@ -14,6 +14,7 @@ [Defines]
> LIBRARY_CLASS = SocLib
>
> [Packages]
> + ArmPkg/ArmPkg.dec
> MdePkg/MdePkg.dec
> Silicon/NXP/Chassis2/Chassis2.dec
> Silicon/NXP/LS1046A/LS1046A.dec
> @@ -25,3 +26,4 @@ [LibraryClasses]
>
> [Sources.common]
> SocLib.c
> +
> diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h b/Silicon/NXP/Chassis2/Include/Chassis.h
> index 7e8bf224884b..f8fa7ed67596 100644
> --- a/Silicon/NXP/Chassis2/Include/Chassis.h
> +++ b/Silicon/NXP/Chassis2/Include/Chassis.h
> @@ -11,6 +11,7 @@
> #include <Uefi.h>
>
> #define NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS 0x1EE0000
> +#define NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS 0x1570000
>
> #define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFE)
> #define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
> @@ -26,6 +27,10 @@
> #define SCR0_CLIENTPD_MASK 0x00000001
> #define SACR_PAGESIZE_MASK 0x00010000
>
> +#define USB_PHY1_BASE_ADDRESS 0x084F0000
> +#define USB_PHY2_BASE_ADDRESS 0x08500000
> +#define USB_PHY3_BASE_ADDRESS 0x08510000
> +
> /**
> The Device Configuration Unit provides general purpose configuration and
> status for the device. These registers only support 32-bit accesses.
> @@ -45,4 +50,111 @@ typedef struct {
> } NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG;
> #pragma pack()
>
> +/* Supplemental Configuration Unit (SCFG) */
> +typedef struct {
> + UINT8 Res000[0x070-0x000];
> + UINT32 Usb1Prm1Cr;
> + UINT32 Usb1Prm2Cr;
> + UINT32 Usb1Prm3Cr;
> + UINT32 Usb2Prm1Cr;
> + UINT32 Usb2Prm2Cr;
> + UINT32 Usb2Prm3Cr;
> + UINT32 Usb3Prm1Cr;
> + UINT32 Usb3Prm2Cr;
> + UINT32 Usb3Prm3Cr;
> + UINT8 Res094[0x100-0x094];
> + UINT32 Usb2Icid;
> + UINT32 Usb3Icid;
> + UINT8 Res108[0x114-0x108];
> + UINT32 DmaIcid;
> + UINT32 SataIcid;
> + UINT32 Usb1Icid;
> + UINT32 QeIcid;
> + UINT32 SdhcIcid;
> + UINT32 EdmaIcid;
> + UINT32 EtrIcid;
> + UINT32 Core0SftRst;
> + UINT32 Core1SftRst;
> + UINT32 Core2SftRst;
> + UINT32 Core3SftRst;
> + UINT8 Res140[0x158-0x140];
> + UINT32 AltCBar;
> + UINT32 QspiCfg;
> + UINT8 Res160[0x180-0x160];
> + UINT32 DmaMcr;
> + UINT8 Res184[0x188-0x184];
> + UINT32 GicAlign;
> + UINT32 DebugIcid;
> + UINT8 Res190[0x1a4-0x190];
> + UINT32 SnpCnfgCr;
> +#define SCFG_SNPCNFGCR_SECRDSNP BIT31
> +#define SCFG_SNPCNFGCR_SECWRSNP BIT30
> +#define SCFG_SNPCNFGCR_SATARDSNP BIT23
> +#define SCFG_SNPCNFGCR_SATAWRSNP BIT22
> +#define SCFG_SNPCNFGCR_USB1RDSNP BIT21
> +#define SCFG_SNPCNFGCR_USB1WRSNP BIT20
> +#define SCFG_SNPCNFGCR_USB2RDSNP BIT15
> +#define SCFG_SNPCNFGCR_USB2WRSNP BIT16
> +#define SCFG_SNPCNFGCR_USB3RDSNP BIT13
> +#define SCFG_SNPCNFGCR_USB3WRSNP BIT14
> + UINT8 Res1a8[0x1ac-0x1a8];
> + UINT32 IntpCr;
> + UINT8 Res1b0[0x204-0x1b0];
> + UINT32 CoreSrEnCr;
> + UINT8 Res208[0x220-0x208];
> + UINT32 RvBar00;
> + UINT32 RvBar01;
> + UINT32 RvBar10;
> + UINT32 RvBar11;
> + UINT32 RvBar20;
> + UINT32 RvBar21;
> + UINT32 RvBar30;
> + UINT32 RvBar31;
> + UINT32 LpmCsr;
> + UINT8 Res244[0x400-0x244];
> + UINT32 QspIdQScr;
> + UINT32 EcgTxcMcr;
> + UINT32 SdhcIoVSelCr;
> + UINT32 RcwPMuxCr0;
> + /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
> + Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
> + Setting RCW PinMux Register bits 25-27 to select USB3_DRVVBUS
> + Setting RCW PinMux Register bits 29-31 to select USB3_DRVVBUS
> + **/
> +#define SCFG_RCWPMUXCRO_SELCR_USB 0x3333
> + /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
> + Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
> + Setting RCW PinMux Register bits 25-27 to select IIC4_SCL
> + Setting RCW PinMux Register bits 29-31 to select IIC4_SDA
> + **/
> +#define SCFG_RCWPMUXCRO_NOT_SELCR_USB 0x3300
> + UINT32 UsbDrvVBusSelCr;
> +#define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
> +#define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
> +#define SCFG_USBDRVVBUS_SELCR_USB3 0x00000003
> + UINT32 UsbPwrFaultSelCr;
> +#define SCFG_USBPWRFAULT_INACTIVE 0x00000000
> +#define SCFG_USBPWRFAULT_SHARED 0x00000001
> +#define SCFG_USBPWRFAULT_DEDICATED 0x00000002
> +#define SCFG_USBPWRFAULT_USB3_SHIFT 4
> +#define SCFG_USBPWRFAULT_USB2_SHIFT 2
> +#define SCFG_USBPWRFAULT_USB1_SHIFT 0
> + UINT32 UsbRefclkSelcr1;
> + UINT32 UsbRefclkSelcr2;
> + UINT32 UsbRefclkSelcr3;
> + UINT8 Res424[0x600-0x424];
> + UINT32 ScratchRw[4];
> + UINT8 Res610[0x680-0x610];
> + UINT32 CoreBCr;
> + UINT8 Res684[0x1000-0x684];
> + UINT32 Pex1MsiIr;
> + UINT32 Pex1MsiR;
> + UINT8 Res1008[0x2000-0x1008];
> + UINT32 Pex2;
> + UINT32 Pex2MsiR;
> + UINT8 Res2008[0x3000-0x2008];
> + UINT32 Pex3MsiIr;
> + UINT32 Pex3MsiR;
> +} NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG;
> +
> #endif // CHASSIS_H__
> diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h b/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h
> new file mode 100644
> index 000000000000..0231ef0a283d
> --- /dev/null
> +++ b/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h
> @@ -0,0 +1,23 @@
> +/** @file
> +* Header defining the Base addresses, sizes, flags etc for Erratas
> +*
> +* Copyright 2020 NXP
> +*
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#ifndef ERRATUM_H__
> +#define ERRATUM_H__
> +
> +#define USB_TXVREFTUNE 0x9
> +#define USB_SQRXTUNE 0xFC7FFFFF
> +#define USB_PCSTXSWINGFULL 0x47
> +#define USB_PHY_RX_EQ_VAL_1 0x0000
> +#define USB_PHY_RX_EQ_VAL_2 0x8000
> +#define USB_PHY_RX_EQ_VAL_3 0x8003
> +#define USB_PHY_RX_EQ_VAL_4 0x800b
> +
> +#define USB_PHY_RX_OVRD_IN_HI 0x200c
> +
> +#endif
> diff --git a/Silicon/NXP/Include/Library/ChassisLib.h b/Silicon/NXP/Include/Library/ChassisLib.h
> index 89992a4b6fd5..c99368b4733d 100644
> --- a/Silicon/NXP/Include/Library/ChassisLib.h
> +++ b/Silicon/NXP/Include/Library/ChassisLib.h
> @@ -13,6 +13,48 @@
> #include <Chassis.h>
>
> /**
> + Or Scfg register
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +**/
> +UINT32
> +EFIAPI
> +ScfgOr32 (
> + IN UINTN Address,
> + IN UINT32 Value
> + );
> +
> +/**
> + Read Scfg register
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +**/
> +UINT32
> +EFIAPI
> +ScfgRead32 (
> + IN UINTN Address
> + );
> +
> +/**
> + Write Scfg register
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> + @return Value.
> +**/
> +UINT32
> +EFIAPI
> +ScfgWrite32 (
> + IN UINTN Address,
> + IN UINT32 Value
> + );
> +
> +/**
> Read Dcfg register
>
> @param Address The MMIO register to read.
> @@ -48,4 +90,24 @@ ChassisInit (
> VOID
> );
>
> +VOID
> +ErratumA009008 (
> + VOID
> + );
> +
> +VOID
> +ErratumA009798 (
> + VOID
> + );
> +
> +VOID
> +ErratumA008997 (
> + VOID
> + );
> +
> +VOID
> +ErratumA009007 (
> + VOID
> + );
> +
> #endif // CHASSIS_LIB_H__
> diff --git a/Silicon/NXP/LS1046A/Include/Soc.h b/Silicon/NXP/LS1046A/Include/Soc.h
> index 84f433d5cb94..e1d97e531263 100644
> --- a/Silicon/NXP/LS1046A/Include/Soc.h
> +++ b/Silicon/NXP/LS1046A/Include/Soc.h
> @@ -25,6 +25,7 @@
> #define LS1046A_QSPI0_SIZE (SIZE_512MB)
>
> #define LS1046A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS
> +#define LS1046A_SCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS
>
> /**
> Reset Control Word (RCW) Bits
> @@ -59,5 +60,6 @@ Bit(s) | Field Name | Description | Notes/comments
> #define SYS_PLL_RAT(x) (((x) >> 25) & 0x1f) // Bits 2-6
>
> typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1046A_DEVICE_CONFIG;
> +typedef NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG LS1046A_SUPPLEMENTAL_CONFIG;
>
> #endif // SOC_H__
> diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> index 91b19f832f00..e6410a53f480 100644
> --- a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> +++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> @@ -15,6 +15,69 @@
> #include <Library/SerialPortLib.h>
>
> /**
> + Or Scfg register
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +**/
> +UINT32
> +EFIAPI
> +ScfgOr32 (
> + IN UINTN Address,
> + IN UINT32 Value
> + )
> +{
> + MMIO_OPERATIONS *ScfgOps;
> +
> + ScfgOps = GetMmioOperations (FeaturePcdGet (PcdScfgBigEndian));
> +
> + return ScfgOps->Or32 (Address, Value);
> +}
> +
> +/**
> + Read Scfg register
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +**/
> +UINT32
> +EFIAPI
> +ScfgRead32 (
> + IN UINTN Address
> + )
> +{
> + MMIO_OPERATIONS *ScfgOps;
> +
> + ScfgOps = GetMmioOperations (FeaturePcdGet (PcdScfgBigEndian));
> +
> + return ScfgOps->Read32 (Address);
> +}
> +
> +/**
> + Write Scfg register
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> + @return Value.
> +**/
> +UINT32
> +EFIAPI
> +ScfgWrite32 (
> + IN UINTN Address,
> + IN UINT32 Value
> + )
> +{
> + MMIO_OPERATIONS *ScfgOps;
> +
> + ScfgOps = GetMmioOperations (FeaturePcdGet (PcdScfgBigEndian));
> +
> + return ScfgOps->Write32 (Address, Value);
> +}
> +
> +/**
> Read Dcfg register
>
> @param Address The MMIO register to read.
> diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c b/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c
> new file mode 100644
> index 000000000000..1806975ec8f5
> --- /dev/null
> +++ b/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c
> @@ -0,0 +1,159 @@
> +/** @file
> + This file containa all erratas need to be applied on different SoCs.
> +
> + Copyright 2020 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Base.h>
> +#include <Library/ArmLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/ChassisLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +
> +#include "Erratum.h"
> +
> +/*
> +* A-009008: USB High Speed (HS) eye height adjustment
> +* Affects: USB
> +* Description: USB HS eye diagram fails with the default value at many corners, particularly at a high
> +* temperature (105°C).
Please rewrap above two lines below 80 columns.
Apply to comment blocks below also.
/
Leif
> +* Impact: USB HS eye diagram may fail using the default value.
> +*/
> +VOID
> +ErratumA009008 (
> + VOID
> + )
> +{
> + NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *Scfg;
> + UINT32 Value;
> +
> + Scfg = (NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *)NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS;
> +
> + Value = ScfgRead32 ((UINTN)&Scfg->Usb1Prm1Cr);
> + Value &= ~(0xF << 6);
> + ScfgWrite32 ((UINTN)&Scfg->Usb1Prm1Cr, Value|(USB_TXVREFTUNE << 6));
> + Value = ScfgRead32 ((UINTN)&Scfg->Usb2Prm1Cr);
> + Value &= ~(0xF << 6);
> + ScfgWrite32 ((UINTN)&Scfg->Usb2Prm1Cr, Value|(USB_TXVREFTUNE << 6));
> + Value = ScfgRead32 ((UINTN)&Scfg->Usb3Prm1Cr);
> + Value &= ~(0xF << 6);
> + ScfgWrite32 ((UINTN)&Scfg->Usb3Prm1Cr, Value|(USB_TXVREFTUNE << 6));
> +
> + return;
> +}
> +
> +/*
> +* A-009798: USB high speed squelch threshold adjustment
> +* Affects: USB
> +* Description: The default setting for USB high speed squelch threshold results in a threshold close to or
> +* lower than 100mV. This leads to a receiver compliance test failure for a 100mV threshold.
> +* Impact: If the errata is not applied, only the USB high speed receiver sensitivity compliance test fails,
> +* however USB data continues to transfer.
> +*/
> +VOID
> +ErratumA009798 (
> + VOID
> + )
> +{
> + NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *Scfg;
> + UINT32 Value;
> +
> + Scfg = (NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *)NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS;
> +
> + Value = ScfgRead32 ((UINTN)&Scfg->Usb1Prm1Cr);
> + ScfgWrite32 ((UINTN)&Scfg->Usb1Prm1Cr, Value & USB_SQRXTUNE);
> + Value = ScfgRead32 ((UINTN)&Scfg->Usb2Prm1Cr);
> + ScfgWrite32 ((UINTN)&Scfg->Usb2Prm1Cr, Value & USB_SQRXTUNE);
> + Value = ScfgRead32 ((UINTN)&Scfg->Usb3Prm1Cr);
> + ScfgWrite32 ((UINTN)&Scfg->Usb3Prm1Cr, Value & USB_SQRXTUNE);
> +
> + return;
> +}
> +
> +/*
> +* A-008997: USB3 LFPS peak-to-peak differential output voltage adjustment settings
> +* Affects: USB
> +* Description: Low Frequency Periodic Signaling (LFPS) peak-to-peak differential output voltage test
> +* compliance fails using default transmitter settings. Software is required to change the
> +* transmitter signal swings to pass compliance tests.
> +* Impact: LFPS peak-to-peak differential output voltage compliance test fails.
> +*/
> +VOID
> +ErratumA008997 (
> + VOID
> + )
> +{
> + NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *Scfg;
> + UINT32 Value;
> +
> + Scfg = (NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *)NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS;
> +
> + Value = ScfgRead32 ((UINTN)&Scfg->Usb1Prm2Cr);
> + Value &= ~(0x7F << 9);
> + ScfgWrite32 ((UINTN)&Scfg->Usb1Prm2Cr, Value | (USB_PCSTXSWINGFULL << 9));
> + Value = ScfgRead32 ((UINTN)&Scfg->Usb2Prm2Cr);
> + Value &= ~(0x7F << 9);
> + ScfgWrite32 ((UINTN)&Scfg->Usb2Prm2Cr, Value | (USB_PCSTXSWINGFULL << 9));
> + Value = ScfgRead32 ((UINTN)&Scfg->Usb3Prm2Cr);
> + Value &= ~(0x7F << 9);
> + ScfgWrite32 ((UINTN)&Scfg->Usb3Prm2Cr, Value | (USB_PCSTXSWINGFULL << 9));
> +
> + return;
> +}
> +
> +/*
> +* A-009007: USB3PHY observing intermittent failure in receive compliance tests
> +* at higher jitter frequency using default register values
> +*
> +* Affects: USB
> +*
> +* Description: Receive compliance tests may fail intermittently at high jitter
> +* frequencies using default register values.
> +*
> +* Impact: Receive compliance test fails at default register setting.
> +*/
> +
> +VOID
> +ConfigUsbLane0 (
> + IN UINTN UsbPhy
> + )
> +{
> + UINTN RegAddress;
> +
> + RegAddress = UsbPhy + USB_PHY_RX_OVRD_IN_HI;
> +
> + ArmDataMemoryBarrier ();
> + MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_1);
> + ArmDataMemoryBarrier ();
> + MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_2);
> + ArmDataMemoryBarrier ();
> + MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_3);
> + ArmDataMemoryBarrier ();
> + MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_4);
> +
> + return;
> +}
> +
> +VOID
> +ErratumA009007 (
> + VOID
> + )
> +{
> + UINTN UsbPhy;
> +
> + UsbPhy = USB_PHY1_BASE_ADDRESS;
> + ConfigUsbLane0 (UsbPhy);
> +
> + UsbPhy = USB_PHY2_BASE_ADDRESS;
> + ConfigUsbLane0 (UsbPhy);
> +
> + UsbPhy = USB_PHY3_BASE_ADDRESS;
> + ConfigUsbLane0 (UsbPhy);
> +
> + return;
> +}
> diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
> index 3b15aee6ecae..80342d7230e4 100644
> --- a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
> +++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
> @@ -11,6 +11,8 @@
> #include <Library/ChassisLib.h>
> #include <Library/DebugLib.h>
> #include <Library/SocLib.h>
> +
> +#include <Library/SocLib.h>
> #include <Soc.h>
>
> /**
> @@ -65,6 +67,47 @@ SocGetClock (
> }
>
> /**
> + Function to select pins depending upon pcd using supplemental
> + configuration unit(SCFG) extended RCW controlled pinmux control
> + register which contains the bits to provide pin multiplexing control.
> + This register is reset on HRESET.
> + **/
> +STATIC
> +VOID
> +ConfigScfgMux (VOID)
> +{
> + LS1046A_SUPPLEMENTAL_CONFIG *Scfg;
> + UINT32 UsbPwrFault;
> +
> + Scfg = (LS1046A_SUPPLEMENTAL_CONFIG *)LS1046A_SCFG_ADDRESS;
> + // Configures functionality of the IIC3_SCL to USB2_DRVVBUS
> + // Configures functionality of the IIC3_SDA to USB2_PWRFAULT
> + // USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA
> + ScfgWrite32 ((UINTN)&Scfg->RcwPMuxCr0, SCFG_RCWPMUXCRO_NOT_SELCR_USB);
> +
> + ScfgWrite32 ((UINTN)&Scfg->UsbDrvVBusSelCr, SCFG_USBDRVVBUS_SELCR_USB1);
> + UsbPwrFault = (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
> + (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
> + (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
> + ScfgWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
> + ScfgWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
> +}
> +
> +STATIC
> +VOID
> +ApplyErrata (
> + VOID
> + )
> +{
> + ErratumA009008 ();
> + ErratumA009798 ();
> + ErratumA008997 ();
> + ErratumA009007 ();
> +}
> +
> +
> +
> +/**
> Function to initialize SoC specific constructs
> **/
> VOID
> @@ -72,7 +115,30 @@ SocInit (
> VOID
> )
> {
> + LS1046A_SUPPLEMENTAL_CONFIG *Scfg;
> +
> + Scfg = (LS1046A_SUPPLEMENTAL_CONFIG *)LS1046A_SCFG_ADDRESS;
> +
> + /* Make SEC, SATA and USB reads and writes snoopable */
> + ScfgOr32((UINTN)&Scfg->SnpCnfgCr, SCFG_SNPCNFGCR_SECRDSNP |
> + SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
> + SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
> + SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
> + SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
> + SCFG_SNPCNFGCR_SATAWRSNP);
> +
> + ApplyErrata ();
> ChassisInit ();
>
> + //
> + // Due to the extensive functionality present on the chip and the limited number of external
> + // signals available, several functional blocks share signal resources through multiplexing.
> + // In this case when there is alternate functionality between multiple functional blocks,
> + // the signal's function is determined at the chip level (rather than at the block level)
> + // typically by a reset configuration word (RCW) option. Some of the signals' function are
> + // determined externel to RCW at Power-on Reset Sequence.
> + //
> + ConfigScfgMux ();
> +
> return;
> }
> --
> 1.9.1
>
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