[edk2-devel] [PATCH v2 12/17] Silicon/AMD: Update Styx code to work with changes ARM_CORE_INFO struct
Rebecca Cran
rebecca at nuviainc.com
Thu Dec 16 22:07:55 UTC 2021
The ARM_CORE_INFO struct has been updated so the MPIDR is now a single
field instead of separate cluster/core fields. Update the Styx code in
AcpiPlatformDxe, PlatInitPei and StyxDtbLoaderLib.
Signed-off-by: Rebecca Cran <rebecca at nuviainc.com>
---
Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c | 3 +--
Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c | 8 +++----
Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c | 22 +++++++++-----------
3 files changed, 15 insertions(+), 18 deletions(-)
diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c
index 7c267542db19..5f059110ff0c 100644
--- a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c
+++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c
@@ -100,8 +100,7 @@ EnableAvailableCores (
while (CoreCount--) {
for (Index = 0; Index < MAX_CORES; Index++) {
- if (GicC[Index].MPIDR == GET_MPID (ArmCoreInfoTable->ClusterId,
- ArmCoreInfoTable->CoreId)) {
+ if (GicC[Index].MPIDR == ArmCoreInfoTable->Mpidr) {
GicC[Index].Flags |= EFI_ACPI_5_1_GIC_ENABLED;
break;
}
diff --git a/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c b/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c
index 3f359ffbd2d8..45490aa33c5a 100644
--- a/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c
+++ b/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c
@@ -166,12 +166,12 @@ PlatInitPeiEntryPoint (
ASSERT (CpuResetInfo.CoreStatus.Status != CPU_CORE_DISABLED);
ASSERT (CpuResetInfo.CoreStatus.Status != CPU_CORE_UNDEFINED);
- mAmdMpCoreInfoTable[Index].ClusterId = CpuResetInfo.CoreStatus.ClusterId;
- mAmdMpCoreInfoTable[Index].CoreId = CpuResetInfo.CoreStatus.CoreId;
+ mAmdMpCoreInfoTable[Index].Mpidr = GET_MPID (CpuResetInfo.CoreStatus.ClusterId,
+ CpuResetInfo.CoreStatus.CoreId);
DEBUG ((EFI_D_ERROR, "Core[%d]: ClusterId = %d CoreId = %d\n",
- Index, mAmdMpCoreInfoTable[Index].ClusterId,
- mAmdMpCoreInfoTable[Index].CoreId));
+ Index, GET_MPIDR_AFF1 (mAmdMpCoreInfoTable[Index].Mpidr),
+ GET_MPIDR_AFF0 (mAmdMpCoreInfoTable[Index].Mpidr)));
// Next core in Table
++Index;
diff --git a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c
index 75e529021d09..178fb5698504 100644
--- a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c
+++ b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c
@@ -50,7 +50,7 @@ ClusterInRange (
)
{
do {
- if (ClusterId == ArmCoreInfoTable[LowIndex].ClusterId)
+ if (ClusterId == GET_MPIDR_AFF1 (ArmCoreInfoTable[LowIndex].Mpidr))
return TRUE;
} while (++LowIndex <= HighIndex);
@@ -70,7 +70,7 @@ NumberOfCoresInCluster (
Cores = 0;
for (Index = 0; Index < NumberOfEntries; ++Index) {
- if (ClusterId == ArmCoreInfoTable[Index].ClusterId)
+ if (ClusterId == GET_MPIDR_AFF1 (ArmCoreInfoTable[Index].Mpidr))
++Cores;
}
@@ -92,7 +92,7 @@ NumberOfClustersInTable (
Cores = NumberOfEntries;
while (Cores) {
++Clusters;
- ClusterId = ArmCoreInfoTable[Index].ClusterId;
+ ClusterId = GET_MPIDR_AFF1 (ArmCoreInfoTable[Index].Mpidr);
Cores -= NumberOfCoresInCluster (ArmCoreInfoTable,
NumberOfEntries,
ClusterId);
@@ -100,7 +100,7 @@ NumberOfClustersInTable (
do {
++Index;
} while (ClusterInRange (ArmCoreInfoTable,
- ArmCoreInfoTable[Index].ClusterId,
+ GET_MPIDR_AFF1 (ArmCoreInfoTable[Index].Mpidr),
0, Index-1));
}
}
@@ -402,8 +402,7 @@ PrepareFdt (
fdt_setprop_string (Fdt, CpuNode, "enable-method", "psci");
- MpId = (UINTN)GET_MPID (ArmCoreInfoTable[Index].ClusterId,
- ArmCoreInfoTable[Index].CoreId);
+ MpId = ArmCoreInfoTable[Index].Mpidr;
MpId = cpu_to_fdt64 (MpId);
fdt_setprop (Fdt, CpuNode, "reg", &MpId, sizeof (MpId));
fdt_setprop (Fdt, CpuNode, "compatible", mCpuCompatible,
@@ -417,7 +416,7 @@ PrepareFdt (
fdt_setprop_cell (Fdt, CpuNode, "d-cache-line-size", 64);
fdt_setprop_cell (Fdt, CpuNode, "d-cache-sets", 256);
fdt_setprop_cell (Fdt, CpuNode, "l2-cache",
- L2Phandle[ArmCoreInfoTable[Index].ClusterId]);
+ L2Phandle[GET_MPIDR_AFF1 (ArmCoreInfoTable[Index].Mpidr)]);
}
// Create /cpu-map node
@@ -435,7 +434,7 @@ PrepareFdt (
return EFI_INVALID_PARAMETER;
}
- ClusterId = ArmCoreInfoTable[ClusterIndex].ClusterId;
+ ClusterId = GET_MPIDR_AFF1 (ArmCoreInfoTable[ClusterIndex].Mpidr);
CoreIndex = ClusterIndex;
CoresInCluster = NumberOfCoresInCluster (ArmCoreInfoTable,
ArmCoreCount,
@@ -454,7 +453,7 @@ PrepareFdt (
if (CoresInCluster) {
do {
--CoreIndex;
- } while (ClusterId != ArmCoreInfoTable[CoreIndex].ClusterId);
+ } while (ClusterId != GET_MPIDR_AFF1 (ArmCoreInfoTable[CoreIndex].Mpidr));
}
}
@@ -463,7 +462,7 @@ PrepareFdt (
do {
--ClusterIndex;
} while (ClusterInRange (ArmCoreInfoTable,
- ArmCoreInfoTable[ClusterIndex].ClusterId,
+ GET_MPIDR_AFF1 (ArmCoreInfoTable[ClusterIndex].Mpidr),
ClusterIndex + 1,
ArmCoreCount - 1));
}
@@ -481,8 +480,7 @@ PrepareFdt (
// append PMU interrupts
for (Index = 0; Index < ArmCoreCount; Index++) {
- MpId = (UINTN)GET_MPID (ArmCoreInfoTable[Index].ClusterId,
- ArmCoreInfoTable[Index].CoreId);
+ MpId = (UINTN)ArmCoreInfoTable[Index].Mpidr;
Status = AmdMpCoreInfoProtocol->GetPmuSpiFromMpId (MpId, &PmuInt.IntId);
if (EFI_ERROR (Status)) {
--
2.31.1
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