[edk2-devel] [PATCH 26/40] TigerlakeSiliconPkg/IpBlock: Add Sata component
Heng Luo
heng.luo at intel.com
Mon Feb 1 01:36:43 UTC 2021
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* IpBlock/Sata/Library
Cc: Sai Chaganty <rangasai.v.chaganty at intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone at intel.com>
Signed-off-by: Heng Luo <heng.luo at intel.com>
---
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/PeiDxeSmmSataLibVer2.inf | 32 ++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/SataLib.c | 138 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/SataLibVer2.c | 83 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 253 insertions(+)
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/PeiDxeSmmSataLibVer2.inf b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/PeiDxeSmmSataLibVer2.inf
new file mode 100644
index 0000000000..1c304fed59
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/PeiDxeSmmSataLibVer2.inf
@@ -0,0 +1,32 @@
+## @file
+# PEI/DXE/SMM PCH SATA library Ver2
+#
+# All function in this library is available for PEI, DXE, and SMM,
+# But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPchSataLibVer2
+FILE_GUID = 2519ADE8-D971-4551-8A8E-2EB55DFC555B
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = SataLib
+
+[LibraryClasses]
+BaseLib
+PciSegmentLib
+PchInfoLib
+PchPciBdfLib
+
+[Packages]
+MdePkg/MdePkg.dec
+TigerlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+SataLib.c
+SataLibVer2.c
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/SataLib.c b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/SataLib.c
new file mode 100644
index 0000000000..49cba49910
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/SataLib.c
@@ -0,0 +1,138 @@
+/** @file
+ Pch SATA library.
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/SataLib.h>
+#include <Register/PchRegs.h>
+#include <Register/SataRegs.h>
+#include <Library/PchPciBdfLib.h>
+
+/**
+ Get SATA controller address that can be passed to the PCI Segment Library functions.
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval SATA controller address in PCI Segment Library representation
+**/
+UINT64
+SataRegBase (
+ IN UINT32 SataCtrlIndex
+ )
+{
+ ASSERT (SataCtrlIndex < MaxSataControllerNum ());
+
+ return SataPciCfgBase (SataCtrlIndex);
+}
+
+/**
+ Get SATA controller's Port Present Status
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval Port Present Status
+**/
+UINT8
+GetSataPortPresentStatus (
+ IN UINT32 SataCtrlIndex
+ )
+{
+ ASSERT (SataCtrlIndex < MaxSataControllerNum ());
+
+ return PciSegmentRead8 (SataPciCfgBase (SataCtrlIndex) + R_SATA_CFG_PCS + 2);
+}
+
+/**
+ Get SATA controller Function Disable Status
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval 0 SATA Controller is not Function Disabled
+ @retval 1 SATA Controller is Function Disabled
+**/
+BOOLEAN
+SataControllerFunctionDisableStatus (
+ IN UINT32 SataCtrlIndex
+ )
+{
+ UINT32 SataGc;
+ ASSERT (SataCtrlIndex < MaxSataControllerNum ());
+ SataGc = PciSegmentRead32 (SataPciCfgBase (SataCtrlIndex) + R_SATA_CFG_SATAGC);
+ return !!(SataGc & BIT10);
+}
+
+/**
+ Get SATA controller ABAR size
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval SATA controller ABAR size
+**/
+UINT32
+GetSataAbarSize (
+ IN UINT32 SataCtrlIndex
+ )
+{
+ UINT32 SataGc;
+ ASSERT (SataCtrlIndex < MaxSataControllerNum ());
+ SataGc = PciSegmentRead32 (SataPciCfgBase (SataCtrlIndex) + R_SATA_CFG_SATAGC);
+
+ switch (SataGc & B_SATA_CFG_SATAGC_ASSEL) {
+ case V_SATA_CFG_SATAGC_ASSEL_2K:
+ return SIZE_2KB;
+ break;
+
+ case V_SATA_CFG_SATAGC_ASSEL_16K:
+ return SIZE_16KB;
+ break;
+
+ case V_SATA_CFG_SATAGC_ASSEL_32K:
+ return SIZE_32KB;
+ break;
+
+ case V_SATA_CFG_SATAGC_ASSEL_64K:
+ return SIZE_64KB;
+ break;
+
+ case V_SATA_CFG_SATAGC_ASSEL_128K:
+ return SIZE_128KB;
+ break;
+
+ case V_SATA_CFG_SATAGC_ASSEL_512K:
+ return SIZE_256KB;
+ break;
+
+ default:
+ return SIZE_2KB;
+ break;
+ }
+}
+
+/**
+ Get SATA controller AHCI base address
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval SATA controller AHCI base address
+**/
+UINT32
+GetSataAhciBase (
+ IN UINT32 SataCtrlIndex
+ )
+{
+ ASSERT (SataCtrlIndex < MaxSataControllerNum ());
+
+ return PciSegmentRead32 (SataPciCfgBase (SataCtrlIndex) + R_SATA_CFG_AHCI_BAR) & 0xFFFFF800;
+}
+
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/SataLibVer2.c b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/SataLibVer2.c
new file mode 100644
index 0000000000..cde74e4e76
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/SataLibVer2.c
@@ -0,0 +1,83 @@
+/** @file
+ Pch SATA library.
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/DebugLib.h>
+#include <Library/PchInfoLib.h>
+#include <PchLimits.h>
+#include <Register/SataRegs.h>
+#include <Library/SataLib.h>
+
+/**
+ Get Maximum Sata Controller Number
+
+ @retval Maximum Sata Controller Number
+**/
+UINT8
+MaxSataControllerNum (
+ VOID
+ )
+{
+ return 1;
+}
+
+/**
+ Get Maximum Sata Port Number
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval Maximum Sata Port Number
+**/
+UINT8
+MaxSataPortNum (
+ IN UINT32 SataCtrlIndex
+ )
+{
+ ASSERT (SataCtrlIndex < MaxSataControllerNum ());
+
+ return 2;
+}
+
+/**
+ Check if SATA controller supports RST remapping
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval TRUE Controller supports remapping
+ @retval FALSE Controller does not support remapping
+
+**/
+BOOLEAN
+IsRemappingSupportedOnSata (
+ IN UINT32 SataCtrlIndex
+ )
+{
+ ASSERT (SataCtrlIndex < MaxSataControllerNum ());
+
+ return FALSE;
+}
+
+/**
+ Checks if SoC supports the SATA PGD power down on given
+ SATA controller.
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval TRUE SATA PGD power down supported
+ @retval FALSE SATA PGD power down not supported
+**/
+BOOLEAN
+IsSataPowerGatingSupported (
+ IN UINT32 SataCtrlIndex
+ )
+{
+ return TRUE;
+}
+
--
2.24.0.windows.2
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