[edk2-devel] [PATCH 11/40] TigerlakeSiliconPkg/Fru: Add TglPch/Include headers
Nate DeSimone
nathaniel.l.desimone at intel.com
Thu Feb 4 03:53:46 UTC 2021
Reviewed-by: Nate DeSimone <nathaniel.l.desimone at intel.com>
> -----Original Message-----
> From: Luo, Heng <heng.luo at intel.com>
> Sent: Sunday, January 31, 2021 5:36 PM
> To: devel at edk2.groups.io
> Cc: Chaganty, Rangasai V <rangasai.v.chaganty at intel.com>; Desimone,
> Nathaniel L <nathaniel.l.desimone at intel.com>
> Subject: [PATCH 11/40] TigerlakeSiliconPkg/Fru: Add TglPch/Include headers
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
>
> Adds the following header files:
> * Fru/TglPch/Include
>
> Cc: Sai Chaganty <rangasai.v.chaganty at intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone at intel.com>
> Signed-off-by: Heng Luo <heng.luo at intel.com>
> ---
> Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchBdfAssignment.h
> | 326
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchPcieRpInfo.h |
> 16 ++++++++++++++++
>
> Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchReservedResources.
> h | 55
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 397 insertions(+)
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchBdfAssignment.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchBdfAssignment.h
> new file mode 100644
> index 0000000000..0d00f25d5e
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchBdfAssignment.h
> @@ -0,0 +1,326 @@
> +/** @file
>
> + Header file for TigerLake PCH devices PCI Bus Device Function map.
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _PCH_BDF_ASSIGNMENT_H_
>
> +#define _PCH_BDF_ASSIGNMENT_H_
>
> +
>
> +#define NOT_PRESENT 0xFF
>
> +
>
> +#define MAX_SATA_CONTROLLER 1
>
> +
>
> +//
>
> +// PCH PCIe Controllers
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_1 28
>
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_2 28
>
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_3 28
>
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_4 28
>
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_5 28
>
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_6 28
>
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_7 28
>
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_8 28
>
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_9 29
>
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_10 29
>
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_11 29
>
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_12 29
>
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_13 29
>
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_14 29
>
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_15 29
>
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_16 29
>
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_17 27
>
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_18 27
>
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_19 27
>
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_20 27
>
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_21 27
>
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_22 27
>
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_23 27
>
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_24 27
>
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_25
> NOT_PRESENT
>
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_26
> NOT_PRESENT
>
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_27
> NOT_PRESENT
>
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_28
> NOT_PRESENT
>
> +
>
> +//
>
> +// USB3 (XHCI) Controller PCI config
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_XHCI 20
>
> +#define PCI_FUNCTION_NUMBER_PCH_XHCI 0
>
> +
>
> +//
>
> +// xDCI (OTG) USB Device Controller
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_XDCI 20
>
> +#define PCI_FUNCTION_NUMBER_PCH_XDCI 1
>
> +
>
> +//
>
> +// Thermal Device
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_THERMAL NOT_PRESENT
>
> +#define PCI_FUNCTION_NUMBER_PCH_THERMAL NOT_PRESENT
>
> +
>
> +//
>
> +// CSME HECI #1
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_HECI1 22
>
> +#define PCI_FUNCTION_NUMBER_PCH_HECI1 0
>
> +
>
> +//
>
> +// CSME HECI #2
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_HECI2 22
>
> +#define PCI_FUNCTION_NUMBER_PCH_HECI2 1
>
> +
>
> +//
>
> +// CSME IDE-Redirection (IDE-R)
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_IDER 22
>
> +#define PCI_FUNCTION_NUMBER_PCH_IDER 2
>
> +
>
> +//
>
> +// CSME Keyboard and Text (KT) Redirection
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_KTR 22
>
> +#define PCI_FUNCTION_NUMBER_PCH_KTR 3
>
> +
>
> +//
>
> +// CSME HECI #3
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_HECI3 22
>
> +#define PCI_FUNCTION_NUMBER_PCH_HECI3 4
>
> +
>
> +//
>
> +// CSME HECI #4
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_HECI4 22
>
> +#define PCI_FUNCTION_NUMBER_PCH_HECI4 5
>
> +
>
> +//
>
> +// CSME MROM
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_MROM NOT_PRESENT
>
> +#define PCI_FUNCTION_NUMBER_PCH_MROM NOT_PRESENT
>
> +
>
> +//
>
> +// CSME WLAN
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_WLAN 22
>
> +#define PCI_FUNCTION_NUMBER_PCH_WLAN 7
>
> +
>
> +//
>
> +// SATA Controllers
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_SATA_1 23
>
> +#define PCI_FUNCTION_NUMBER_PCH_SATA_1 0
>
> +#define PCI_DEVICE_NUMBER_PCH_SATA_2 NOT_PRESENT
>
> +#define PCI_FUNCTION_NUMBER_PCH_SATA_2 NOT_PRESENT
>
> +#define PCI_DEVICE_NUMBER_PCH_SATA_3 NOT_PRESENT
>
> +#define PCI_FUNCTION_NUMBER_PCH_SATA_3 NOT_PRESENT
>
> +
>
> +//
>
> +// PCH LP Serial IO I2C #0 Controller
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C0 21
>
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C0 0
>
> +
>
> +//
>
> +// PCH LP Serial IO I2C #1 Controller
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C1 21
>
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C1 1
>
> +
>
> +//
>
> +// PCH LP Serial IO I2C #2 Controller
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C2 21
>
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C2 2
>
> +
>
> +//
>
> +// PCH LP Serial IO I2C #3 Controller
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C3 21
>
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C3 3
>
> +
>
> +//
>
> +// PCH LP Serial IO I2C #4 Controller
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C4 25
>
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C4 0
>
> +
>
> +//
>
> +// PCH LP Serial IO I2C #5 Controller
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C5 25
>
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C5 1
>
> +
>
> +//
>
> +// PCH LP Serial IO I2C #6 Controller
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C6 16
>
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C6 0
>
> +
>
> +//
>
> +// PCH LP Serial IO I2C #7 Controller
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C7 16
>
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C7 1
>
> +
>
> +//
>
> +// PCH LP Serial IO SPI #0 Controller
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI0 30
>
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI0 2
>
> +
>
> +//
>
> +// PCH LP Serial IO SPI #1 Controller
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI1 30
>
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI1 3
>
> +
>
> +//
>
> +// PCH LP Serial IO SPI #2 Controller
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI2 18
>
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI2 6
>
> +
>
> +//
>
> +// PCH LP Serial IO SPI #3 Controller
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI3 19
>
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI3 0
>
> +
>
> +//
>
> +// PCH LP Serial IO SPI #4 Controller
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI4 19
>
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI4 1
>
> +
>
> +//
>
> +// PCH LP Serial IO SPI #5 Controller
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI5 19
>
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI5 2
>
> +
>
> +//
>
> +// PCH LP Serial IO SPI #6 Controller
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI6 19
>
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI6 3
>
> +
>
> +//
>
> +// PCH LP Serial IO UART #0 Controller
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART0 30
>
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART0 0
>
> +
>
> +//
>
> +// PCH LP Serial IO UART #1 Controller
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART1 30
>
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART1 1
>
> +
>
> +//
>
> +// PCH LP Serial IO UART #2 Controller
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART2 25
>
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART2 2
>
> +
>
> +//
>
> +// PCH LP Serial IO UART #3 Controller
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART3 17
>
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART3 0
>
> +
>
> +//
>
> +// PCH LP Serial IO UART #4 Controller
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART4 17
>
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART4 1
>
> +
>
> +//
>
> +// PCH LP Serial IO UART #5 Controller
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART5 17
>
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART5 2
>
> +
>
> +//
>
> +// PCH LP Serial IO UART #6 Controller
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART6 17
>
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART6 3
>
> +
>
> +//
>
> +// DMA-SMBus Controller
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_DMA_SMBUS 30
>
> +#define PCI_FUNCTION_NUMBER_PCH_DMA_SMBUS 4
>
> +
>
> +//
>
> +// TSN GbE Controller #1
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_TSN0 30
>
> +#define PCI_FUNCTION_NUMBER_PCH_TSN0 4
>
> +
>
> +//
>
> +// TSN GbE Controller #2
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_TSN1 30
>
> +#define PCI_FUNCTION_NUMBER_PCH_TSN1 5
>
> +
>
> +//
>
> +// LPC Controller
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_LPC 31
>
> +#define PCI_FUNCTION_NUMBER_PCH_LPC 0
>
> +
>
> +//
>
> +// eSPI Controller
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_ESPI 31
>
> +#define PCI_FUNCTION_NUMBER_PCH_ESPI 0
>
> +
>
> +//
>
> +// Primary to Sideband (P2SB) Bridge
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_P2SB 31
>
> +#define PCI_FUNCTION_NUMBER_PCH_P2SB 1
>
> +
>
> +//
>
> +// PMC (D31:F2)
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_PMC 31
>
> +#define PCI_FUNCTION_NUMBER_PCH_PMC 2
>
> +
>
> +//
>
> +// PMC SSRAM Registers
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_PMC_SSRAM 20
>
> +#define PCI_FUNCTION_NUMBER_PCH_PMC_SSRAM 2
>
> +
>
> +//
>
> +// HD-A Controller
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_HDA 31
>
> +#define PCI_FUNCTION_NUMBER_PCH_HDA 3
>
> +
>
> +//
>
> +// SMBus Controller
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_SMBUS 31
>
> +#define PCI_FUNCTION_NUMBER_PCH_SMBUS 4
>
> +
>
> +//
>
> +// SPI Controller (D31:F5)
>
> +//
>
> +#define PCI_DEVICE_NUMBER_PCH_SPI 31
>
> +#define PCI_FUNCTION_NUMBER_PCH_SPI 5
>
> +
>
> +//
>
> +// Gigabit Ethernet LAN Controller (D31:F6)
>
> +//
>
> +#define PCI_DEVICE_NUMBER_GBE 31
>
> +#define PCI_FUNCTION_NUMBER_GBE 6
>
> +
>
> +#endif // _PCH_BDF_ASSIGNMENT_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchPcieRpInfo.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchPcieRpInfo.h
> new file mode 100644
> index 0000000000..d3548796a3
> --- /dev/null
> +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchPcieRpInfo.h
> @@ -0,0 +1,16 @@
> +/** @file
>
> + Pcie Root Port info header
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +
>
> +#ifndef _PCH_PCIERP_INFO_H_
>
> +#define _PCH_PCIERP_INFO_H_
>
> +
>
> +//
>
> +// Number of PCIe ports per PCIe controller
>
> +//
>
> +#define PCH_PCIE_CONTROLLER_PORTS 4u
>
> +
>
> +#endif
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchReservedResourc
> es.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchReservedResourc
> es.h
> new file mode 100644
> index 0000000000..283246692f
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchReservedResourc
> es.h
> @@ -0,0 +1,55 @@
> +/** @file
>
> + PCH preserved MMIO resource definitions.
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _PCH_PRESERVED_RESOURCES_H_
>
> +#define _PCH_PRESERVED_RESOURCES_H_
>
> +
>
> +/**
>
> + Detailed recommended static allocation
>
> + +-------------------------------------------------------------------------+
>
> + | PCH preserved MMIO range, 32 MB, from 0xFC800000 to 0xFE7FFFFF
> |
>
> + +-------------------------------------------------------------------------+
>
> + | Size | Start | End | Usage |
>
> + | 8 MB | 0xFC800000 | 0xFCFFFFFF | TraceHub SW BAR |
>
> + | 16 MB | 0xFD000000 | 0xFDFFFFFF | SBREG |
>
> + | 64 KB | 0xFE000000 | 0xFE00FFFF | PMC MBAR |
>
> + | 4 KB | 0xFE010000 | 0xFE010FFF | SPI BAR0 |
>
> + | 176 KB | 0xFE020000 | 0xFE04BFFF | SerialIo BAR in ACPI mode |
>
> + | 400 KB | 0xFE04C000 | 0xFE0AFFFF | Unused |
>
> + | 64 KB | 0xFE0B0000 | 0xFE0BFFFF | eSPI LGMR BAR |
>
> + | 64 KB | 0xFE0C0000 | 0xFE0CFFFF | eSPI2 SEGMR BAR |
>
> + | 192 KB | 0xFE0D0000 | 0xFE0FFFFF | Unused |
>
> + | 1 MB | 0xFE100000 | 0xFE1FFFFF | TraceHub MTB BAR |
>
> + | 2 MB | 0xFE200000 | 0xFE3FFFFF | TraceHub FW BAR |
>
> + | 2 MB | 0xFE400000 | 0xFE5FFFFF | Unused |
>
> + | 2 MB | 0xFE600000 | 0xFE7FFFFF | Temp address |
>
> + +-------------------------------------------------------------------------+
>
> +**/
>
> +#define PCH_PRESERVED_BASE_ADDRESS 0xFC800000 ///< Pch
> preserved MMIO base address
>
> +#define PCH_PRESERVED_MMIO_SIZE 0x02000000 ///< 32MB
>
> +#define PCH_TRACE_HUB_SW_BASE_ADDRESS 0xFC800000 ///<
> TraceHub SW MMIO base address
>
> +#define PCH_TRACE_HUB_SW_MMIO_SIZE 0x00800000 ///< 8MB
>
> +#define PCH_PCR_BASE_ADDRESS 0xFD000000 ///< SBREG MMIO
> base address
>
> +#define PCH_PCR_MMIO_SIZE 0x01000000 ///< 16MB
>
> +#define PCH_PWRM_BASE_ADDRESS 0xFE000000 ///< PMC MBAR
> MMIO base address
>
> +#define PCH_PWRM_MMIO_SIZE 0x00010000 ///< 64KB
>
> +#define PCH_SPI_BASE_ADDRESS 0xFE010000 ///< SPI BAR0 MMIO
> base address
>
> +#define PCH_SPI_MMIO_SIZE 0x00001000 ///< 4KB
>
> +#define PCH_SERIAL_IO_BASE_ADDRESS 0xFE020000 ///< SerialIo
> MMIO base address
>
> +#define PCH_SERIAL_IO_MMIO_SIZE 0x0002C000 ///< 176KB
>
> +#define PCH_ESPI_LGMR_BASE_ADDRESS 0xFE0B0000 ///< eSPI LGMR
> MMIO base address
>
> +#define PCH_ESPI_LGMR_MMIO_SIZE 0x00010000 ///< 64KB
>
> +#define PCH_ESPI_SEGMR_BASE_ADDRESS 0xFE0C0000 ///< Second
> eSPI GMR MMIO base address
>
> +#define PCH_ESPI_SEGMR_MMIO_SIZE 0x00010000 ///< 64KB
>
> +#define PCH_TRACE_HUB_MTB_BASE_ADDRESS 0xFE100000 ///<
> TraceHub MTB MMIO base address
>
> +#define PCH_TRACE_HUB_MTB_MMIO_SIZE 0x00100000 ///< 1MB
>
> +#define PCH_TRACE_HUB_FW_BASE_ADDRESS 0xFE200000 ///<
> TraceHub FW MMIO base address
>
> +#define PCH_TRACE_HUB_FW_MMIO_SIZE 0x00200000 ///< 2MB
>
> +#define PCH_TEMP_BASE_ADDRESS 0xFE600000 ///< preserved
> temp address for misc usage,
>
> +#define PCH_TEMP_MMIO_SIZE 0x00200000 ///< 2MB
>
> +
>
> +#endif // _PCH_PRESERVED_RESOURCES_H_
>
> +
>
> --
> 2.24.0.windows.2
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