[edk2-devel] [PATCH 39/40] TigerlakeSiliconPkg: Add package DSC files
Nate DeSimone
nathaniel.l.desimone at intel.com
Thu Feb 4 03:56:47 UTC 2021
Hi Heng,
Please see comments inline.
Thanks,
Nate
> -----Original Message-----
> From: Luo, Heng <heng.luo at intel.com>
> Sent: Sunday, January 31, 2021 5:37 PM
> To: devel at edk2.groups.io
> Cc: Chaganty, Rangasai V <rangasai.v.chaganty at intel.com>; Desimone,
> Nathaniel L <nathaniel.l.desimone at intel.com>
> Subject: [PATCH 39/40] TigerlakeSiliconPkg: Add package DSC files
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
>
> Cc: Sai Chaganty <rangasai.v.chaganty at intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone at intel.com>
> Signed-off-by: Heng Luo <heng.luo at intel.com>
> ---
> Silicon/Intel/TigerlakeSiliconPkg/SiPkgBuildOption.dsc | 122
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++
> Silicon/Intel/TigerlakeSiliconPkg/SiPkgCommonLib.dsc | 49
> +++++++++++++++++++++++++++++++++++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/SiPkgDxe.dsc | 47
> +++++++++++++++++++++++++++++++++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/SiPkgDxeLib.dsc | 40
> ++++++++++++++++++++++++++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/SiPkgPei.dsc | 20
> ++++++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/SiPkgPeiLib.dsc | 20
> ++++++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc | 229
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++
> 7 files changed, 527 insertions(+)
>
> diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SiPkgBuildOption.dsc
> b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgBuildOption.dsc
> new file mode 100644
> index 0000000000..51c40812ea
> --- /dev/null
> +++ b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgBuildOption.dsc
> @@ -0,0 +1,122 @@
> +## @file
>
> +# Silicon build option configuration file.
>
> +#
>
> +# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +#
>
> +##
>
> +
>
> +[BuildOptions]
>
> +# Define Build Options both for EDK and EDKII drivers.
>
> +
>
> + DEFINE PCH_BUILD_OPTIONS = -DPCH_TGL
>
> +#
>
> +# SA
>
> +#
>
> +!if gSiPkgTokenSpaceGuid.PcdBdatEnable == TRUE
>
> + DEFINE BDAT_BUILD_OPTION = -DBDAT_SUPPORT=1
>
> +!else
>
> + DEFINE BDAT_BUILD_OPTION =
>
> +!endif
>
> +
>
> + DEFINE SLE_BUILD_OPTIONS =
>
> +!if $(TARGET) == RELEASE
>
> +!if gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable == TRUE
>
> + DEFINE DEBUG_BUILD_OPTIONS =
>
> +!else
>
> + # MDEPKG_NDEBUG is introduced for the intention
>
> + # of size reduction when compiler optimization is disabled. If
> MDEPKG_NDEBUG is
>
> + # defined, then debug and assert related macros wrapped by it are the
> NULL implementations.
>
> + DEFINE DEBUG_BUILD_OPTIONS = -DMDEPKG_NDEBUG
>
> +!endif
>
> +!else
>
> + DEFINE DEBUG_BUILD_OPTIONS =
>
> +!endif
>
> +
>
> +!if ($(TARGET) == RELEASE) AND
> (gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable == TRUE)
>
> + DEFINE RELEASE_CATALOG_BUILD_OPTIONS = -DRELEASE_CATALOG
>
> +!else
>
> + DEFINE RELEASE_CATALOG_BUILD_OPTIONS =
>
> +!endif
>
> +
>
> +!if gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable == FALSE
>
> + DEFINE OPTIMIZE_DISABLE_OPTIONS = -Od -GL-
>
> +!else
>
> + DEFINE OPTIMIZE_DISABLE_OPTIONS =
>
> +!endif
>
> +
>
> + DEFINE HSLE_BUILD_OPTIONS =
>
> +
>
> +
>
> + DEFINE CPU_FLAGS = -DCPU_ICL -DCPU_TGL
>
> +
>
> +
>
> + DEFINE RESTRICTED_OPTION =
>
> +
>
> +!if gSiPkgTokenSpaceGuid.PcdMrcTraceMessageSupported == FALSE
>
> + *_*_*_MRC_NDEBUG = -DMDEPKG_NDEBUG
>
> +!endif
>
> +
>
> +DEFINE DSC_SIPKG_FEATURE_BUILD_OPTIONS = $(BDAT_BUILD_OPTION)
> $(DEBUG_BUILD_OPTIONS)
>
> +DEFINE DSC_SIPKG_FEATURE_BUILD_OPTIONS =
> $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(PCH_BUILD_OPTIONS)
> $(CPU_FLAGS) $(HSLE_BUILD_OPTIONS)
>
> +
>
> +!if gSiPkgTokenSpaceGuid.PcdSourceDebugEnable == TRUE
>
> + *_*_X64_GENFW_FLAGS = --keepexceptiontable
>
> +!endif
>
> +
>
> +[BuildOptions.Common.EDKII]
>
> +
>
> +#
>
> +# For IA32 Global Build Flag
>
> +#
>
> + *_*_IA32_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D
> PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI
>
> + *_*_IA32_VFRPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
>
> + *_*_IA32_APP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
>
> + *_*_IA32_ASLPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
>
> + *_*_IA32_ASLCC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
>
> +
>
> +#
>
> +# For IA32 Specific Build Flag
>
> +#
>
> +GCC: *_*_IA32_PP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
>
> +MSFT: *_*_IA32_ASM_FLAGS =
> $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
>
> +MSFT: *_*_IA32_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
> $(OPTIMIZE_DISABLE_OPTIONS) -D
> PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI /w34668
>
> +MSFT: *_*_IA32_VFRPP_FLAGS =
> $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
>
> +MSFT: *_*_IA32_APP_FLAGS =
> $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
>
> +MSFT: *_*_IA32_ASLPP_FLAGS =
> $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
>
> +MSFT: *_*_IA32_ASLCC_FLAGS =
> $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
>
> +
>
> +#
>
> +# For X64 Global Build Flag
>
> +#
>
> + *_*_X64_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D
> PI_SPECIFICATION_VERSION=0x00010015
>
> + *_*_X64_VFRPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
>
> + *_*_X64_APP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
>
> + *_*_X64_ASLPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
>
> + *_*_X64_ASLCC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
>
> +
>
> +#
>
> +# For X64 Specific Build Flag
>
> +#
>
> +GCC: *_*_X64_PP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
>
> +MSFT: *_*_X64_ASM_FLAGS =
> $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
>
> +MSFT: *_*_X64_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
> $(OPTIMIZE_DISABLE_OPTIONS) -D
> PI_SPECIFICATION_VERSION=0x00010015 /w34668
>
> +MSFT: *_*_X64_VFRPP_FLAGS =
> $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
>
> +MSFT: *_*_X64_APP_FLAGS =
> $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
>
> +MSFT: *_*_X64_ASLPP_FLAGS =
> $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
>
> +MSFT: *_*_X64_ASLCC_FLAGS =
> $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
>
> +
>
> +#
>
> +# For Xcode Specific Build Flag
>
> +#
>
> +# Override assembly code build order
>
> +*_XCODE5_*_*_BUILDRULEORDER = nasm S s
>
> +# Align 47bfbd7f8069e523798ef973c8eb0abd5c6b0746 to fix the usage of
> VA_START in undefined way
>
> +*_XCODE5_*_CC_FLAGS = -Wno-varargs
>
> +
>
> +# Force PE/COFF sections to be aligned at 4KB boundaries to support page
> level protection of runtime modules
>
> +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
>
> + MSFT: *_*_*_DLINK_FLAGS = /ALIGN:4096
>
> + GCC: *_GCC*_*_DLINK_FLAGS = -z common-page-size=0x1000
>
> +
>
> +
>
> diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SiPkgCommonLib.dsc
> b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgCommonLib.dsc
> new file mode 100644
> index 0000000000..d93ecfc9d6
> --- /dev/null
> +++ b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgCommonLib.dsc
> @@ -0,0 +1,49 @@
> +## @file
>
> +# Component description file for the TigerLake silicon package both Pei and
> Dxe libraries DSC file.
>
> +#
>
> +# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +#
>
> +##
>
> +
>
> +#
>
> +# Set PCH generation according PCD.
>
> +# The DEFINE will be used to select PCH library INF file corresponding to PCH
> generation
>
> +#
>
> +DEFINE PCH = Cnl
This define is not used. Please delete it.
>
> +
>
> +#
>
> +# FRUs
>
> +#
>
> +!include $(PLATFORM_SI_PACKAGE)/Fru/TglCpu/CommonLib.dsc
>
> +!include $(PLATFORM_SI_PACKAGE)/Fru/TglPch/CommonLib.dsc
>
> +
>
> +#
>
> +# Common
>
> +#
>
> +
> MmPciLib|$(PLATFORM_SI_PACKAGE)/Library/PeiDxeSmmMmPciLib/PeiDx
> eSmmMmPciLib.inf
>
> +
> PciSegmentLib|$(PLATFORM_SI_PACKAGE)/Library/BasePciSegmentMultiSe
> gLibPci/BasePciSegmentMultiSegLibPci.inf
>
> +
>
> +#
>
> +# Pch
>
> +#
>
> +
> PchCycleDecodingLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmP
> chCycleDecodingLib/PeiDxeSmmPchCycleDecodingLib.inf
>
> +
> PchInfoLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchInfoLib/
> PeiDxeSmmPchInfoLibTgl.inf
>
> +
> CpuPcieInitCommonLib|$(PLATFORM_SI_PACKAGE)/IpBlock/CpuPcieRp/Libr
> ary/PeiDxeSmmCpuPcieInitCommonLib/PeiDxeSmmCpuPcieInitCommonLib.i
> nf
>
> +
> CpuPcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/CpuPcieRp/Library/PeiDx
> eSmmCpuPcieRpLib/PeiDxeSmmCpuPcieRpLib.inf
>
> +
>
> +
> SerialIoAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/SerialIo/Library/PeiDx
> eSmmSerialIoAccessLib/PeiDxeSmmSerialIoAccessLib.inf
>
> +
> SerialIoPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/SerialIo/LibraryPrivat
> e/PeiDxeSmmSerialIoPrivateLib/PeiDxeSmmSerialIoPrivateLibVer2.inf
>
> +
> ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/BaseResetSystem
> Lib/BaseResetSystemLib.inf
>
> + #private
>
> +
> GpioPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/Pei
> DxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
>
> +
>
> +
> SiScheduleResetLib|$(PLATFORM_SI_PACKAGE)/Pch/LibraryPrivate/BaseSiS
> cheduleResetLib/BaseSiScheduleResetLib.inf
>
> +
> PchPciBdfLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/BasePchPciBdfLib/Bas
> ePchPciBdfLib.inf
>
> +
> PcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PcieRp/LibraryPrivate/PcieCli
> entRpLib/PcieClientRpLib.inf
>
> +
>
> +#
>
> +# SA
>
> +#
>
> +
> SaPlatformLib|$(PLATFORM_SI_PACKAGE)/SystemAgent/Library/PeiDxeSm
> mSaPlatformLib/PeiDxeSmmSaPlatformLib.inf
>
> +
> CpuRegbarAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/Library/PeiD
> xeSmmCpuRegbarAccessLib/PeiDxeSmmCpuRegbarAccessLib.inf
>
> diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SiPkgDxe.dsc
> b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgDxe.dsc
> new file mode 100644
> index 0000000000..1a08fbc24c
> --- /dev/null
> +++ b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgDxe.dsc
> @@ -0,0 +1,47 @@
> +## @file
>
> +# Component description file for the TigerLake silicon package DXE drivers.
>
> +#
>
> +# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +#
>
> +##
>
> +
>
> +#
>
> +# FRUs
>
> +#
>
> +!include $(PLATFORM_SI_PACKAGE)/Fru/TglCpu/Dxe.dsc
>
> +!include $(PLATFORM_SI_PACKAGE)/Fru/TglPch/Dxe.dsc
>
> +
>
> +#
>
> +# Common
>
> +#
>
> +
>
> +#
>
> +# Pch
>
> +#
>
> + $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxeTgl.inf
>
> +
> $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmControl.inf
>
> +
>
> +
> $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSmiDispatcher.
> inf{
>
> + <LibraryClasses>
>
> +
> #SmiHandlerProfileLib|MdeModulePkg/Library/SmmSmiHandlerProfileLib/S
> mmSmiHandlerProfileLib.inf
>
> +
> SmiHandlerProfileLib|MdePkg/Library/SmiHandlerProfileLibNull/SmiHandler
> ProfileLibNull.inf
>
> + }
>
> + $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Smm/PchInitSmm.inf
>
> +
>
> +#
>
> +# SystemAgent
>
> +#
>
> +
>
> + $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf
>
> +
>
> + $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Smm/SaLateInitSmm.inf
> {
>
> + <LibraryClasses>
>
> +
> S3BootScriptLib|MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptL
> ibNull.inf
>
> + }
>
> +
>
> +!if gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE
>
> + $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf
>
> + $(PLATFORM_SI_PACKAGE)/IpBlock/Graphics/AcpiTables/IgfxSsdt.inf
>
> +!endif
>
> +
>
> diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SiPkgDxeLib.dsc
> b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgDxeLib.dsc
> new file mode 100644
> index 0000000000..210fb37332
> --- /dev/null
> +++ b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgDxeLib.dsc
> @@ -0,0 +1,40 @@
> +## @file
>
> +# Component description file for the TigerLake silicon package DXE libraries.
>
> +#
>
> +# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +#
>
> +##
>
> +
>
> +#
>
> +# Silicon Init Dxe Library
>
> +#
>
> +
>
> +#
>
> +# FRUs
>
> +#
>
> +!include $(PLATFORM_SI_PACKAGE)/Fru/TglCpu/DxeLib.dsc
>
> +!include $(PLATFORM_SI_PACKAGE)/Fru/TglPch/DxeLib.dsc
>
> +
>
> +#
>
> +# Common
>
> +#
>
> +SiConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseSiConfigBlockLib/
> BaseSiConfigBlockLib.inf
>
> +
>
> +#
>
> +# Pch
>
> +#
>
> +DxePchPolicyLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxePchPolicyLib/
> DxePchPolicyLib.inf
>
> +SmmPchPrivateLib|$(PLATFORM_SI_PACKAGE)/Pch/LibraryPrivate/SmmPc
> hPrivateLib/SmmPchPrivateLib.inf
>
> +
>
> +#
>
> +# SystemAgent
>
> +#
>
> +DxeSaPolicyLib|$(PLATFORM_SI_PACKAGE)/SystemAgent/Library/DxeSaP
> olicyLib/DxeSaPolicyLib.inf
>
> +DxeVtdPolicyLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Vtd/LibraryPrivate/D
> xeVtdPolicyLib/DxeVtdPolicyLib.inf
>
> +
>
> +#
>
> +# CPU PCIe IpBlock
>
> +#
>
> +
>
> +DxeCpuPcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/CpuPcieRp/LibraryP
> rivate/DxeCpuPcieRpLib/DxeCpuPcieRpLib.inf
>
> diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SiPkgPei.dsc
> b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgPei.dsc
> new file mode 100644
> index 0000000000..15fc5685a5
> --- /dev/null
> +++ b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgPei.dsc
> @@ -0,0 +1,20 @@
> +## @file
>
> +# Component description file for the TigerLake silicon package PEI drivers.
>
> +#
>
> +# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +#
>
> +##
>
> +
>
> +#
>
> +# Common
>
> +#
>
> +
>
> +#
>
> +# SystemAgent
>
> +#
>
> +
>
> +#
>
> +# Cpu
>
> +#
>
> +
>
> diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SiPkgPeiLib.dsc
> b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgPeiLib.dsc
> new file mode 100644
> index 0000000000..6f90ff02bb
> --- /dev/null
> +++ b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgPeiLib.dsc
> @@ -0,0 +1,20 @@
> +## @file
>
> +# Component description file for the TigerLake silicon package PEI libraries.
>
> +#
>
> +# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +#
>
> +##
>
> +
>
> +#
>
> +# Silicon Init Pei Library
>
> +#
>
> +
>
> +#
>
> +# FRUs
>
> +#
>
> +!include $(PLATFORM_SI_PACKAGE)/Fru/TglCpu/PeiLib.dsc
>
> +
>
> +!include $(PLATFORM_SI_PACKAGE)/Fru/TglPch/PeiLib.dsc
>
> +
>
> +
> SiConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseSiConfigBlockLib/B
> aseSiConfigBlockLib.inf
>
> diff --git a/Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc
> b/Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc
> new file mode 100644
> index 0000000000..73a2594887
> --- /dev/null
> +++ b/Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc
> @@ -0,0 +1,229 @@
> +## @file
>
> +# Component description file for the TigerLake silicon package DSC file.
>
> +#
>
> +# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +#
>
> +##
>
> +[Packages]
>
> +MdePkg/MdePkg.dec
>
> +UefiCpuPkg/UefiCpuPkg.dec
>
> +TigerlakeSiliconPkg/SiPkg.dec
>
> +
>
> +[PcdsFixedAtBuild]
>
> +gSiPkgTokenSpaceGuid.PcdSmmVariableEnable |TRUE
>
> +gSiPkgTokenSpaceGuid.PcdAtaEnable |FALSE
>
> +
>
> +gSiPkgTokenSpaceGuid.PcdAcpiEnable |TRUE
>
> +gSiPkgTokenSpaceGuid.PcdSourceDebugEnable |FALSE
>
> +gSiPkgTokenSpaceGuid.PcdPpmEnable |TRUE
>
> +gSiPkgTokenSpaceGuid.PcdPttEnable |FALSE
>
> +gSiPkgTokenSpaceGuid.PcdJhiEnable |FALSE
>
> +gSiPkgTokenSpaceGuid.PcdSmbiosEnable |TRUE
>
> +gSiPkgTokenSpaceGuid.PcdS3Enable |TRUE
>
> +gSiPkgTokenSpaceGuid.PcdOverclockEnable |FALSE
>
> +gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable |FALSE
>
> +gSiPkgTokenSpaceGuid.PcdBdatEnable |TRUE
>
> +gSiPkgTokenSpaceGuid.PcdIgdEnable |TRUE
>
> +gSiPkgTokenSpaceGuid.PcdPegEnable |TRUE
>
> +gSiPkgTokenSpaceGuid.PcdSaDmiEnable |TRUE
>
> +gSiPkgTokenSpaceGuid.PcdVtdEnable |TRUE
>
> +gSiPkgTokenSpaceGuid.PcdBiosGuardEnable |FALSE
> #BiosGuardModule.bin
>
> +gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable |TRUE
>
> +gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable |TRUE
>
> +gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable |FALSE
>
> +gSiPkgTokenSpaceGuid.PcdMrcTraceMessageSupported |TRUE
>
> +gSiPkgTokenSpaceGuid.PcdOcWdtEnable |TRUE
>
> +gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable |TRUE
>
> +
>
> +gSiPkgTokenSpaceGuid.PcdThcEnable |TRUE
>
> +gSiPkgTokenSpaceGuid.PcdPpamEnable |TRUE
>
> +gSiPkgTokenSpaceGuid.PcdEmbeddedEnable |0x0
>
> +gSiPkgTokenSpaceGuid.PcdCpuPcieEnable |TRUE
>
> +gSiPkgTokenSpaceGuid.PcdHybridStorageSupport |TRUE
>
> +
>
> +!if gSiPkgTokenSpaceGuid.PcdPpamEnable == TRUE
>
> +#
>
> +# PCD for State Save Support on DGR
>
> +# TRUE - SMM State Save region access is protected
>
> +# FALSE - SMM can have Read/Write access to SMM State Save region
>
> +#
>
> +gSiPkgTokenSpaceGuid.PcdSpsStateSaveEnable |FALSE
>
> +#
>
> +# PCD to enable SPA Support on DGR
>
> +# Note: This PCD is mainly used for Debugging purpose. Not recommended
> to set for End Product.
>
> +#
>
> +gSiPkgTokenSpaceGuid.PcdSpaEnable |FALSE
>
> +!endif
>
> +
>
> +[PcdsFixedAtBuild.common]
>
> +gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress |0xC0000000
>
> +gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress
> |gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
>
> +gSiPkgTokenSpaceGuid.PcdTemporaryPciExpressRegionLength
> |0x10000000
>
> +
>
> +[PcdsDynamicDefault.common]
>
> +gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength |0x10000000
>
> +## Specifies the AP wait loop state during POST phase.
>
> +# The value is defined as below.
>
> +# 1: Place AP in the Hlt-Loop state.
>
> +# 2: Place AP in the Mwait-Loop state.
>
> +# 3: Place AP in the Run-Loop state.
>
> +# @Prompt The AP wait loop state.
>
> +gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
>
> +## Specifies the AP target C-state for Mwait during POST phase.
>
> +# The default value 0 means C1 state.
>
> +# The value is defined as below.<BR><BR>
>
> +# @Prompt The specified AP target C-state for Mwait.
>
> +gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0
>
> +
>
> +[Defines]
>
> + PLATFORM_NAME = TigerlakeSiliconPkg
>
> + PLATFORM_GUID = CCD38CA7-61D3-4185-9CDA-A9FDF209CB31
>
> + PLATFORM_VERSION = 0.4
>
> + DSC_SPECIFICATION = 0x00010005
>
> + OUTPUT_DIRECTORY = Build/TigerlakeSiliconPkg
>
> + SUPPORTED_ARCHITECTURES = IA32|X64
>
> + BUILD_TARGETS = DEBUG|RELEASE
>
> + SKUID_IDENTIFIER = DEFAULT
>
> +
>
> + DEFINE PLATFORM_SI_PACKAGE = TigerlakeSiliconPkg
>
> + #
>
> + # Definition for Build Flag
>
> + #
>
> + !include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc
>
> +
>
> +[LibraryClasses.common]
>
> + #
>
> + # Entry point
>
> + #
>
> +
> PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.in
> f
>
> + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
>
> +
> DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint
> .inf
>
> +
> UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry
> Point.inf
>
> +
> UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA
> pplicationEntryPoint.inf
>
> +
> PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BaseP
> eCoffExtraActionLibNull.inf
>
> +
>
> + #
>
> + # Basic
>
> + #
>
> + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
>
> +
> BaseMemoryLib|MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibR
> epStr.inf
>
> + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
>
> + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
>
> + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
>
> +
> PciSegmentLib|$(PLATFORM_SI_PACKAGE)/Library/BasePciSegmentMultiSe
> gLibPci/BasePciSegmentMultiSegLibPci.inf
>
> + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
>
> + PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
>
> +
> CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCac
> heMaintenanceLib.inf
>
> + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
>
> +
> PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/Base
> PeCoffGetEntryPointLib.inf
>
> + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
>
> +
> PostCodeLib|MdePkg/Library/BasePostCodeLibPort80/BasePostCodeLibPort
> 80.inf
>
> +
>
> + #
>
> + # UEFI & PI
>
> + #
>
> +
> UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBo
> otServicesTableLib.inf
>
> +
> UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib
> /UefiRuntimeServicesTableLib.inf
>
> + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
>
> + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
>
> + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
>
> +
> PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/P
> eiServicesTablePointerLibIdt.inf
>
> + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
>
> + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
>
> +
> DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTabl
> eLib.inf
>
> +
>
> +
> S3BootScriptLib|MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptL
> ibNull.inf
>
> + S3IoLib|MdePkg/Library/BaseS3IoLib/BaseS3IoLib.inf
>
> + S3PciLib|MdePkg/Library/BaseS3PciLib/BaseS3PciLib.inf
>
> +
>
> + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
>
> + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
>
> +
> SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchroniz
> ationLib.inf
>
> +
>
> +
> DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/Bas
> eDebugPrintErrorLevelLib.inf
>
> +
>
> + #
>
> + # Misc
>
> + #
>
> + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
>
> +
> PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanc
> eLibNull.inf
>
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
>
> +
> TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTem
> plate.inf
>
> +
> ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseR
> eportStatusCodeLibNull.inf
>
> + MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf
>
> + RngLib|MdePkg/Library/BaseRngLib/BaseRngLib.inf
>
> +
>
> +#########################################################
> ############################################
>
> +
>
> +#
>
> +# Silicon Init Common Library
>
> +#
>
> +!include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc
>
> +ConfigBlockLib|IntelSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlock
> Lib.inf
>
> +
>
> +[LibraryClasses.IA32]
>
> +#
>
> +# PEI phase common
>
> +#
>
> + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
>
> + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
>
> +
> MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemory
> AllocationLib.inf
>
> +
> ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiEx
> tractGuidedSectionLib.inf
>
> +
> PeiGetVtdPmrAlignmentLib|IntelSiliconPkg/Library/PeiGetVtdPmrAlignment
> Lib/PeiGetVtdPmrAlignmentLib.inf
>
> +
>
> +#########################################################
> ##########################################################
> ##################
>
> +
>
> +#
>
> +# Silicon Init Pei Library
>
> +#
>
> +!include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc
>
> +
>
> +[LibraryClasses.IA32.SEC]
>
> +
> GpioHelpersLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/Ba
> seGpioHelpersLibNull/BaseGpioHelpersLibNull.inf
>
> +
>
> +[LibraryClasses.X64]
>
> + #
>
> + # DXE phase common
>
> + #
>
> + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
>
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
>
> +
> MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemo
> ryAllocationLib.inf
>
> +
> ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeE
> xtractGuidedSectionLib.inf
>
> +
>
> +#
>
> +# Hsti
>
> +#
>
> + HstiLib|MdePkg/Library/DxeHstiLib/DxeHstiLib.inf
>
> +
>
> +#########################################################
> ##########################################
>
> +#
>
> +# Silicon Init Dxe Library
>
> +#
>
> +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc
>
> +
>
> +[LibraryClasses.X64.PEIM]
>
> +
>
> +[LibraryClasses.X64.DXE_CORE]
>
> + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
>
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
>
> +
>
> +[LibraryClasses.X64.DXE_SMM_DRIVER]
>
> +
> SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesT
> ableLib.inf
>
> +
> MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMe
> moryAllocationLib.inf
>
> + SmmIoLib|MdePkg/Library/SmmIoLib/SmmIoLib.inf
>
> + SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf
>
> +
>
> +[LibraryClasses.X64.SMM_CORE]
>
> +
>
> +[LibraryClasses.X64.UEFI_DRIVER]
>
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
>
> +
>
> +[LibraryClasses.X64.UEFI_APPLICATION]
>
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
>
> +
>
> +[Components.IA32]
>
> +!include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc
>
> +
>
> +[Components.X64]
>
> +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc
>
> --
> 2.24.0.windows.2
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