[edk2-devel] [edk2-platforms PATCH v2 1/4] Marvell/Armada7k8k: Remove device tree sources from edk2-platforms
Marcin Wojtas
mw at semihalf.com
Mon Mar 22 01:32:29 UTC 2021
edk2-non-osi project is a more proper place for keeping
the device tree sources, so move it there. It is a preparation
for the DT upgrade for the Armada 7k8k SoC family.
Signed-off-by: Marcin Wojtas <mw at semihalf.com>
---
Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf | 22 -
Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf | 22 -
Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf | 22 -
Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi | 16 -
Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts | 267 ----------
Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi | 16 -
Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi | 64 ---
Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi | 26 -
Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts | 336 ------------
Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts | 377 -------------
Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi | 25 -
Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi | 108 ----
Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi | 31 --
Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi | 43 --
Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi | 264 ---------
Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi | 10 -
Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi | 560 --------------------
17 files changed, 2209 deletions(-)
delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf
delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf
delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf
delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi
delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts
delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi
delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi
delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi
delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts
delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts
delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi
delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi
delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi
delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi
delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi
delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi
delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf b/Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf
deleted file mode 100644
index b533578a89..0000000000
--- a/Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf
+++ /dev/null
@@ -1,22 +0,0 @@
-## @file
-#
-# Device tree description of the Marvell Armada 7040 DB platform
-#
-# Copyright (c) 2018, Marvell International Ltd. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-##
-
-[Defines]
- INF_VERSION = 0x0001001A
- BASE_NAME = Armada70x0DbDeviceTree
- FILE_GUID = 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDefaultDtbFileGuid
- MODULE_TYPE = USER_DEFINED
- VERSION_STRING = 1.0
-
-[Sources]
- armada-7040-db.dts
-
-[Packages]
- MdePkg/MdePkg.dec
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf b/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf
deleted file mode 100644
index 378fad240b..0000000000
--- a/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf
+++ /dev/null
@@ -1,22 +0,0 @@
-## @file
-#
-# Device tree description of the Marvell Armada 8040 DB platform
-#
-# Copyright (c) 2018, Marvell International Ltd. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-##
-
-[Defines]
- INF_VERSION = 0x0001001A
- BASE_NAME = Armada80x0DbDeviceTree
- FILE_GUID = 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDefaultDtbFileGuid
- MODULE_TYPE = USER_DEFINED
- VERSION_STRING = 1.0
-
-[Sources]
- armada-8040-db.dts
-
-[Packages]
- MdePkg/MdePkg.dec
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf b/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf
deleted file mode 100644
index 540e1a79f3..0000000000
--- a/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf
+++ /dev/null
@@ -1,22 +0,0 @@
-## @file
-#
-# Device tree description of the Marvell Armada 8040 MacchiatoBin platform
-#
-# Copyright (c) 2018, Marvell International Ltd. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-##
-
-[Defines]
- INF_VERSION = 0x0001001A
- BASE_NAME = Armada80x0McBinDeviceTree
- FILE_GUID = 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDefaultDtbFileGuid
- MODULE_TYPE = USER_DEFINED
- VERSION_STRING = 1.0
-
-[Sources]
- armada-8040-mcbin.dts
-
-[Packages]
- MdePkg/MdePkg.dec
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi
deleted file mode 100644
index e2edc26271..0000000000
--- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi
+++ /dev/null
@@ -1,16 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * Device Tree file for the Armada 7020 SoC, made of an AP806 Dual and
- * one CP110.
- */
-
-#include "armada-ap806-dual.dtsi"
-#include "armada-70x0.dtsi"
-
-/ {
- model = "Marvell Armada 7020";
- compatible = "marvell,armada7020", "marvell,armada-ap806-dual",
- "marvell,armada-ap806";
-};
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts
deleted file mode 100644
index f5878efc06..0000000000
--- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts
+++ /dev/null
@@ -1,267 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * Device Tree file for Marvell Armada 7040 Development board platform
- */
-
-#include "armada-7040.dtsi"
-
-#define GPIO_ACTIVE_HIGH 0
-#define GPIO_ACTIVE_LOW 1
-
-/ {
- model = "Marvell Armada 7040 DB board";
- compatible = "marvell,armada7040-db", "marvell,armada7040",
- "marvell,armada-ap806-quad", "marvell,armada-ap806";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory at 0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x80000000>;
- };
-
- aliases {
- ethernet0 = &cp0_eth0;
- ethernet1 = &cp0_eth1;
- ethernet2 = &cp0_eth2;
- };
-
- cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
- compatible = "regulator-fixed";
- regulator-name = "usb3h0-vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
- };
-
- cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
- compatible = "regulator-fixed";
- regulator-name = "usb3h1-vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
- };
-
- cp0_usb3_0_phy: cp0-usb3-0-phy {
- compatible = "usb-nop-xceiv";
- vcc-supply = <&cp0_reg_usb3_0_vbus>;
- };
-
- cp0_usb3_1_phy: cp0-usb3-1-phy {
- compatible = "usb-nop-xceiv";
- vcc-supply = <&cp0_reg_usb3_1_vbus>;
- };
-};
-
-&i2c0 {
- status = "okay";
- clock-frequency = <100000>;
-};
-
-&spi0 {
- status = "okay";
-
- spi-flash at 0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <10000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition at 0 {
- label = "U-Boot";
- reg = <0 0x200000>;
- };
- partition at 400000 {
- label = "Filesystem";
- reg = <0x200000 0xce0000>;
- };
- };
- };
-};
-
-&uart0 {
- status = "okay";
- pinctrl-0 = <&uart0_pins>;
- pinctrl-names = "default";
-};
-
-
-&cp0_pcie2 {
- status = "okay";
-};
-
-&cp0_i2c0 {
- status = "okay";
- clock-frequency = <100000>;
-
- expander0: pca9555 at 21 {
- compatible = "nxp,pca9555";
- pinctrl-names = "default";
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x21>;
- /*
- * IO0_0: USB3_PWR_EN0 IO1_0: USB_3_1_Dev_Detect
- * IO0_1: USB3_PWR_EN1 IO1_1: USB2_1_current_limit
- * IO0_2: DDR3_4_Detect IO1_2: Hcon_IO_RstN
- * IO0_3: USB2_DEVICE_DETECT
- * IO0_4: GPIO_0 IO1_4: SD_Status
- * IO0_5: GPIO_1 IO1_5: LDO_5V_Enable
- * IO0_6: IHB_5V_Enable IO1_6: PWR_EN_eMMC
- * IO0_7: IO1_7: SDIO_Vcntrl
- */
- };
-};
-
-&cp0_nand_controller {
- /*
- * SPI on CPM and NAND have common pins on this board. We can
- * use only one at a time. To enable the NAND (which will
- * disable the SPI), the "status = "okay";" line have to be
- * added here.
- */
- pinctrl-0 = <&nand_pins>, <&nand_rb>;
- pinctrl-names = "default";
-
- nand at 0 {
- reg = <0>;
- label = "pxa3xx_nand-0";
- nand-rb = <0>;
- nand-on-flash-bbt;
- nand-ecc-strength = <4>;
- nand-ecc-step-size = <512>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition at 0 {
- label = "U-Boot";
- reg = <0 0x200000>;
- };
-
- partition at 200000 {
- label = "Linux";
- reg = <0x200000 0xe00000>;
- };
-
- partition at 1000000 {
- label = "Filesystem";
- reg = <0x1000000 0x3f000000>;
- };
-
- };
- };
-};
-
-&cp0_spi1 {
- status = "disabled";
-
- spi-flash at 0 {
- #address-cells = <0x1>;
- #size-cells = <0x1>;
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- spi-max-frequency = <20000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition at 0 {
- label = "U-Boot";
- reg = <0x0 0x200000>;
- };
-
- partition at 400000 {
- label = "Filesystem";
- reg = <0x200000 0xe00000>;
- };
- };
- };
-};
-
-&cp0_sata0 {
- status = "okay";
-};
-
-&cp0_usb3_0 {
- usb-phy = <&cp0_usb3_0_phy>;
- status = "okay";
-};
-
-&cp0_usb3_1 {
- usb-phy = <&cp0_usb3_1_phy>;
- status = "okay";
-};
-
-&ap_sdhci0 {
- status = "okay";
- bus-width = <4>;
- no-1-8-v;
- non-removable;
-};
-
-&cp0_sdhci0 {
- status = "okay";
- bus-width = <4>;
- no-1-8-v;
- cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>;
-};
-
-&cp0_mdio {
- status = "okay";
-
- phy0: ethernet-phy at 0 {
- reg = <0>;
- };
- phy1: ethernet-phy at 1 {
- reg = <1>;
- };
-};
-
-&cp0_ethernet {
- status = "okay";
-};
-
-&cp0_eth0 {
- status = "okay";
- /* Network PHY */
- phy-mode = "10gbase-kr";
- /* Generic PHY, providing serdes lanes */
- phys = <&cp0_comphy2 0>;
-
- fixed-link {
- speed = <10000>;
- full-duplex;
- };
-};
-
-&cp0_eth1 {
- status = "okay";
- /* Network PHY */
- phy = <&phy0>;
- phy-mode = "sgmii";
- /* Generic PHY, providing serdes lanes */
- phys = <&cp0_comphy0 1>;
-};
-
-&cp0_eth2 {
- status = "okay";
- phy = <&phy1>;
- phy-mode = "rgmii-id";
-};
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi
deleted file mode 100644
index 03109b2bb7..0000000000
--- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi
+++ /dev/null
@@ -1,16 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * Device Tree file for the Armada 7040 SoC, made of an AP806 Quad and
- * one CP110.
- */
-
-#include "armada-ap806-quad.dtsi"
-#include "armada-70x0.dtsi"
-
-/ {
- model = "Marvell Armada 7040";
- compatible = "marvell,armada7040", "marvell,armada-ap806-quad",
- "marvell,armada-ap806";
-};
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi
deleted file mode 100644
index 78f9d874c6..0000000000
--- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi
+++ /dev/null
@@ -1,64 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2017 Marvell Technology Group Ltd.
- *
- * Device Tree file for the Armada 70x0 SoC
- */
-
-/ {
- aliases {
- gpio1 = &cp0_gpio1;
- gpio2 = &cp0_gpio2;
- spi1 = &cp0_spi0;
- spi2 = &cp0_spi1;
- };
-};
-
-/*
- * Instantiate the CP110
- */
-#define CP110_NAME cp0
-#define CP110_BASE f2000000
-#define CP110_PCIE_IO_BASE 0xf9000000
-#define CP110_PCIE_MEM_BASE 0xf6000000
-#define CP110_PCIE0_BASE f2600000
-#define CP110_PCIE1_BASE f2620000
-#define CP110_PCIE2_BASE f2640000
-
-#include "armada-cp110.dtsi"
-
-#undef CP110_NAME
-#undef CP110_BASE
-#undef CP110_PCIE_IO_BASE
-#undef CP110_PCIE_MEM_BASE
-#undef CP110_PCIE0_BASE
-#undef CP110_PCIE1_BASE
-#undef CP110_PCIE2_BASE
-
-&cp0_gpio1 {
- status = "okay";
-};
-
-&cp0_gpio2 {
- status = "okay";
-};
-
-&cp0_syscon0 {
- cp0_pinctrl: pinctrl {
- compatible = "marvell,armada-7k-pinctrl";
-
- nand_pins: nand-pins {
- marvell,pins =
- "mpp15", "mpp16", "mpp17", "mpp18",
- "mpp19", "mpp20", "mpp21", "mpp22",
- "mpp23", "mpp24", "mpp25", "mpp26",
- "mpp27";
- marvell,function = "dev";
- };
-
- nand_rb: nand-rb {
- marvell,pins = "mpp13";
- marvell,function = "nf";
- };
- };
-};
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi
deleted file mode 100644
index 5d763450c5..0000000000
--- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi
+++ /dev/null
@@ -1,26 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and
- * two CP110.
- */
-
-#include "armada-ap806-dual.dtsi"
-#include "armada-80x0.dtsi"
-
-/ {
- model = "Marvell Armada 8020";
- compatible = "marvell,armada8020", "marvell,armada-ap806-dual",
- "marvell,armada-ap806";
-};
-
-/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock
- * in CP master is not connected (by package) to the oscillator. So
- * disable it. However, the RTC clock in CP slave is connected to the
- * oscillator so this one is let enabled.
- */
-
-&cp0_rtc {
- status = "disabled";
-};
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts
deleted file mode 100644
index e81392241c..0000000000
--- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts
+++ /dev/null
@@ -1,336 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * Device Tree file for Marvell Armada 8040 Development board platform
- */
-
-#include "armada-8040.dtsi"
-
-#define GPIO_ACTIVE_HIGH 0
-#define GPIO_ACTIVE_LOW 1
-
-/ {
- model = "Marvell Armada 8040 DB board";
- compatible = "marvell,armada8040-db", "marvell,armada8040",
- "marvell,armada-ap806-quad", "marvell,armada-ap806";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory at 0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x80000000>;
- };
-
- aliases {
- ethernet0 = &cp0_eth0;
- ethernet1 = &cp0_eth2;
- ethernet2 = &cp1_eth0;
- ethernet3 = &cp1_eth1;
- };
-
- cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
- compatible = "regulator-fixed";
- regulator-name = "cp0-usb3h0-vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
- };
-
- cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
- compatible = "regulator-fixed";
- regulator-name = "cp0-usb3h1-vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
- };
-
- cp0_usb3_0_phy: cp0-usb3-0-phy {
- compatible = "usb-nop-xceiv";
- vcc-supply = <&cp0_reg_usb3_0_vbus>;
- };
-
- cp0_usb3_1_phy: cp0-usb3-1-phy {
- compatible = "usb-nop-xceiv";
- vcc-supply = <&cp0_reg_usb3_1_vbus>;
- };
-
- cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {
- compatible = "regulator-fixed";
- regulator-name = "cp1-usb3h0-vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&expander1 0 GPIO_ACTIVE_HIGH>;
- };
-
- cp1_usb3_0_phy: cp1-usb3-0-phy {
- compatible = "usb-nop-xceiv";
- vcc-supply = <&cp1_reg_usb3_0_vbus>;
- };
-};
-
-&i2c0 {
- status = "okay";
- clock-frequency = <100000>;
-};
-
-&spi0 {
- status = "okay";
-
- spi-flash at 0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <10000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition at 0 {
- label = "U-Boot";
- reg = <0 0x200000>;
- };
- partition at 400000 {
- label = "Filesystem";
- reg = <0x200000 0xce0000>;
- };
- };
- };
-};
-
-/* Accessible over the mini-USB CON9 connector on the main board */
-&uart0 {
- status = "okay";
- pinctrl-0 = <&uart0_pins>;
- pinctrl-names = "default";
-};
-
-/* CON6 on CP0 expansion */
-&cp0_pcie0 {
- status = "okay";
-};
-
-/* CON5 on CP0 expansion */
-&cp0_pcie2 {
- status = "okay";
-};
-
-&cp0_i2c0 {
- status = "okay";
- clock-frequency = <100000>;
-
- /* U31 */
- expander0: pca9555 at 21 {
- compatible = "nxp,pca9555";
- pinctrl-names = "default";
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x21>;
- };
-
- /* U25 */
- expander1: pca9555 at 25 {
- compatible = "nxp,pca9555";
- pinctrl-names = "default";
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x25>;
- };
-
-};
-
-/* CON4 on CP0 expansion */
-&cp0_sata0 {
- status = "okay";
-};
-
-/* CON9 on CP0 expansion */
-&cp0_usb3_0 {
- usb-phy = <&cp0_usb3_0_phy>;
- status = "okay";
-};
-
-/* CON10 on CP0 expansion */
-&cp0_usb3_1 {
- usb-phy = <&cp0_usb3_1_phy>;
- status = "okay";
-};
-
-&cp0_mdio {
- status = "okay";
-
- phy1: ethernet-phy at 1 {
- reg = <1>;
- };
-};
-
-&cp0_ethernet {
- status = "okay";
-};
-
-&cp0_eth0 {
- status = "okay";
- phy-mode = "10gbase-kr";
-
- fixed-link {
- speed = <10000>;
- full-duplex;
- };
-};
-
-&cp0_eth2 {
- status = "okay";
- phy = <&phy1>;
- phy-mode = "rgmii-id";
-};
-
-/* CON6 on CP1 expansion */
-&cp1_pcie0 {
- status = "okay";
-};
-
-/* CON7 on CP1 expansion */
-&cp1_pcie1 {
- status = "okay";
-};
-
-/* CON5 on CP1 expansion */
-&cp1_pcie2 {
- status = "okay";
-};
-
-&cp1_i2c0 {
- status = "okay";
- clock-frequency = <100000>;
-};
-
-&cp1_spi1 {
- status = "disabled";
-
- spi-flash at 0 {
- #address-cells = <0x1>;
- #size-cells = <0x1>;
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- spi-max-frequency = <20000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition at 0 {
- label = "Boot";
- reg = <0x0 0x200000>;
- };
- partition at 200000 {
- label = "Filesystem";
- reg = <0x200000 0xd00000>;
- };
- partition at f00000 {
- label = "Boot_2nd";
- reg = <0xf00000 0x100000>;
- };
- };
- };
-};
-
-/*
- * Proper NAND usage will require DPR-76 to be in position 1-2, which disables
- * MDIO signal of CP1.
- */
-&cp1_nand_controller {
- pinctrl-0 = <&nand_pins>, <&nand_rb>;
- pinctrl-names = "default";
-
- nand at 0 {
- reg = <0>;
- nand-rb = <0>;
- nand-on-flash-bbt;
- nand-ecc-strength = <4>;
- nand-ecc-step-size = <512>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition at 0 {
- label = "U-Boot";
- reg = <0 0x200000>;
- };
- partition at 200000 {
- label = "Linux";
- reg = <0x200000 0xe00000>;
- };
- partition at 1000000 {
- label = "Filesystem";
- reg = <0x1000000 0x3f000000>;
- };
- };
- };
-};
-
-/* CON4 on CP1 expansion */
-&cp1_sata0 {
- status = "okay";
-};
-
-/* CON9 on CP1 expansion */
-&cp1_usb3_0 {
- usb-phy = <&cp1_usb3_0_phy>;
- status = "okay";
-};
-
-/* CON10 on CP1 expansion */
-&cp1_usb3_1 {
- status = "okay";
-};
-
-&cp1_mdio {
- status = "okay";
-
- phy0: ethernet-phy at 0 {
- reg = <0>;
- };
-};
-
-&cp1_ethernet {
- status = "okay";
-};
-
-&cp1_eth0 {
- status = "okay";
- phy-mode = "10gbase-kr";
-
- fixed-link {
- speed = <10000>;
- full-duplex;
- };
-};
-
-&cp1_eth1 {
- status = "okay";
- phy = <&phy0>;
- phy-mode = "rgmii-id";
-};
-
-&ap_sdhci0 {
- status = "okay";
- bus-width = <4>;
- non-removable;
-};
-
-&cp0_sdhci0 {
- status = "okay";
- bus-width = <8>;
- non-removable;
-};
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts
deleted file mode 100644
index d9c9348b53..0000000000
--- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts
+++ /dev/null
@@ -1,377 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * Device Tree file for MACCHIATOBin Armada 8040 community board platform
- */
-
-#include "armada-8040.dtsi"
-
-#define GPIO_ACTIVE_HIGH 0
-#define GPIO_ACTIVE_LOW 1
-
-/ {
- model = "Marvell 8040 MACCHIATOBin";
- compatible = "marvell,armada8040-mcbin", "marvell,armada8040",
- "marvell,armada-ap806-quad", "marvell,armada-ap806";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory at 0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x80000000>;
- };
-
- aliases {
- ethernet0 = &cp0_eth0;
- ethernet1 = &cp1_eth0;
- ethernet2 = &cp1_eth1;
- ethernet3 = &cp1_eth2;
- };
-
- /* Regulator labels correspond with schematics */
- v_3_3: regulator-3-3v {
- compatible = "regulator-fixed";
- regulator-name = "v_3_3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- status = "okay";
- };
-
- v_vddo_h: regulator-1-8v {
- compatible = "regulator-fixed";
- regulator-name = "v_vddo_h";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- status = "okay";
- };
-
- v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_xhci_vbus_pins>;
- regulator-name = "v_5v0_usb3_hst_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- status = "okay";
- };
-
- usb3h0_phy: usb3_phy0 {
- compatible = "usb-nop-xceiv";
- vcc-supply = <&v_5v0_usb3_hst_vbus>;
- };
-
- sfp_eth0: sfp-eth0 {
- /* CON15,16 - CPM lane 4 */
- compatible = "sff,sfp";
- i2c-bus = <&sfpp0_i2c>;
- los-gpio = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;
- tx-fault-gpio = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&cp1_sfpp0_pins>;
- };
-
- sfp_eth1: sfp-eth1 {
- /* CON17,18 - CPS lane 4 */
- compatible = "sff,sfp";
- i2c-bus = <&sfpp1_i2c>;
- los-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>;
- tx-fault-gpio = <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>;
- };
-
- sfp_eth3: sfp-eth3 {
- /* CON3,4 - CPS lane 5 */
- compatible = "sff,sfp";
- i2c-bus = <&sfp_1g_i2c>;
- los-gpio = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&cp0_gpio2 21 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>;
- tx-fault-gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>;
- };
-};
-
-&uart0 {
- status = "okay";
- pinctrl-0 = <&uart0_pins>;
- pinctrl-names = "default";
-};
-
-&ap_sdhci0 {
- bus-width = <8>;
- /*
- * Not stable in HS modes - phy needs "more calibration", so add
- * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
- */
- marvell,xenon-phy-slow-mode;
- no-1-8-v;
- no-sd;
- no-sdio;
- non-removable;
- status = "okay";
- vqmmc-supply = <&v_vddo_h>;
-};
-
-&cp0_i2c0 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_i2c0_pins>;
- status = "okay";
-};
-
-&cp0_i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_i2c1_pins>;
- status = "okay";
-
- i2c-switch at 70 {
- compatible = "nxp,pca9548";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x70>;
-
- sfpp0_i2c: i2c at 0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
- };
- sfpp1_i2c: i2c at 1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
- };
- sfp_1g_i2c: i2c at 2 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <2>;
- };
- };
-};
-
-/* J25 UART header */
-&cp0_uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_uart1_pins>;
- status = "okay";
-};
-
-&cp0_mdio {
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_ge_mdio_pins>;
- status = "okay";
-
- ge_phy: ethernet-phy at 0 {
- reg = <0>;
- };
-};
-
-&cp0_pcie0 {
- compatible = "marvell,armada8k-pcie-ecam", "snps,dw-pcie-ecam";
- reg = <0 0xe0000000 0 0xff00000>;
- bus-range = <0 0xfe>;
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_pcie_pins>;
- num-lanes = <4>;
- num-viewport = <8>;
- reset-gpio = <&cp0_gpio1 20 GPIO_ACTIVE_LOW>;
- ranges = <0x1000000 0x0 0x00000000 0x0 0xeff00000 0x0 0x00010000>,
- <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>,
- <0x3000000 0x8 0x00000000 0x8 0x00000000 0x1 0x00000000>;
- status = "okay";
-};
-
-&cp0_pinctrl {
- cp0_ge_mdio_pins: ge-mdio-pins {
- marvell,pins = "mpp32", "mpp34";
- marvell,function = "ge";
- };
- cp0_i2c1_pins: i2c1-pins {
- marvell,pins = "mpp35", "mpp36";
- marvell,function = "i2c1";
- };
- cp0_i2c0_pins: i2c0-pins {
- marvell,pins = "mpp37", "mpp38";
- marvell,function = "i2c0";
- };
- cp0_uart1_pins: uart1-pins {
- marvell,pins = "mpp40", "mpp41";
- marvell,function = "uart1";
- };
- cp0_xhci_vbus_pins: xhci0-vbus-pins {
- marvell,pins = "mpp47";
- marvell,function = "gpio";
- };
- cp0_sfp_1g_pins: sfp-1g-pins {
- marvell,pins = "mpp51", "mpp53", "mpp54";
- marvell,function = "gpio";
- };
- cp0_pcie_pins: pcie-pins {
- marvell,pins = "mpp52";
- marvell,function = "gpio";
- };
- cp0_sdhci_pins: sdhci-pins {
- marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
- "mpp60", "mpp61";
- marvell,function = "sdio";
- };
- cp0_sfpp1_pins: sfpp1-pins {
- marvell,pins = "mpp62";
- marvell,function = "gpio";
- };
-};
-
-&cp0_xmdio {
- status = "okay";
-
- phy0: ethernet-phy at 0 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <0>;
- sfp = <&sfp_eth0>;
- };
-
- phy8: ethernet-phy at 8 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <8>;
- sfp = <&sfp_eth1>;
- };
-};
-
-&cp0_ethernet {
- status = "okay";
-};
-
-&cp0_eth0 {
- status = "okay";
- /* Network PHY */
- phy = <&phy0>;
- phy-mode = "10gbase-kr";
- /* Generic PHY, providing serdes lanes */
- phys = <&cp0_comphy4 0>;
-};
-
-&cp0_sata0 {
- /* CPM Lane 0 - U29 */
- status = "okay";
-};
-
-&cp0_sdhci0 {
- /* U6 */
- broken-cd;
- bus-width = <4>;
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_sdhci_pins>;
- status = "okay";
- vqmmc-supply = <&v_3_3>;
-};
-
-&cp0_usb3_0 {
- /* J38? - USB2.0 only */
- status = "okay";
-};
-
-&cp0_usb3_1 {
- /* J38? - USB2.0 only */
- status = "okay";
-};
-
-&cp1_ethernet {
- status = "okay";
-};
-
-&cp1_eth0 {
- status = "okay";
- /* Network PHY */
- phy = <&phy8>;
- phy-mode = "10gbase-kr";
- /* Generic PHY, providing serdes lanes */
- phys = <&cp1_comphy4 0>;
-};
-
-&cp1_eth1 {
- /* CPS Lane 0 - J5 (Gigabit RJ45) */
- status = "okay";
- /* Network PHY */
- phy = <&ge_phy>;
- phy-mode = "sgmii";
- /* Generic PHY, providing serdes lanes */
- phys = <&cp1_comphy0 1>;
-};
-
-&cp1_eth2 {
- /* CPS Lane 5 */
- status = "okay";
- /* Network PHY */
- phy-mode = "2500base-x";
- managed = "in-band-status";
- /* Generic PHY, providing serdes lanes */
- phys = <&cp1_comphy5 2>;
- sfp = <&sfp_eth3>;
-};
-
-&cp1_pinctrl {
- cp1_sfpp1_pins: sfpp1-pins {
- marvell,pins = "mpp8", "mpp10", "mpp11";
- marvell,function = "gpio";
- };
- cp1_spi1_pins: spi1-pins {
- marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
- marvell,function = "spi1";
- };
- cp1_uart0_pins: uart0-pins {
- marvell,pins = "mpp6", "mpp7";
- marvell,function = "uart0";
- };
- cp1_sfp_1g_pins: sfp-1g-pins {
- marvell,pins = "mpp24";
- marvell,function = "gpio";
- };
- cp1_sfpp0_pins: sfpp0-pins {
- marvell,pins = "mpp26", "mpp27", "mpp28", "mpp29";
- marvell,function = "gpio";
- };
-};
-
-/* J27 UART header */
-&cp1_uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&cp1_uart0_pins>;
- status = "okay";
-};
-
-&cp1_sata0 {
- /* CPS Lane 1 - U32 */
- /* CPS Lane 3 - U31 */
- status = "okay";
-};
-
-&cp1_spi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&cp1_spi1_pins>;
- status = "disabled";
-
- spi-flash at 0 {
- compatible = "st,w25q32";
- spi-max-frequency = <50000000>;
- reg = <0>;
- };
-};
-
-&cp1_usb3_0 {
- /* CPS Lane 2 - CON7 */
- usb-phy = <&usb3h0_phy>;
- status = "okay";
-};
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi
deleted file mode 100644
index 784ef3f311..0000000000
--- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * Device Tree file for the Armada 8040 SoC, made of an AP806 Quad and
- * two CP110.
- */
-
-#include "armada-ap806-quad.dtsi"
-#include "armada-80x0.dtsi"
-
-/ {
- model = "Marvell Armada 8040";
- compatible = "marvell,armada8040", "marvell,armada-ap806-quad",
- "marvell,armada-ap806";
-};
-
-/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock
- * in CP master is not connected (by package) to the oscillator. So
- * disable it. However, the RTC clock in CP slave is connected to the
- * oscillator so this one is let enabled.
- */
-&cp0_rtc {
- status = "disabled";
-};
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi
deleted file mode 100644
index 81967e20d3..0000000000
--- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi
+++ /dev/null
@@ -1,108 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2017 Marvell Technology Group Ltd.
- *
- * Device Tree file for the Armada 80x0 SoC family
- */
-
-/ {
- aliases {
- gpio1 = &cp1_gpio1;
- gpio2 = &cp0_gpio2;
- spi1 = &cp0_spi0;
- spi2 = &cp0_spi1;
- spi3 = &cp1_spi0;
- spi4 = &cp1_spi1;
- };
-};
-
-/*
- * Instantiate the master CP110
- */
-#define CP110_NAME cp0
-#define CP110_BASE f2000000
-#define CP110_PCIE_IO_BASE 0xf9000000
-#define CP110_PCIE_MEM_BASE 0xf6000000
-#define CP110_PCIE0_BASE f2600000
-#define CP110_PCIE1_BASE f2620000
-#define CP110_PCIE2_BASE f2640000
-
-#include "armada-cp110.dtsi"
-
-#undef CP110_NAME
-#undef CP110_BASE
-#undef CP110_PCIE_IO_BASE
-#undef CP110_PCIE_MEM_BASE
-#undef CP110_PCIE0_BASE
-#undef CP110_PCIE1_BASE
-#undef CP110_PCIE2_BASE
-
-/*
- * Instantiate the slave CP110
- */
-#define CP110_NAME cp1
-#define CP110_BASE f4000000
-#define CP110_PCIE_IO_BASE 0xfd000000
-#define CP110_PCIE_MEM_BASE 0xfa000000
-#define CP110_PCIE0_BASE f4600000
-#define CP110_PCIE1_BASE f4620000
-#define CP110_PCIE2_BASE f4640000
-
-#include "armada-cp110.dtsi"
-
-#undef CP110_NAME
-#undef CP110_BASE
-#undef CP110_PCIE_IO_BASE
-#undef CP110_PCIE_MEM_BASE
-#undef CP110_PCIE0_BASE
-#undef CP110_PCIE1_BASE
-#undef CP110_PCIE2_BASE
-
-/* The 80x0 has two CP blocks, but uses only one block from each. */
-&cp1_gpio1 {
- status = "okay";
-};
-
-&cp0_gpio2 {
- status = "okay";
-};
-
-&cp0_syscon0 {
- cp0_pinctrl: pinctrl {
- compatible = "marvell,armada-8k-cpm-pinctrl";
- };
-};
-
-&cp1_syscon0 {
- cp1_pinctrl: pinctrl {
- compatible = "marvell,armada-8k-cps-pinctrl";
-
- nand_pins: nand-pins {
- marvell,pins =
- "mpp0", "mpp1", "mpp2", "mpp3",
- "mpp4", "mpp5", "mpp6", "mpp7",
- "mpp8", "mpp9", "mpp10", "mpp11",
- "mpp15", "mpp16", "mpp17", "mpp18",
- "mpp19", "mpp20", "mpp21", "mpp22",
- "mpp23", "mpp24", "mpp25", "mpp26",
- "mpp27";
- marvell,function = "dev";
- };
-
- nand_rb: nand-rb {
- marvell,pins = "mpp13", "mpp12";
- marvell,function = "nf";
- };
- };
-};
-
-&cp1_crypto {
- /*
- * The cryptographic engine found on the cp110
- * master is enabled by default at the SoC
- * level. Because it is not possible as of now
- * to enable two cryptographic engines in
- * parallel, disable this one by default.
- */
- status = "disabled";
-};
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi
deleted file mode 100644
index 5985843fcc..0000000000
--- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi
+++ /dev/null
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * Device Tree file for Marvell Armada AP806.
- */
-
-#include "armada-ap806.dtsi"
-
-/ {
- model = "Marvell Armada AP806 Dual";
- compatible = "marvell,armada-ap806-dual", "marvell,armada-ap806";
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu at 0 {
- device_type = "cpu";
- compatible = "arm,cortex-a72", "arm,armv8";
- reg = <0x000>;
- enable-method = "psci";
- };
- cpu at 1 {
- device_type = "cpu";
- compatible = "arm,cortex-a72", "arm,armv8";
- reg = <0x001>;
- enable-method = "psci";
- };
- };
-};
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi
deleted file mode 100644
index bae0ed9ca7..0000000000
--- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi
+++ /dev/null
@@ -1,43 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * Device Tree file for Marvell Armada AP806.
- */
-
-#include "armada-ap806.dtsi"
-
-/ {
- model = "Marvell Armada AP806 Quad";
- compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu at 0 {
- device_type = "cpu";
- compatible = "arm,cortex-a72", "arm,armv8";
- reg = <0x000>;
- enable-method = "psci";
- };
- cpu at 1 {
- device_type = "cpu";
- compatible = "arm,cortex-a72", "arm,armv8";
- reg = <0x001>;
- enable-method = "psci";
- };
- cpu at 100 {
- device_type = "cpu";
- compatible = "arm,cortex-a72", "arm,armv8";
- reg = <0x100>;
- enable-method = "psci";
- };
- cpu at 101 {
- device_type = "cpu";
- compatible = "arm,cortex-a72", "arm,armv8";
- reg = <0x101>;
- enable-method = "psci";
- };
- };
-};
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi
deleted file mode 100644
index 66124bf483..0000000000
--- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi
+++ /dev/null
@@ -1,264 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * Device Tree file for Marvell Armada AP806.
- */
-
-#define IRQ_TYPE_LEVEL_HIGH (1 << 2)
-#define IRQ_TYPE_LEVEL_LOW (1 << 3)
-
-#define GIC_SPI 0
-#define GIC_PPI 1
-
-#define GIC_CPU_MASK_RAW(x) ((x) << 8)
-#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1)
-
-/dts-v1/;
-
-/ {
- model = "Marvell Armada AP806";
- compatible = "marvell,armada-ap806";
- #address-cells = <2>;
- #size-cells = <2>;
-
- aliases {
- serial0 = &uart0;
- serial1 = &uart1;
- gpio0 = &ap_gpio;
- spi0 = &spi0;
- };
-
- psci {
- compatible = "arm,psci-0.2";
- method = "smc";
- };
-
- ap806 {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- ranges;
-
- config-space at f0000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- ranges = <0x0 0x0 0xf0000000 0x1000000>;
-
- gic: interrupt-controller at 210000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- interrupt-controller;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- reg = <0x210000 0x10000>,
- <0x220000 0x20000>,
- <0x240000 0x20000>,
- <0x260000 0x20000>;
-
- gic_v2m0: v2m at 280000 {
- compatible = "arm,gic-v2m-frame";
- msi-controller;
- reg = <0x280000 0x1000>;
- arm,msi-base-spi = <160>;
- arm,msi-num-spis = <32>;
- };
- gic_v2m1: v2m at 290000 {
- compatible = "arm,gic-v2m-frame";
- msi-controller;
- reg = <0x290000 0x1000>;
- arm,msi-base-spi = <192>;
- arm,msi-num-spis = <32>;
- };
- gic_v2m2: v2m at 2a0000 {
- compatible = "arm,gic-v2m-frame";
- msi-controller;
- reg = <0x2a0000 0x1000>;
- arm,msi-base-spi = <224>;
- arm,msi-num-spis = <32>;
- };
- gic_v2m3: v2m at 2b0000 {
- compatible = "arm,gic-v2m-frame";
- msi-controller;
- reg = <0x2b0000 0x1000>;
- arm,msi-base-spi = <256>;
- arm,msi-num-spis = <32>;
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
- pmu {
- compatible = "arm,cortex-a72-pmu";
- interrupt-parent = <&pic>;
- interrupts = <17>;
- };
-
- odmi: odmi at 300000 {
- compatible = "marvell,odmi-controller";
- interrupt-controller;
- msi-controller;
- marvell,odmi-frames = <4>;
- reg = <0x300000 0x4000>,
- <0x304000 0x4000>,
- <0x308000 0x4000>,
- <0x30C000 0x4000>;
- marvell,spi-base = <128>, <136>, <144>, <152>;
- };
-
- gicp: gicp at 3f0040 {
- compatible = "marvell,ap806-gicp";
- reg = <0x3f0040 0x10>;
- marvell,spi-ranges = <64 64>, <288 64>;
- msi-controller;
- };
-
- pic: interrupt-controller at 3f0100 {
- compatible = "marvell,armada-8k-pic";
- reg = <0x3f0100 0x10>;
- #interrupt-cells = <1>;
- interrupt-controller;
- interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- xor at 400000 {
- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
- reg = <0x400000 0x1000>,
- <0x410000 0x1000>;
- msi-parent = <&gic_v2m0>;
- clocks = <&ap_clk 3>;
- dma-coherent;
- };
-
- xor at 420000 {
- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
- reg = <0x420000 0x1000>,
- <0x430000 0x1000>;
- msi-parent = <&gic_v2m0>;
- clocks = <&ap_clk 3>;
- dma-coherent;
- };
-
- xor at 440000 {
- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
- reg = <0x440000 0x1000>,
- <0x450000 0x1000>;
- msi-parent = <&gic_v2m0>;
- clocks = <&ap_clk 3>;
- dma-coherent;
- };
-
- xor at 460000 {
- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
- reg = <0x460000 0x1000>,
- <0x470000 0x1000>;
- msi-parent = <&gic_v2m0>;
- clocks = <&ap_clk 3>;
- dma-coherent;
- };
-
- spi0: spi at 510600 {
- compatible = "marvell,armada-380-spi";
- reg = <0x510600 0x50>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ap_clk 3>;
- status = "disabled";
- };
-
- i2c0: i2c at 511000 {
- compatible = "marvell,mv78230-i2c";
- reg = <0x511000 0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- timeout-ms = <1000>;
- clocks = <&ap_clk 3>;
- status = "disabled";
- };
-
- uart0: serial at 512000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x512000 0x100>;
- reg-shift = <2>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- reg-io-width = <1>;
- clocks = <&ap_clk 3>;
- status = "disabled";
- };
-
- uart1: serial at 512100 {
- compatible = "snps,dw-apb-uart";
- reg = <0x512100 0x100>;
- reg-shift = <2>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- reg-io-width = <1>;
- clocks = <&ap_clk 3>;
- status = "disabled";
-
- };
-
- watchdog: watchdog at 610000 {
- compatible = "arm,sbsa-gwdt";
- reg = <0x610000 0x1000>, <0x600000 0x1000>;
- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- ap_sdhci0: sdhci at 6e0000 {
- compatible = "marvell,armada-ap806-sdhci";
- reg = <0x6e0000 0x300>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "core";
- clocks = <&ap_clk 4>;
- dma-coherent;
- marvell,xenon-phy-slow-mode;
- status = "disabled";
- };
-
- ap_syscon: system-controller at 6f4000 {
- compatible = "syscon", "simple-mfd";
- reg = <0x6f4000 0x2000>;
-
- ap_clk: clock {
- compatible = "marvell,ap806-clock";
- #clock-cells = <1>;
- };
-
- ap_pinctrl: pinctrl {
- compatible = "marvell,ap806-pinctrl";
-
- uart0_pins: uart0-pins {
- marvell,pins = "mpp11", "mpp19";
- marvell,function = "uart0";
- };
- };
-
- ap_gpio: gpio at 1040 {
- compatible = "marvell,armada-8k-gpio";
- offset = <0x1040>;
- ngpios = <20>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&ap_pinctrl 0 0 20>;
- };
- };
-
- ap_thermal: thermal at 6f808c {
- compatible = "marvell,armada-ap806-thermal";
- reg = <0x6f808c 0x4>,
- <0x6f8084 0x8>;
- };
- };
- };
-};
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi
deleted file mode 100644
index 8b610fd2b3..0000000000
--- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi
+++ /dev/null
@@ -1,10 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- */
-
-/* Common definitions used by Armada 7K/8K DTs */
-#define PASTER(x, y) x ## y
-#define EVALUATOR(x, y) PASTER(x, y)
-#define CP110_LABEL(name) EVALUATOR(CP110_NAME, EVALUATOR(_, name))
-#define ADDRESSIFY(addr) EVALUATOR(0x, addr)
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi
deleted file mode 100644
index 5e8e524cf7..0000000000
--- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi
+++ /dev/null
@@ -1,560 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * Device Tree file for Marvell Armada CP110.
- */
-
-#include "armada-common.dtsi"
-
-#define ICU_GRP_NSR 0x0
-#define ICU_GRP_SR 0x1
-#define ICU_GRP_SEI 0x4
-#define ICU_GRP_REI 0x5
-
-#define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * 0x10000))
-#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface * 0x1000000))
-#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0xf00000)
-
-/ {
- /*
- * The contents of the node are defined below, in order to
- * save one indentation level
- */
- CP110_NAME: CP110_NAME { };
-};
-
-&CP110_NAME {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "simple-bus";
- interrupt-parent = <&CP110_LABEL(icu)>;
- ranges;
-
- config-space at CP110_BASE {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>;
-
- CP110_LABEL(ethernet): ethernet at 0 {
- compatible = "marvell,armada-7k-pp22";
- reg = <0x0 0x100000>, <0x129000 0xb000>;
- clocks = <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL(ppv2_clk)>,
- <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL(core_clk)>,
- <&CP110_LABEL(core_clk)>;
- clock-names = "pp_clk", "gop_clk",
- "mg_clk", "mg_core_clk", "axi_clk";
- marvell,system-controller = <&CP110_LABEL(syscon0)>;
- status = "disabled";
- dma-coherent;
-
- CP110_LABEL(eth0): eth0 {
- interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
- "tx-cpu3", "rx-shared", "link";
- port-id = <0>;
- gop-port-id = <0>;
- status = "disabled";
- };
-
- CP110_LABEL(eth1): eth1 {
- interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
- "tx-cpu3", "rx-shared", "link";
- port-id = <1>;
- gop-port-id = <2>;
- status = "disabled";
- };
-
- CP110_LABEL(eth2): eth2 {
- interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
- "tx-cpu3", "rx-shared", "link";
- port-id = <2>;
- gop-port-id = <3>;
- status = "disabled";
- };
- };
-
- CP110_LABEL(comphy): phy at 120000 {
- compatible = "marvell,comphy-cp110";
- reg = <0x120000 0x6000>;
- marvell,system-controller = <&CP110_LABEL(syscon0)>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- CP110_LABEL(comphy0): phy at 0 {
- reg = <0>;
- #phy-cells = <1>;
- };
-
- CP110_LABEL(comphy1): phy at 1 {
- reg = <1>;
- #phy-cells = <1>;
- };
-
- CP110_LABEL(comphy2): phy at 2 {
- reg = <2>;
- #phy-cells = <1>;
- };
-
- CP110_LABEL(comphy3): phy at 3 {
- reg = <3>;
- #phy-cells = <1>;
- };
-
- CP110_LABEL(comphy4): phy at 4 {
- reg = <4>;
- #phy-cells = <1>;
- };
-
- CP110_LABEL(comphy5): phy at 5 {
- reg = <5>;
- #phy-cells = <1>;
- };
- };
-
- CP110_LABEL(mdio): mdio at 12a200 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "marvell,orion-mdio";
- reg = <0x12a200 0x10>;
- clocks = <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL(ppv2_clk)>,
- <&CP110_LABEL(core_clk)>, <&CP110_LABEL(core_clk)>;
- status = "disabled";
- };
-
- CP110_LABEL(xmdio): mdio at 12a600 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "marvell,xmdio";
- reg = <0x12a600 0x10>;
- clocks = <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL(ppv2_clk)>,
- <&CP110_LABEL(core_clk)>;
- status = "disabled";
- };
-
- CP110_LABEL(icu): interrupt-controller at 1e0000 {
- compatible = "marvell,cp110-icu";
- reg = <0x1e0000 0x440>;
- #interrupt-cells = <3>;
- interrupt-controller;
- msi-parent = <&gicp>;
- };
-
- CP110_LABEL(rtc): rtc at 284000 {
- compatible = "marvell,armada-8k-rtc";
- reg = <0x284000 0x20>, <0x284080 0x24>;
- reg-names = "rtc", "rtc-soc";
- interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- CP110_LABEL(thermal): thermal at 400078 {
- compatible = "marvell,armada-cp110-thermal";
- reg = <0x400078 0x4>,
- <0x400070 0x8>;
- };
-
- CP110_LABEL(syscon0): system-controller at 440000 {
- compatible = "syscon", "simple-mfd";
- reg = <0x440000 0x2000>;
-
- CP110_LABEL(clk): clock {
- compatible = "marvell,cp110-clock";
- status = "disabled";
- #clock-cells = <2>;
- };
-
- CP110_LABEL(gpio1): gpio at 100 {
- compatible = "marvell,armada-8k-gpio";
- offset = <0x100>;
- ngpios = <32>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
- interrupt-controller;
- interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- CP110_LABEL(gpio2): gpio at 140 {
- compatible = "marvell,armada-8k-gpio";
- offset = <0x140>;
- ngpios = <31>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>;
- interrupt-controller;
- interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
- };
-
- CP110_LABEL(usb3_0): usb3 at 500000 {
- compatible = "marvell,armada-8k-xhci",
- "generic-xhci";
- reg = <0x500000 0x4000>;
- dma-coherent;
- interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(core_clk)>,
- <&CP110_LABEL(core_clk)>;
- status = "disabled";
- };
-
- CP110_LABEL(usb3_1): usb3 at 510000 {
- compatible = "marvell,armada-8k-xhci",
- "generic-xhci";
- reg = <0x510000 0x4000>;
- dma-coherent;
- interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(core_clk)>,
- <&CP110_LABEL(core_clk)>;
- status = "disabled";
- };
-
- CP110_LABEL(sata0): sata at 540000 {
- compatible = "marvell,armada-8k-ahci",
- "generic-ahci";
- reg = <0x540000 0x30000>;
- dma-coherent;
- interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&CP110_LABEL(core_clk)>,
- <&CP110_LABEL(core_clk)>;
- status = "disabled";
- };
-
- CP110_LABEL(xor0): xor at 6a0000 {
- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
- reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
- dma-coherent;
- msi-parent = <&gic_v2m0>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(core_clk)>,
- <&CP110_LABEL(x2core_clk)>;
- };
-
- CP110_LABEL(xor1): xor at 6c0000 {
- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
- reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
- dma-coherent;
- msi-parent = <&gic_v2m0>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(core_clk)>,
- <&CP110_LABEL(x2core_clk)>;
- };
-
- CP110_LABEL(spi0): spi at 700600 {
- compatible = "marvell,armada-380-spi";
- reg = <0x700600 0x50>;
- #address-cells = <0x1>;
- #size-cells = <0x0>;
- clock-names = "core", "axi";
- clocks = <&CP110_LABEL(slow_io_clk)>,
- <&CP110_LABEL(x2core_clk)>;
- status = "disabled";
- };
-
- CP110_LABEL(spi1): spi at 700680 {
- compatible = "marvell,armada-380-spi";
- reg = <0x700680 0x50>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "core", "axi";
- clocks = <&CP110_LABEL(slow_io_clk)>,
- <&CP110_LABEL(x2core_clk)>;
- status = "disabled";
- };
-
- CP110_LABEL(i2c0): i2c at 701000 {
- compatible = "marvell,mv78230-i2c";
- reg = <0x701000 0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(slow_io_clk)>,
- <&CP110_LABEL(x2core_clk)>;
- status = "disabled";
- };
-
- CP110_LABEL(i2c1): i2c at 701100 {
- compatible = "marvell,mv78230-i2c";
- reg = <0x701100 0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(slow_io_clk)>,
- <&CP110_LABEL(x2core_clk)>;
- status = "disabled";
- };
-
- CP110_LABEL(uart0): serial at 702000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x702000 0x100>;
- reg-shift = <2>;
- interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>;
- reg-io-width = <1>;
- clock-names = "baudclk", "apb_pclk";
- clocks = <&CP110_LABEL(slow_io_clk)>,
- <&CP110_LABEL(x2core_clk)>;
- status = "disabled";
- };
-
- CP110_LABEL(uart1): serial at 702100 {
- compatible = "snps,dw-apb-uart";
- reg = <0x702100 0x100>;
- reg-shift = <2>;
- interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>;
- reg-io-width = <1>;
- clock-names = "baudclk", "apb_pclk";
- clocks = <&CP110_LABEL(slow_io_clk)>,
- <&CP110_LABEL(x2core_clk)>;
- status = "disabled";
- };
-
- CP110_LABEL(uart2): serial at 702200 {
- compatible = "snps,dw-apb-uart";
- reg = <0x702200 0x100>;
- reg-shift = <2>;
- interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>;
- reg-io-width = <1>;
- clock-names = "baudclk", "apb_pclk";
- clocks = <&CP110_LABEL(slow_io_clk)>,
- <&CP110_LABEL(x2core_clk)>;
- status = "disabled";
- };
-
- CP110_LABEL(uart3): serial at 702300 {
- compatible = "snps,dw-apb-uart";
- reg = <0x702300 0x100>;
- reg-shift = <2>;
- interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>;
- reg-io-width = <1>;
- clock-names = "baudclk", "apb_pclk";
- clocks = <&CP110_LABEL(slow_io_clk)>,
- <&CP110_LABEL(x2core_clk)>;
- status = "disabled";
- };
-
- CP110_LABEL(nand_controller): nand at 720000 {
- /*
- * Due to the limitation of the pins available
- * this controller is only usable on the CPM
- * for A7K and on the CPS for A8K.
- */
- compatible = "marvell,armada-8k-nand-controller",
- "marvell,armada370-nand-controller";
- reg = <0x720000 0x54>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(nand_clk)>,
- <&CP110_LABEL(x2core_clk)>;
- marvell,system-controller = <&CP110_LABEL(syscon0)>;
- status = "disabled";
- };
-
- CP110_LABEL(trng): trng at 760000 {
- compatible = "marvell,armada-8k-rng",
- "inside-secure,safexcel-eip76";
- reg = <0x760000 0x7d>;
- interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(x2core_clk)>,
- <&CP110_LABEL(x2core_clk)>;
- status = "okay";
- };
-
- CP110_LABEL(sdhci0): sdhci at 780000 {
- compatible = "marvell,armada-cp110-sdhci";
- reg = <0x780000 0x300>;
- interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "core", "axi";
- clocks = <&CP110_LABEL(sdio_clk)>, <&CP110_LABEL(core_clk)>;
- dma-coherent;
- status = "disabled";
- };
-
- CP110_LABEL(crypto): crypto at 800000 {
- compatible = "inside-secure,safexcel-eip197";
- reg = <0x800000 0x200000>;
- interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "mem", "ring0", "ring1",
- "ring2", "ring3", "eip";
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(x2core_clk)>,
- <&CP110_LABEL(x2core_clk)>;
- dma-coherent;
- };
- };
-
- CP110_LABEL(pcie0): pcie at CP110_PCIE0_BASE {
- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
- reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>,
- <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>;
- reg-names = "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- dma-coherent;
- msi-parent = <&gic_v2m0>;
-
- bus-range = <0 0xff>;
- ranges =
- /* downstream I/O */
- <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BASE(0) 0 0x10000
- /* non-prefetchable memory */
- 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
- num-lanes = <1>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_clk)>;
- status = "disabled";
- };
-
- CP110_LABEL(pcie1): pcie at CP110_PCIE1_BASE {
- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
- reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>,
- <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>;
- reg-names = "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- dma-coherent;
- msi-parent = <&gic_v2m0>;
-
- bus-range = <0 0xff>;
- ranges =
- /* downstream I/O */
- <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BASE(1) 0 0x10000
- /* non-prefetchable memory */
- 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
-
- num-lanes = <1>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_clk)>;
- status = "disabled";
- };
-
- CP110_LABEL(pcie2): pcie at CP110_PCIE2_BASE {
- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
- reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>,
- <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>;
- reg-names = "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- dma-coherent;
- msi-parent = <&gic_v2m0>;
-
- bus-range = <0 0xff>;
- ranges =
- /* downstream I/O */
- <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BASE(2) 0 0x10000
- /* non-prefetchable memory */
- 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
-
- num-lanes = <1>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_clk)>;
- status = "disabled";
- };
-
- /* 1 GHz fixed main PLL */
- CP110_LABEL(mainpll): CP110_LABEL(mainpll) {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <1000000000>;
- };
-
- CP110_LABEL(x2core_clk): CP110_LABEL(x2core_clk) {
- compatible = "fixed-factor-clock";
- clocks = <&CP110_LABEL(mainpll)>;
- #clock-cells = <0>;
- clock-mult = <1>;
- clock-div = <2>;
- };
-
- CP110_LABEL(core_clk): CP110_LABEL(core_clk) {
- compatible = "fixed-factor-clock";
- clocks = <&CP110_LABEL(mainpll)>;
- #clock-cells = <0>;
- clock-mult = <1>;
- clock-div = <2>;
- };
-
- CP110_LABEL(sdio_clk): CP110_LABEL(sdio_clk) {
- compatible = "fixed-factor-clock";
- clocks = <&CP110_LABEL(mainpll)>;
- #clock-cells = <0>;
- clock-mult = <2>;
- clock-div = <5>;
- };
-
- CP110_LABEL(nand_clk): CP110_LABEL(nand_clk) {
- compatible = "fixed-factor-clock";
- clocks = <&CP110_LABEL(mainpll)>;
- #clock-cells = <0>;
- clock-mult = <2>;
- clock-div = <5>;
- };
-
- CP110_LABEL(ppv2_clk): CP110_LABEL(ppv2_clk) {
- compatible = "fixed-factor-clock";
- clocks = <&CP110_LABEL(mainpll)>;
- #clock-cells = <0>;
- clock-mult = <1>;
- clock-div = <3>;
- };
-
- CP110_LABEL(slow_io_clk): CP110_LABEL(slow_io_clk) {
- compatible = "fixed-factor-clock";
- clocks = <&CP110_LABEL(mainpll)>;
- #clock-cells = <0>;
- clock-mult = <1>;
- clock-div = <4>;
- };
-};
--
2.29.0
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