[edk2-devel] [PATCH v1] MdePkg: Support Extended Control Register(XCR) Read and Write.
Wu, Jiaxin
jiaxin.wu at intel.com
Wed Mar 31 04:21:30 UTC 2021
Thanks the comments, I will refine the patch according the feedback.
> -----Original Message-----
> From: Yao, Jiewen <jiewen.yao at intel.com>
> Sent: Wednesday, March 31, 2021 10:20 AM
> To: devel at edk2.groups.io; gaoliming at byosoft.com.cn; Wu, Jiaxin
> <jiaxin.wu at intel.com>
> Cc: Kinney, Michael D <michael.d.kinney at intel.com>; Liu, Zhiguang
> <zhiguang.liu at intel.com>; Zhang, Hongbin1 <hongbin1.zhang at intel.com>
> Subject: RE: [edk2-devel] [PATCH v1] MdePkg: Support Extended Control
> Register(XCR) Read and Write.
>
> Agree with Liming.
>
> For IA32, you get parameter from stack -
> mov edx, [esp + 12]
> mov eax, [esp + 8]
> mov ecx, [esp + 4]
>
> For X64, you get parameter from GP register - RCX, RDX, R8, R9 for the first 4
> parameter. They are on the stack since the 5th parameter.
>
> The code may be sharable only if they do not have any input parameter. But
> not in this case.
>
> Even though, I still recommend we have two copy - like AsmReadCs() in 2
> ReadCs.nasm, because we need different context definition, such as "DEFAULT
> REL"
>
> Thank you
> Yao Jiewen
>
>
> > -----Original Message-----
> > From: devel at edk2.groups.io <devel at edk2.groups.io> On Behalf Of
> gaoliming
> > Sent: Wednesday, March 31, 2021 10:05 AM
> > To: devel at edk2.groups.io; Wu, Jiaxin <jiaxin.wu at intel.com>
> > Cc: Kinney, Michael D <michael.d.kinney at intel.com>; Liu, Zhiguang
> > <zhiguang.liu at intel.com>; Zhang, Hongbin1 <hongbin1.zhang at intel.com>
> > Subject: 回复: [edk2-devel] [PATCH v1] MdePkg: Support Extended Control
> > Register(XCR) Read and Write.
> >
> > Jiaxin:
> > 32bit function and 64bit function have the different calling convention.
> > Their assembly function can't be shared.
> >
> > This new API interface is same to AsmWriteMsr64(). You can refer
> > AsmWriteMsr64() implementation in BaseLib.
> >
> > Thanks
> > Liming
> > > -----邮件原件-----
> > > 发件人: devel at edk2.groups.io <devel at edk2.groups.io> 代表 Wu, Jiaxin
> > > 发送时间: 2021年3月31日 9:56
> > > 收件人: devel at edk2.groups.io; gaoliming at byosoft.com.cn
> > > 抄送: Kinney, Michael D <michael.d.kinney at intel.com>; Liu, Zhiguang
> > > <zhiguang.liu at intel.com>; Zhang, Hongbin1 <hongbin1.zhang at intel.com>
> > > 主题: Re: [edk2-devel] [PATCH v1] MdePkg: Support Extended Control
> > > Register(XCR) Read and Write.
> > >
> > > Actually, the implementation under ia32 should be also workable for X64, I
> > > just put it under ia32.
> > >
> > > Liming, do you have suggestion where can we place the code?
> > >
> > > Thanks,
> > > Jiaxin
> > >
> > > > -----Original Message-----
> > > > From: devel at edk2.groups.io <devel at edk2.groups.io> On Behalf Of
> > > gaoliming
> > > > Sent: Wednesday, March 31, 2021 9:51 AM
> > > > To: devel at edk2.groups.io; Wu, Jiaxin <jiaxin.wu at intel.com>
> > > > Cc: Kinney, Michael D <michael.d.kinney at intel.com>; Liu, Zhiguang
> > > > <zhiguang.liu at intel.com>; Zhang, Hongbin1 <hongbin1.zhang at intel.com>
> > > > Subject: 回复: [edk2-devel] [PATCH v1] MdePkg: Support Extended
> Control
> > > > Register(XCR) Read and Write.
> > > >
> > > > Where is X64 implementation for this new API?
> > > >
> > > > > -----邮件原件-----
> > > > > 发件人: devel at edk2.groups.io <devel at edk2.groups.io> 代表 Wu,
> > > Jiaxin
> > > > > 发送时间: 2021年3月31日 9:20
> > > > > 收件人: devel at edk2.groups.io
> > > > > 抄送: Michael D Kinney <michael.d.kinney at intel.com>; Liming Gao
> > > > > <gaoliming at byosoft.com.cn>; Zhiguang Liu <zhiguang.liu at intel.com>;
> > > Zhang
> > > > > Hongbin1 <hongbin1.zhang at intel.com>
> > > > > 主题: [edk2-devel] [PATCH v1] MdePkg: Support Extended Control
> > > > > Register(XCR) Read and Write.
> > > > >
> > > > > https://bugzilla.tianocore.org/show_bug.cgi?id=3284
> > > > >
> > > > > This patch is to support Extended Control Register(XCR) Read
> > > > > and Write.
> > > > >
> > > > > Cc: Michael D Kinney <michael.d.kinney at intel.com>
> > > > > Cc: Liming Gao <gaoliming at byosoft.com.cn>
> > > > > Cc: Zhiguang Liu <zhiguang.liu at intel.com>
> > > > > Signed-off-by: Zhang Hongbin1 <hongbin1.zhang at intel.com>
> > > > > Signed-off-by: Jiaxin Wu <Jiaxin.wu at intel.com>
> > > > > ---
> > > > > MdePkg/Include/Library/BaseLib.h | 46
> > > > > ++++++++++++++++++++++++++++++-
> > > > > MdePkg/Library/BaseLib/BaseLib.inf | 4 ++-
> > > > > MdePkg/Library/BaseLib/Ia32/ReadXcr.nasm | 31
> > > > > +++++++++++++++++++++
> > > > > MdePkg/Library/BaseLib/Ia32/WriteXcr.nasm | 34
> > > > > +++++++++++++++++++++++
> > > > > 4 files changed, 113 insertions(+), 2 deletions(-)
> > > > > create mode 100644 MdePkg/Library/BaseLib/Ia32/ReadXcr.nasm
> > > > > create mode 100644 MdePkg/Library/BaseLib/Ia32/WriteXcr.nasm
> > > > >
> > > > > diff --git a/MdePkg/Include/Library/BaseLib.h
> > > > > b/MdePkg/Include/Library/BaseLib.h
> > > > > index 1171a0ffb5..c51633ad73 100644
> > > > > --- a/MdePkg/Include/Library/BaseLib.h
> > > > > +++ b/MdePkg/Include/Library/BaseLib.h
> > > > > @@ -1,10 +1,10 @@
> > > > > /** @file
> > > > > Provides string functions, linked list functions, math functions,
> > > > > synchronization
> > > > > functions, file path functions, and CPU architecture-specific
> > > > functions.
> > > > >
> > > > > -Copyright (c) 2006 - 2019, Intel Corporation. All rights
> > reserved.<BR>
> > > > > +Copyright (c) 2006 - 2021, Intel Corporation. All rights
> > reserved.<BR>
> > > > > Portions copyright (c) 2008 - 2009, Apple Inc. All rights
> > reserved.<BR>
> > > > > Copyright (c) Microsoft Corporation.<BR>
> > > > > Portions Copyright (c) 2020, Hewlett Packard Enterprise Development
> > > LP.
> > > > All
> > > > > rights reserved.<BR>
> > > > >
> > > > > SPDX-License-Identifier: BSD-2-Clause-Patent
> > > > > @@ -7493,7 +7493,51 @@ PatchInstructionX86 (
> > > > > OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,
> > > > > IN UINT64 PatchValue,
> > > > > IN UINTN ValueSize
> > > > > );
> > > > >
> > > > > +/**
> > > > > + Returns a 64-bit Extended Control Register(XCR).
> > > > > +
> > > > > + Reads and returns the 64-bit XCR specified by Index. No parameter
> > > > > checking is
> > > > > + performed on Index, and some Index values may cause CPU
> > > exceptions.
> > > > > The
> > > > > + caller must either guarantee that Index is valid, or the caller
> > must
> > > > set up
> > > > > + exception handlers to catch the exceptions. This function is only
> > > > available
> > > > > + on IA-32 and x64.
> > > > > +
> > > > > + @param Index The 32-bit XCR index to read.
> > > > > +
> > > > > + @return The value of the XCR identified by Index.
> > > > > +
> > > > > +**/
> > > > > +UINT64
> > > > > +EFIAPI
> > > > > +AsmReadXcr (
> > > > > + IN UINT32 Index
> > > > > + );
> > > > > +
> > > > > +/**
> > > > > + Writes a 64-bit value to a Extended Control Register(XCR), and
> > returns
> > > > the
> > > > > + value.
> > > > > +
> > > > > + Writes the 64-bit value specified by Value to the XCR specified by
> > > > Index.
> > > > > The
> > > > > + 64-bit value written to the XCR is returned. No parameter checking
> > is
> > > > > + performed on Index or Value, and some of these may cause CPU
> > > > > exceptions. The
> > > > > + caller must either guarantee that Index and Value are valid, or the
> > > > caller
> > > > > + must establish proper exception handlers. This function is only
> > > > available
> > > > > on
> > > > > + IA-32 and x64.
> > > > > +
> > > > > + @param Index The 32-bit XCR index to write.
> > > > > + @param Value The 64-bit value to write to the XCR.
> > > > > +
> > > > > + @return Value
> > > > > +
> > > > > +**/
> > > > > +UINT64
> > > > > +EFIAPI
> > > > > +AsmWriteXcr (
> > > > > + IN UINT32 Index,
> > > > > + IN UINT64 Value
> > > > > + );
> > > > > +
> > > > > #endif // defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
> > > > > #endif // !defined (__BASE_LIB__)
> > > > > diff --git a/MdePkg/Library/BaseLib/BaseLib.inf
> > > > > b/MdePkg/Library/BaseLib/BaseLib.inf
> > > > > index 3b85c56c3c..e62031ea11 100644
> > > > > --- a/MdePkg/Library/BaseLib/BaseLib.inf
> > > > > +++ b/MdePkg/Library/BaseLib/BaseLib.inf
> > > > > @@ -1,9 +1,9 @@
> > > > > ## @file
> > > > > # Base Library implementation.
> > > > > #
> > > > > -# Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.
> > <BR>
> > > > > +# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.
> > <BR>
> > > > > # Portions copyright (c) 2008 - 2009, Apple Inc. All rights
> > > > reserved.<BR>
> > > > > # Portions copyright (c) 2011 - 2013, ARM Ltd. All rights
> > reserved.<BR>
> > > > > # Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All
> > > > > rights reserved.<BR>
> > > > > #
> > > > > # SPDX-License-Identifier: BSD-2-Clause-Patent
> > > > > @@ -63,10 +63,12 @@
> > > > > BaseLibInternals.h
> > > > >
> > > > > [Sources.Ia32]
> > > > > Ia32/WriteTr.nasm
> > > > > Ia32/Lfence.nasm
> > > > > + Ia32/ReadXcr.nasm
> > > > > + Ia32/WriteXcr.nasm
> > > > >
> > > > > Ia32/Wbinvd.c | MSFT
> > > > > Ia32/WriteMm7.c | MSFT
> > > > > Ia32/WriteMm6.c | MSFT
> > > > > Ia32/WriteMm5.c | MSFT
> > > > > diff --git a/MdePkg/Library/BaseLib/Ia32/ReadXcr.nasm
> > > > > b/MdePkg/Library/BaseLib/Ia32/ReadXcr.nasm
> > > > > new file mode 100644
> > > > > index 0000000000..5d50d8ba01
> > > > > --- /dev/null
> > > > > +++ b/MdePkg/Library/BaseLib/Ia32/ReadXcr.nasm
> > > > > @@ -0,0 +1,31 @@
> > > > >
> > > >
> > +;--------------------------------------------------------------------------
> > > > ----
> > > > > +;
> > > > > +; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> > > > > +; SPDX-License-Identifier: BSD-2-Clause-Patent
> > > > > +;
> > > > > +; Module Name:
> > > > > +;
> > > > > +; ReadXcr.Asm
> > > > > +;
> > > > > +; Abstract:
> > > > > +;
> > > > > +; AsmReadXcr function
> > > > > +;
> > > > > +; Notes:
> > > > > +;
> > > > >
> > > >
> > +;--------------------------------------------------------------------------
> > > > ----
> > > > > +
> > > > > + SECTION .text
> > > > > +
> > > > >
> > > >
> > +;--------------------------------------------------------------------------
> > > > ----
> > > > > +; UINT64
> > > > > +; EFIAPI
> > > > > +; AsmReadXcr (
> > > > > +; IN UINT32 Index
> > > > > +; );
> > > > >
> > > >
> > +;--------------------------------------------------------------------------
> > > > ----
> > > > > +global ASM_PFX(AsmReadXcr)
> > > > > +ASM_PFX(AsmReadXcr):
> > > > > + mov ecx, [esp + 4]
> > > > > + xgetbv
> > > > > + ret
> > > > > \ No newline at end of file
> > > > > diff --git a/MdePkg/Library/BaseLib/Ia32/WriteXcr.nasm
> > > > > b/MdePkg/Library/BaseLib/Ia32/WriteXcr.nasm
> > > > > new file mode 100644
> > > > > index 0000000000..009d41864b
> > > > > --- /dev/null
> > > > > +++ b/MdePkg/Library/BaseLib/Ia32/WriteXcr.nasm
> > > > > @@ -0,0 +1,34 @@
> > > > >
> > > >
> > +;--------------------------------------------------------------------------
> > > > ----
> > > > > +;
> > > > > +; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> > > > > +; SPDX-License-Identifier: BSD-2-Clause-Patent
> > > > > +;
> > > > > +; Module Name:
> > > > > +;
> > > > > +; WriteXcr.nasm
> > > > > +;
> > > > > +; Abstract:
> > > > > +;
> > > > > +; AsmWriteXcr function
> > > > > +;
> > > > > +; Notes:
> > > > > +;
> > > > >
> > > >
> > +;--------------------------------------------------------------------------
> > > > ----
> > > > > +
> > > > > + SECTION .text
> > > > > +
> > > > >
> > > >
> > +;--------------------------------------------------------------------------
> > > > ----
> > > > > +; UINT64
> > > > > +; EFIAPI
> > > > > +; AsmWriteXcr (
> > > > > +; IN UINT32 Index,
> > > > > +; IN UINT64 Value
> > > > > +; );
> > > > >
> > > >
> > +;--------------------------------------------------------------------------
> > > > ----
> > > > > +global ASM_PFX(AsmWriteXcr)
> > > > > +ASM_PFX(AsmWriteXcr):
> > > > > + mov edx, [esp + 12]
> > > > > + mov eax, [esp + 8]
> > > > > + mov ecx, [esp + 4]
> > > > > + xsetbv
> > > > > + ret
> > > > > \ No newline at end of file
> > > > > --
> > > > > 2.16.2.windows.1
> > > > >
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