[edk2-devel] [edk2-platforms][PATCH 24/30] RiscV/ProcessorPkg: Use mtime CSR library
Abner Chang
abner.chang at hpe.com
Tue Oct 19 08:10:01 UTC 2021
Use mtime CSR library interface to access mtime
CSR.
Cc: Sunil V L <sunilvl at ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer at hpe.com>
Signed-off-by: Abner Chang <abner.chang at hpe.com>
---
.../Library/RiscVTimerLib/BaseRiscVTimerLib.inf | 3 ++-
Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf | 1 +
.../ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c | 6 +++---
Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c | 2 +-
4 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
index c914d3b4b6..3c61149da8 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
@@ -30,5 +30,6 @@
BaseLib
PcdLib
RiscVCpuLib
- RiscVPlatformTimerLib
+ MachineModeTimerLib
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf
index 29cc4413bd..a422c12e32 100644
--- a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf
@@ -26,6 +26,7 @@
CpuLib
CpuExceptionHandlerLib
DebugLib
+ MachineModeTimerLib
RiscVCpuLib
TimerLib
UefiBootServicesTableLib
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c
index 97fe2aef4b..54ca99787e 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c
@@ -36,9 +36,9 @@ InternalRiscVTimerDelay (
//
// The target timer count is calculated here
//
- Ticks = RiscVReadMachineTimer () + Delay;
+ Ticks = RiscVReadMachineTimerInterface () + Delay;
Delay = 1 << (RISCV_TIMER_COMPARE_BITS - 2);
- while (((Ticks - RiscVReadMachineTimer ()) & ( 1 << (RISCV_TIMER_COMPARE_BITS - 1))) == 0) {
+ while (((Ticks - RiscVReadMachineTimerInterface ()) & ( 1 << (RISCV_TIMER_COMPARE_BITS - 1))) == 0) {
CpuPause ();
}
} while (Times-- > 0);
@@ -118,7 +118,7 @@ GetPerformanceCounter (
VOID
)
{
- return (UINT64)RiscVReadMachineTimer ();
+ return (UINT64)RiscVReadMachineTimerInterface ();
}
/**return
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c
index b8b8e91a6c..3104c6d2de 100644
--- a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c
@@ -223,7 +223,7 @@ CpuGetTimerValue (
return EFI_INVALID_PARAMETER;
}
- *TimerValue = (UINT64)RiscVReadMachineTimer ();
+ *TimerValue = (UINT64)RiscVReadMachineTimerInterface ();
if (TimerPeriod != NULL) {
*TimerPeriod = DivU64x32 (
1000000000000000u,
--
2.31.1
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