[edk2-devel] [PATCH v3] UefiCpuPkg: VTF0 Linear-Address Translation to a 1-GByte Page till 512GB
Ni, Ray
ray.ni at intel.com
Tue Sep 14 02:19:39 UTC 2021
5. There are duplication macros for BIT definition.
Can you check the Intel Software Development Manual Volume 3 chapter 4.5 "4-Level Paging and 5-Level Paging"
and define the proper macro in a common file "PageTables.inc"?
Thanks,
Ray
-----Original Message-----
From: Ni, Ray
Sent: Tuesday, September 14, 2021 10:15 AM
To: S, Ashraf Ali <ashraf.ali.s at intel.com>; devel at edk2.groups.io
Cc: Kumar, Rahul1 <Rahul1.Kumar at intel.com>; De, Debkumar <debkumar.de at intel.com>; Han, Harry <harry.han at intel.com>; West, Catharine <Catharine.West at intel.com>; V, Sangeetha <sangeetha.v at intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty at intel.com>; Dureja, Sahil <sahil.dureja at intel.com>
Subject: RE: [PATCH v3] UefiCpuPkg: VTF0 Linear-Address Translation to a 1-GByte Page till 512GB
1. Can you please update the copyright year?
2. The original code uses naming rule like "debugType". The first letter of first word is in lower case.
Can you make your changes be consistent to the existing code? For example:
"pageTable", "fileName"
3. Can you evaluate below my changes? It avoids to explicitly check the pageTable later.
commandLine = (
'nasm',
'-D', 'ARCH_%s' % arch.upper(),
'-D', 'DEBUG_%s' % str(debugType).upper(),
+ '-D', pageTable.upper(),
'-o', output,
'Vtf0.nasmb',
)
4. Can you use FILE_FORMAT in below code as well?
for filename in glob.glob(os.path.join('Bin', PageTable, '*.raw')):
Thanks,
Ray
-----Original Message-----
From: S, Ashraf Ali <ashraf.ali.s at intel.com>
Sent: Saturday, September 11, 2021 8:07 PM
To: devel at edk2.groups.io
Cc: S, Ashraf Ali <ashraf.ali.s at intel.com>; Ni, Ray <ray.ni at intel.com>; Kumar, Rahul1 <rahul1.kumar at intel.com>; De, Debkumar <debkumar.de at intel.com>; Han, Harry <harry.han at intel.com>; West, Catharine <catharine.west at intel.com>; V, Sangeetha <sangeetha.v at intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty at intel.com>; Dureja, Sahil <sahil.dureja at intel.com>
Subject: [PATCH v3] UefiCpuPkg: VTF0 Linear-Address Translation to a 1-GByte Page till 512GB
[edk2-devel] [PATCH V3]
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3473
X64 Reset Vector Code can access the memory range till 4GB using the
Linear-Address Translation to a 2-MByte Page, when user wants to use
more than 4G using 2M Page it will leads to use more number of Page
table entries. using the 1-GByte Page table user can use more than
4G Memory by reducing the page table entries using 1-GByte Page,
this patch attached can access memory range till 512GByte via Linear-
Address Translation to a 1-GByte Page
Test Result: Tested in both Simulation environment and Hardware
both works fine without any issues.
Cc: Ray Ni <ray.ni at intel.com>
Cc: Rahul Kumar <rahul1.kumar at intel.com>
Cc: Debkumar De <debkumar.de at intel.com>
Cc: Harry Han <harry.han at intel.com>
Cc: Catharine West <catharine.west at intel.com>
Cc: Sangeetha V <sangeetha.v at intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty at intel.com>
Cc: Sahil Dureja <sahil.dureja at intel.com>
Signed-off-by: Ashraf Ali S <ashraf.ali.s at intel.com>
---
.../PageTable1G/ResetVector.ia32.port80.raw | Bin 0 -> 484 bytes
.../Vtf0/Bin/PageTable1G/ResetVector.ia32.raw | Bin 0 -> 468 bytes
.../PageTable1G/ResetVector.ia32.serial.raw | Bin 0 -> 868 bytes
.../PageTable1G/ResetVector.x64.port80.raw | Bin 0 -> 12292 bytes
.../Vtf0/Bin/PageTable1G/ResetVector.x64.raw | Bin 0 -> 12292 bytes
.../PageTable1G/ResetVector.x64.serial.raw | Bin 0 -> 12292 bytes
.../PageTable2M/ResetVector.ia32.port80.raw | Bin 0 -> 484 bytes
.../Vtf0/Bin/PageTable2M/ResetVector.ia32.raw | Bin 0 -> 468 bytes
.../PageTable2M/ResetVector.ia32.serial.raw | Bin 0 -> 868 bytes
.../ResetVector.x64.port80.raw | Bin 28676 -> 28676 bytes
.../Bin/{ => PageTable2M}/ResetVector.x64.raw | Bin 28676 -> 28676 bytes
.../ResetVector.x64.serial.raw | Bin 28676 -> 28676 bytes
.../Vtf0/Bin/ResetVector.ia32.port80.raw | Bin 516 -> 0 bytes
.../ResetVector/Vtf0/Bin/ResetVector.ia32.raw | Bin 484 -> 0 bytes
.../Vtf0/Bin/ResetVector.ia32.serial.raw | Bin 884 -> 0 bytes
.../ResetVector/Vtf0/Bin/ResetVector.inf | 4 +-
.../ResetVector/Vtf0/Bin/ResetVector1G.inf | 31 +++++++
UefiCpuPkg/ResetVector/Vtf0/Build.py | 83 ++++++++++++------
UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt | 2 +-
UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 6 +-
.../ResetVector/Vtf0/X64/1GPageTables.asm | 66 ++++++++++++++
.../X64/{PageTables.asm => 2MPageTables.asm} | 0
22 files changed, 159 insertions(+), 33 deletions(-)
create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.ia32.port80.raw
create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.ia32.raw
create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.ia32.serial.raw
create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.x64.port80.raw
create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.x64.raw
create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.x64.serial.raw
create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable2M/ResetVector.ia32.port80.raw
create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable2M/ResetVector.ia32.raw
create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable2M/ResetVector.ia32.serial.raw
rename UefiCpuPkg/ResetVector/Vtf0/Bin/{ => PageTable2M}/ResetVector.x64.port80.raw (56%)
rename UefiCpuPkg/ResetVector/Vtf0/Bin/{ => PageTable2M}/ResetVector.x64.raw (56%)
rename UefiCpuPkg/ResetVector/Vtf0/Bin/{ => PageTable2M}/ResetVector.x64.serial.raw (56%)
delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw
delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.raw
delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.serial.raw
create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector1G.inf
create mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm
rename UefiCpuPkg/ResetVector/Vtf0/X64/{PageTables.asm => 2MPageTables.asm} (100%)
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.ia32.port80.raw b/UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.ia32.port80.raw
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diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.x64.raw b/UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable2M/ResetVector.x64.raw
similarity index 56%
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diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.raw b/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.raw
deleted file mode 100644
index e34780a3a2c9b22bd10a1d5a405e344faaff94f3..0000000000000000000000000000000000000000
GIT binary patch
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diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.serial.raw b/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.serial.raw
deleted file mode 100644
index 6dfa68eabb48a44bc50a0b7fe678f80b5cdadfd5..0000000000000000000000000000000000000000
GIT binary patch
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diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf b/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf
index 8fc9564ebb..8c4de04bbc 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf
+++ b/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf
@@ -22,10 +22,10 @@
#
[Binaries.Ia32]
- RAW|ResetVector.ia32.raw|*
+ RAW|PageTable2M/ResetVector.ia32.raw|*
[Binaries.X64]
- RAW|ResetVector.x64.raw|*
+ RAW|PageTable2M/ResetVector.x64.raw|*
[UserExtensions.TianoCore."ExtraFiles"]
ResetVectorExtra.uni
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector1G.inf b/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector1G.inf
new file mode 100644
index 0000000000..4f5a2d14e3
--- /dev/null
+++ b/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector1G.inf
@@ -0,0 +1,31 @@
+## @file
+# Reset Vector binary
+#
+# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ResetVector
+ MODULE_UNI_FILE = ResetVector.uni
+ FILE_GUID = 1BA0062E-C779-4582-8566-336AE8F78F09
+ MODULE_TYPE = SEC
+ VERSION_STRING = 1.1
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[Binaries.Ia32]
+ RAW|PageTable1G/ResetVector.ia32.raw|*
+
+[Binaries.X64]
+ RAW|PageTable1G/ResetVector.x64.raw|*
+
+[UserExtensions.TianoCore."ExtraFiles"]
+ ResetVectorExtra.uni
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Build.py b/UefiCpuPkg/ResetVector/Vtf0/Build.py
index b791d32762..0bcc31554c 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Build.py
+++ b/UefiCpuPkg/ResetVector/Vtf0/Build.py
@@ -11,40 +11,65 @@ import os
import subprocess
import sys
+PAGE_TABLE_2M = 'PageTable2M'
+PAGE_TABLE_1G = 'PageTable1G'
+
+FILE_FORMAT = '.raw'
+PAGE_TABLES = [PAGE_TABLE_2M, PAGE_TABLE_1G]
+
def RunCommand(commandLine):
#print ' '.join(commandLine)
return subprocess.call(commandLine)
-for filename in glob.glob(os.path.join('Bin', '*.raw')):
- os.remove(filename)
+for PageTable in PAGE_TABLES:
+ for filename in glob.glob(os.path.join('Bin', PageTable, '*.raw')):
+ os.remove(filename)
for arch in ('ia32', 'x64'):
for debugType in (None, 'port80', 'serial'):
- output = os.path.join('Bin', 'ResetVector')
- output += '.' + arch
- if debugType is not None:
- output += '.' + debugType
- output += '.raw'
- commandLine = (
- 'nasm',
- '-D', 'ARCH_%s' % arch.upper(),
- '-D', 'DEBUG_%s' % str(debugType).upper(),
- '-o', output,
- 'Vtf0.nasmb',
- )
- print(f"Command : {' '.join(commandLine)}")
- ret = RunCommand(commandLine)
- if ret != 0:
- print(f"something went wrong while executing {commandLine[-1]}")
- sys.exit()
- print('\tASM\t' + output)
-
- commandLine = (
- 'python',
- 'Tools/FixupForRawSection.py',
- output,
- )
- print('\tFIXUP\t' + output)
- ret = RunCommand(commandLine)
- if ret != 0: sys.exit(ret)
+ for PageTable in PAGE_TABLES:
+ directory = os.path.join('Bin', PageTable)
+
+ # output raw binary name with arch type
+ filename = 'ResetVector' + '.' + arch
+
+ if debugType is not None:
+ filename += '.' + debugType
+ filename += FILE_FORMAT
+
+ output = os.path.join(directory, filename)
+
+ # if the directory not exists then create it
+ if not os.path.isdir(directory):
+ os.mkdir(directory)
+
+ # Prepare the command to execute the nasmb
+ commandLine = (
+ 'nasm',
+ '-D', 'ARCH_%s' % arch.upper(),
+ '-D', 'DEBUG_%s' % str(debugType).upper(),
+ '-o', output,
+ 'Vtf0.nasmb',
+ )
+
+ # if the Page table is Linear-Address Translation to a 1-GByte Page
+ # append Pre-Define a Macro PAGE_TABLE_1G
+ if PageTable == PAGE_TABLE_1G:
+ commandLine += ('-dPAGE_TABLE_1G',)
+
+ print(f"Command : {' '.join(commandLine)}")
+ ret = RunCommand(commandLine)
+ if ret != 0:
+ print(f"something went wrong while executing {commandLine[-1]}")
+ sys.exit()
+ print('\tASM\t' + output)
+
+ commandLine = (
+ 'python',
+ 'Tools/FixupForRawSection.py',
+ output,
+ )
+ print('\tFIXUP\t' + output)
+ ret = RunCommand(commandLine)
+ if ret != 0: sys.exit(ret)
diff --git a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt b/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt
index e6e5b54243..97f4600968 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt
+++ b/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt
@@ -29,7 +29,7 @@ EBP/RBP - Pointer to the start of the Boot Firmware Volume
=== HOW TO BUILD VTF0 ===
Dependencies:
-* Python 2.5~2.7
+* Python 3 or newer
* Nasm 2.03 or newer
To rebuild the VTF0 binaries:
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
index 493738c79c..556feac5c2 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
+++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
@@ -36,7 +36,11 @@
%include "PostCodes.inc"
%ifdef ARCH_X64
-%include "X64/PageTables.asm"
+ %ifdef PAGE_TABLE_1G
+ %include "X64/1GPageTables.asm"
+ %else
+ %include "X64/2MPageTables.asm"
+ %endif
%endif
%ifdef DEBUG_PORT80
diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm
new file mode 100644
index 0000000000..11d73637d2
--- /dev/null
+++ b/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm
@@ -0,0 +1,66 @@
+;------------------------------------------------------------------------------
+; @file
+; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x8000000000 (512GB)
+;
+; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+; Linear-Address Translation to a 1-GByte Page
+;
+;------------------------------------------------------------------------------
+
+BITS 64
+
+%define ALIGN_TOP_TO_4K_FOR_PAGING
+
+%define PAGE_PRESENT 0x01
+%define PAGE_READ_WRITE 0x02
+%define PAGE_USER_SUPERVISOR 0x04
+%define PAGE_WRITE_THROUGH 0x08
+%define PAGE_CACHE_DISABLE 0x010
+%define PAGE_ACCESSED 0x020
+%define PAGE_DIRTY 0x040
+%define PAGE_PAT 0x080
+%define PAGE_GLOBAL 0x0100
+%define PAGE_2M_MBO 0x080
+%define PAGE_2M_PAT 0x01000
+%define PAGE_1G 0x80
+
+%define PAGE_PDP_ATTR (PAGE_ACCESSED + \
+ PAGE_READ_WRITE + \
+ PAGE_PRESENT)
+
+%define PAGE_PDP_1G_ATTR (PAGE_ACCESSED + \
+ PAGE_READ_WRITE + \
+ PAGE_DIRTY + \
+ PAGE_PRESENT + \
+ PAGE_1G)
+
+%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory)
+%define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x))
+
+%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \
+ PAGE_PDP_ATTR)
+
+%define PDP_1G(x) ((x << 30) + PAGE_PDP_1G_ATTR)
+
+ALIGN 16
+
+TopLevelPageDirectory:
+
+ ;
+ ; Top level Page Directory Pointers (1 * 512GB entry)
+ ;
+ DQ PDP(0x1000)
+
+ TIMES 0x1000-PGTBLS_OFFSET($) DB 0
+ ;
+ ; Next level Page Directory Pointers (512 * 1GB entries => 512GB)
+ ;
+%assign i 0
+%rep 512
+ DQ PDP_1G(i)
+ %assign i i+1
+%endrep
+ TIMES 0x2000-PGTBLS_OFFSET($) DB 0
+
+EndOfPageTables:
diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/2MPageTables.asm
similarity index 100%
rename from UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
rename to UefiCpuPkg/ResetVector/Vtf0/X64/2MPageTables.asm
--
2.30.2.windows.1
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