[edk2-devel] [edk2-platforms][PATCH V2 4/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-N1-Edge-X2 platform
Pranav Madhu
pranav.madhu at arm.com
Mon Apr 18 11:54:26 UTC 2022
Update the Rd-N1-Edge multichip platform specific ACPI tables to ACPI
version v6.4.
Signed-off-by: Pranav Madhu <pranav.madhu at arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc | 52 ++++---
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc | 151 ++++++++++----------
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc | 92 ++++++------
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Srat.aslc | 74 +++++-----
4 files changed, 196 insertions(+), 173 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
index 704708f94baf..4a55c33396b6 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
@@ -1,17 +1,25 @@
/** @file
-* Heterogeneous Memory Attribute Table (HMAT)
-*
-* Copyright (c) 2020-2021, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Heterogeneous Memory Attribute Table (HMAT)
+
+ The (HMAT) describes the memory attributes, such as memory side cache
+ attributes and bandwidth and latency details, related to Memory Proximity
+ Domains. The software is expected to use this information as a hint for
+ optimization, or when the system has heterogeneous memory. The attributes of
+ the memory connected to the two chips on this platform are listed in this
+ table.
+
+ Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.27, Heterogeneous Memory Attribute Table
**/
-#include <IndustryStandard/Acpi.h>
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
-#include <SgiAcpiHeader.h>
-#include <SgiPlatform.h>
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CHIP_CNT FixedPcdGet32 (PcdChipCount)
#define INITATOR_PROXIMITY_DOMAIN_CNT 2
@@ -29,12 +37,12 @@ typedef struct InitiatorTargetProximityMatrix {
} INITIATOR_TARGET_PROXIMITY_MATRIX;
typedef struct {
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER Header;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES Proximity[CHIP_CNT];
- EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO LatencyInfo;
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER Header;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES Proximity[CHIP_CNT];
+ EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO LatencyInfo;
INITIATOR_TARGET_PROXIMITY_MATRIX Matrix;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache0;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache1;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache0;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache1;
} EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE;
#pragma pack ()
@@ -43,9 +51,9 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
// Header
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE,
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
),
{
EFI_ACPI_RESERVED_BYTE,
@@ -57,15 +65,15 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
// Memory Proximity Domain
{
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x0, 0x0),
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x1, 0x1),
},
// Latency Info
- EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT (
- 0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMAIN_CNT, 100),
+ EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT (
+ 0, 0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMAIN_CNT, 100),
{
{0, 1},
{0, 1},
@@ -82,7 +90,7 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
},
// Memory Side Cache
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
0x0,
SIZE_8MB,
HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
@@ -94,7 +102,7 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
),
0),
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
0x1,
SIZE_8MB,
HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc
index f9210cc6226a..ecf444028e2e 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc
@@ -1,18 +1,24 @@
/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2019-2020, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-N1-Edge
+ dual chip platform is included in this table.
+
+ Copyright (c) 2019 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
-#include <IndustryStandard/Acpi.h>
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))
@@ -23,114 +29,115 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE_CNT * CHIP_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor[CHIP_CNT];
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE GicInterfaces[CORE_CNT * CHIP_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor[CHIP_CNT];
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
- // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
+ // Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
- // Efficiency)
+ // Efficiency,
+ // SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
- // (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
+ // (see note in 5.2.12.14 GICC Structure of ACPI v6.4).
// Chip - 0 CPUs
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-1
- 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-1
+ 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-2
- 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-2
+ 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-3
- 0, 3, GET_MPID(0x0, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-3
+ 0, 3, GET_MPID(0x0, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-4
- 0, 4, GET_MPID(0x100, 0x00), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-4
+ 0, 4, GET_MPID(0x100, 0x00), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-5
- 0, 5, GET_MPID(0x100, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-5
+ 0, 5, GET_MPID(0x100, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-6
- 0, 6, GET_MPID(0x100, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-6
+ 0, 6, GET_MPID(0x100, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-7
- 0, 7, GET_MPID(0x100, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-7
+ 0, 7, GET_MPID(0x100, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
// Chip - 1 CPUs
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-8
- 0, 8, GET_MPID(0x01000000ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-8
+ 0, 8, GET_MPID(0x01000000ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-9
- 0, 9, GET_MPID(0x01000000ULL, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-9
+ 0, 9, GET_MPID(0x01000000ULL, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-10
- 0, 10, GET_MPID(0x01000000ULL, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-10
+ 0, 10, GET_MPID(0x01000000ULL, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-11
- 0, 11, GET_MPID(0x01000000ULL, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-11
+ 0, 11, GET_MPID(0x01000000ULL, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-12
- 0, 12, GET_MPID(0x01000100ULL, 0x00ULL), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-12
+ 0, 12, GET_MPID(0x01000100ULL, 0x00ULL), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-13
- 0, 13, GET_MPID(0x01000100ULL, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-13
+ 0, 13, GET_MPID(0x01000100ULL, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-14
- 0, 14, GET_MPID(0x01000100ULL, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-14
+ 0, 14, GET_MPID(0x01000100ULL, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-15
- 0, 15, GET_MPID(0x01000100ULL, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-15
+ 0, 15, GET_MPID(0x01000100ULL, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */)
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0)
},
// GIC Distributor Entry
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
0, 3),
{
// GIC Redistributor for Chip 0
- EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
+ EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
SIZE_1MB),
// GIC Redistributor for Chip 1
- EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase)
+ EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase)
+ SGI_REMOTE_CHIP_MEM_OFFSET(1),
SIZE_1MB)
}
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc
index d78afb00c3b0..927b7a27e0c0 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc
@@ -1,30 +1,28 @@
/** @file
-* Processor Properties Topology Table (PPTT) for RD-N1-Edge dual-chip platform
-*
-* This file describes the topological structure of the processor block on the
-* RD-N1-Edge dual-chip platform in the form as defined by ACPI PPTT table. The
-* RD-N1-Edge dual-chip platform includes two RD-N1-Edge single-chip platforms
-* connected over cache coherent interconnect. Each of the RD-N1-Edge single-chip
-* platform includes two clusters with four single-thread CPUS. Each of the CPUs
-* include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cache. Each
-* cluster includes a 2MB L3 cache. Each instance of the chip includes a system
-* level cache of 8MB.
-*
-* Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-* @par Specification Reference:
-* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+ Processor Properties Topology Table (PPTT) for RD-N1-Edge dual-chip platform
+
+ This file describes the topological structure of the processor block on the
+ RD-N1-Edge dual-chip platform in the form as defined by ACPI PPTT table. The
+ RD-N1-Edge dual-chip platform includes two RD-N1-Edge single-chip platforms
+ connected over cache coherent interconnect. Each of the RD-N1-Edge single-chip
+ platform includes two clusters with four single-thread CPUS. Each of the CPUs
+ include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cache. Each
+ cluster includes a 2MB L3 cache. Each instance of the chip includes a system
+ level cache of 8MB.
+
+ Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.29, Processor Properties Topology Table
**/
-#include <IndustryStandard/Acpi.h>
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
-
-#include "SgiPlatform.h"
#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CHIP_COUNT FixedPcdGet32 (PcdChipCount)
@@ -37,10 +35,10 @@
#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) \
{ \
/* Parameters for CPU Core */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ \
PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package[PackageId].Cluster[ClusterId]), /* Parent */ \
((PackageId << 3) | (ClusterId << 2) | CpuId), /* ACPI Id */ \
2 /* Num of private resource */ \
@@ -48,47 +46,50 @@
\
/* Offsets of the private resources */ \
{ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package[PackageId].Cluster[ClusterId].Core[CpuId].DCache), \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package[PackageId].Cluster[ClusterId].Core[CpuId].ICache) \
}, \
\
/* L1 data cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package[PackageId].Cluster[ClusterId].Core[CpuId].L2Cache), \
/* Next level of cache */ \
SIZE_64KB, /* Size */ \
256, /* Num of sets */ \
4, /* Associativity */ \
PPTT_DATA_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ (((PackageId << 3) | (ClusterId << 2) | CpuId) + 1) /* Cache id */ \
), \
\
/* L1 instruction cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package[PackageId].Cluster[ClusterId].Core[CpuId].L2Cache), \
/* Next level of cache */ \
SIZE_64KB, /* Size */ \
256, /* Num of sets */ \
4, /* Associativity */ \
PPTT_INST_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ (((PackageId << 3) | (ClusterId << 2) | CpuId) + 1) /* Cache id */ \
), \
\
/* L2 cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
0, /* Next level of cache */ \
SIZE_512KB, /* Size */ \
1024, /* Num of sets */ \
8, /* Associativity */ \
PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ (((PackageId << 3) | (ClusterId << 2) | CpuId) + 1) /* Cache id */ \
), \
}
@@ -100,28 +101,29 @@
#define PPTT_CLUSTER_INIT(PackageId, ClusterId) \
{ \
/* Parameters for Cluster */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
OFFSET_OF (RD_PPTT_CLUSTER, L3Cache), /* Length */ \
PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package[PackageId]), /* Parent */ \
((PackageId << 1) | ClusterId), /* ACPI Id */ \
1 /* Num of private resource */ \
), \
\
/* Offsets of the private resources */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package[PackageId].Cluster[ClusterId].L3Cache), \
\
/* L3 cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
0, /* Next level of cache */ \
SIZE_2MB, /* Size */ \
2048, /* Num of sets */ \
16, /* Associativity */ \
PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ (((PackageId << 1) | ClusterId) + 1) /* Cache id */ \
), \
\
/* Initialize child cores */ \
@@ -139,7 +141,7 @@
**/
#define PPTT_PACKAGE_INIT(PackageId) \
{ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
OFFSET_OF (RDN1EDGEX2_PPTT_PACKAGE , Cluster[0]), /* Length */ \
PPTT_PROCESSOR_PACKAGE_FLAGS, /* Flag */ \
0, /* Parent */ \
@@ -155,7 +157,7 @@
#pragma pack(1)
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Package;
RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT];
} RDN1EDGEX2_PPTT_PACKAGE;
@@ -163,17 +165,17 @@ typedef struct {
* Processor Properties Topology Table
*/
typedef struct {
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
RDN1EDGEX2_PPTT_PACKAGE Package[CHIP_COUNT];
-} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+STATIC EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
)
},
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Srat.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Srat.aslc
index 361db7506845..9be3f3f9b527 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Srat.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Srat.aslc
@@ -1,17 +1,23 @@
/** @file
-* Static Resource Affinity Table (SRAT)
-*
-* Copyright (c) 2020, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Static Resource Affinity Table (SRAT)
+
+ SRAT table provides information that allows OSPM to associate devices such as
+ processors with system locality / proximity domains and clock domains. The
+ memory attached to the two chips on this platform and its affinity to the
+ CPUs on its respective chips is listed in this table.
+
+ Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.16, System Resource Affinity Table
**/
-#include "SgiAcpiHeader.h"
-#include "SgiPlatform.h"
-#include <IndustryStandard/Acpi.h>
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
//
// Static Resource Affinity Table
@@ -19,9 +25,9 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header;
- EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE Memory[4];
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE Gicc[16];
+ EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header;
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE Memory[4];
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE Gicc[16];
} EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE;
#pragma pack ()
@@ -30,9 +36,9 @@ EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat = {
// Header
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE,
EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE,
- EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION
+ EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION
),
0x00000001,
EFI_ACPI_RESERVED_QWORD
@@ -40,54 +46,54 @@ EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat = {
// Memory Affinity
{
// Chip 0 (2GB and 6GB)
- EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT (
0x0, FixedPcdGet64 (PcdSystemMemoryBase),
FixedPcdGet64 (PcdSystemMemorySize), 0x00000001),
- EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT (
0x0, FixedPcdGet64 (PcdDramBlock2Base),
FixedPcdGet64 (PcdDramBlock2Size), 0x00000001),
// Chip 1 (2GB and 6GB)
- EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT (
0x1, SYSTEM_MEMORY_BASE_REMOTE(1),
FixedPcdGet64 (PcdSystemMemorySize), 0x00000001),
- EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT (
0x1, DRAM_BLOCK2_BASE_REMOTE(1),
FixedPcdGet64 (PcdDramBlock2Size), 0x00000001),
},
// Processor Affinity
{
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x0, 0x00000000, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x0, 0x00000001, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x0, 0x00000002, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x0, 0x00000003, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x0, 0x00000004, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x0, 0x00000005, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x0, 0x00000006, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x0, 0x00000007, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x1, 0x00000008, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x1, 0x00000009, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x1, 0x0000000A, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x1, 0x0000000B, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x1, 0x0000000C, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x1, 0x0000000D, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x1, 0x0000000E, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x1, 0x0000000F, 0x00000001, 0x00000000),
},
};
--
2.17.1
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