[edk2-devel] [PATCH 1/4] MdeModulePkg/XhciDxe/XhciReg: Handle incorrect PSIV indices
Sean Rhodes
sean at starlabs.systems
Fri Dec 2 16:38:18 UTC 2022
Hi Hao
They are now resolved
Thanks
Sean
On Fri, 2 Dec 2022 at 06:25, Wu, Hao A <hao.a.wu at intel.com> wrote:
> Hello,
>
> I saw there are several CI check failures for this 4 patches:
> https://github.com/tianocore/edk2/pull/3702
>
> Could you help to resolve them? Thanks.
>
> Best Regards,
> Hao Wu
>
> > -----Original Message-----
> > From: devel at edk2.groups.io <devel at edk2.groups.io> On Behalf Of Sean
> > Rhodes
> > Sent: Friday, December 2, 2022 4:25 AM
> > To: devel at edk2.groups.io
> > Cc: Matt DeVillier <matt.devillier at gmail.com>; Wu, Hao A
> > <hao.a.wu at intel.com>; Ni, Ray <ray.ni at intel.com>; Rhodes, Sean
> > <sean at starlabs.systems>
> > Subject: [edk2-devel] [PATCH 1/4] MdeModulePkg/XhciDxe/XhciReg: Handle
> > incorrect PSIV indices
> >
> > From: Matt DeVillier <matt.devillier at gmail.com>
> >
> > On some platforms, including Sky Lake and Kaby Lake, the PSIV (Protocol
> Speed
> > ID Value) indicesare shared between Protocol Speed ID DWORD' in the
> > extended capabilities registers for both USB2 (Full Speed) and USB3
> (Super
> > Speed).
> >
> > An example can be found below:
> >
> > XhcCheckUsbPortSpeedUsedPsic: checking for USB2 ext caps
> > XhciPsivGetPsid: found 3 PSID entries
> > XhciPsivGetPsid: looking for port speed 1
> > XhciPsivGetPsid: PSIV 1 PSIE 2 PLT 0 PSIM 12
> > XhciPsivGetPsid: PSIV 2 PSIE 1 PLT 0 PSIM 1500
> > XhciPsivGetPsid: PSIV 3 PSIE 2 PLT 0 PSIM 480
> > XhcCheckUsbPortSpeedUsedPsic: checking for USB3 ext caps
> > XhciPsivGetPsid: found 3 PSID entries
> > XhciPsivGetPsid: looking for port speed 1
> > XhciPsivGetPsid: PSIV 1 PSIE 3 PLT 0 PSIM 5
> > XhciPsivGetPsid: PSIV 2 PSIE 3 PLT 0 PSIM 10
> > XhciPsivGetPsid: PSIV 34 PSIE 2 PLT 0 PSIM 1248
> >
> > The result is edk2 detecting USB2 devices as USB3 devices, which
> consequently
> > causes enumeration to fail.
> >
> > To avoid incorrect detection, check the extended capability registers
> for USB2
> > before USB3. If edk2 finds a match for a USB 2 device, don't check for
> USB 3.
> >
> > Cc: Hao A Wu <hao.a.wu at intel.com>
> > Cc: Ray Ni <ray.ni at intel.com>
> > Reviewed-by: Sean Rhodes <sean at starlabs.systems>
> > Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
> > Change-Id: I5bcf32105ce85fda95b4ba98a5e420e8f522374c
> > ---
> > MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c | 36 +++++++++++++++-----------
> > MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h | 1 +
> > 2 files changed, 22 insertions(+), 15 deletions(-)
> >
> > diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
> > b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
> > index 2b4a4b2444..c992323443 100644
> > --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
> > +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
> > @@ -698,25 +698,11 @@ XhcCheckUsbPortSpeedUsedPsic (
> > SpField.Dword = 0; UsbSpeedIdMap = 0; - //- // Check xHCI
> Supported
> > Protocol Capability, find the PSIV field to match- // PortSpeed
> definition when
> > the Major Revision is 03h.- //- if (Xhc->Usb3SupOffset != 0xFFFFFFFF)
> {-
> > SpField.Dword = XhciPsivGetPsid (Xhc, Xhc->Usb3SupOffset, PortSpeed);-
> if
> > (SpField.Dword != 0) {- //- // Found the corresponding PORTSC
> value in
> > PSIV field of USB3 offset.- //- UsbSpeedIdMap =
> > USB_PORT_STAT_SUPER_SPEED;- }- }- // // Check xHCI Supported
> Protocol
> > Capability, find the PSIV field to match // PortSpeed definition when
> the Major
> > Revision is 02h. //- if ((UsbSpeedIdMap == 0) && (Xhc->Usb2SupOffset
> !=
> > 0xFFFFFFFF)) {+ if (Xhc->Usb2SupOffset != 0xFFFFFFFF) {
> SpField.Dword =
> > XhciPsivGetPsid (Xhc, Xhc->Usb2SupOffset, PortSpeed); if
> (SpField.Dword != 0)
> > { //@@ -733,6 +719,12 @@ XhcCheckUsbPortSpeedUsedPsic (
> > // PSIM shows as default High-speed protocol, apply to
> High-speed
> > mapping // UsbSpeedIdMap =
> > USB_PORT_STAT_HIGH_SPEED;+ } else if (SpField.Data.Psim ==
> > XHC_SUPPORTED_PROTOCOL_USB2_FULL_SPEED_PSIM) {+ //+ //
> > PSIM shows as default Full-speed protocol, return 0+ // to
> ensure no port
> > status set+ //+ return 0; } } else if
> (SpField.Data.Psie == 1)
> > { //@@ -750,6 +742,20 @@ XhcCheckUsbPortSpeedUsedPsic (
> > } } + //+ // Check xHCI Supported Protocol Capability, find the
> PSIV field to
> > match+ // PortSpeed definition when the Major Revision is 03h.+ //+ if
> > ((UsbSpeedIdMap == 0) && (Xhc->Usb3SupOffset != 0xFFFFFFFF)) {+
> > SpField.Dword = XhciPsivGetPsid (Xhc, Xhc->Usb3SupOffset, PortSpeed);+
> if
> > (SpField.Dword != 0) {+ //+ // Found the corresponding PORTSC
> value in
> > PSIV field of USB3 offset.+ //+ UsbSpeedIdMap =
> > USB_PORT_STAT_SUPER_SPEED;+ }+ }+ return UsbSpeedIdMap; } diff
> --git
> > a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
> > b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
> > index 5fe2ba4f0e..74ac6297ba 100644
> > --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
> > +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
> > @@ -85,6 +85,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> > #define XHC_SUPPORTED_PROTOCOL_DW2_OFFSET 0x08 #define
> > XHC_SUPPORTED_PROTOCOL_PSI_OFFSET 0x10 #define
> > XHC_SUPPORTED_PROTOCOL_USB2_HIGH_SPEED_PSIM 480+#define
> > XHC_SUPPORTED_PROTOCOL_USB2_FULL_SPEED_PSIM 12 #define
> > XHC_SUPPORTED_PROTOCOL_USB2_LOW_SPEED_PSIM 1500 #pragma
> > pack (1)--
> > 2.37.2
> >
> >
> >
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