[edk2-devel][edk2-platforms][PATCH V1 3/8] WhitleyOpenBoardPkg/AcpiTables: South Cluster ASL
Nate DeSimone
nathaniel.l.desimone at intel.com
Wed Feb 9 03:21:00 UTC 2022
Reviewed-by: Nate DeSimone <nathaniel.l.desimone at intel.com>
> -----Original Message-----
> From: Oram, Isaac W <isaac.w.oram at intel.com>
> Sent: Monday, February 7, 2022 11:03 AM
> To: devel at edk2.groups.io
> Cc: Desimone, Nathaniel L <nathaniel.l.desimone at intel.com>; Chiu, Chasel
> <chasel.chiu at intel.com>
> Subject: [edk2-devel][edk2-platforms][PATCH V1 3/8]
> WhitleyOpenBoardPkg/AcpiTables: South Cluster ASL
>
> LBG ACPI DSDT content
>
> Cc: Nate DeSimone <nathaniel.l.desimone at intel.com>
> Cc: Chasel Chiu <chasel.chiu at intel.com>
> Signed-off-by: Isaac Oram <isaac.w.oram at intel.com>
> ---
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch.as
> l | 833 ++++++++++++++++++++
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchHd
> a.asl | 307 ++++++++
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchNv
> s.asl | 271 +++++++
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchPci
> e.asl | 203 +++++
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchSa
> ta.asl | 50 ++
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchXh
> ci.asl | 558 +++++++++++++
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP01_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP02_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP03_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP04_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP05_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP06_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP07_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP08_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP09_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP10_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP11_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP12_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP13_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP14_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP15_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP16_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP17_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP18_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP19_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP20_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Trace
> HubDebug.asl | 150 ++++
> Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec | 1 +
> 28 files changed, 2673 insertions(+)
>
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch.
> asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch.
> asl
> new file mode 100644
> index 0000000000..a8ea35534c
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch.
> asl
> @@ -0,0 +1,833 @@
> +/** @file
> +
> + @copyright
> + Copyright 1999 - 2020 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <Register/PchRegsPcr.h>
> +
> +Name (PNVB, 0xFFFF0000) // PCH NVS Base address
> +Name (PNVL, 0xAA55) // PCH NVS Length
> +Include ("PchNvs.asl")
> +
> +//
> +// Trace Hub debug library
> +// Include it earlier so the debug function can be used as soon as possible
> +//
> +Include ("TraceHubDebug.asl")
> +
> +Name(SPTH,1)
> +Name(SPTL,2)
> +Method(PCHV) {
> + If(LEqual(PCHS, 1)) { Return (SPTH) } // series=H -> SPT-H
> + If(LEqual(PCHS, 2)) { Return (SPTL) } // series=LP -> SPT-LP
> + Return (0)
> +}
> +
> +//
> +// This PME event (PCH's GPE 6Dh) is received when any PCH internal
> device with
> +// PCI Power Management capabilities on bus 0 asserts the equivalent of
> the PME# signal.
> +//
> +Scope(\_GPE) {
> + Method(_L6D, 0, Serialized) {
> + \_SB.PC00.XHCI.GPEH()
> + \_SB.PC00.CAVS.GPEH()
> + \_SB.PC00.GBE1.GPEH()
> + }
> +}
> +
> +Scope (\_SB.PC00) {
> +
> + //
> + // PCH reserved resource
> + //
> + Device(PRRE) {
> + Name(_HID,EISAID("PNP0C02")) // motherboard resource
> + Name(_UID,"PCHRESV")
> + Name(_STA,0x3) // device present and decodes its resources, but not to
> be displayed in OSPM
> +
> + Method(_CRS,0,Serialized)
> + {
> + Name(BUF0,ResourceTemplate(){
> + //
> + // PCH RESERVED MMIO RANGE
> + // 0xFD000000 to 0xFE7FFFFF
> + // to skip over address range that might be claimed by the GPIO, Intel
> Serial IO, Thermal, TraceHub and CIO2 devices
> + // need to split this into 5 ranges
> + // The GPIO COMM0,1,3 and SerialIO ranges will be handled by SIRC
> device.
> + //
> + Memory32Fixed(ReadWrite,0xFD000000,0x00AC0000) // 0xFD000000 -
> 0xFDABFFFF
> + // Skip 0xFDAC0000 - 0xFDACFFFF for GPIO_COMM3
> + Memory32Fixed(ReadWrite,0xFDAD0000,0x00010000) // 0xFDAD0000 -
> 0xFDADFFFF, only cover GPIO_COMM2 range
> + // Skip 0xFDAE0000 - 0xFDAFFFFF for GPIO_COMM0 and GPIO_COMM1
> + Memory32Fixed(ReadWrite,0xFDB00000,0x00500000) // 0xFDB00000 -
> 0xFDFFFFFF
> + Memory32Fixed(ReadWrite,0xFE000000,0x00010000) // 0xFE000000 -
> 0xFE00FFFF
> + Memory32Fixed(ReadWrite,0xFE011000,0x0000f000) // 0xFE011000 -
> 0xFE01FFFF
> + // Skip 0xFE020000 - 0xFE035FFF for Serial IO
> + Memory32Fixed(ReadWrite,0xFE036000,0x00006000) // 0xFE036000 -
> 0xFE03BFFF
> + // Skip 0xFE03C000 - 0xFE03CFFF for Thermal Device in ACPI mode
> + Memory32Fixed(ReadWrite,0xFE03D000,0x003C3000) // 0xFE03D000 -
> 0xFE3FFFFF
> + // Skip 0xFE400000 - 0xFE40FFFF for CIO2 in ACPI mode
> + Memory32Fixed(ReadWrite,0xFE410000,0x003F0000) // 0xFE410000 -
> 0xFE7FFFFF
> + })
> + Return(BUF0)
> + }
> + }
> + Device(IOTR) {
> + //
> + // This device claims IO range reserved for IO traps
> + // to prevent OS from reusing it for other purposes
> + //
> + Name(_HID,EISAID("PNP0C02"))
> + Name(_UID,"IoTraps")
> + Name(BUF0,ResourceTemplate(){
> + Io(Decode16,0x0,0x0,0x1,0xFF,TAG0)
> + Io(Decode16,0x0,0x0,0x1,0xFF,TAG1)
> + Io(Decode16,0x0,0x0,0x1,0xFF,TAG2)
> + Io(Decode16,0x0,0x0,0x1,0xFF,TAG3)
> + })
> + CreateWordField(BUF0,TAG0._MIN,AMI0)
> + CreateWordField(BUF0,TAG0._MAX,AMA0)
> + CreateWordField(BUF0,TAG1._MIN,AMI1)
> + CreateWordField(BUF0,TAG1._MAX,AMA1)
> + CreateWordField(BUF0,TAG2._MIN,AMI2)
> + CreateWordField(BUF0,TAG2._MAX,AMA2)
> + CreateWordField(BUF0,TAG3._MIN,AMI3)
> + CreateWordField(BUF0,TAG3._MAX,AMA3)
> + CreateByteField(BUF0,TAG0._LEN,LEN0)
> + CreateByteField(BUF0,TAG1._LEN,LEN1)
> + CreateByteField(BUF0,TAG2._LEN,LEN2)
> + CreateByteField(BUF0,TAG3._LEN,LEN3)
> + Method(_CRS) {
> + Store(ITA0,AMI0);Store(ITA0,AMA0)
> + Store(ITA1,AMI1);Store(ITA1,AMA1)
> + Store(ITA2,AMI2);Store(ITA2,AMA2)
> + Store(ITA3,AMI3);Store(ITA3,AMA3)
> + if(LNotEqual(ITS0,1)) { Store(0, LEN0) }
> + if(LNotEqual(ITS1,1)) { Store(0, LEN1) }
> + if(LNotEqual(ITS2,1)) { Store(0, LEN2) }
> + if(LNotEqual(ITS3,1)) { Store(0, LEN3) }
> + return (BUF0)
> + }
> + }
> +
> +
> + //
> + // LPC Bridge - Device 31, Function 0, this is only for PCH register Memory
> Region declare,
> + // it's better to be declared as early as possible since it's widely used in
> whole ACPI name space.
> + // Please add any code which needs to reference any register of it after
> this
> + //
> + Scope (\_SB.PC00.LPC0) {
> + Method(_DSM,4,serialized){if(PCIC(Arg0)) {
> return(PCID(Arg0,Arg1,Arg2,Arg3)) }; Return(Buffer() {0x00})}
> +
> + OperationRegion(LPC, PCI_Config, 0x00, 0x100)
> + Field(LPC, AnyAcc, NoLock, Preserve)
> + {
> + Offset(0x02),
> + CDID, 16,
> + Offset(0x08),
> + CRID, 8,
> + Offset(0x80),
> + IOD0, 8,
> + IOD1, 8,
> + Offset(0xA0),
> + , 9,
> + PRBL, 1,
> + Offset(0xAC),
> + , 8,
> + , 8,
> + XUSB, 1,
> + Offset(0xB8),
> + , 22,
> + GR0B, 2,
> + , 8,
> + Offset(0xBC),
> + , 2,
> + GR19, 2,
> + , 28,
> + Offset(0xDC),
> + , 2,
> + ESPI, 1,
> + }
> + }
> +
> + //
> + // PCH Power Management Controller
> + //
> + Scope(\_SB.PC00.PMC1) {
> + Method(_DSM,4,serialized){if(PCIC(Arg0)) {
> return(PCID(Arg0,Arg1,Arg2,Arg3)) }; Return(Buffer() {0x00})}
> +
> + OperationRegion(PMCB, PCI_Config, 0x00, 0x100)
> + Field(PMCB, AnyAcc, NoLock, Preserve) {
> + VDID, 32,
> + Offset(0x40),
> + , 8,
> + ACBA, 8,
> + Offset(0x48),
> + , 12,
> + PWBA, 20,
> + }
> + }
> +
> + //
> + // SMBus Controller - Device 31, Function 4
> + //
> + Device(SBUS) {
> + Name(_ADR,0x001F0004)
> + Method(_DSM,4,serialized){if(PCIC(Arg0)) {
> return(PCID(Arg0,Arg1,Arg2,Arg3)) }; Return(Buffer() {0x00})}
> + }
> +}
> +
> +Scope(\)
> +{
> + //
> + // PCR Register Access Methods
> + //
> + // PCR Dword Read
> + // arg0: PID
> + // arg1: Offset
> + //
> + Method (PCRR, 2, Serialized) {
> + Add (ShiftLeft (arg0, 16), arg1, Local0)
> + Add (SBRG, Local0, Local0)
> + OperationRegion (PCR0, SystemMemory, Local0, 0x4)
> + Field(PCR0,DWordAcc,Lock,Preserve) {
> + Offset(0x00),
> + DAT0, 32
> + } // End Field PCR0
> + Return (DAT0)
> + } // End Method PCRR
> +
> + //
> + // PCR Dword Write
> + // arg0: PID
> + // arg1: Offset
> + // arg2: write data
> + //
> + Method (PCRW, 3, Serialized) {
> + Add (ShiftLeft (arg0, 16), arg1, Local0)
> + Add (SBRG, Local0, Local0)
> + OperationRegion (PCR0, SystemMemory, Local0, 0x4)
> + Field(PCR0,DWordAcc,Lock,Preserve) {
> + Offset(0x00),
> + DAT0, 32
> + } // End Field PCR0
> + Store (arg2, DAT0)
> +
> + // read back for PCR back to back limitation
> + OperationRegion (PCR1, SystemMemory, ADD (SBRG, 0x00C73418), 0x4)
> + Field(PCR1,DWordAcc,Lock,Preserve) {
> + Offset(0x00),
> + DAT1, 32
> + } // End Field PCR1
> + } // End Method PCRW
> +
> + //
> + // PCR Dword Or
> + // arg0: PID
> + // arg1: Offset
> + // arg2: Or data
> + //
> + Method (PCRO, 3, Serialized) {
> + Store(PCRR(arg0,arg1),Local0) // Store PCR Read data in Local0
> + Store(Or(Local0,arg2),Local1) // Or data
> + PCRW(arg0,arg1,Local1) // Write data back
> + }
> +
> + //
> + // PCR Dword And
> + // arg0: PID
> + // arg1: Offset
> + // arg2: And data
> + //
> + Method (PCRA, 3, Serialized) {
> + Store(PCRR(arg0,arg1),Local0) // Store PCR Read data in Local0
> + Store(And(Local0,arg2),Local1) // And data
> + PCRW(arg0,arg1,Local1) // Write data back
> + }
> +
> + //
> + // PCR Dword AndThenOr
> + // arg0: PID
> + // arg1: Offset
> + // arg2: And data
> + // arg3: Or data
> + //
> + Method (PCAO, 4, Serialized) {
> + Store(PCRR(arg0,arg1),Local0) // Store PCR Read data in Local0
> + Store(Or(And(Local0,arg2),arg3),Local1) // AndThenOr
> + PCRW(arg0,arg1,Local1) // Write data back
> + }
> +
> + Name (PMBV, 0) // ACPI I/O base address value
> + Method (PMB1, 0) {
> + If (LEqual(PMBV, 0)) {
> + Store (ShiftLeft (\_SB.PC00.PMC1.ACBA, 8), PMBV)
> + }
> + Return (PMBV)
> + }
> +
> + Name (PWRV, 0) // PWRM base address value
> + Method (PWRM, 0) {
> + If (LEqual(PWRV, 0)) {
> + Store (ShiftLeft (\_SB.PC00.PMC1.PWBA, 12), PWRV)
> + }
> + Return (PWRV)
> + }
> +
> +
> + //
> + // Define PCH ACPIBASE I/O as an ACPI operating region. The base address
> + // can be found in Device 31, Function 2, Offset 40h.
> + //
> + OperationRegion(PMIO, SystemIo, PMB1, 0x80)
> + Field(PMIO, ByteAcc, NoLock, Preserve) {
> + , 8,
> + PBSS, 1, // Power Button Status
> + Offset(0x40), // General Purpose Event Control
> + , 17,
> + GPEC, 1 // Software GPE Control
> + }
> + OperationRegion(PMLP, SystemIo, Add(\PMB1,0x80), 0x20)
> + Field(PMLP, ByteAcc, NoLock, Preserve) {
> + Offset(0x10), // GPE0 Enable
> + , 8,
> + GE08, 1,
> + , 8,
> + GE17, 1,
> + , 17,
> + GE35, 1,
> + , 9,
> + GE45, 1,
> + , 2,
> + GE48, 1,
> + , 2,
> + GE51, 1,
> + , 76,
> + }
> + Field(PMLP, ByteAcc, NoLock, WriteAsZeros) {
> + Offset(0x00), // GPE0 Status
> + , 8,
> + GS08, 1,
> + , 8,
> + GS17, 1,
> + , 17,
> + GS35, 1,
> + , 9,
> + GS45, 1,
> + , 2,
> + GS48, 1,
> + , 2,
> + GS51, 1,
> + , 2,
> + GS54, 1,
> + GS55, 1,
> + , 42,
> + GS98, 1,
> + , 29,
> + }
> +
> +
> +
> + //
> + // PWRM register definitions
> + //
> + OperationRegion(PWMR, SystemMemory, \PWRM, 0x800)
> + Field(PWMR, AnyAcc, NoLock, Preserve) {
> + Offset(0x0E0),
> + , 16,
> + DWLE, 1, // Deep-Sx WLAN Phy Power Enable
> + HWLE, 1, // Host Wireless LAN Phy Power Enable
> + }
> +
> + //
> + //
> + OperationRegion(PMST, SystemMemory, PWRV, 0x80)
> + Field(PMST, DWordAcc, NoLock, Preserve) {
> + Offset(0x18), // Power Management Configuration Reg 1 (PM_CFG)
> + , 25, //
> + USBP, 1, // Allow USB2 PHY Core Power Gating
> (ALLOW_USB2_CORE_PG)
> + Offset(0x1C), // PCH Power Management Status (PCH_PM_STS)
> + , 24, //
> + PMFS, 1, // PMC Message Full Status (PMC_MSG_FULL_STS)
> + Offset(0x20), // Message to PMC (MTPMC)
> + MPMC, 32, // Message to PMC (MTPMC)
> + Offset(0x24), // PCH Power Management Status (PCH_PM_STS2)
> + , 20, //
> + UWAB, 1, // USB2 Workaround Available Bit
> + }
> +
> +} //end Scope(\)
> +
> +Scope (\_SB.PC00) {
> + Name(LTRN, 0)
> + Name(OBFN, 0)
> +
> + Name(LMSL, 0)
> + Name(LNSL, 0)
> +
> + //
> + // LAN Controller - Device 31, Function 6
> + //
> + Scope(\_SB.PC00.GBE1) {
> + Method(_DSM,4,serialized){if(PCIC(Arg0)) {
> return(PCID(Arg0,Arg1,Arg2,Arg3)) }; Return(Buffer() {0x00})}
> + OperationRegion(GLBA, PCI_Config, 0,0x100)
> + Field(GLBA,AnyAcc,NoLock,Preserve)
> + {
> + DVID, 16,
> + Offset(0xCC),
> + , 8,
> + PMEE, 1, // PME Enable
> + , 6,
> + PMES, 1, // PME Status
> + }
> +
> + Method(_PRW, 0) { Return(GPRW(0x0D, 4)) } // can wakeup from S4
> state
> +
> + Method(_DSW, 3)
> + {
> + Store(Arg0, PMEE)
> + }
> +
> + //
> + // GPE handler for GbE, this is part of _Lxx handler for bus 0 PME
> + //
> + Method(GPEH)
> + {
> + If(LEqual(DVID, 0xFFFF)) {
> + Return()
> + }
> + If(LAnd(PMEE, PMES)) {
> + Store(1, PMES) // clear PME Status
> + Notify(GBE1, 0x02)
> + }
> + }
> + } // end "GbE Controller"
> +
> +} //scope
> +
> +//
> +// xHCI Controller - Device 20, Function 0
> +//
> +Include("PchXhci.asl")
> +
> +// xDCI (OTG) Controller is not used in Server
> +// Comment out as ifdefs don't work at Trim stage of ASL preparation
> +
> +Scope(\_SB_.PC00) {
> + //
> + // High Definition Audio Controller - Device 31, Function 3
> + //
> + include("PchHda.asl")
> +
> + //
> + // PCIE Root Port #01
> + //
> + Scope(\_SB.PC00.RP01) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTR1, LTRN)
> + Store (PML1, LMSL)
> + Store (PNL1, LNSL)
> + Store (OBF1, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #01"
> +
> + //
> + // PCIE Root Port #02
> + //
> + Scope(\_SB.PC00.RP02) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTR2, LTRN)
> + Store (PML2, LMSL)
> + Store (PNL2, LNSL)
> + Store (OBF2, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #02"
> +
> + //
> + // PCIE Root Port #03
> + //
> + Scope(\_SB.PC00.RP03) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTR3, LTRN)
> + Store (PML3, LMSL)
> + Store (PNL3, LNSL)
> + Store (OBF3, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #03"
> +
> + //
> + // PCIE Root Port #04
> + //
> + Scope(\_SB.PC00.RP04) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTR4, LTRN)
> + Store (PML4, LMSL)
> + Store (PNL4, LNSL)
> + Store (OBF4, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #04"
> +
> + //
> + // PCIE Root Port #05
> + //
> + Scope(\_SB.PC00.RP05) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTR5, LTRN)
> + Store (PML5, LMSL)
> + Store (PNL5, LNSL)
> + Store (OBF5, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #05"
> +
> + //
> + // PCIE Root Port #06
> + //
> + Scope(\_SB.PC00.RP06) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTR6, LTRN)
> + Store (PML6, LMSL)
> + Store (PNL6, LNSL)
> + Store (OBF6, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #06"
> +
> + //
> + // PCIE Root Port #07
> + //
> + Scope(\_SB.PC00.RP07) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTR7, LTRN)
> + Store (PML7, LMSL)
> + Store (PNL7, LNSL)
> + Store (OBF7, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #07"
> +
> + //
> + // PCIE Root Port #08
> + //
> + Scope(\_SB.PC00.RP08) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTR8, LTRN)
> + Store (PML8, LMSL)
> + Store (PNL8, LNSL)
> + Store (OBF8, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #08"
> +
> + //
> + // PCIE Root Port #09
> + //
> + Scope(\_SB.PC00.RP09) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTR9, LTRN)
> + Store (PML9, LMSL)
> + Store (PNL9, LNSL)
> + Store (OBF9, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #09"
> +
> + //
> + // PCIE Root Port #10
> + //
> + Scope(\_SB.PC00.RP10) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTRA, LTRN)
> + Store (PMLA, LMSL)
> + Store (PNLA, LNSL)
> + Store (OBFA, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #10"
> +
> + //
> + // PCIE Root Port #11
> + //
> + Scope(\_SB.PC00.RP11) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTRB, LTRN)
> + Store (PMLB, LMSL)
> + Store (PNLB, LNSL)
> + Store (OBFB, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #11"
> +
> + //
> + // PCIE Root Port #12
> + //
> + Scope(\_SB.PC00.RP12) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTRC, LTRN)
> + Store (PMLC, LMSL)
> + Store (PNLC, LNSL)
> + Store (OBFC, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #12"
> +
> + //
> + // PCIE Root Port #13
> + //
> + Scope(\_SB.PC00.RP13) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTRD, LTRN)
> + Store (PMLD, LMSL)
> + Store (PNLD, LNSL)
> + Store (OBFD, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #13"
> +
> + //
> + // PCIE Root Port #14
> + //
> + Scope(\_SB.PC00.RP14) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTRE, LTRN)
> + Store (PMLE, LMSL)
> + Store (PNLE, LNSL)
> + Store (OBFE, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #14"
> +
> + //
> + // PCIE Root Port #15
> + //
> + Scope(\_SB.PC00.RP15) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTRF, LTRN)
> + Store (PMLF, LMSL)
> + Store (PNLF, LNSL)
> + Store (OBFF, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #15"
> +
> + //
> + // PCIE Root Port #16
> + //
> + Scope(\_SB.PC00.RP16) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTRG, LTRN)
> + Store (PMLG, LMSL)
> + Store (PNLG, LNSL)
> + Store (OBFG, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #16"
> +
> + //
> + // PCIE Root Port #17
> + //
> + Scope(\_SB.PC00.RP17) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTRH, LTRN)
> + Store (PMLH, LMSL)
> + Store (PNLH, LNSL)
> + Store (OBFH, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #17"
> +
> + //
> + // PCIE Root Port #18
> + //
> + Scope(\_SB.PC00.RP18) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTRI, LTRN)
> + Store (PMLI, LMSL)
> + Store (PNLI, LNSL)
> + Store (OBFI, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #18"
> +
> + //
> + // PCIE Root Port #19
> + //
> + Scope(\_SB.PC00.RP19) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTRJ, LTRN)
> + Store (PMLJ, LMSL)
> + Store (PNLJ, LNSL)
> + Store (OBFJ, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #19"
> +
> + //
> + // PCIE Root Port #20
> + //
> + Scope(\_SB.PC00.RP20) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTRK, LTRN)
> + Store (PMLK, LMSL)
> + Store (PNLK, LNSL)
> + Store (OBFK, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #20"
> +
> + //
> + // Serial ATA Host Controller - Device 31, Function 2
> + //
> +External(\_SB.PC00.SAT0.SDSM, MethodObj)
> +
> +Scope (\_SB.PC00.SAT1) {
> + Include ("PchSata.asl")
> + Device(PRT6)
> + {
> + Name(_ADR,0x0006FFFF) // Port 6
> + }
> + Device(PRT7)
> + {
> + Name(_ADR,0x0007FFFF) // Port 7
> + }
> +}
> +Scope (\_SB.PC00.SAT2) {
> + Include ("PchSata.asl")
> +}
> + //Server does not support CIO Camera I/O
> +
> + //
> + // Thermal Device
> + //
> + Scope(\_SB.PC00.TERM) {
> + Name (_HID, "INT3536")
> + Name (_UID, 1)
> + Name (RBUF, ResourceTemplate () {
> + Memory32Fixed (ReadWrite, 0xFE03C000, 0x00001000, BAR0)
> + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , IRQ) { 18 }
> + })
> +
> + CreateDWordField(RBUF,IRQ._INT,IRQN)
> + Method (_CRS, 0x0, NotSerialized) {
> + Store(TIRQ, IRQN)
> +
> + Return (RBUF)
> + }
> +
> + Method (_STA, 0x0, NotSerialized)
> + {
> + If(LEqual(TAEN, 0)) { Return(0x0) } // device not enabled in ACPI mode
> + If(LEqual(TIRQ, 0)) { Return(0x0) } // IRQ number not updated
> + Return(0xF)
> + }
> + }
> +}
> +
> +// Comment out as ifdefs don't work at Trim stage of ASL preparation
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch
> Hda.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch
> Hda.asl
> new file mode 100644
> index 0000000000..ab5b5c42dd
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch
> Hda.asl
> @@ -0,0 +1,307 @@
> +/** @file
> +
> + @copyright
> + Copyright 1999 - 2020 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +//
> +// Bit Difinitions
> +//
> +#ifndef BIT0
> +#define BIT0 0x0001
> +#define BIT1 0x0002
> +#define BIT2 0x0004
> +#define BIT3 0x0008
> +#define BIT4 0x0010
> +#define BIT5 0x0020
> +#define BIT6 0x0040
> +#define BIT7 0x0080
> +#define BIT8 0x0100
> +#define BIT9 0x0200
> +#endif //BIT0
> +
> +//
> +// High Definition Audio Controller - Device 31, Function 3
> +//
> +Scope(\_SB.PC00.CAVS) {
> +
> +#ifndef BIT0
> +#define BIT0 0x00000001
> +#endif
> +#ifndef BIT1
> +#define BIT1 0x00000002
> +#endif
> +#ifndef BIT2
> +#define BIT2 0x00000004
> +#endif
> +#ifndef BIT3
> +#define BIT3 0x00000008
> +#endif
> +#ifndef BIT4
> +#define BIT4 0x00000010
> +#endif
> +#ifndef BIT5
> +#define BIT5 0x00000020
> +#endif
> +#ifndef BIT6
> +#define BIT6 0x00000040
> +#endif
> +#ifndef BIT7
> +#define BIT7 0x00000080
> +#endif
> +#ifndef BIT8
> +#define BIT8 0x00000100
> +#endif
> +#ifndef BIT9
> +#define BIT9 0x00000200
> +#endif
> +#ifndef BIT10
> +#define BIT10 0x00000400
> +#endif
> +#ifndef BIT11
> +#define BIT11 0x00000800
> +#endif
> +#ifndef BIT12
> +#define BIT12 0x00001000
> +#endif
> +#ifndef BIT13
> +#define BIT13 0x00002000
> +#endif
> +#ifndef BIT14
> +#define BIT14 0x00004000
> +#endif
> +#ifndef BIT15
> +#define BIT15 0x00008000
> +#endif
> +#ifndef BIT16
> +#define BIT16 0x00010000
> +#endif
> +#ifndef BIT17
> +#define BIT17 0x00020000
> +#endif
> +#ifndef BIT18
> +#define BIT18 0x00040000
> +#endif
> +#ifndef BIT19
> +#define BIT19 0x00080000
> +#endif
> +#ifndef BIT20
> +#define BIT20 0x00100000
> +#endif
> +#ifndef BIT21
> +#define BIT21 0x00200000
> +#endif
> +#ifndef BIT22
> +#define BIT22 0x00400000
> +#endif
> +#ifndef BIT23
> +#define BIT23 0x00800000
> +#endif
> +#ifndef BIT24
> +#define BIT24 0x01000000
> +#endif
> +#ifndef BIT25
> +#define BIT25 0x02000000
> +#endif
> +#ifndef BIT26
> +#define BIT26 0x04000000
> +#endif
> +#ifndef BIT27
> +#define BIT27 0x08000000
> +#endif
> +#ifndef BIT28
> +#define BIT28 0x10000000
> +#endif
> +#ifndef BIT29
> +#define BIT29 0x20000000
> +#endif
> +#ifndef BIT30
> +#define BIT30 0x40000000
> +#endif
> +#ifndef BIT31
> +#define BIT31 0x80000000
> +#endif
> +
> + //
> + // Define a Memory Region that will allow access to the HDA PCI
> Configuration Space
> + //
> + OperationRegion(HDAR, PCI_Config, 0x00, 0x100)
> + Field(HDAR,WordAcc,NoLock,Preserve) {
> + VDID,32, // 0x00, VID DID
> + Offset(0x48), // 0x48, CGCTL - Clock Gating Control
> + ,6,
> + MBCG,1, // MISCBDCGE [BIT6]
> + Offset(0x54), // 0x54, Power Management Control and Status Register
> + ,8,
> + PMEE,1,
> + ,6,
> + PMES,1 // PME Status
> + }
> +
> + Name(_S0W, 3) // Device can wake itself from D3 in S0
> +
> + Method(_DSW, 3) { Store(Arg0, PMEE) } // Device wake enable
> +
> +
> + Method(_PRW, 0) { Return(GPRW(0x0D, 4)) } // Can wakeup from S4 state
> +
> + // GPE handler for HDA, this is part of _Lxx handler for bus 0 PME
> + Method(GPEH) {
> + If(LEqual(VDID, 0xFFFFFFFF)) {
> + Return()
> + }
> +
> + If(LAnd(PMEE, PMES)) {
> + ADBG("HDAS GPEH")
> + Store(1, PMES) // clear PME Status
> + Notify(CAVS, 0x02)
> + }
> + }
> +
> + // NHLT Table memory descriptor, returned from _DSM
> + Name(NBUF, ResourceTemplate () {
> + // NHLT table address (_MIN = NHLT 64bit pointer, _MAX = _MIN + _LEN -
> 1) and length (_LEN)
> + QWordMemory (ResourceConsumer, , MinNotFixed, MaxNotFixed,
> NonCacheable, ReadOnly,
> + 0x1, // AddressGranularity
> + 0x0000000000000000, // AddressMinimum _MIN
> + 0x0000000000000000, // AddressMaximum _MAX
> + 0x0,
> + 0x0, // RangeLength _LEN
> + , , NHLT, AddressRangeACPI,)
> + })
> +
> + Method(AUWA,0,Serialized)
> + {
> + If(LEqual(PCHS, 1)) {
> + If(LEqual(\_SB.PC00.LPC0.CRID, 0x0)) { Return (1) } // Apply to SPT-H A0
> stepping (RevID = 0x0)
> + } else {
> + If(LEqual(\_SB.PC00.LPC0.CRID, 0x0)) { Return (1) } // Apply to SPT-LP A0
> stepping (RevID = 0x0)
> + If(LEqual(\_SB.PC00.LPC0.CRID, 0x1)) { Return (1) } // Apply to SPT-LP A1
> stepping (RevID = 0x1)
> + If(LEqual(\_SB.PC00.LPC0.CRID, 0x9)) { Return (1) } // Apply to SPT-LP A2
> stepping (RevID = 0x9)
> + }
> + Return (0)
> + }
> +
> + Method(_INI) {
> + // Update resource according to NVS
> + ADBG("HDAS _INI")
> +
> + // Set NHLT base address and length
> + CreateQWordField(NBUF, ^NHLT._MIN, NBAS)
> + CreateQWordField(NBUF, ^NHLT._MAX, NMAS)
> + CreateQWordField(NBUF, ^NHLT._LEN, NLEN)
> + Store(NHLA, NBAS)
> + Add(NHLA, Subtract(NHLL, 1), NMAS)
> + Store(NHLL, NLEN)
> +
> + If(LEqual(AUWA(), 1)) {
> + Store(0, \_SB.PC00.CAVS.MBCG)
> + }
> + }
> +
> + Method(_DSM, 0x4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj,
> PkgObj}) {
> + // Arg0 - UUID: A69F886E-6CEB-4594-A41F-7B5DCE24C553 (Buffer)
> + // Arg1 - Revision ID: 0x01 (Integer)
> + // Arg2 - Function Index: 0x0 - 0x3 (Integer) - See below for details.
> + // Arg3 - Depends on Function Index - See below for details.
> + // Return - Depends on Function Index - See below for details.
> +
> + ADBG("HDAS _DSM")
> +
> + if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }
> +
> + // Verify UUID
> + If (LEqual(Arg0, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553"))) {
> +
> + Switch(ToInteger(Arg2)) {
> +
> + // Function 0: Function Support Query
> + // Arg2 - Function Index: 0x00 (Integer)
> + // Arg3: Unused
> + // Return: Bitmask of functions supported. (Buffer)
> + Case(0) {
> + // Supports function 0 - 3
> + Return(Buffer(One) { 0x0F })
> + }
> +
> + // Function 1: Query Non HD Audio Descriptor Table
> + // Used by the Intel Offload Engine Driver to discover the
> + // non HD Audio devices supported by the Audio DSP.
> + // Arg2 - Function Index: 0x01 (Integer)
> + // Arg3 - Unused
> + // Return - ACPI Table describing the non HD Audio links and devices
> supported by the ADSP (ResourceBuffer)
> + Case(1) {
> + ADBG("_DSM Fun 1 NHLT")
> + // NBUF - Memory Resource Descriptor buffer with address and
> length of NHLT
> + Return(NBUF)
> + }
> +
> + // Function 2: Query Feature Mask
> + // Used by the Intel Offload Engine Driver to retrieve a
> bitmask
> + // of features allowable on this platform.
> + // Arg2 - Function Index: 0x02 (Integer)
> + // Arg3: Unused
> + // Return: Bitmask of supported features.
> + Case (2) {
> + ADBG("_DSM Fun 2 FMSK")
> + // Bit 0 == '1', WoV is supported, Bit 0 == '0', WoV not supported
> + // Bit 1 == '1', BT Sideband is supported, Bit 1 == '0', BT not supported
> + // Bit 2 == '1', codec based VAD support allowable
> + // Bit 3 - 4 Reserved
> + // Bit 5 == '1', BT Intel HFP SCO is supported
> + // Bit 6 == '1', BT Intel A2DP is supported
> + // Bit 7 == '1', DSP based speech pre-processing disabled
> + // Bit 8 == '1', Windows Voice Activation, Bit 8 == '0', Intel Wake on
> Voice
> + // Bit 9 - 31 Reserved, shall be set to '0'
> + // ADFM - NVS AudioDSP Feature Bit Mask updated from PchPolicy
> + Return(ADFM)
> + }
> +
> + // Function 3: Query Pre/Post Processing Module Support
> + // Used by the Intel Offload Engine Driver to determine if a
> + // specified PP Module is allowed to be supported on this
> platform
> + // Arg2 - Function Index: 0x03 (Integer)
> + // Arg3 - UUID: Specifies the UUID of the PP module to check (Buffer)
> + // Return - TRUE if PP Module supported, else FALSE.
> + Case (3) {
> + ADBG("_DSM Fun 3 PPMS")
> + // ADPM - NVS AudioDSP Post-Processing Module Bit Mask updated
> from PchPolicy: HdaConfig->DspPpModuleMask
> +
> + //
> + // Example (to be updated with real GUIDs of supported 3rd party
> IP):
> + //
> + // 3rd Party DSP Processing Module 1 placeholder (enabled by policy
> HdaConfig->DspPpModuleMask |= BIT0)
> + // Check PP module with GUID AABBCCDD-EEFF-1122-3344-
> 556677889900
> + // If (LEqual(Arg3, ToUUID ("AABBCCDD-EEFF-1122-3344-
> 556677889900"))){
> + // Return(And(ADPM, 0x1)) // DspPpModuleMask[BIT0] /
> ADPM[BIT0] set - supported 3rd Party Processing Module 1(return true)
> + // }
> + //
> + // 3rd Party DSP Processing Module 5 placeholder (enabled by policy
> HdaConfig->DspPpModuleMask |= BIT5)
> + // Check PP module with GUID 11111111-2222-3333-4444-
> AABBCCDDEEFF
> + // If (LEqual(Arg3, ToUUID ("11111111-2222-3333-4444-
> AABBCCDDEEFF"))){
> + // Return(And(ADPM, 0x20)) // DspPpModuleMask[BIT5] /
> ADPM[BIT5] set - supported 3rd Party Processing Module 5(return true)
> + // }
> + //
> + // Implement for all supported PP modules
> + //
> + Return(Buffer() {0x00}) // Is not supported
> + }
> +
> + Default {
> + // Function not supported (Arg2)
> + ADBG("_DSM Fun NOK")
> + Return(Buffer(One) { 0x00 })
> + }
> + } // Switch(Arg2) End
> + } // If(Arg0, UUID) End
> +
> +
> + // UUID not supported (Arg0)
> + ADBG("_DSM UUID NOK")
> + //Fix warning: not all control paths return a value
> + Return(Buffer() {0x00})
> + } // _DSM End
> +
> +} // end "High Definition Audio Controller"
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch
> Nvs.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch
> Nvs.asl
> new file mode 100644
> index 0000000000..bd27ca7342
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch
> Nvs.asl
> @@ -0,0 +1,271 @@
> +/** @file
> +
> + @copyright
> + Copyright 2013 - 2016 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> + //
> + // Define PCH NVS Area operatino region.
> + //
> +
> +
> +
> + OperationRegion(PNVA,SystemMemory,PNVB,PNVL)
> + Field(PNVA,AnyAcc,Lock,Preserve)
> + {
> + Offset(0), RCRV, 32, // Offset(0), RC Revision
> + Offset(4), PCHS, 16, // Offset(4), PCH Series
> + Offset(6), PCHG, 16, // Offset(6), PCH Generation
> + Offset(8), RPA1, 32, // Offset(8), Root Port address 1
> + Offset(12), RPA2, 32, // Offset(12), Root Port address 2
> + Offset(16), RPA3, 32, // Offset(16), Root Port address 3
> + Offset(20), RPA4, 32, // Offset(20), Root Port address 4
> + Offset(24), RPA5, 32, // Offset(24), Root Port address 5
> + Offset(28), RPA6, 32, // Offset(28), Root Port address 6
> + Offset(32), RPA7, 32, // Offset(32), Root Port address 7
> + Offset(36), RPA8, 32, // Offset(36), Root Port address 8
> + Offset(40), RPA9, 32, // Offset(40), Root Port address 9
> + Offset(44), RPAA, 32, // Offset(44), Root Port address 10
> + Offset(48), RPAB, 32, // Offset(48), Root Port address 11
> + Offset(52), RPAC, 32, // Offset(52), Root Port address 12
> + Offset(56), RPAD, 32, // Offset(56), Root Port address 13
> + Offset(60), RPAE, 32, // Offset(60), Root Port address 14
> + Offset(64), RPAF, 32, // Offset(64), Root Port address 15
> + Offset(68), RPAG, 32, // Offset(68), Root Port address 16
> + Offset(72), RPAH, 32, // Offset(72), Root Port address 17
> + Offset(76), RPAI, 32, // Offset(76), Root Port address 18
> + Offset(80), RPAJ, 32, // Offset(80), Root Port address 19
> + Offset(84), RPAK, 32, // Offset(84), Root Port address 20
> + Offset(88), NHLA, 64, // Offset(88), HD-Audio NHLT ACPI address
> + Offset(96), NHLL, 32, // Offset(96), HD-Audio NHLT ACPI length
> + Offset(100), ADFM, 32, // Offset(100), HD-Audio DSP Feature Mask
> + Offset(104), SBRG, 32, // Offset(104), SBREG_BAR
> + Offset(108), GPEM, 32, // Offset(108), GPP_X to GPE_DWX mapping
> + Offset(112), G2L0, 32, // Offset(112), GPE 2-tier level edged enabled
> Gpio pads (Group Index 0)
> + Offset(116), G2L1, 32, // Offset(116), GPE 2-tier level edged enabled
> Gpio pads (Group Index 1)
> + Offset(120), G2L2, 32, // Offset(120), GPE 2-tier level edged enabled
> Gpio pads (Group Index 2)
> + Offset(124), G2L3, 32, // Offset(124), GPE 2-tier level edged enabled
> Gpio pads (Group Index 3)
> + Offset(128), G2L4, 32, // Offset(128), GPE 2-tier level edged enabled
> Gpio pads (Group Index 4)
> + Offset(132), G2L5, 32, // Offset(132), GPE 2-tier level edged enabled
> Gpio pads (Group Index 5)
> + Offset(136), G2L6, 32, // Offset(136), GPE 2-tier level edged enabled
> Gpio pads (Group Index 6)
> + Offset(140), G2L7, 32, // Offset(140), GPE 2-tier level edged enabled
> Gpio pads (Group Index 7)
> + Offset(144), G2L8, 32, // Offset(144), GPE 2-tier level edged enabled
> Gpio pads (Group Index 8)
> + Offset(148), G2L9, 32, // Offset(148), GPE 2-tier level edged enabled
> Gpio pads (Group Index 9)
> + Offset(152), G2LA, 32, // Offset(152), GPE 2-tier level edged enabled
> Gpio pads (Group Index 10)
> + Offset(156), G2LB, 32, // Offset(156), GPE 2-tier level edged enabled
> Gpio pads (Group Index 11)
> + Offset(160), G2LC, 32, // Offset(160), GPE 2-tier level edged enabled
> Gpio pads (Groip Index 12)
> +
> + Offset(164), PML1, 16, // Offset(164), PCIE LTR max snoop Latency 1
> + Offset(166), PML2, 16, // Offset(166), PCIE LTR max snoop Latency 2
> + Offset(168), PML3, 16, // Offset(168), PCIE LTR max snoop Latency 3
> + Offset(170), PML4, 16, // Offset(170), PCIE LTR max snoop Latency 4
> + Offset(172), PML5, 16, // Offset(172), PCIE LTR max snoop Latency 5
> + Offset(174), PML6, 16, // Offset(174), PCIE LTR max snoop Latency 6
> + Offset(176), PML7, 16, // Offset(176), PCIE LTR max snoop Latency 7
> + Offset(178), PML8, 16, // Offset(178), PCIE LTR max snoop Latency 8
> + Offset(180), PML9, 16, // Offset(180), PCIE LTR max snoop Latency 9
> + Offset(182), PMLA, 16, // Offset(182), PCIE LTR max snoop Latency 10
> + Offset(184), PMLB, 16, // Offset(184), PCIE LTR max snoop Latency 11
> + Offset(186), PMLC, 16, // Offset(186), PCIE LTR max snoop Latency 12
> + Offset(188), PMLD, 16, // Offset(188), PCIE LTR max snoop Latency 13
> + Offset(190), PMLE, 16, // Offset(190), PCIE LTR max snoop Latency 14
> + Offset(192), PMLF, 16, // Offset(192), PCIE LTR max snoop Latency 15
> + Offset(194), PMLG, 16, // Offset(194), PCIE LTR max snoop Latency 16
> + Offset(196), PMLH, 16, // Offset(196), PCIE LTR max snoop Latency 17
> + Offset(198), PMLI, 16, // Offset(198), PCIE LTR max snoop Latency 18
> + Offset(200), PMLJ, 16, // Offset(200), PCIE LTR max snoop Latency 19
> + Offset(202), PMLK, 16, // Offset(202), PCIE LTR max snoop Latency 20
> + Offset(204), PNL1, 16, // Offset(204), PCIE LTR max no snoop Latency 1
> + Offset(206), PNL2, 16, // Offset(206), PCIE LTR max no snoop Latency 2
> + Offset(208), PNL3, 16, // Offset(208), PCIE LTR max no snoop Latency 3
> + Offset(210), PNL4, 16, // Offset(210), PCIE LTR max no snoop Latency 4
> + Offset(212), PNL5, 16, // Offset(212), PCIE LTR max no snoop Latency 5
> + Offset(214), PNL6, 16, // Offset(214), PCIE LTR max no snoop Latency 6
> + Offset(216), PNL7, 16, // Offset(216), PCIE LTR max no snoop Latency 7
> + Offset(218), PNL8, 16, // Offset(218), PCIE LTR max no snoop Latency 8
> + Offset(220), PNL9, 16, // Offset(220), PCIE LTR max no snoop Latency 9
> + Offset(222), PNLA, 16, // Offset(222), PCIE LTR max no snoop Latency 10
> + Offset(224), PNLB, 16, // Offset(224), PCIE LTR max no snoop Latency 11
> + Offset(226), PNLC, 16, // Offset(226), PCIE LTR max no snoop Latency 12
> + Offset(228), PNLD, 16, // Offset(228), PCIE LTR max no snoop Latency 13
> + Offset(230), PNLE, 16, // Offset(230), PCIE LTR max no snoop Latency 14
> + Offset(232), PNLF, 16, // Offset(232), PCIE LTR max no snoop Latency 15
> + Offset(234), PNLG, 16, // Offset(234), PCIE LTR max no snoop Latency 16
> + Offset(236), PNLH, 16, // Offset(236), PCIE LTR max no snoop Latency 17
> + Offset(238), PNLI, 16, // Offset(238), PCIE LTR max no snoop Latency 18
> + Offset(240), PNLJ, 16, // Offset(240), PCIE LTR max no snoop Latency 19
> + Offset(242), PNLK, 16, // Offset(242), PCIE LTR max no snoop Latency 20
> + Offset(244), U0C0, 32, // Offset(244), SerialIo Hidden UART0 BAR 0
> + Offset(248), U1C0, 32, // Offset(248), SerialIo Hidden UART1 BAR 0
> + Offset(252), ADPM, 32, // Offset(252), HD-Audio DSP Post-Processing
> Module Mask
> + Offset(256), XHPC, 8, // Offset(256), Number of HighSpeed ports
> implemented in XHCI controller
> + Offset(257), XRPC, 8, // Offset(257), Number of USBR ports
> implemented in XHCI controller
> + Offset(258), XSPC, 8, // Offset(258), Number of SuperSpeed ports
> implemented in XHCI controller
> + Offset(259), XSPA, 8, // Offset(259), Address of 1st SuperSpeed port
> + Offset(260), HPTB, 32, // Offset(260), HPET base address
> + Offset(264), HPTE, 8, // Offset(264), HPET enable
> + //110-bytes large SerialIo block
> + Offset(265), SMD0, 8, // Offset(265), SerialIo controller 0 (sdma) mode
> (0: disabled, 1: pci, 2: acpi, 3: debug port)
> + Offset(266), SMD1, 8, // Offset(266), SerialIo controller 1 (i2c0) mode (0:
> disabled, 1: pci, 2: acpi, 3: debug port)
> + Offset(267), SMD2, 8, // Offset(267), SerialIo controller 2 (i2c1) mode (0:
> disabled, 1: pci, 2: acpi, 3: debug port)
> + Offset(268), SMD3, 8, // Offset(268), SerialIo controller 3 (spi0) mode (0:
> disabled, 1: pci, 2: acpi, 3: debug port)
> + Offset(269), SMD4, 8, // Offset(269), SerialIo controller 4 (spi1) mode (0:
> disabled, 1: pci, 2: acpi, 3: debug port)
> + Offset(270), SMD5, 8, // Offset(270), SerialIo controller 5 (ua00) mode
> (0: disabled, 1: pci, 2: acpi, 3: debug port)
> + Offset(271), SMD6, 8, // Offset(271), SerialIo controller 6 (ua01) mode
> (0: disabled, 1: pci, 2: acpi, 3: debug port)
> + Offset(272), SMD7, 8, // Offset(272), SerialIo controller 7 (shdc) mode
> (0: disabled, 1: pci, 2: acpi, 3: debug port)
> + Offset(273), SMD8, 8, // Offset(273), SerialIo controller 8 (shdc) mode
> (0: disabled, 1: pci, 2: acpi, 3: debug port)
> + Offset(274), SMD9, 8, // Offset(274), SerialIo controller 9 (shdc) mode
> (0: disabled, 1: pci, 2: acpi, 3: debug port)
> + Offset(275), SMDA, 8, // Offset(275), SerialIo controller A (shdc) mode
> (0: disabled, 1: pci, 2: acpi, 3: debug port)
> + Offset(276), SIR0, 8, // Offset(276), SerialIo controller 0 (sdma) irq
> number
> + Offset(277), SIR1, 8, // Offset(277), SerialIo controller 1 (i2c0) irq
> number
> + Offset(278), SIR2, 8, // Offset(278), SerialIo controller 2 (i2c1) irq
> number
> + Offset(279), SIR3, 8, // Offset(279), SerialIo controller 3 (spi0) irq
> number
> + Offset(280), SIR4, 8, // Offset(280), SerialIo controller 4 (spi1) irq
> number
> + Offset(281), SIR5, 8, // Offset(281), SerialIo controller 5 (ua00) irq
> number
> + Offset(282), SIR6, 8, // Offset(282), SerialIo controller 6 (ua01) irq
> number
> + Offset(283), SIR7, 8, // Offset(283), SerialIo controller 7 (shdc) irq
> number
> + Offset(284), SIR8, 8, // Offset(284), SerialIo controller 8 (shdc) irq
> number
> + Offset(285), SIR9, 8, // Offset(285), SerialIo controller 9 (shdc) irq
> number
> + Offset(286), SIRA, 8, // Offset(286), SerialIo controller A (shdc) irq
> number
> + Offset(287), SB00, 32, // Offset(287), SerialIo controller 0 (sdma) BAR0
> + Offset(291), SB01, 32, // Offset(291), SerialIo controller 1 (i2c0) BAR0
> + Offset(295), SB02, 32, // Offset(295), SerialIo controller 2 (i2c1) BAR0
> + Offset(299), SB03, 32, // Offset(299), SerialIo controller 3 (spi0) BAR0
> + Offset(303), SB04, 32, // Offset(303), SerialIo controller 4 (spi1) BAR0
> + Offset(307), SB05, 32, // Offset(307), SerialIo controller 5 (ua00) BAR0
> + Offset(311), SB06, 32, // Offset(311), SerialIo controller 6 (ua01) BAR0
> + Offset(315), SB07, 32, // Offset(315), SerialIo controller 7 (shdc) BAR0
> + Offset(319), SB08, 32, // Offset(319), SerialIo controller 8 (shdc) BAR0
> + Offset(323), SB09, 32, // Offset(323), SerialIo controller 9 (shdc) BAR0
> + Offset(327), SB0A, 32, // Offset(327), SerialIo controller A (shdc) BAR0
> + Offset(331), SB10, 32, // Offset(331), SerialIo controller 0 (sdma) BAR1
> + Offset(335), SB11, 32, // Offset(335), SerialIo controller 1 (i2c0) BAR1
> + Offset(339), SB12, 32, // Offset(339), SerialIo controller 2 (i2c1) BAR1
> + Offset(343), SB13, 32, // Offset(343), SerialIo controller 3 (spi0) BAR1
> + Offset(347), SB14, 32, // Offset(347), SerialIo controller 4 (spi1) BAR1
> + Offset(351), SB15, 32, // Offset(351), SerialIo controller 5 (ua00) BAR1
> + Offset(355), SB16, 32, // Offset(355), SerialIo controller 6 (ua01) BAR1
> + Offset(359), SB17, 32, // Offset(359), SerialIo controller 7 (shdc) BAR1
> + Offset(363), SB18, 32, // Offset(363), SerialIo controller 8 (shdc) BAR1
> + Offset(367), SB19, 32, // Offset(367), SerialIo controller 9 (shdc) BAR1
> + Offset(371), SB1A, 32, // Offset(371), SerialIo controller A (shdc) BAR1
> + //end of SerialIo block
> + Offset(375), GPEN, 8, // Offset(375), GPIO enabled
> + Offset(376), SGIR, 8, // Offset(376), GPIO IRQ
> + Offset(377), NIT1, 8, // Offset(377), RST PCIe Storage Cycle Router#1
> Interface Type
> + Offset(378), NIT2, 8, // Offset(378), RST PCIe Storage Cycle Router#2
> Interface Type
> + Offset(379), NIT3, 8, // Offset(379), RST PCIe Storage Cycle Router#3
> Interface Type
> + Offset(380), NPM1, 8, // Offset(380), RST PCIe Storage Cycle Router#1
> Power Management Capability Pointer
> + Offset(381), NPM2, 8, // Offset(381), RST PCIe Storage Cycle Router#2
> Power Management Capability Pointer
> + Offset(382), NPM3, 8, // Offset(382), RST PCIe Storage Cycle Router#3
> Power Management Capability Pointer
> + Offset(383), NPC1, 8, // Offset(383), RST PCIe Storage Cycle Router#1
> PCIe Capabilities Pointer
> + Offset(384), NPC2, 8, // Offset(384), RST PCIe Storage Cycle Router#2
> PCIe Capabilities Pointer
> + Offset(385), NPC3, 8, // Offset(385), RST PCIe Storage Cycle Router#3
> PCIe Capabilities Pointer
> + Offset(386), NL11, 16, // Offset(386), RST PCIe Storage Cycle Router#1
> L1SS Capability Pointer
> + Offset(388), NL12, 16, // Offset(388), RST PCIe Storage Cycle Router#2
> L1SS Capability Pointer
> + Offset(390), NL13, 16, // Offset(390), RST PCIe Storage Cycle Router#3
> L1SS Capability Pointer
> + Offset(392), ND21, 8, // Offset(392), RST PCIe Storage Cycle Router#1
> Endpoint L1SS Control Data2
> + Offset(393), ND22, 8, // Offset(393), RST PCIe Storage Cycle Router#2
> Endpoint L1SS Control Data2
> + Offset(394), ND23, 8, // Offset(394), RST PCIe Storage Cycle Router#3
> Endpoint L1SS Control Data2
> + Offset(395), ND11, 32, // Offset(395), RST PCIe Storage Cycle Router#1
> Endpoint L1SS Control Data1
> + Offset(399), ND12, 32, // Offset(399), RST PCIe Storage Cycle Router#2
> Endpoint L1SS Control Data1
> + Offset(403), ND13, 32, // Offset(403), RST PCIe Storage Cycle Router#3
> Endpoint L1SS Control Data1
> + Offset(407), NLR1, 16, // Offset(407), RST PCIe Storage Cycle Router#1
> LTR Capability Pointer
> + Offset(409), NLR2, 16, // Offset(409), RST PCIe Storage Cycle Router#2
> LTR Capability Pointer
> + Offset(411), NLR3, 16, // Offset(411), RST PCIe Storage Cycle Router#3
> LTR Capability Pointer
> + Offset(413), NLD1, 32, // Offset(413), RST PCIe Storage Cycle Router#1
> Endpoint LTR Data
> + Offset(417), NLD2, 32, // Offset(417), RST PCIe Storage Cycle Router#2
> Endpoint LTR Data
> + Offset(421), NLD3, 32, // Offset(421), RST PCIe Storage Cycle Router#3
> Endpoint LTR Data
> + Offset(425), NEA1, 16, // Offset(425), RST PCIe Storage Cycle Router#1
> Endpoint LCTL Data
> + Offset(427), NEA2, 16, // Offset(427), RST PCIe Storage Cycle Router#2
> Endpoint LCTL Data
> + Offset(429), NEA3, 16, // Offset(429), RST PCIe Storage Cycle Router#3
> Endpoint LCTL Data
> + Offset(431), NEB1, 16, // Offset(431), RST PCIe Storage Cycle Router#1
> Endpoint DCTL Data
> + Offset(433), NEB2, 16, // Offset(433), RST PCIe Storage Cycle Router#2
> Endpoint DCTL Data
> + Offset(435), NEB3, 16, // Offset(435), RST PCIe Storage Cycle Router#3
> Endpoint DCTL Data
> + Offset(437), NEC1, 16, // Offset(437), RST PCIe Storage Cycle Router#1
> Endpoint DCTL2 Data
> + Offset(439), NEC2, 16, // Offset(439), RST PCIe Storage Cycle Router#2
> Endpoint DCTL2 Data
> + Offset(441), NEC3, 16, // Offset(441), RST PCIe Storage Cycle Router#3
> Endpoint DCTL2 Data
> + Offset(443), NRA1, 16, // Offset(443), RST PCIe Storage Cycle Router#1
> RootPort DCTL2 Data
> + Offset(445), NRA2, 16, // Offset(445), RST PCIe Storage Cycle Router#2
> RootPort DCTL2 Data
> + Offset(447), NRA3, 16, // Offset(447), RST PCIe Storage Cycle Router#3
> RootPort DCTL2 Data
> + Offset(449), NMB1, 32, // Offset(449), RST PCIe Storage Cycle Router#1
> Endpoint unique MSI-X Table BAR
> + Offset(453), NMB2, 32, // Offset(453), RST PCIe Storage Cycle Router#2
> Endpoint unique MSI-X Table BAR
> + Offset(457), NMB3, 32, // Offset(457), RST PCIe Storage Cycle Router#3
> Endpoint unique MSI-X Table BAR
> + Offset(461), NMV1, 32, // Offset(461), RST PCIe Storage Cycle Router#1
> Endpoint unique MSI-X Table BAR value
> + Offset(465), NMV2, 32, // Offset(465), RST PCIe Storage Cycle Router#2
> Endpoint unique MSI-X Table BAR value
> + Offset(469), NMV3, 32, // Offset(469), RST PCIe Storage Cycle Router#3
> Endpoint unique MSI-X Table BAR value
> + Offset(473), NPB1, 32, // Offset(473), RST PCIe Storage Cycle Router#1
> Endpoint unique MSI-X PBA BAR
> + Offset(477), NPB2, 32, // Offset(477), RST PCIe Storage Cycle Router#2
> Endpoint unique MSI-X PBA BAR
> + Offset(481), NPB3, 32, // Offset(481), RST PCIe Storage Cycle Router#3
> Endpoint unique MSI-X PBA BAR
> + Offset(485), NPV1, 32, // Offset(485), RST PCIe Storage Cycle Router#1
> Endpoint unique MSI-X PBA BAR value
> + Offset(489), NPV2, 32, // Offset(489), RST PCIe Storage Cycle Router#2
> Endpoint unique MSI-X PBA BAR value
> + Offset(493), NPV3, 32, // Offset(493), RST PCIe Storage Cycle Router#3
> Endpoint unique MSI-X PBA BAR value
> + Offset(497), , 8, // Offset(497), Flag indicating Exit Boot Service, to
> inform SMM
> + Offset(498), SXRB, 32, // Offset(498), Sx handler reserved MMIO base
> + Offset(502), SXRS, 32, // Offset(502), Sx handler reserved MMIO size
> + Offset(506), CIOE, 8, // Offset(506), Cio2 Device Enabled as ACPI device
> + Offset(507), CIOI, 8, // Offset(507), Cio2 Interrupt Number
> + Offset(508), TAEN, 8, // Offset(508), Thermal Device Acpi mode enabled
> + Offset(509), TIRQ, 8, // Offset(509), Thermal Device IRQ number
> + Offset(510), XWMB, 32, // Offset(510), XHCI memory base address
> + Offset(514), EMH4, 8, // Offset(514), eMMC HS400 mode enabled
> + Offset(515), CSKU, 8, // Offset(515), CPU SKU
> + Offset(516), ITA0, 16, // Offset(516),
> + Offset(518), ITA1, 16, // Offset(518),
> + Offset(520), ITA2, 16, // Offset(520),
> + Offset(522), ITA3, 16, // Offset(522),
> + Offset(524), ITS0, 8, // Offset(524),
> + Offset(525), ITS1, 8, // Offset(525),
> + Offset(526), ITS2, 8, // Offset(526),
> + Offset(527), ITS3, 8, // Offset(527),
> + Offset(528), LTR1, 8, // Offset(528), Latency Tolerance Reporting Enable
> + Offset(529), LTR2, 8, // Offset(529), Latency Tolerance Reporting Enable
> + Offset(530), LTR3, 8, // Offset(530), Latency Tolerance Reporting Enable
> + Offset(531), LTR4, 8, // Offset(531), Latency Tolerance Reporting Enable
> + Offset(532), LTR5, 8, // Offset(532), Latency Tolerance Reporting Enable
> + Offset(533), LTR6, 8, // Offset(533), Latency Tolerance Reporting Enable
> + Offset(534), LTR7, 8, // Offset(534), Latency Tolerance Reporting Enable
> + Offset(535), LTR8, 8, // Offset(535), Latency Tolerance Reporting Enable
> + Offset(536), LTR9, 8, // Offset(536), Latency Tolerance Reporting Enable
> + Offset(537), LTRA, 8, // Offset(537), Latency Tolerance Reporting Enable
> + Offset(538), LTRB, 8, // Offset(538), Latency Tolerance Reporting Enable
> + Offset(539), LTRC, 8, // Offset(539), Latency Tolerance Reporting Enable
> + Offset(540), LTRD, 8, // Offset(540), Latency Tolerance Reporting Enable
> + Offset(541), LTRE, 8, // Offset(541), Latency Tolerance Reporting Enable
> + Offset(542), LTRF, 8, // Offset(542), Latency Tolerance Reporting Enable
> + Offset(543), LTRG, 8, // Offset(543), Latency Tolerance Reporting Enable
> + Offset(544), LTRH, 8, // Offset(544), Latency Tolerance Reporting Enable
> + Offset(545), LTRI, 8, // Offset(545), Latency Tolerance Reporting Enable
> + Offset(546), LTRJ, 8, // Offset(546), Latency Tolerance Reporting Enable
> + Offset(547), LTRK, 8, // Offset(547), Latency Tolerance Reporting Enable
> + Offset(548), OBF1, 8, // Offset(548), Optimized Buffer Flush and Fill
> + Offset(549), OBF2, 8, // Offset(549), Optimized Buffer Flush and Fill
> + Offset(550), OBF3, 8, // Offset(550), Optimized Buffer Flush and Fill
> + Offset(551), OBF4, 8, // Offset(551), Optimized Buffer Flush and Fill
> + Offset(552), OBF5, 8, // Offset(552), Optimized Buffer Flush and Fill
> + Offset(553), OBF6, 8, // Offset(553), Optimized Buffer Flush and Fill
> + Offset(554), OBF7, 8, // Offset(554), Optimized Buffer Flush and Fill
> + Offset(555), OBF8, 8, // Offset(555), Optimized Buffer Flush and Fill
> + Offset(556), OBF9, 8, // Offset(556), Optimized Buffer Flush and Fill
> + Offset(557), OBFA, 8, // Offset(557), Optimized Buffer Flush and Fill
> + Offset(558), OBFB, 8, // Offset(558), Optimized Buffer Flush and Fill
> + Offset(559), OBFC, 8, // Offset(559), Optimized Buffer Flush and Fill
> + Offset(560), OBFD, 8, // Offset(560), Optimized Buffer Flush and Fill
> + Offset(561), OBFE, 8, // Offset(561), Optimized Buffer Flush and Fill
> + Offset(562), OBFF, 8, // Offset(562), Optimized Buffer Flush and Fill
> + Offset(563), OBFG, 8, // Offset(563), Optimized Buffer Flush and Fill
> + Offset(564), OBFH, 8, // Offset(564), Optimized Buffer Flush and Fill
> + Offset(565), OBFI, 8, // Offset(565), Optimized Buffer Flush and Fill
> + Offset(566), OBFJ, 8, // Offset(566), Optimized Buffer Flush and Fill
> + Offset(567), OBFK, 8, // Offset(567), Optimized Buffer Flush and Fill
> + Offset(568), ECR1, 8, // Offset(568), External Change Request
> + Offset(569), AG1L, 64, // Offset(569), HDA PP module custom GUID 1 -
> first 64bit [0-63]
> + Offset(577), AG1H, 64, // Offset(577), HDA PP module custom GUID 1 -
> second 64bit [64-127]
> + Offset(585), AG2L, 64, // Offset(585), HDA PP module custom GUID 2 -
> first 64bit [0-63]
> + Offset(593), AG2H, 64, // Offset(593), HDA PP module custom GUID 2 -
> second 64bit [64-127]
> + Offset(601), AG3L, 64, // Offset(601), HDA PP module custom GUID 3 -
> first 64bit [0-63]
> + Offset(609), AG3H, 64, // Offset(609), HDA PP module custom GUID 3 -
> second 64bit [64-127]
> + Offset(617), MCFG, 32 // Offset(617), PcieMmCfgBaseAddress
> + }
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch
> Pcie.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch
> Pcie.asl
> new file mode 100644
> index 0000000000..21d68c55bc
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch
> Pcie.asl
> @@ -0,0 +1,203 @@
> +/** @file
> +
> + @copyright
> + Copyright 1999 - 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> + OperationRegion(PXCS,PCI_Config,0x00,0x480)
> + Field(PXCS,AnyAcc, NoLock, Preserve)
> + {
> + Offset(0),
> + VDID, 32,
> + Offset(0x50), // LCTL - Link Control Register
> + L0SE, 1, // 0, L0s Entry Enabled
> + , 3,
> + LDIS, 1,
> + , 3,
> + Offset(0x52), // LSTS - Link Status Register
> + , 13,
> + LASX, 1, // 0, Link Active Status
> + Offset(0x5A), // SLSTS[7:0] - Slot Status Register
> + ABPX, 1, // 0, Attention Button Pressed
> + , 2,
> + PDCX, 1, // 3, Presence Detect Changed
> + , 2,
> + PDSX, 1, // 6, Presence Detect State
> + , 1,
> + Offset(0x60), // RSTS - Root Status Register
> + , 16,
> + PSPX, 1, // 16, PME Status
> + Offset(0xA4),
> + D3HT, 2, // Power State
> + Offset(0xD8), // MPC - Miscellaneous Port Configuration Register
> + , 30,
> + HPEX, 1, // 30, Hot Plug SCI Enable
> + PMEX, 1, // 31, Power Management SCI Enable
> + Offset(0xE2), // RPPGEN - Root Port Power Gating Enable
> + , 2,
> + L23E, 1, // 2, L23_Rdy Entry Request (L23ER)
> + L23R, 1, // 3, L23_Rdy to Detect Transition (L23R2DT)
> + Offset(0x324),
> + , 3,
> + LEDM, 1, // PCIEDBG.DMIL1EDM
> + Offset(0x420), // Offset 420h: PCIEPMECTL - PCIe PM Extension Control
> + , 30,
> + DPGE, 1, // PCIEPMECTL[30]: Disabled, Detect and L23_Rdy State PHY
> Lane Power Gating Enable (DLSULPPGE):
> + }
> + Field(PXCS,AnyAcc, NoLock, WriteAsZeros)
> + {
> + Offset(0xDC), // SMSCS - SMI/SCI Status Register
> + , 30,
> + HPSX, 1, // 30, Hot Plug SCI Status
> + PMSX, 1 // 31, Power Management SCI Status
> + }
> +
> +
> + Name(LTRV, Package(){0,0,0,0})
> +
> + //
> + // _DSM Device Specific Method
> + //
> + // Arg0: UUID Unique function identifier
> + // Arg1: Integer Revision Level
> + // Arg2: Integer Function Index (0 = Return Supported Functions)
> + // Arg3: Package Parameters
> + Method(_DSM, 4, Serialized) {
> + //
> + // Switch based on which unique function identifier was passed in
> + //
> + If (LEqual(Arg0, ToUUID ("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {
> + //
> + // _DSM Definitions for Latency Tolerance Reporting
> + //
> + // Arguments:
> + // Arg0: UUID: E5C937D0-3553-4d7a-9117-EA4D19C3434D
> + // Arg1: Revision ID: 2
> + // Arg2: Function Index: 1, 4 or 6
> + // Arg3: Empty Package
> + //
> + // Return:
> + // A Package of four integers corresponding with the LTR encoding
> defined
> + // in the PCI Express Base Specification, as follows:
> + // Integer 0: Maximum Snoop Latency Scale
> + // Integer 1: Maximum Snoop Latency Value
> + // Integer 2: Maximum No-Snoop Latency Scale
> + // Integer 3: Maximum No-Snoop Latency Value
> + // These values correspond directly to the LTR Extended Capability
> Structure
> + // fields described in the PCI Express Base Specification.
> + //
> + //
> + // Switch by function index
> + //
> + Switch(ToInteger(Arg2)) {
> + //
> + // Function Index:0
> + // Standard query - A bitmask of functions supported
> + //
> + Case (0) {
> + Name(OPTS,Buffer(2){0,0})
> + CreateBitField(OPTS,0,FUN0)
> + CreateBitField(OPTS,4,FUN4)
> + CreateBitField(OPTS,6,FUN6)
> + CreateBitField(OPTS,8,FUN8)
> + CreateBitField(OPTS,9,FUN9)
> +
> + if (LGreaterEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2
> + Store(1,FUN0)
> + if (LTRE){
> + Store(1,Fun6)
> + }
> + if (OBFF){
> + Store(1,Fun4)
> + }
> + if(LEqual(ECR1,1)){
> + if (LGreaterEqual(Arg1, 3)){ // test Arg1 for Revision ID: 3
> + Store(1,Fun8)
> + Store(1,Fun9)
> + }
> + }
> + }
> + Return (OPTS)
> + }
> + //
> + // Function Index: 4
> + //
> + Case(4) {
> + if (LGreaterEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2
> + if (OBFN){
> + Return (Buffer () {0,0,0,0,0,0,0,0,0,0,0,8,0,0,0,0}) // OBFF capable,
> offset 4[08h]
> + } else {
> + Return (Buffer () {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0})
> + }
> + }
> + }
> + //
> + // Function Index: 6
> + // LTR Extended Capability Structure
> + //
> + Case(6) {
> + if (LGreaterEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2
> + if (LTRN){
> + if (LOr(LEqual(LMSL, 0),LEqual(LNSL, 0)))
> + {
> + if (LEqual (PCHS, SPTH)) {
> + Store (0x0846, LMSL)
> + Store (0x0846, LNSL)
> + } elseif (LEqual (PCHS, SPTL)) {
> + Store (0x1003, LMSL)
> + Store (0x1003, LNSL)
> + }
> + }
> + Store(And(ShiftRight(LMSL,10),7), Index(LTRV, 0))
> + Store(And(LMSL,0x3FF), Index(LTRV, 1))
> + Store(And(ShiftRight(LNSL,10),7), Index(LTRV, 2))
> + Store(And(LNSL,0x3FF), Index(LTRV, 3))
> +
> + Return (LTRV)
> + } else {
> + Return (0)
> + }
> + }
> + }
> + Case(8) { //ECR ACPI additions for FW latency optimizations, DSM for
> Avoiding Power-On Reset Delay Duplication on Sx Resume
> + if(LEqual(ECR1,1)){
> + if (LGreaterEqual(Arg1, 3)) { // test Arg1 for Revision ID: 3
> + return (1)
> + }
> + }
> + }
> + Case(9) { //ECR ACPI additions for FW latency optimizations, DSM for
> Specifying Device Readiness Durations
> + if(LEqual(ECR1,1)){
> + if (LGreaterEqual(Arg1, 3)) { // test Arg1 for Revision ID: 3
> + return(Package(5){50000,Ones,Ones,50000,Ones})
> + }
> + }
> + }
> + } // End of switch(Arg2)
> + } // End of if
> + return (Buffer() {0x00})
> + } // End of _DSM
> +
> + Device(PXSX)
> + {
> + Name(_ADR, 0x00000000)
> +
> + // NOTE: Any PCIE Hot-Plug dependency for this port is
> + // specific to the CRB. Please modify the code based on
> + // your platform requirements.
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + }
> +
> + //
> + // PCI_EXP_STS Handler for PCIE Root Port
> + //
> + Method(HPME,0,Serialized) {
> + If(LAnd(LNotEqual(VDID,0xFFFFFFFF), LEqual(PMSX,1))) { //if port exists
> and has PME SCI Status set...
> + Notify (PXSX, 0x2) //notify child device; this will cause its driver to clear
> PME_Status from device
> + Store(1,PMSX) // clear rootport's PME SCI status
> + Store(1,PSPX) // consume one pending PME notification to prevent it
> from blocking the queue
> + }
> + }
> +
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch
> Sata.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch
> Sata.asl
> new file mode 100644
> index 0000000000..4150833906
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch
> Sata.asl
> @@ -0,0 +1,50 @@
> +/** @file
> +
> + @copyright
> + Copyright 2013 - 2020 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#define ROOTPORT_READ 0
> +#define ROOTPORT_WRITE 1
> +#define ENDPOINT_READ 2
> +#define ENDPOINT_WRITE 3
> +
> +//
> +// SDSM is Device Specific Method supporting AHCI DEVSLP
> +// It is not guaranteed to be available on every boot
> +//
> +// move one level up to Pch.asl
> +
> + Method(_DSM,4,serialized){
> + if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) };
> + if(CondRefOf(\_SB.PC00.SAT0.SDSM)) { return
> (\_SB.PC00.SAT0.SDSM(Arg0,Arg1,Arg2,Arg3)) };
> + Return(Buffer() {0})
> + }
> +
> + Device(PRT0)
> + {
> + Name(_ADR,0x0000FFFF) // Port 0
> + }
> + Device(PRT1)
> + {
> + Name(_ADR,0x0001FFFF) // Port 1
> + }
> + Device(PRT2)
> + {
> + Name(_ADR,0x0002FFFF) // Port 2
> + }
> + Device(PRT3)
> + {
> + Name(_ADR,0x0003FFFF) // Port 3
> + }
> + Device(PRT4)
> + {
> + Name(_ADR,0x0004FFFF) // Port 4
> + }
> + Device(PRT5)
> + {
> + Name(_ADR,0x0005FFFF) // Port 5
> + }
> +
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch
> Xhci.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch
> Xhci.asl
> new file mode 100644
> index 0000000000..5b9d7ed57e
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch
> Xhci.asl
> @@ -0,0 +1,558 @@
> +/** @file
> +
> + @copyright
> + Copyright 2010 - 2020 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +External(\_SB.PC00.XHCI.PS0X, MethodObj)
> +External(\_SB.PC00.XHCI.PS3X, MethodObj)
> +External(\_SB.PC00.XHCI.RHUB.PS0X, MethodObj)
> +External(\_SB.PC00.XHCI.RHUB.PS2X, MethodObj)
> +External(\_SB.PC00.XHCI.RHUB.PS3X, MethodObj)
> +External(\_SB.PC00.XHCI.RHUB.INIR, MethodObj)
> +
> +
> +Scope(\_SB_.PC00.XHCI) {
> +
> + OperationRegion(XPRT,PCI_Config,0x00,0x100)
> + Field(XPRT,AnyAcc,NoLock,Preserve)
> + {
> + DVID, 16,
> + Offset(0x74),
> + D0D3, 2, // 0x74 BIT[1:0]
> + , 6,
> + PMEE, 1, // PME Enable
> + , 6,
> + PMES, 1, // PME Status
> + Offset(0xA8), // SSCFG Reg for WPTLP
> + , 13,
> + MW13, 1, // 0xA8 BIT[13]
> + MW14, 1, // 0xA8 BIT[14]
> + , 17,
> + Offset(0xB0), // SSCFG Reg for LPTLP
> + , 13,
> + MB13, 1, // 0xB0 BIT[13]
> + MB14, 1, // 0xB0 BIT[14]
> + , 17,
> + Offset(0xD0),
> + PR2, 32, // XUSB2PR: xHC USB 2.0 Port Routing Register.
> + PR2M, 32, // XUSB2PRM: xHC USB 2.0 Port Routing Mask Register.
> + PR3, 32, // USB3_PSSEN: USB3.0 Port SuperSpeed Enable Register.
> + PR3M, 32 // USB3PRM: USB3.0 Port Routing Mask Register
> + }
> +
> + //
> + // Variable to store the maximum D state supported in S0.
> + //
> + Name (XFLT, 0)
> + //
> + // XHCI controller won't go into D3Hot during S0 until _DSM method is
> evaluated by filter driver.
> + //
> + Method(_DSM,4,serialized){
> + If(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }
> + //
> + // Check GUID ac340cb7-e901-45bf-b7e6-2b34ec931e23
> + //
> + If(LEqual(Arg0, Buffer(0x10) { 0xb7, 0x0c, 0x34, 0xac, 0x01, 0xe9, 0xbf,
> 0x45, 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23 }))
> + {
> + //
> + // Only Supported value is "0x3"
> + //
> + If(LEqual(Arg1, 0x3))
> + {
> + Store(Arg1,XFLT)
> + }
> + }
> + Return(Buffer() {0})
> + }
> +
> + Method(_S3D, 0, NotSerialized)
> + {
> + Return(3)
> + }
> + Method(_S4D, 0, NotSerialized)
> + {
> + Return(3)
> + }
> + Method(_S3W, 0, NotSerialized)
> + {
> + Return(3)
> + }
> + Method(_S4W, 0, NotSerialized)
> + {
> + Return(3)
> + }
> +
> + //
> + // Once the filter driver is installed, D3 is allowed.
> + //
> + Method(_S0W, 0x0, NotSerialized)
> + {
> + If(LEqual(XFLT, Zero))
> + {
> + Return(0x0)
> + }
> + Else
> + {
> + Return(0x3)
> + }
> + }
> +
> + Method(_PRW, 0)
> + {
> + Return(GPRW(0x6D, 4)) // can wakeup from S4 state
> + }
> +
> + Method(_DSW, 3)
> + {
> + Store(Arg0, PMEE)
> + }
> +
> + Method(_INI) {
> + // _INI for RTD3 run conditionally if implemented in platform specific
> code
> + If(CondRefOf(\_SB.PC00.XHCI.RHUB.INIR)) { // _INI for RTD3
> + \_SB.PC00.XHCI.RHUB.INIR()
> + }
> + }
> +
> + //
> + // GPE handler for XHCI, this is part of _Lxx handler for bus 0 PME
> + //
> + Method(GPEH)
> + {
> + If(LEqual(DVID, 0xFFFF)) {
> + Return()
> + }
> + Store(PMES, Local0)
> + Store(1, PMES) // clear PME Status
> + If(LAnd(PMEE, Local0)) {
> + Notify(XHCI, 0x02)
> + }
> + }
> +
> + OperationRegion(XHCP, SystemMemory, Add(MCFG, 0xA0000), 0x100)
> + Field(XHCP,AnyAcc,Lock,Preserve)
> + {
> + Offset(0x4),
> + PDBM, 16,
> + Offset(0x10),
> + MEMB, 64
> + }
> +
> + //
> + // USRA (USbR port Address), method for calculating address of first USBR
> port in XHCI controller
> + //
> + Method(USRA,0,Serialized) {
> + If(LEqual(PCHV, SPTH)) { // SPT-H
> + Return (15)
> + } Else { // SPT-LP
> + Return (11)
> + }
> + }
> +
> + //
> + // SSPA (SuperSpeed Port Address), method for calculating address of
> first SS port in XHCI controller
> + //
> + Method(SSPA,0,Serialized) {
> + If(LEqual(PCHV, SPTH)) { // SPT-H
> + Return (17)
> + } Else { // SPT-LP
> + Return (13)
> + }
> + }
> +
> + Name(XRST, Zero)
> +
> + Method(_PS0,0,Serialized)
> + {
> +
> + If(LEqual(^DVID,0xFFFF))
> + {
> + Return()
> + }
> +
> + Store(^MEMB,Local2) // Save MBAR
> + Store(^PDBM,Local1) // Save CMD
> +
> + And(^PDBM,Not(0x06),^PDBM) // Clear MSE/BME
> +
> + //
> + // Switch to D0
> + //
> + Store(0,^D0D3)
> +
> + Store(\XWMB,^MEMB) // Set MBAR
> + Or(Local1,0x0002,^PDBM) // Set MSE
> +
> + //
> + //
> + //
> +
> + And(^PDBM,Not(0x02),^PDBM) // Clear MSE
> +
> + Store(Local2,^MEMB) // Restore MBAR
> + Store(Local1,^PDBM) // Restore CMD
> +
> + //
> + // Call platform XHC PS0 method if present
> + //
> + If(CondRefOf(\_SB.PC00.XHCI.PS0X))
> + {
> + \_SB.PC00.XHCI.PS0X()
> + }
> + //
> + //
> + If(LAnd(UWAB,LEqual(D0D3,0))) {
> +
> + //
> + // If the USB WA Bit is set and any XHCI or XDCI controller is in D0
> + //
> + //
> + // USB2 PHPY Power Gating - SW WA
> + //
> + // 1. BIOS writes a new command to the MTPMC register to cause the
> PMC to disable power gating
> + Store(1,MPMC)
> +
> + // 2. BIOS waits for PCH_PM_STS.MSG_FULL_STS to be 0
> + // In parallel and in response to the previous command from BIOS,
> PMC FW will:
> + // * Make the USB2 force common lane PG match the BIOS policy
> (common lane PG disallowed)
> + // * Disable SUS power gating in XHCI
> + // * Wait for USB2 PHY side_pok to be 1
> + // * Disable core power gating in USB2 PHY
> + // * Disable common lane power gating in USB2 PHY (probably not
> necessary, consider removal)
> + // * Wait for USB2 SUS restoration status to be set, and do USB2
> SUS power gating restoration
> + // * Get the PHY in the correct state before allowing transition to
> D0.
> + // * Clear MSG_FULL_STS
> + // BIOS sees MSG_FULL_STS clear and exits the method
> + //
> + While(PMFS) {
> + Sleep(10)
> + }
> + } // End If(UWAB)
> +
> + }
> +
> + Method(_PS3,0,Serialized)
> + {
> +
> + If(LEqual(^DVID,0xFFFF))
> + {
> + Return()
> + }
> +
> + Store(^MEMB,Local2) // Save MBAR
> + Store(^PDBM,Local1) // Save CMD
> +
> + And(^PDBM,Not(0x06),^PDBM) // Clear MSE/BME
> +
> + //
> + // Switch back to D0
> + //
> + Store(0,^D0D3)
> +
> + Store(\XWMB,^MEMB) // Set MBAR
> + Or(Local1,0x0002,^PDBM) // Set MSE
> +
> + //
> + //
> + //
> +
> + And(^PDBM,Not(0x02),^PDBM) // Clear MSE
> +
> + //
> + // Switch back to D3
> + //
> + Store(3,^D0D3)
> +
> + Store(Local2,^MEMB) // Restore MBAR
> + Store(Local1,^PDBM) // Restore CMD
> +
> + //
> + // Call platform XHC PS3 method if present
> + //
> + If(CondRefOf(\_SB.PC00.XHCI.PS3X))
> + {
> + \_SB.PC00.XHCI.PS3X()
> + }
> + If(LAnd(UWAB,LEqual(D0D3,3))) {
> + //
> + // If the USB WA Bit is set and XHCI is in D3
> + //
> +
> + // 1. BIOS writes a new command to the MTPMC register to enable
> power gating
> + Store(3,MPMC)
> +
> + // 2. BIOS waits for PCH_PM_STS.MSG_FULL_STS to be 0
> + // In parallel and in response to the previous command from BIOS,
> PMC FW will:
> + // * Make the USB2 force common lane PG match the BIOS policy
> (common lane PG allowed)
> + // * Enable SUS power gating in XHCI
> + // * Enable core power gating in USB2 PHY
> + // * Enable common lane power gating in the USB2 PHY
> + // * Clear MSG_FULL_STS
> + // BIOS sees MSG_FULL_STS clear and exits the method
> + //
> + While(PMFS) {
> + Sleep(10)
> + }
> + } // End If(UWAB)
> + }
> +
> +
> + // Apply S3 workaround.
> + // Arguments :
> + // None
> + // Changes 8090 Bit 10 before S3.
> + //
> + Method(XHCS,0, Serialized) {
> + Store(^MEMB,Local2) // Save MBAR
> + Store(^PDBM,Local1) // Save CMD
> +
> + And(^PDBM,Not(0x06),^PDBM) // Clear MSE/BME
> +
> + Store(\XWMB,^MEMB) // Set MBAR
> + Or(Local1,0x0002,^PDBM) // Set MSE
> +
> + OperationRegion(MC11,SystemMemory,\XWMB,0x9000)
> + Field(MC11,DWordAcc,Lock,Preserve)
> + {
> + Offset(0x8090), // HC Transfer Manager - TRM
> + , 10,
> + UCLI, 1, // CLEAR IN EP
> + }
> +
> + Store(0x1,UCLI)
> +
> + And(^PDBM,Not(0x02),^PDBM) // Clear MSE
> +
> + Store(Local2,^MEMB) // Restore MBAR
> + Store(Local1,^PDBM) // Restore CMD
> +
> + }
> +
> + //
> + //
> + // Check for XHCI switch UUID
> + //
> + // Arguments:
> + // Arg0 (Buffer) : UUID
> + //
> + // Returns:
> + // 1: It's valid UUID
> + // 0: Invalid UUID
> + //
> + Method(CUID,1,Serialized) {
> + If(LEqual(Arg0,ToUUID("7c9512a9-1705-4cb4-af7d-506a2423ab71"))) {
> + Return(1)
> + }
> + Return(0)
> + }
> +
> + Device(RHUB)
> + {
> + Name(_ADR, Zero)
> +
> + // PS0 Method for xHCI Root Hub
> + Method(_PS0,0,Serialized)
> + {
> + If(LEqual(\_SB.PC00.XHCI.DVID,0xFFFF))
> + {
> + Return()
> + }
> + //
> + // Call platform XHC.RHUB PS0 method if present.
> + //
> + If(CondRefOf(\_SB.PC00.XHCI.RHUB.PS0X))
> + {
> + \_SB.PC00.XHCI.RHUB.PS0X()
> + }
> + }
> +
> + // PS2 Method for xHCI Root Hub
> + Method(_PS2,0,Serialized)
> + {
> + If(LEqual(\_SB.PC00.XHCI.DVID,0xFFFF))
> + {
> + Return()
> + }
> + //
> + // Call platform XHC.RHUB PS2 method if present.
> + //
> + If(CondRefOf(\_SB.PC00.XHCI.RHUB.PS2X))
> + {
> + \_SB.PC00.XHCI.RHUB.PS2X()
> + }
> + }
> +
> + // PS3 Method for xHCI Root Hub
> + Method(_PS3,0,Serialized)
> + {
> + If(LEqual(\_SB.PC00.XHCI.DVID,0xFFFF))
> + {
> + Return()
> + }
> + //
> + // Call platform XHC.RHUB PS3 method if present.
> + //
> + If(CondRefOf(\_SB.PC00.XHCI.RHUB.PS3X))
> + {
> + \_SB.PC00.XHCI.RHUB.PS3X()
> + }
> + }
> +
> + //
> + // High Speed Ports (without USBR)
> + //
> + Device(HS01)
> + {
> + Name(_ADR, 0x01)
> + }
> +
> + Device(HS02)
> + {
> + Name(_ADR, 0x02)
> + }
> +
> + Device(HS03)
> + {
> + Name(_ADR, 0x03)
> + }
> +
> + Device(HS04)
> + {
> + Name(_ADR, 0x04)
> + }
> +
> + Device(HS05)
> + {
> + Name(_ADR, 0x05)
> + }
> +
> + Device(HS06)
> + {
> + Name(_ADR, 0x06)
> + }
> +
> + Device(HS07)
> + {
> + Name(_ADR, 0x07)
> + }
> +
> + Device(HS08)
> + {
> + Name(_ADR, 0x08)
> + }
> +
> + Device(HS09)
> + {
> + Name(_ADR, 0x09)
> + }
> +
> + Device(HS10)
> + {
> + Name(_ADR, 0x0A)
> + }
> +
> + //
> + // USBR port will be known as USBR instead of HS09 / HS15
> + //
> + Device(USR1)
> + {
> + Method(_ADR) { Return (Add(USRA(),0)) }
> + }
> +
> + //
> + // USBR port 2 will be known as USBR instead of xxxx
> + //
> + Device(USR2)
> + {
> + Method(_ADR) { Return (Add(USRA(),1)) }
> + }
> +
> + //
> + // Super Speed Ports
> + //
> + Device(SS01)
> + {
> + Method(_ADR) { Return (Add(SSPA(),0)) }
> + }
> +
> + Device(SS02)
> + {
> + Method(_ADR) { Return (Add(SSPA(),1)) }
> + }
> +
> + Device(SS03)
> + {
> + Method(_ADR) { Return (Add(SSPA(),2)) }
> + }
> +
> + Device(SS04)
> + {
> + Method(_ADR) { Return (Add(SSPA(),3)) }
> + }
> +
> + Device(SS05)
> + {
> + Method(_ADR) { Return (Add(SSPA(),4)) }
> + }
> +
> + Device(SS06)
> + {
> + Method(_ADR) { Return (Add(SSPA(),5)) }
> + }
> +
> + } // device rhub
> +} //scope
> +
> +//
> +// SPT-H
> +//
> +
> + Scope(\_SB_.PC00.XHCI.RHUB) {
> +
> +
> +
> + Device(HS11)
> + {
> + Name(_ADR, 0xB)
> + }
> +
> +
> + Device(HS12)
> + {
> + Name(_ADR, 0xC)
> + }
> +
> + Device(HS13)
> + {
> + Name(_ADR, 0xD)
> + }
> +
> + Device(HS14)
> + {
> + Name(_ADR, 0xE)
> + }
> +
> + Device(SS07)
> + {
> + Method(_ADR) { Return (Add(SSPA(),6)) }
> + }
> +
> + Device(SS08)
> + {
> + Method(_ADR) { Return (Add(SSPA(),7)) }
> + }
> +
> + Device(SS09)
> + {
> + Method(_ADR) { Return (Add(SSPA(),8)) }
> + }
> +
> + Device(SS10)
> + {
> + Method(_ADR) { Return (Add(SSPA(),9)) }
> + }
> +
> + } //scope
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 1_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 1_ADR.asl
> new file mode 100644
> index 0000000000..cfacfdbfd4
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 1_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPA1,0)) {
> + Return (RPA1)
> + } Else {
> + Return (0x001C0000)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 2_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 2_ADR.asl
> new file mode 100644
> index 0000000000..14d239597c
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 2_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPA2,0)) {
> + Return (RPA2)
> + } Else {
> + Return (0x001C0001)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 3_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 3_ADR.asl
> new file mode 100644
> index 0000000000..e116aa3fcf
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 3_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPA3,0)) {
> + Return (RPA3)
> + } Else {
> + Return (0x001C0002)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 4_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 4_ADR.asl
> new file mode 100644
> index 0000000000..a89ba41f87
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 4_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPA4,0)) {
> + Return (RPA4)
> + } Else {
> + Return (0x001C0003)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 5_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 5_ADR.asl
> new file mode 100644
> index 0000000000..82ac284b8c
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 5_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPA5,0)) {
> + Return (RPA5)
> + } Else {
> + Return (0x001C0004)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 6_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 6_ADR.asl
> new file mode 100644
> index 0000000000..153b4b3fce
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 6_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPA6,0)) {
> + Return (RPA6)
> + } Else {
> + Return (0x001C0005)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 7_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 7_ADR.asl
> new file mode 100644
> index 0000000000..b8f93ff22b
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 7_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPA7,0)) {
> + Return (RPA7)
> + } Else {
> + Return (0x001C0006)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 8_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 8_ADR.asl
> new file mode 100644
> index 0000000000..ad786680b1
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 8_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPA8,0)) {
> + Return (RPA8)
> + } Else {
> + Return (0x001C0007)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 9_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 9_ADR.asl
> new file mode 100644
> index 0000000000..8fea09fb6d
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 9_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPA9,0)) {
> + Return (RPA9)
> + } Else {
> + Return (0x001D0000)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 0_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 0_ADR.asl
> new file mode 100644
> index 0000000000..e5faa36089
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 0_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPAA,0)) {
> + Return (RPAA)
> + } Else {
> + Return (0x001D0001)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 1_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 1_ADR.asl
> new file mode 100644
> index 0000000000..f35101300c
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 1_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPAB,0)) {
> + Return (RPAB)
> + } Else {
> + Return (0x001D0002)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 2_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 2_ADR.asl
> new file mode 100644
> index 0000000000..b8b8b305cd
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 2_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPAC,0)) {
> + Return (RPAC)
> + } Else {
> + Return (0x001D0003)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 3_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 3_ADR.asl
> new file mode 100644
> index 0000000000..c81ce74af9
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 3_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPAD,0)) {
> + Return (RPAD)
> + } Else {
> + Return (0x001D0004)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 4_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 4_ADR.asl
> new file mode 100644
> index 0000000000..3a79d7b90b
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 4_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPAE,0)) {
> + Return (RPAE)
> + } Else {
> + Return (0x001D0005)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 5_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 5_ADR.asl
> new file mode 100644
> index 0000000000..6c5e812a02
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 5_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPAF,0)) {
> + Return (RPAF)
> + } Else {
> + Return (0x001D0006)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 6_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 6_ADR.asl
> new file mode 100644
> index 0000000000..0099005840
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 6_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPAG,0)) {
> + Return (RPAG)
> + } Else {
> + Return (0x001D0007)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 7_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 7_ADR.asl
> new file mode 100644
> index 0000000000..745d5523b0
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 7_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPAH,0)) {
> + Return (RPAH)
> + } Else {
> + Return (0x001B0000)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 8_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 8_ADR.asl
> new file mode 100644
> index 0000000000..e32e1ab276
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 8_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPAI,0)) {
> + Return (RPAI)
> + } Else {
> + Return (0x001B0001)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 9_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 9_ADR.asl
> new file mode 100644
> index 0000000000..06b8a23ab4
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 9_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPAJ,0)) {
> + Return (RPAJ)
> + } Else {
> + Return (0x001B0002)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP2
> 0_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP2
> 0_ADR.asl
> new file mode 100644
> index 0000000000..baa96d405c
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP2
> 0_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPAK,0)) {
> + Return (RPAK)
> + } Else {
> + Return (0x001B0003)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Trac
> eHubDebug.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Trac
> eHubDebug.asl
> new file mode 100644
> index 0000000000..4c1dd36692
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Trac
> eHubDebug.asl
> @@ -0,0 +1,150 @@
> +/** @file
> + Trace Hub debug library for ASL code.
> +
> + @copyright
> + Copyright 2015 - 2020 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +External(PTHM, IntObj)
> +External(\_SB.PC00.PTHT.THEN, MethodObj, IntObj)
> +External(\_SB.PTHH.THEN, MethodObj, IntObj)
> +
> +Name (THMN, 0x20) // Master number should align with
> gSiPkgTokenSpaceGuid.PcdTraceHubDebugLibMaster
> +Name (THCN, 0x16) // Channel number could be different from
> gSiPkgTokenSpaceGuid.PcdTraceHubDebugLibChannel, 0~80h are available
> +
> +//
> +// @note Only include register definition macros in ASL.
> +// GCC will leak C function definitions in to ASL
> +// code, causing compilation errors in some cases.
> +//
> +#include <PchReservedResources.h>
> +#include <Register/PchRegsTraceHub.h>
> +
> +Scope(\) {
> + // Trace Hub debug address
> + // This is internal helper runtine of THDS
> + // Arg0 : Master number
> + // Arg1 : Channel number
> + Method (THDA, 2, Serialized) {
> + // Local0 = PCH_TRACE_HUB_SW_BASE_ADDRESS + 0x40 *
> (V_PCH_TRACE_HUB_MTB_CHLCNT * (Master -
> V_PCH_TRACE_HUB_MTB_STHMSTR)) + 0x40 * Channel;
> + Store (PCH_TRACE_HUB_SW_BASE_ADDRESS, Local0)
> + Add (Local0, Multiply (0x40, Multiply (V_PCH_TRACE_HUB_MTB_CHLCNT,
> Subtract (Arg0, V_PCH_TRACE_HUB_MTB_STHMSTR))), Local0)
> + Add (Local0, Multiply (0x40, Arg1), Local0)
> + Return (Local0)
> + }
> +
> + // String to raw data
> + // This is internal helper runtine of THDS
> + // Arg0 : string
> + // Arg1 : Index
> + // Arg2 : size
> + Method (STRD, 3, Serialized) {
> + If (LGreater (Add (Arg1, Arg2), SizeOf (Arg0))) {
> + Return (0)
> + }
> + // Local0 is return value
> + // Lccal1 is loop index
> + // Local2 is char of string
> + // Local3 is buffer of string
> + ToBuffer (Arg0, Local3)
> + Store (0, Local0)
> + Store (0, Local1)
> + While (LLess (Local1, Arg2)) {
> + Store (DeRefOf (Index (Local3, Add (Arg1, Local1))), Local2)
> + Add (Local0, ShiftLeft (Local2, Multiply (8, Local1)), Local0)
> + Increment (Local1)
> + }
> + Return (Local0)
> + }
> +
> + // Trace Hub debug string
> + // Arg0 : debug string
> + Method (THDS, 1, Serialized) {
> + //
> + // Check if BIOS trace is enabled.
> + //
> + If (LEqual (PTHM, 0)) {
> + Return
> + } ElseIf (LEqual (PTHM, 1)) {
> + If (LNot (\_SB.PC00.PTHT.THEN())) {
> + Return
> + }
> + } ElseIf (LEqual (PTHM, 2)) {
> + If (LNot (\_SB.PTHH.THEN())) {
> + Return
> + }
> + } Else {
> + Return
> + }
> +
> + // Local0 is the length of string
> + // Local1 is the debug base address
> + Store (Sizeof (Arg0), Local0)
> + Store (THDA (THMN, THCN), Local1)
> + OperationRegion (THBA, SystemMemory, local1, 0x40)
> + Field (THBA, QWordAcc, NoLock, Preserve) {
> + Offset (0x00),
> + QO00, 64,
> + }
> + Field (THBA, DWordAcc, NoLock, Preserve) {
> + Offset (0x00),
> + DO00, 32,
> + Offset (0x10),
> + DO10, 32,
> + offset (0x30),
> + DO30, 32,
> + }
> + Field (THBA, WordAcc, NoLock, Preserve) {
> + Offset (0x00),
> + WO00, 16,
> + }
> + Field (THBA, ByteAcc, NoLock, Preserve) {
> + Offset (0x00),
> + BO00, 8,
> + }
> +
> + // time stamp
> + Store (0x01000242, DO10)
> + // length of string
> + Store (Local0, WO00)
> + // string
> + Store (0, Local6)
> + Store (Local0, Local7)
> + while (LGreaterEqual(Local7, 8)) {
> + Store (STRD (Arg0, Local6, 8), QO00)
> + Add (Local6, 8, Local6)
> + Subtract (Local7, 8, Local7)
> + }
> + If (LGreaterEqual(Local7, 4)) {
> + Store (STRD (Arg0, Local6, 4), DO00)
> + Add (Local6, 4, Local6)
> + Subtract (Local7, 4, Local7)
> + }
> + If (LGreaterEqual(Local7, 2)) {
> + Store (STRD (Arg0, Local6, 2), WO00)
> + Add (Local6, 2, Local6)
> + Subtract (Local7, 2, Local7)
> + }
> + If (LGreaterEqual(Local7, 1)) {
> + Store (STRD (Arg0, Local6, 1), BO00)
> + Add (Local6, 1, Local6)
> + Subtract (Local7, 1, Local7)
> + }
> + // flag
> + Store (0, DO30)
> + }
> +
> + // Trace Hub debug Hex string
> + // Arg0 : Integer, buffer
> + Method (THDH, 1, Serialized) {
> + THDS (ToHexString (Arg0))
> + }
> +
> + // Trace Hub debug decimal string
> + // Arg0 : Integer, buffer
> + Method (THDD, 1, Serialized) {
> + THDS (ToDecimalString (Arg0))
> + }
> +}
> diff --git a/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
> b/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
> index c4993cb897..e03ee6d5d8 100644
> --- a/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
> +++ b/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
> @@ -19,6 +19,7 @@
> Security/Include
> Pch/SouthClusterLbg
> Pch/SouthClusterLbg/Include
> + Pch/SouthClusterLbg/AcpiTables/Dsdt
>
> Cpu/Include
>
> --
> 2.27.0.windows.1
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