[edk2-devel] [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library
Abner Chang
abner.chang at hpe.com
Sat Jan 8 04:10:22 UTC 2022
(This is migrated from edk2-platforms:Silicon/RISC-V)
This library provides CSR assembly functions to read/write RISC-V
specific Control and Status registers.
Signed-off-by: Abner Chang <abner.chang at hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen at hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm at linaro.org>
Cc: Leif Lindholm <leif.lindholm at linaro.org>
Cc: Gilbert Chen <gilbert.chen at hpe.com>
---
.../Library/RiscVCpuLib/RiscVCpuLib.inf | 34 ++++++
.../Include/Library/RiscVCpuLib.h | 71 +++++++++++
.../ProcessorPkg/Library/RiscVCpuLib/Cpu.S | 111 ++++++++++++++++++
3 files changed, 216 insertions(+)
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
new file mode 100644
index 0000000000..7928dd5536
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
@@ -0,0 +1,34 @@
+## @file
+# RISC-V RV64 CPU library
+#
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVCpuLib
+ FILE_GUID = 8C6CFB0D-A0EE-40D5-90DA-2E51EAE0583F
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVCpuLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+
+[Sources.RISCV64]
+ Cpu.S
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
new file mode 100644
index 0000000000..f37d4c20d0
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
@@ -0,0 +1,71 @@
+/** @file
+ RISC-V CPU library definitions.
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef RISCV_CPU_LIB_H_
+#define RISCV_CPU_LIB_H_
+
+#include "RiscVImpl.h"
+
+/**
+ RISCV_TRAP_HANDLER
+**/
+typedef
+VOID
+(EFIAPI *RISCV_TRAP_HANDLER)(
+ VOID
+ );
+
+VOID
+RiscVSetMachineScratch (RISCV_MACHINE_MODE_CONTEXT *RiscvContext);
+
+UINT32
+RiscVGetMachineScratch (VOID);
+
+UINT32
+RiscVGetMachineTrapCause (VOID);
+
+UINT64
+RiscVReadMachineTimer (VOID);
+
+VOID
+RiscVSetMachineTimerCmp (UINT64);
+
+UINT64
+RiscVReadMachineTimerCmp(VOID);
+
+UINT64
+RiscVReadMachineInterruptEnable(VOID);
+
+UINT64
+RiscVReadMachineInterruptPending(VOID);
+
+UINT64
+RiscVReadMachineStatus(VOID);
+
+VOID
+RiscVWriteMachineStatus(UINT64);
+
+UINT64
+RiscVReadMachineTrapVector(VOID);
+
+UINT64
+RiscVReadMachineIsa (VOID);
+
+UINT64
+RiscVReadMachineVendorId (VOID);
+
+UINT64
+RiscVReadMachineArchitectureId (VOID);
+
+UINT64
+RiscVReadMachineImplementId (VOID);
+
+VOID
+RiscVSetSupervisorAddressTranslationRegister(UINT64);
+
+#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S b/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
new file mode 100644
index 0000000000..06ba80cb5f
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
@@ -0,0 +1,111 @@
+//------------------------------------------------------------------------------
+//
+// RISC-V CPU functions.
+//
+// Copyright (c) 2016 - 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+#include <Base.h>
+#include <RiscVImpl.h>
+
+.data
+
+.text
+.align 3
+
+//
+// Set machine mode scratch.
+// @param a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT.
+//
+ASM_FUNC (RiscVSetMachineScratch)
+ csrrw a1, RISCV_CSR_MACHINE_MSCRATCH, a0
+ ret
+
+//
+// Get machine mode scratch.
+// @retval a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT.
+//
+ASM_FUNC (RiscVGetMachineScratch)
+ csrrs a0, RISCV_CSR_MACHINE_MSCRATCH, 0
+ ret
+
+//
+// Get machine trap cause CSR.
+//
+ASM_FUNC (RiscVGetMachineTrapCause)
+ csrrs a0, RISCV_CSR_MACHINE_MCAUSE, 0
+ ret
+
+//
+// Get machine interrupt enable
+//
+ASM_FUNC (RiscVReadMachineInterruptEnable)
+ csrr a0, RISCV_CSR_MACHINE_MIE
+ ret
+
+//
+// Get machine interrupt pending
+//
+ASM_FUNC (RiscVReadMachineInterruptPending)
+ csrr a0, RISCV_CSR_MACHINE_MIP
+ ret
+
+//
+// Get machine status
+//
+ASM_FUNC (RiscVReadMachineStatus)
+ csrr a0, RISCV_CSR_MACHINE_MSTATUS
+ ret
+
+//
+// Set machine status
+//
+ASM_FUNC (RiscVWriteMachineStatus)
+ csrw RISCV_CSR_MACHINE_MSTATUS, a0
+ ret
+
+//
+// Get machine trap vector
+//
+ASM_FUNC (RiscVReadMachineTrapVector)
+ csrr a0, RISCV_CSR_MACHINE_MTVEC
+ ret
+
+//
+// Read machine ISA
+//
+ASM_FUNC (RiscVReadMachineIsa)
+ csrr a0, RISCV_CSR_MACHINE_MISA
+ ret
+
+//
+// Read machine vendor ID
+//
+ASM_FUNC (RiscVReadMachineVendorId)
+ csrr a0, RISCV_CSR_MACHINE_MVENDORID
+ ret
+
+//
+// Read machine architecture ID
+//
+ASM_FUNC (RiscVReadMachineArchitectureId)
+ csrr a0, RISCV_CSR_MACHINE_MARCHID
+ ret
+
+//
+// Read machine implementation ID
+//
+ASM_FUNC (RiscVReadMachineImplementId)
+ csrr a0, RISCV_CSR_MACHINE_MIMPID
+ ret
+
+//
+// Set Supervisor Address Translation and
+// Protection Register.
+//
+ASM_FUNC (RiscVSetSupervisorAddressTranslationRegister)
+ csrw RISCV_CSR_SUPERVISOR_SATP, a0
+ ret
+
--
2.31.1
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