[edk2-devel] [PATCH 41/79] RISC-V: Create opensbi firmware domains
Abner Chang
abner.chang at hpe.com
Sat Jan 8 07:23:43 UTC 2022
(This is migrated from edk2-platforms)
Incorporate with opensbi to create three firmware domains,
- Boot firmware domain, which built with opensbi library as
M-mode access only region.
- Firmware domain which includes PEI and DXE regions, the
PMP attribute is readable, wriable and executable.
- EFI Variable region which is readable and writable.
Cc: Sunil V L <sunilvl at ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer at hpe.com>
Signed-off-by: Abner Chang <abner.chang at hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer at hpe.com>
Reviewed-by: Sunil V L <sunilvl at ventanamicro.com>
---
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 40 ++++-----
.../OpensbiPlatformLib/OpensbiPlatformLib.inf | 9 +-
.../PlatformPkg/Universal/Sec/SecMain.inf | 6 +-
.../Library/OpensbiPlatformLib/Platform.c | 84 ++++++++++++++++---
.../PlatformPkg/Universal/Sec/SecMain.c | 53 +++++-------
.../Universal/Sec/Riscv64/SecEntry.S | 7 +-
6 files changed, 124 insertions(+), 75 deletions(-)
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
index ad15a155fe..7e41e7bdb2 100644
--- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
@@ -1,7 +1,7 @@
## @file RiscVPlatformPkg.dec
# This Package provides UEFI RISC-V platform modules and libraries.
#
-# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -31,33 +31,33 @@
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize|0x0|UINT32|0x00001003
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase|0x0|UINT32|0x00001004
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize|0x0|UINT32|0x00001005
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvBase|0x0|UINT32|0x00001016
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvSize|0x0|UINT32|0x00001017
-
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvBase|0x0|UINT32|0x00001006
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvSize|0x0|UINT32|0x00001007
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress|0x0|UINT32|0x00001008
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize|0x0|UINT32|0x00001009
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress|0x0|UINT32|0x0000100a
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize|0x0|UINT32|0x0000100b
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress|0x0|UINT32|0x0000100c
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize|0x0|UINT32|0x0000100d
#
# Definition of EFI Variable region
#
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress|0|UINT32|0x00001010
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize|0|UINT32|0x00001011
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize|0|UINT32|0x00001012
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBase|0|UINT32|0x00001013
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingBase|0|UINT32|0x00001014
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBase|0|UINT32|0x00001015
-#
-# Firmware region which is protected by PMP.
-#
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwBlockSize|0|UINT32|0x00001020
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress|0|UINT32|0x00001021
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress|0|UINT32|0x00001022
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress|0|UINT32|0x00001040
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize|0|UINT32|0x00001041
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize|0|UINT32|0x00001042
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBase|0|UINT32|0x00001043
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingBase|0|UINT32|0x00001044
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBase|0|UINT32|0x00001045
+
#
# Definition of RISC-V Hart
#
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount|0|UINT32|0x00001023
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId|0|UINT32|0x00001024
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount|0|UINT32|0x00001083
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId|0|UINT32|0x00001084
#
# The bootable hart core number, which is incorporate with OpenSBI platform hart_index2id value.
#
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber|0|UINT32|0x00001025
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber|0|UINT32|0x00001085
#
# Definitions for OpenSbi
#
@@ -73,7 +73,7 @@
[PcdsPatchableInModule]
[PcdsFeatureFlag]
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootlogoOnlyEnable|FALSE|BOOLEAN|0x00001006
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootlogoOnlyEnable|FALSE|BOOLEAN|0x00001200
[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
index f9f2073a5b..a408737961 100644
--- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
+++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
@@ -3,7 +3,7 @@
# This is the the library which provides platform
# level opensbi functions follow RISC-V OpenSBI implementation.
#
-# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -54,3 +54,10 @@
gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5UartBase
gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5PlatformSystemClock
+
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
index 78bd75e3ac..bcb8b9f908 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
@@ -1,7 +1,7 @@
## @file
# RISC-V SEC module.
#
-# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -64,8 +64,8 @@
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
index 79a78b834e..9926911297 100644
--- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
+++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
@@ -1,7 +1,7 @@
/*
* SPDX-License-Identifier: BSD-2-Clause
*
- * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
*
* Authors:
* Anup Patel <anup.patel at wdc.com>
@@ -10,6 +10,7 @@
#include <libfdt.h>
#include <PlatformOverride.h>
#include <sbi/riscv_asm.h>
+#include <sbi/sbi_domain.h>
#include <sbi/sbi_hartmask.h>
#include <sbi/sbi_platform.h>
#include <sbi/sbi_string.h>
@@ -185,20 +186,77 @@ static u64 generic_tlbr_flush_limit(void)
return SBI_PLATFORM_TLB_RANGE_FLUSH_LIMIT_DEFAULT;
}
+static int generic_system_reset_check(u32 reset_type, u32 reset_reason)
+{
+ if (generic_plat && generic_plat->system_reset_check)
+ return generic_plat->system_reset_check(reset_type,
+ reset_reason,
+ generic_plat_match);
+ return fdt_system_reset_check(reset_type, reset_reason);
+}
+
+static void generic_system_reset(u32 reset_type, u32 reset_reason)
+{
+ if (generic_plat && generic_plat->system_reset) {
+ generic_plat->system_reset(reset_type, reset_reason,
+ generic_plat_match);
+ return;
+ }
+
+ fdt_system_reset(reset_type, reset_reason);
+}
+
+#define EDK2_ROOT_FW_REGION 0
+#define EDK2_FW_REGION 1
+#define EDK2_VARIABLE_REGION 2
+#define EDK2_ALL_REGION 3
+#define EDK2_END_REGION 4
+static struct sbi_domain_memregion root_memregs[EDK2_END_REGION + 1] = { 0 };
+
+struct sbi_domain_memregion *get_mem_regions(void) {
+ /* EDK2 root firmware domain memory region */
+ root_memregs[EDK2_ROOT_FW_REGION].order = log2roundup(FixedPcdGet32(PcdRootFirmwareDomainSize));
+ root_memregs[EDK2_ROOT_FW_REGION].base = FixedPcdGet32(PcdRootFirmwareDomainBaseAddress);
+ root_memregs[EDK2_ROOT_FW_REGION].flags = 0;
+
+ /*EDK2 firmware domain memory region */
+ root_memregs[EDK2_FW_REGION].order = log2roundup(FixedPcdGet32(PcdFirmwareDomainSize));
+ root_memregs[EDK2_FW_REGION].base = FixedPcdGet32(PcdFirmwareDomainBaseAddress);
+ root_memregs[EDK2_FW_REGION].flags = SBI_DOMAIN_MEMREGION_EXECUTABLE | SBI_DOMAIN_MEMREGION_READABLE;
+
+ /*EDK2 firmware domain memory region */
+ root_memregs[EDK2_VARIABLE_REGION].order = log2roundup(FixedPcdGet32(PcdVariableFirmwareRegionSize));
+ root_memregs[EDK2_VARIABLE_REGION].base = FixedPcdGet32(PcdVariableFirmwareRegionBaseAddress);
+ root_memregs[EDK2_VARIABLE_REGION].flags = SBI_DOMAIN_MEMREGION_READABLE | SBI_DOMAIN_MEMREGION_WRITEABLE;
+
+ /* EDK2 domain allow everything memory region */
+ root_memregs[EDK2_ALL_REGION].order = __riscv_xlen;
+ root_memregs[EDK2_ALL_REGION].base = 0;
+ root_memregs[EDK2_ALL_REGION].flags = (SBI_DOMAIN_MEMREGION_READABLE |
+ SBI_DOMAIN_MEMREGION_WRITEABLE |
+ SBI_DOMAIN_MEMREGION_EXECUTABLE);
+
+ /* EDK2 domain memory region end */
+ root_memregs[EDK2_END_REGION].order = 0;
+
+ return root_memregs;
+}
+
const struct sbi_platform_operations platform_ops = {
- .early_init = generic_early_init,
- .final_init = generic_final_init,
- .early_exit = generic_early_exit,
- .final_exit = generic_final_exit,
- .domains_init = generic_domains_init,
- .console_init = fdt_serial_init,
- .irqchip_init = fdt_irqchip_init,
- .irqchip_exit = fdt_irqchip_exit,
- .ipi_init = fdt_ipi_init,
- .ipi_exit = fdt_ipi_exit,
+ .early_init = generic_early_init,
+ .final_init = generic_final_init,
+ .early_exit = generic_early_exit,
+ .final_exit = generic_final_exit,
+ .domains_root_regions = get_mem_regions,
+ .domains_init = generic_domains_init,
+ .console_init = fdt_serial_init,
+ .irqchip_init = fdt_irqchip_init,
+ .irqchip_exit = fdt_irqchip_exit,
+ .ipi_init = fdt_ipi_init,
+ .ipi_exit = fdt_ipi_exit,
.get_tlbr_flush_limit = generic_tlbr_flush_limit,
- .timer_init = fdt_timer_init,
- .timer_exit = fdt_timer_exit,
+ .timer_init = fdt_timer_init,
+ .timer_exit = fdt_timer_exit,
};
#if FixedPcdGet32(PcdBootableHartNumber) == 4
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
index e9f030f352..e88a7b8e80 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
@@ -1,7 +1,7 @@
/** @file
RISC-V SEC phase module.
- Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -336,7 +336,7 @@ FindAndReportEntryPoints (
**/
VOID
-DebutPrintFirmwareContext (
+DebugPrintFirmwareContext (
EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext
)
{
@@ -398,7 +398,7 @@ TemporaryRamMigration (
//
FirmwareContext->PeiServiceTable += (unsigned long)((UINTN)NewStack - (UINTN)OldStack);
DEBUG ((DEBUG_INFO, "%a: OpenSBI Firmware Context is relocated to 0x%x\n", __FUNCTION__, FirmwareContext));
- DebutPrintFirmwareContext ((EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)FirmwareContext);
+ DebugPrintFirmwareContext ((EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)FirmwareContext);
register uintptr_t a0 asm ("a0") = (uintptr_t)((UINTN)NewStack - (UINTN)OldStack);
asm volatile ("add sp, sp, a0"::"r"(a0):);
@@ -496,12 +496,12 @@ RegisterFirmwareSbiExtension (
This function transits to S-mode PEI phase from M-mode SEC phase.
@param[in] BootHartId Hardware thread ID of boot hart.
- @param[in] FuncArg1 Arg1 delivered from previous phase.
+ @param[in] Scratch Pointer to sbi_scratch structure.
**/
VOID EFIAPI PeiCore (
- IN UINTN BootHartId,
- IN UINTN FuncArg1
+ IN UINTN BootHartId,
+ IN struct sbi_scratch *Scratch
)
{
EFI_SEC_PEI_HAND_OFF SecCoreData;
@@ -529,7 +529,7 @@ VOID EFIAPI PeiCore (
//
DEBUG ((DEBUG_INFO, "%a: OpenSBI scratch address for each hart:\n", __FUNCTION__));
for (HartId = 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) {
- SbiGetMscratchHartid (HartId, &ScratchSpace);
+ ScratchSpace = sbi_hartid_to_scratch (HartId);
if(ScratchSpace != NULL) {
DEBUG((DEBUG_INFO, " Hart %d: 0x%x\n", HartId, ScratchSpace));
}
@@ -540,9 +540,8 @@ VOID EFIAPI PeiCore (
// Firmware context residents in stack and will be switched to memory when
// temporary RAM migration.
//
- SbiGetMscratchHartid (BootHartId, &ScratchSpace);
ZeroMem ((VOID *)&FirmwareContext, sizeof (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT));
- ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(ScratchSpace);
+ ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(Scratch);
if (ThisSbiPlatform->opensbi_version > OPENSBI_VERSION) {
DEBUG ((DEBUG_ERROR, "%a: OpenSBI platform table version 0x%x is newer than OpenSBI version 0x%x.\n"
"There maybe be some backward compatable issues.\n",
@@ -562,13 +561,13 @@ VOID EFIAPI PeiCore (
//
// Save Flattened Device tree in firmware context
//
- FirmwareContext.FlattenedDeviceTree = FuncArg1;
+ FirmwareContext.FlattenedDeviceTree = Scratch->next_arg1;
//
// Set firmware context Hart-specific pointer
//
for (HartId = 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) {
- SbiGetMscratchHartid (HartId, &ScratchSpace);
+ ScratchSpace = sbi_hartid_to_scratch (HartId);
if (ScratchSpace != NULL) {
FirmwareContext.HartSpecific[HartId] =
(EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *)((UINT8 *)ScratchSpace - FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE);
@@ -588,6 +587,10 @@ VOID EFIAPI PeiCore (
//
// Transfer the control to the PEI core
//
+ Scratch->next_addr = (UINTN)(*PeiCoreEntryPoint);
+ Scratch->next_mode = PRV_S;
+ DEBUG ((DEBUG_INFO, "%a: Initializing OpenSBI library for booting hart %d\n", __FUNCTION__, BootHartId));
+ sbi_init(Scratch);
(*PeiCoreEntryPoint) (&SecCoreData, (EFI_PEI_PPI_DESCRIPTOR *)&mPrivateDispatchTable);
}
@@ -598,34 +601,19 @@ VOID EFIAPI PeiCore (
To register the SBI extension we stay in M-Mode and then transition here,
rather than before in sbi_init.
- @param[in] ThisHartId Hardware thread ID.
- @param[in] FuncArg1 Arg1 delivered from previous phase.
+ @param[in] ThisHartId Hardware thread ID.
+ @param[in] Scratch Pointer to sbi_scratch structure.
**/
VOID
EFIAPI
LaunchPeiCore (
IN UINTN ThisHartId,
- IN UINTN FuncArg1
+ IN struct sbi_scratch *Scratch
)
{
- UINT32 PeiCoreMode;
-
- DEBUG ((DEBUG_INFO, "%a: Set boot hart done.\n", __FUNCTION__));
- atomic_write (&BootHartDone, (UINT64)TRUE);
RegisterFirmwareSbiExtension ();
-
- PeiCoreMode = FixedPcdGet32 (PcdPeiCorePrivilegeMode);
- if (PeiCoreMode == PRV_S) {
- DEBUG ((DEBUG_INFO, "%a: Switch to S-Mode for PeiCore.\n", __FUNCTION__));
- sbi_hart_switch_mode (ThisHartId, FuncArg1, (UINTN)PeiCore, PRV_S, FALSE);
- } else if (PeiCoreMode == PRV_M) {
- DEBUG ((DEBUG_INFO, "%a: Switch to M-Mode for PeiCore.\n", __FUNCTION__));
- PeiCore (ThisHartId, FuncArg1);
- } else {
- DEBUG ((DEBUG_INFO, "%a: The privilege mode specified in PcdPeiCorePrivilegeMode is not supported.\n", __FUNCTION__));
- while (TRUE);
- }
+ PeiCore (ThisHartId, Scratch);
}
/**
@@ -750,10 +738,7 @@ VOID EFIAPI SecCoreStartUpWithStack(
HartFirmwareContext->HartSwitchMode = RiscVOpenSbiHartSwitchMode;
if (HartId == FixedPcdGet32(PcdBootHartId)) {
- Scratch->next_addr = (UINTN)LaunchPeiCore;
- Scratch->next_mode = PRV_M;
- DEBUG ((DEBUG_INFO, "%a: Initializing OpenSBI library for booting hart %d\n", __FUNCTION__, HartId));
- sbi_init(Scratch);
+ LaunchPeiCore (HartId, Scratch);
}
//
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
index 692985cefb..b3eccf92eb 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020 , Hewlett Packard Enterprise Development LP. All rights reserved.
+ * Copyright (c) 2021 , Hewlett Packard Enterprise Development LP. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause
*
@@ -71,9 +71,8 @@ _scratch_init:
/* Initialize scratch space */
/* Firmware range and size */
- li a4, FixedPcdGet32 (PcdFwStartAddress)
- li a5, FixedPcdGet32 (PcdFwEndAddress)
- sub a5, a5, a4
+ li a4, FixedPcdGet32 (PcdRootFirmwareDomainBaseAddress)
+ li a5, FixedPcdGet32 (PcdRootFirmwareDomainSize)
sd a4, SBI_SCRATCH_FW_START_OFFSET(tp)
sd a5, SBI_SCRATCH_FW_SIZE_OFFSET(tp)
--
2.31.1
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