[edk2-devel] [PATCH v1 1/1] UefiCpuPackage: Add APIs for CPU physical address mask calculation
Yu Pu
yu.pu at intel.com
Thu Jan 13 02:31:52 UTC 2022
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3394
Firmware contains lots of code that deals with page table.These
code need the information of cpu physical address mask which
can be calculated from CPUID result.Today all these code implements
directly calls CPUID and calculates the address mask.
This bugzilla requests to add a new API as below so that all the
duplicated code can be removed.
Cc: Eric Dong <eric.dong at intel.com>
Cc: Ray Ni <ray.ni at intel.com>
Signed-off-by: Yu Pu <yu.pu at intel.com>
---
UefiCpuPkg/CpuDxe/CpuDxe.c | 16 +------
UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c | 47 ++++++++++++++++++++
UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 9 +---
UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 9 +---
UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c | 9 +---
UefiCpuPkg/Include/Library/UefiCpuLib.h | 17 +++++++
6 files changed, 70 insertions(+), 37 deletions(-)
diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.c b/UefiCpuPkg/CpuDxe/CpuDxe.c
index 00f3cb09572c..8aca1bf72b4c 100644
--- a/UefiCpuPkg/CpuDxe/CpuDxe.c
+++ b/UefiCpuPkg/CpuDxe/CpuDxe.c
@@ -503,21 +503,7 @@ InitializeMtrrMask (
VOID
)
{
- UINT32 RegEax;
- UINT8 PhysicalAddressBits;
-
- AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
-
- if (RegEax >= 0x80000008) {
- AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
-
- PhysicalAddressBits = (UINT8)RegEax;
- } else {
- PhysicalAddressBits = 36;
- }
-
- mValidMtrrBitsMask = LShiftU64 (1, PhysicalAddressBits) - 1;
- mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL;
+ GetPhysicalAddressBits(&mValidMtrrBitsMask, &mValidMtrrAddressMask);
}
/**
diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c
index 5d925bc273f8..bb1343f3cd21 100644
--- a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c
+++ b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c
@@ -79,3 +79,50 @@ GetCpuSteppingId (
return (UINT8)Eax.Bits.SteppingId;
}
+
+/**
+ Get the physical address width supported by the processor.
+ @param[out] ValidAddressMask Bitmask with valid address bits set to
+ one; other bits are clear. Optional
+ parameter.
+ @param[out] ValidPageBaseAddressMask Bitmask with valid page base address
+ bits set to one; other bits are clear.
+ Optional parameter.
+ @return The physical address width supported by the processor.
+**/
+UINT8
+EFIAPI
+GetPhysicalAddressBits (
+ OUT UINT64 *ValidAddressMask OPTIONAL,
+ OUT UINT64 *ValidPageBaseAddressMask OPTIONAL
+ )
+{
+ UINT32 MaxExtendedFunction;
+ CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize;
+ UINT64 AddressMask;
+ UINT64 PageBaseAddressMask;
+
+ AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunction, NULL, NULL, NULL);
+ if (MaxExtendedFunction >= CPUID_VIR_PHY_ADDRESS_SIZE) {
+ AsmCpuid (
+ CPUID_VIR_PHY_ADDRESS_SIZE,
+ &VirPhyAddressSize.Uint32,
+ NULL,
+ NULL,
+ NULL
+ );
+ } else {
+ VirPhyAddressSize.Bits.PhysicalAddressBits = 36;
+ }
+
+ AddressMask = LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1;
+ PageBaseAddressMask = AddressMask & ~(UINT64)0xFFF;
+
+ if (ValidAddressMask != NULL) {
+ *ValidAddressMask = AddressMask;
+ }
+ if (ValidPageBaseAddressMask != NULL) {
+ *ValidPageBaseAddressMask = PageBaseAddressMask;
+ }
+ return (UINT8)VirPhyAddressSize.Bits.PhysicalAddressBits;
+}
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
index 4e8f897f5e9c..ec7cd4013132 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
@@ -15,6 +15,7 @@
#include <Library/UefiBootServicesTableLib.h>
#include <Library/SmmServicesTableLib.h>
#include <Library/TpmMeasurementLib.h>
+#include <Library/UefiCpuLib.h>
#include <Register/Intel/Cpuid.h>
#include <Register/Intel/ArchitecturalMsr.h>
#include <Register/Intel/SmramSaveStateMap.h>
@@ -330,13 +331,7 @@ SmmCpuFeaturesInstallSmiHandler (
if (Hob != NULL) {
Psd->PhysicalAddressBits = ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace;
} else {
- AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
- if (RegEax >= 0x80000008) {
- AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
- Psd->PhysicalAddressBits = (UINT8)RegEax;
- } else {
- Psd->PhysicalAddressBits = 36;
- }
+ Psd->PhysicalAddressBits = GetPhysicalAddressBits (NULL, NULL);
}
if (!mStmConfigurationTableInitialized) {
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
index 538394f23910..de1385a86948 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
@@ -194,7 +194,6 @@ CalculateMaximumSupportAddress (
VOID
)
{
- UINT32 RegEax;
UINT8 PhysicalAddressBits;
VOID *Hob;
@@ -205,13 +204,7 @@ CalculateMaximumSupportAddress (
if (Hob != NULL) {
PhysicalAddressBits = ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace;
} else {
- AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
- if (RegEax >= 0x80000008) {
- AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
- PhysicalAddressBits = (UINT8)RegEax;
- } else {
- PhysicalAddressBits = 36;
- }
+ PhysicalAddressBits = GetPhysicalAddressBits (NULL, NULL);
}
return PhysicalAddressBits;
diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
index 8419a4e32acb..1017f0316093 100644
--- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
+++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
@@ -42,6 +42,7 @@
#include <Library/HobLib.h>
#include <Library/LockBoxLib.h>
#include <IndustryStandard/Acpi.h>
+#include <Library/UefiCpuLib.h>
/**
This macro aligns the address of a variable with auto storage
@@ -646,13 +647,7 @@ RestoreS3PageTables (
if (Hob != NULL) {
PhysicalAddressBits = ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace;
} else {
- AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
- if (RegEax >= 0x80000008) {
- AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
- PhysicalAddressBits = (UINT8)RegEax;
- } else {
- PhysicalAddressBits = 36;
- }
+ PhysicalAddressBits = GetPhysicalAddressBits (NULL, NULL);
}
//
diff --git a/UefiCpuPkg/Include/Library/UefiCpuLib.h b/UefiCpuPkg/Include/Library/UefiCpuLib.h
index 0ff4a35774c1..dabed95ab38a 100644
--- a/UefiCpuPkg/Include/Library/UefiCpuLib.h
+++ b/UefiCpuPkg/Include/Library/UefiCpuLib.h
@@ -62,4 +62,21 @@ GetCpuSteppingId (
VOID
);
+/**
+ Get the physical address width supported by the processor.
+ @param[out] ValidAddressMask Bitmask with valid address bits set to
+ one; other bits are clear. Optional
+ parameter.
+ @param[out] ValidPageBaseAddressMask Bitmask with valid page base address
+ bits set to one; other bits are clear.
+ Optional parameter.
+ @return The physical address width supported by the processor.
+**/
+UINT8
+EFIAPI
+GetPhysicalAddressBits (
+ OUT UINT64 *ValidAddressMask OPTIONAL,
+ OUT UINT64 *ValidPageBaseAddressMask OPTIONAL
+ );
+
#endif
--
2.30.0.windows.2
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