[edk2-devel] [PATCH v5 3/4] Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support

[Sami Mujawar]

Hi Khasim,

Thank you for this patch.

These changes look good to me.

Reviewed-by: Sami Mujawar <sami.mujawar at arm.com>

Regards,

Sami Mujawar


On 22/12/2021 01:14 AM, Khasim Mohammed via groups.io wrote:
> This patch enables CCIX root complex support by updating
> the root complex node info in PciHostBridge library.
>
> Signed-off-by: Khasim Syed Mohammed <khasim.mohammed at arm.com>
> ---
>   .../PciHostBridgeLib/PciHostBridgeLib.c       | 71 +++++++++++++++++--
>   .../PciHostBridgeLib/PciHostBridgeLib.inf     | 11 ++-
>   2 files changed, 76 insertions(+), 6 deletions(-)
>
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
> index 9332939f63..c3a14a6c17 100644
> --- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
> @@ -1,7 +1,7 @@
>   /** @file
>   *  PCI Host Bridge Library instance for ARM Neoverse N1 platform
>   *
> -*  Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.
> +*  Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.<BR>
>   *
>   *  SPDX-License-Identifier: BSD-2-Clause-Patent
>   *
> @@ -16,6 +16,8 @@
>   #include <Protocol/PciHostBridgeResourceAllocation.h>
>   #include <Protocol/PciRootBridgeIo.h>
>   
> +#define ROOT_COMPLEX_NUM 2
> +
>   GLOBAL_REMOVE_IF_UNREFERENCED
>   STATIC CHAR16 CONST * CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
>     L"Mem", L"I/O", L"Bus"
> @@ -28,7 +30,7 @@ typedef struct {
>   } EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
>   #pragma pack ()
>   
> -STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
> +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[ROOT_COMPLEX_NUM] = {
>     // PCIe
>     {
>       {
> @@ -51,10 +53,33 @@ STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
>           0
>         }
>       }
> -  }
> +  },
> +  //CCIX
> +  {
> +    {
> +      {
> +        ACPI_DEVICE_PATH,
> +        ACPI_DP,
> +        {
> +          (UINT8)sizeof (ACPI_HID_DEVICE_PATH),
> +          (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
> +        }
> +      },
> +      EISA_PNP_ID(0x0A09), // CCIX
> +      0
> +    },
> +    {
> +      END_DEVICE_PATH_TYPE,
> +      END_ENTIRE_DEVICE_PATH_SUBTYPE,
> +      {
> +        END_DEVICE_PATH_LENGTH,
> +        0
> +      }
> +    }
> +  },
>   };
>   
> -STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = {
> +STATIC PCI_ROOT_BRIDGE mPciRootBridge[ROOT_COMPLEX_NUM] = {
>     {
>       0,                                              // Segment
>       0,                                              // Supports
> @@ -90,7 +115,43 @@ STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = {
>         0
>       },
>       (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0]
> -  }
> +  },
> +  {
> +    1,                                              // Segment
> +    0,                                              // Supports
> +    0,                                              // Attributes
> +    TRUE,                                           // DmaAbove4G
> +    FALSE,                                          // NoExtendedConfigSpace
> +    FALSE,                                          // ResourceAssigned
> +    EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM |          // AllocationAttributes
> +    EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
> +    {
> +      // Bus
> +      FixedPcdGet32 (PcdCcixBusMin),
> +      FixedPcdGet32 (PcdCcixBusMax)
> +    }, {
> +      // Io
> +      FixedPcdGet64 (PcdCcixIoBase),
> +      FixedPcdGet64 (PcdCcixIoBase) + FixedPcdGet64 (PcdCcixIoSize) - 1
> +    }, {
> +      // Mem
> +      FixedPcdGet32 (PcdCcixMmio32Base),
> +      FixedPcdGet32 (PcdCcixMmio32Base) + FixedPcdGet32 (PcdCcixMmio32Size) - 1
> +    }, {
> +      // MemAbove4G
> +      FixedPcdGet64 (PcdCcixMmio64Base),
> +      FixedPcdGet64 (PcdCcixMmio64Base) + FixedPcdGet64 (PcdCcixMmio64Size) - 1
> +    }, {
> +      // PMem
> +      MAX_UINT64,
> +      0
> +    }, {
> +      // PMemAbove4G
> +      MAX_UINT64,
> +      0
> +    },
> +    (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1]
> +  },
>   };
>   
>   /**
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> index 3ff1c592f2..3356c3ad35 100644
> --- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> @@ -1,7 +1,7 @@
>   ## @file
>   #  PCI Host Bridge Library instance for ARM Neoverse N1 platform.
>   #
> -#  Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.
> +#  Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.<BR>
>   #
>   #  SPDX-License-Identifier: BSD-2-Clause-Patent
>   #
> @@ -42,6 +42,15 @@
>     gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base
>     gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size
>   
> +  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin
> +  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax
> +  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase
> +  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize
> +  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base
> +  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size
> +  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base
> +  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size
> +
>   [Protocols]
>     gEfiCpuIo2ProtocolGuid
>   



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