[edk2-devel] [edk2-platforms] [PATCH V1 0/4] Enable CPU pwr mgmt in FADT for Intel client boards
Nate DeSimone
nathaniel.l.desimone at intel.com
Mon Jun 6 22:50:26 UTC 2022
This patch series sets the DUTY_OFFSET and DUTY_WIDTH fields in the ACPI FADT
to 1 and 3 respectively. This will enable OS power management to set the CPU
clock speed in the P_CNT register on these platforms.
Cc: Chasel Chiu <chasel.chiu at intel.com>
Cc: Ankit Sinha <ankit.sinha at intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty at intel.com>
Cc: Michael Kubacki <michael.kubacki at microsoft.com>
Cc: Heng Luo <heng.luo at intel.com>
Cc: Deepika Kethi Reddy <deepika.kethi.reddy at intel.com>
Cc: Kathappan Esakkithevar <kathappan.esakkithevar at intel.com>
Cc: Benjamin Doron <benjamin.doron00 at gmail.com>
Cc: Jeremy Soller <jeremy at system76.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone at intel.com>
Nate DeSimone (4):
KabylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT
WhiskeylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT
CometlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT
TigerlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT
.../CometlakeURvp/OpenBoardPkgPcd.dsc | 9 +++-
.../AspireVn7Dash572G/OpenBoardPkgPcd.dsc | 9 +++-
.../GalagoPro3/OpenBoardPkgPcd.dsc | 52 +++++++++++++++++--
.../KabylakeRvp3/OpenBoardPkgPcd.dsc | 11 +++-
.../TigerlakeURvp/OpenBoardPkgPcd.dsc | 10 +++-
.../UpXtreme/OpenBoardPkgPcd.dsc | 9 +++-
.../WhiskeylakeURvp/OpenBoardPkgPcd.dsc | 9 +++-
7 files changed, 98 insertions(+), 11 deletions(-)
--
2.27.0.windows.1
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