[edk2-devel] [edk2-platforms] [PATCH V2 4/4] TigerlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Nate DeSimone]

Set the location of the DUTY_CYCLE field in the P_CNT register
and indicate the width of the clock duty cycle to OS power management

Cc: Sai Chaganty <rangasai.v.chaganty at intel.com>
Cc: Michael Kubacki <michael.kubacki at microsoft.com>
Cc: Heng Luo <heng.luo at intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone at intel.com>
---
 .../TigerlakeURvp/OpenBoardPkgPcd.dsc                  | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
index ebbbc7b9f9..aba3c8d6d0 100644
--- a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  PCD configuration build description file for the TigerlakeURvp board.
 #
-#  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+#  Copyright (c) 2021 - 2022, Intel Corporation. All rights reserved.<BR>
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 ##
@@ -118,6 +118,14 @@
   gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
 #!endif
   gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x40000
+
+  #
+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
 [PcdsFeatureFlag.common]
   ######################################
   # Edk2 Configuration
-- 
2.27.0.windows.1



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