[edk2-devel] [edk2-platforms][PATCH V3 3/9] Platform/Sgi: Update ACPI version to v6.4 for RD-N1-Edge platform
Pranav Madhu
pranav.madhu at arm.com
Thu Jun 9 16:56:42 UTC 2022
Update the RD-N1-Edge platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu <pranav.madhu at arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc | 105 ++++++++++---------
Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc | 108 ++++++++++++--------
2 files changed, 121 insertions(+), 92 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc
index 05eb78c5616a..df2576e1d9b7 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc
@@ -1,18 +1,24 @@
/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2018-2020, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-N1-Edge
+ platform is included in this table.
+
+ Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
-#include <IndustryStandard/Acpi.h>
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))
@@ -21,75 +27,76 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicIts;
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE GicInterfaces[CORE_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTURE GicIts;
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
- // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
+ // Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
- // Efficiency)
+ // Efficiency,
+ // SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
- // (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ // (see note in 5.2.12.14 GICC Structure of ACPI v6.4).
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-1
- 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-1
+ 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-2
- 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-2
+ 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-3
- 0, 3, GET_MPID(0x0, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-3
+ 0, 3, GET_MPID(0x0, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-4
- 0, 4, GET_MPID(0x100, 0x00), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-4
+ 0, 4, GET_MPID(0x100, 0x00), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-5
- 0, 5, GET_MPID(0x100, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-5
+ 0, 5, GET_MPID(0x100, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-6
- 0, 6, GET_MPID(0x100, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-6
+ 0, 6, GET_MPID(0x100, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-7
- 0, 7, GET_MPID(0x100, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-7
+ 0, 7, GET_MPID(0x100, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */)
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0)
},
// GIC Distributor Entry
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
0, 3),
// GIC Redistributor
- EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
+ EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
SIZE_1MB),
// GIC ITS
- EFI_ACPI_6_2_GIC_ITS_INIT(0, 0x30040000)
+ EFI_ACPI_6_4_GIC_ITS_INIT(0, 0x30040000)
};
//
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc
index 923ee9014970..0d9dcb0ad6a2 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc
@@ -1,28 +1,43 @@
/** @file
-* Processor Properties Topology Table (PPTT) for RD-N1-Edge single-chip platform
-*
-* This file describes the topological structure of the processor block on the
-* RD-N1-Edge single-chip platform in the form as defined by ACPI PPTT table. The
-* RD-N1-Edge platform includes two clusters with four single-thread CPUS. Each
-* of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2
-* cache. Each cluster includes a 2MB L3 cache. The platform also includes a
-* system level cache of 8MB.
-*
-* Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-* @par Specification Reference:
-* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+ Processor Properties Topology Table (PPTT) for RD-N1-Edge single-chip platform
+
+ This file describes the topological structure of the processor block on the
+ RD-N1-Edge single-chip platform in the form as defined by ACPI PPTT table. The
+ RD-N1-Edge platform includes two clusters with four single-thread CPUS. Each
+ of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2
+ cache. Each cluster includes a 2MB L3 cache. The platform also includes a
+ system level cache of 8MB.
+
+ Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.29, Processor Properties Topology Table
**/
-#include <IndustryStandard/Acpi.h>
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
-
-#include "SgiPlatform.h"
#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
+
+/** Define helper macro to calculate a unique cache ID for a CPU cache
+
+ @param [in] CacheType Identifier for cache type.
+ @param [in] ClueterId Cluster instance number.
+ @param [in] CpuId CPU instance number.
+**/
+#define RDN1EDGE_PPTT_CORE_CACHE_ID(CacheType, ClusterId, CpuId) \
+ ((CLUSTER_COUNT * CORE_COUNT * CacheType) + ((ClusterId << 2) | CpuId) + 1)
+
+/** Define helper macro to calculate a unique cache ID for a cluster cache
+
+ @param [in] CacheType Identifier for cache type.
+ @param [in] ClueterId Cluster instance number.
+**/
+#define RDN1EDGE_PPTT_CLUSTER_CACHE_ID(CacheType, ClusterId) \
+ ((CLUSTER_COUNT * CORE_COUNT * CacheType) + ClusterId + 1)
/** Define helper macro for populating processor core information.
@@ -33,10 +48,10 @@
#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) \
{ \
/* Parameters for CPU Core */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ \
PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId]), /* Parent */ \
((PackageId << 3) | (ClusterId << 2) | CpuId), /* ACPI Id */ \
2 /* Num of private resource */ \
@@ -44,47 +59,53 @@
\
/* Offsets of the private resources */ \
{ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].DCache), \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].ICache) \
}, \
\
/* L1 data cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
/* Next level of cache */ \
SIZE_64KB, /* Size */ \
256, /* Num of sets */ \
4, /* Associativity */ \
PPTT_DATA_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RDN1EDGE_PPTT_CORE_CACHE_ID(L1DataCache, ClusterId, CpuId) \
+ /* Cache id */ \
), \
\
/* L1 instruction cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
/* Next level of cache */ \
SIZE_64KB, /* Size */ \
256, /* Num of sets */ \
4, /* Associativity */ \
PPTT_INST_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RDN1EDGE_PPTT_CORE_CACHE_ID(L1InstructionCache, ClusterId, CpuId) \
+ /* Cache id */ \
), \
\
/* L2 cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
0, /* Next level of cache */ \
SIZE_512KB, /* Size */ \
1024, /* Num of sets */ \
8, /* Associativity */ \
PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RDN1EDGE_PPTT_CORE_CACHE_ID(L2Cache, ClusterId, CpuId) \
+ /* Cache id */ \
), \
}
@@ -96,28 +117,29 @@
#define PPTT_CLUSTER_INIT(PackageId, ClusterId) \
{ \
/* Parameters for Cluster */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
OFFSET_OF (RD_PPTT_CLUSTER, L3Cache), /* Length */ \
PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package), /* Parent */ \
((PackageId << 1) | ClusterId), /* ACPI Id */ \
1 /* Num of private resource */ \
), \
\
/* Offsets of the private resources */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].L3Cache), \
\
/* L3 cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
0, /* Next level of cache */ \
SIZE_2MB, /* Size */ \
2048, /* Num of sets */ \
16, /* Associativity */ \
PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RDN1EDGE_PPTT_CLUSTER_CACHE_ID(L3Cache, ClusterId) /* Cache id */ \
), \
\
/* Initialize child cores */ \
@@ -131,7 +153,7 @@
#pragma pack(1)
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Package;
RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT];
} RDN1EDGE_PPTT_PACKAGE ;
@@ -139,22 +161,22 @@ typedef struct {
* Processor Properties Topology Table
*/
typedef struct {
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
RDN1EDGE_PPTT_PACKAGE Package;
-} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+STATIC EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
)
},
{
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT (
OFFSET_OF (RDN1EDGE_PPTT_PACKAGE , Cluster[0]),
PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 0),
--
2.25.1
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