[edk2-devel] [PATCH 03/14] OvmfPkg/PlatformPei: Move global variables to PlatformInfoHob
Min Xu
min.m.xu at intel.com
Tue Mar 8 02:36:04 UTC 2022
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863
The intention of PlatformInitLib is to extract the common function used
in OvmfPkg/PlatformPei. This lib will be used not only in PEI phase but
also in SEC phase. SEC phase cannot use global variables between
different functions. So PlatformInfoHob is created to hold the
informations shared between functions. For example, HostBridgeDevId
corespond to mHostBridgeDevId in PlatformPei.
In this patch we will first move below global variables to
PlatformInfoHob.
- mBootMode
- mS3Supported
- mPhysMemAddressWidth
- mMaxCpuCount
- mHostBridgeDevId
- mQ35SmramAtDefaultSmbase
- mQemuUc32Base
- mS3AcpiReservedMemorySize
- mS3AcpiReservedMemoryBase
PlatformInfoHob also holds other information, for example,
PciIoBase / PciIoSize. This is because in SEC phase, PcdSetxxx
doesn't work. So we will restruct the functions which set PCDs
into two, one for PlatformInfoLib, one for PlatformPei.
So in this patch we first move global variables and PCDs to
PlatformInfoHob. All the changes are in OvmfPkg/PlatformPei.
Cc: Ard Biesheuvel <ardb+tianocore at kernel.org>
Cc: Jordan Justen <jordan.l.justen at intel.com>
Cc: Brijesh Singh <brijesh.singh at amd.com>
Cc: Erdem Aktas <erdemaktas at google.com>
Cc: James Bottomley <jejb at linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao at intel.com>
Cc: Tom Lendacky <thomas.lendacky at amd.com>
Cc: Gerd Hoffmann <kraxel at redhat.com>
Cc: Sebastien Boeuf <sebastien.boeuf at intel.com>
Signed-off-by: Min Xu <min.m.xu at intel.com>
---
OvmfPkg/PlatformPei/AmdSev.c | 10 +-
OvmfPkg/PlatformPei/Fv.c | 6 +-
OvmfPkg/PlatformPei/MemDetect.c | 210 +++++++++++++++---------------
OvmfPkg/PlatformPei/MemTypeInfo.c | 4 +-
OvmfPkg/PlatformPei/Platform.c | 109 ++++++++--------
OvmfPkg/PlatformPei/Platform.h | 43 +++---
6 files changed, 201 insertions(+), 181 deletions(-)
diff --git a/OvmfPkg/PlatformPei/AmdSev.c b/OvmfPkg/PlatformPei/AmdSev.c
index fb7e21ec140f..c180383b42b0 100644
--- a/OvmfPkg/PlatformPei/AmdSev.c
+++ b/OvmfPkg/PlatformPei/AmdSev.c
@@ -24,6 +24,8 @@
#include "Platform.h"
+extern EFI_HOB_PLATFORM_INFO mPlatformInfoHob;
+
STATIC
UINT64
GetHypervisorFeature (
@@ -228,7 +230,7 @@ AmdSevEsInitialize (
// Since the pages must survive across the UEFI to OS transition
// make them reserved.
//
- GhcbPageCount = mMaxCpuCount * 2;
+ GhcbPageCount = mPlatformInfoHob.PcdCpuMaxLogicalProcessorNumber * 2;
GhcbBase = AllocateReservedPages (GhcbPageCount);
ASSERT (GhcbBase != NULL);
@@ -266,7 +268,7 @@ AmdSevEsInitialize (
// Allocate #VC recursion backup pages. The number of backup pages needed is
// one less than the maximum VC count.
//
- GhcbBackupPageCount = mMaxCpuCount * (VMGEXIT_MAXIMUM_VC_COUNT - 1);
+ GhcbBackupPageCount = mPlatformInfoHob.PcdCpuMaxLogicalProcessorNumber * (VMGEXIT_MAXIMUM_VC_COUNT - 1);
GhcbBackupBase = AllocatePages (GhcbBackupPageCount);
ASSERT (GhcbBackupBase != NULL);
@@ -367,7 +369,7 @@ AmdSevInitialize (
// until after re-encryption, in order to prevent an information leak to the
// hypervisor.
//
- if (FeaturePcdGet (PcdSmmSmramRequire) && (mBootMode != BOOT_ON_S3_RESUME)) {
+ if (mPlatformInfoHob.SmmSmramRequire && (mPlatformInfoHob.BootMode != BOOT_ON_S3_RESUME)) {
RETURN_STATUS LocateMapStatus;
UINTN MapPagesBase;
UINTN MapPagesCount;
@@ -378,7 +380,7 @@ AmdSevInitialize (
);
ASSERT_RETURN_ERROR (LocateMapStatus);
- if (mQ35SmramAtDefaultSmbase) {
+ if (mPlatformInfoHob.Q35SmramAtDefaultSmbase) {
//
// The initial SMRAM Save State Map has been covered as part of a larger
// reserved memory allocation in InitializeRamRegions().
diff --git a/OvmfPkg/PlatformPei/Fv.c b/OvmfPkg/PlatformPei/Fv.c
index 8cd8cacc5913..b9bf1a1d8b01 100644
--- a/OvmfPkg/PlatformPei/Fv.c
+++ b/OvmfPkg/PlatformPei/Fv.c
@@ -13,6 +13,8 @@
#include <Library/PeiServicesLib.h>
#include <Library/PcdLib.h>
+extern EFI_HOB_PLATFORM_INFO mPlatformInfoHob;
+
/**
Publish PEI & DXE (Decompressed) Memory based FVs to let PEI
and DXE know about them.
@@ -37,7 +39,7 @@ PeiFvInitialization (
BuildMemoryAllocationHob (
PcdGet32 (PcdOvmfPeiMemFvBase),
PcdGet32 (PcdOvmfPeiMemFvSize),
- mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData
+ mPlatformInfoHob.S3Supported ? EfiACPIMemoryNVS : EfiBootServicesData
);
//
@@ -45,7 +47,7 @@ PeiFvInitialization (
//
BuildFvHob (PcdGet32 (PcdOvmfDxeMemFvBase), PcdGet32 (PcdOvmfDxeMemFvSize));
- SecureS3Needed = mS3Supported && FeaturePcdGet (PcdSmmSmramRequire);
+ SecureS3Needed = mPlatformInfoHob.S3Supported && mPlatformInfoHob.SmmSmramRequire;
//
// Create a memory allocation HOB for the DXE FV.
diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c
index e5e105f377dd..981a9ff28685 100644
--- a/OvmfPkg/PlatformPei/MemDetect.c
+++ b/OvmfPkg/PlatformPei/MemDetect.c
@@ -37,20 +37,10 @@ Module Name:
#include <Library/MtrrLib.h>
#include <Library/QemuFwCfgLib.h>
#include <Library/QemuFwCfgSimpleParserLib.h>
-#include <Library/PlatformInitLib.h>
#include "Platform.h"
-UINT8 mPhysMemAddressWidth;
-
-STATIC UINT32 mS3AcpiReservedMemoryBase;
-STATIC UINT32 mS3AcpiReservedMemorySize;
-
-STATIC UINT16 mQ35TsegMbytes;
-
-BOOLEAN mQ35SmramAtDefaultSmbase;
-
-UINT32 mQemuUc32Base;
+extern EFI_HOB_PLATFORM_INFO mPlatformInfoHob;
VOID
Q35TsegMbytesInitialization (
@@ -60,7 +50,7 @@ Q35TsegMbytesInitialization (
UINT16 ExtendedTsegMbytes;
RETURN_STATUS PcdStatus;
- ASSERT (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);
+ ASSERT (mPlatformInfoHob.HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);
//
// Check if QEMU offers an extended TSEG.
@@ -81,7 +71,7 @@ Q35TsegMbytesInitialization (
PciWrite16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB), MCH_EXT_TSEG_MB_QUERY);
ExtendedTsegMbytes = PciRead16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB));
if (ExtendedTsegMbytes == MCH_EXT_TSEG_MB_QUERY) {
- mQ35TsegMbytes = PcdGet16 (PcdQ35TsegMbytes);
+ mPlatformInfoHob.Q35TsegMbytes = PcdGet16 (PcdQ35TsegMbytes);
return;
}
@@ -93,7 +83,7 @@ Q35TsegMbytesInitialization (
));
PcdStatus = PcdSet16S (PcdQ35TsegMbytes, ExtendedTsegMbytes);
ASSERT_RETURN_ERROR (PcdStatus);
- mQ35TsegMbytes = ExtendedTsegMbytes;
+ mPlatformInfoHob.Q35TsegMbytes = ExtendedTsegMbytes;
}
VOID
@@ -103,9 +93,9 @@ Q35SmramAtDefaultSmbaseInitialization (
{
RETURN_STATUS PcdStatus;
- ASSERT (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);
+ ASSERT (mPlatformInfoHob.HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);
- mQ35SmramAtDefaultSmbase = FALSE;
+ mPlatformInfoHob.Q35SmramAtDefaultSmbase = FALSE;
if (FeaturePcdGet (PcdCsmEnable)) {
DEBUG ((
DEBUG_INFO,
@@ -118,37 +108,36 @@ Q35SmramAtDefaultSmbaseInitialization (
CtlReg = DRAMC_REGISTER_Q35 (MCH_DEFAULT_SMBASE_CTL);
PciWrite8 (CtlReg, MCH_DEFAULT_SMBASE_QUERY);
- CtlRegVal = PciRead8 (CtlReg);
- mQ35SmramAtDefaultSmbase = (BOOLEAN)(CtlRegVal ==
- MCH_DEFAULT_SMBASE_IN_RAM);
+ CtlRegVal = PciRead8 (CtlReg);
+ mPlatformInfoHob.Q35SmramAtDefaultSmbase = (BOOLEAN)(CtlRegVal ==
+ MCH_DEFAULT_SMBASE_IN_RAM);
DEBUG ((
DEBUG_INFO,
"%a: SMRAM at default SMBASE %a\n",
__FUNCTION__,
- mQ35SmramAtDefaultSmbase ? "found" : "not found"
+ mPlatformInfoHob.Q35SmramAtDefaultSmbase ? "found" : "not found"
));
}
PcdStatus = PcdSetBoolS (
PcdQ35SmramAtDefaultSmbase,
- mQ35SmramAtDefaultSmbase
+ mPlatformInfoHob.Q35SmramAtDefaultSmbase
);
ASSERT_RETURN_ERROR (PcdStatus);
}
VOID
QemuUc32BaseInitialization (
- VOID
+ IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
)
{
UINT32 LowerMemorySize;
- UINT32 Uc32Size;
- if (mHostBridgeDevId == 0xffff /* microvm */) {
+ if (PlatformInfoHob->HostBridgeDevId == 0xffff /* microvm */) {
return;
}
- if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
+ if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
//
// On q35, the 32-bit area that we'll mark as UC, through variable MTRRs,
// starts at PcdPciExpressBaseAddress. The platform DSC is responsible for
@@ -157,40 +146,40 @@ QemuUc32BaseInitialization (
// variable MTRRs (preferably 1 or 2).
//
ASSERT (FixedPcdGet64 (PcdPciExpressBaseAddress) <= MAX_UINT32);
- mQemuUc32Base = (UINT32)FixedPcdGet64 (PcdPciExpressBaseAddress);
+ PlatformInfoHob->Uc32Base = (UINT32)FixedPcdGet64 (PcdPciExpressBaseAddress);
return;
}
- if (mHostBridgeDevId == CLOUDHV_DEVICE_ID) {
- Uc32Size = CLOUDHV_MMIO_HOLE_SIZE;
- mQemuUc32Base = CLOUDHV_MMIO_HOLE_ADDRESS;
+ if (PlatformInfoHob->HostBridgeDevId == CLOUDHV_DEVICE_ID) {
+ PlatformInfoHob->Uc32Size = CLOUDHV_MMIO_HOLE_SIZE;
+ PlatformInfoHob->Uc32Base = CLOUDHV_MMIO_HOLE_ADDRESS;
return;
}
- ASSERT (mHostBridgeDevId == INTEL_82441_DEVICE_ID);
+ ASSERT (PlatformInfoHob->HostBridgeDevId == INTEL_82441_DEVICE_ID);
//
// On i440fx, start with the [LowerMemorySize, 4GB) range. Make sure one
// variable MTRR suffices by truncating the size to a whole power of two,
// while keeping the end affixed to 4GB. This will round the base up.
//
- LowerMemorySize = GetSystemMemorySizeBelow4gb ();
- Uc32Size = GetPowerOfTwo32 ((UINT32)(SIZE_4GB - LowerMemorySize));
- mQemuUc32Base = (UINT32)(SIZE_4GB - Uc32Size);
+ LowerMemorySize = GetSystemMemorySizeBelow4gb (PlatformInfoHob);
+ PlatformInfoHob->Uc32Size = GetPowerOfTwo32 ((UINT32)(SIZE_4GB - LowerMemorySize));
+ PlatformInfoHob->Uc32Base = (UINT32)(SIZE_4GB - PlatformInfoHob->Uc32Size);
//
// Assuming that LowerMemorySize is at least 1 byte, Uc32Size is at most 2GB.
// Therefore mQemuUc32Base is at least 2GB.
//
- ASSERT (mQemuUc32Base >= BASE_2GB);
+ ASSERT (PlatformInfoHob->Uc32Base >= BASE_2GB);
- if (mQemuUc32Base != LowerMemorySize) {
+ if (PlatformInfoHob->Uc32Base != LowerMemorySize) {
DEBUG ((
DEBUG_VERBOSE,
"%a: rounded UC32 base from 0x%x up to 0x%x, for "
"an UC32 size of 0x%x\n",
__FUNCTION__,
LowerMemorySize,
- mQemuUc32Base,
- Uc32Size
+ PlatformInfoHob->Uc32Base,
+ PlatformInfoHob->Uc32Size
));
}
}
@@ -385,7 +374,7 @@ GetHighestSystemMemoryAddressFromPvhMemmap (
UINT32
GetSystemMemorySizeBelow4gb (
- VOID
+ IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob
)
{
EFI_STATUS Status;
@@ -393,7 +382,7 @@ GetSystemMemorySizeBelow4gb (
UINT8 Cmos0x34;
UINT8 Cmos0x35;
- if (mHostBridgeDevId == CLOUDHV_DEVICE_ID) {
+ if (PlatformInfoHob->HostBridgeDevId == CLOUDHV_DEVICE_ID) {
// Get the information from PVH memmap
return (UINT32)GetHighestSystemMemoryAddressFromPvhMemmap (TRUE);
}
@@ -448,11 +437,10 @@ GetSystemMemorySizeAbove4gb (
STATIC
UINT64
GetFirstNonAddress (
- VOID
+ IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
)
{
UINT64 FirstNonAddress;
- UINT64 Pci64Base, Pci64Size;
UINT32 FwCfgPciMmio64Mb;
EFI_STATUS Status;
FIRMWARE_CONFIG_ITEM FwCfgItem;
@@ -493,7 +481,7 @@ GetFirstNonAddress (
// Otherwise, in order to calculate the highest address plus one, we must
// consider the 64-bit PCI host aperture too. Fetch the default size.
//
- Pci64Size = PcdGet64 (PcdPciMmio64Size);
+ PlatformInfoHob->PcdPciMmio64Size = PcdGet64 (PcdPciMmio64Size);
//
// See if the user specified the number of megabytes for the 64-bit PCI host
@@ -513,7 +501,7 @@ GetFirstNonAddress (
break;
case EFI_SUCCESS:
if (FwCfgPciMmio64Mb <= 0x1000000) {
- Pci64Size = LShiftU64 (FwCfgPciMmio64Mb, 20);
+ PlatformInfoHob->PcdPciMmio64Size = LShiftU64 (FwCfgPciMmio64Mb, 20);
break;
}
@@ -529,8 +517,8 @@ GetFirstNonAddress (
break;
}
- if (Pci64Size == 0) {
- if (mBootMode != BOOT_ON_S3_RESUME) {
+ if (PlatformInfoHob->PcdPciMmio64Size == 0) {
+ if (PlatformInfoHob->BootMode != BOOT_ON_S3_RESUME) {
DEBUG ((
DEBUG_INFO,
"%a: disabling 64-bit PCI host aperture\n",
@@ -577,8 +565,8 @@ GetFirstNonAddress (
// SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB, so
// that the host can map it with 1GB hugepages. Follow suit.
//
- Pci64Base = ALIGN_VALUE (FirstNonAddress, (UINT64)SIZE_1GB);
- Pci64Size = ALIGN_VALUE (Pci64Size, (UINT64)SIZE_1GB);
+ PlatformInfoHob->PcdPciMmio64Base = ALIGN_VALUE (FirstNonAddress, (UINT64)SIZE_1GB);
+ PlatformInfoHob->PcdPciMmio64Size = ALIGN_VALUE (PlatformInfoHob->PcdPciMmio64Size, (UINT64)SIZE_1GB);
//
// The 64-bit PCI host aperture should also be "naturally" aligned. The
@@ -586,32 +574,32 @@ GetFirstNonAddress (
// next smaller or equal power of two. That is, align the aperture by the
// largest BAR size that can fit into it.
//
- Pci64Base = ALIGN_VALUE (Pci64Base, GetPowerOfTwo64 (Pci64Size));
+ PlatformInfoHob->PcdPciMmio64Base = ALIGN_VALUE (PlatformInfoHob->PcdPciMmio64Base, GetPowerOfTwo64 (PlatformInfoHob->PcdPciMmio64Size));
- if (mBootMode != BOOT_ON_S3_RESUME) {
+ if (PlatformInfoHob->BootMode != BOOT_ON_S3_RESUME) {
//
// The core PciHostBridgeDxe driver will automatically add this range to
// the GCD memory space map through our PciHostBridgeLib instance; here we
// only need to set the PCDs.
//
- PcdStatus = PcdSet64S (PcdPciMmio64Base, Pci64Base);
+ PcdStatus = PcdSet64S (PcdPciMmio64Base, PlatformInfoHob->PcdPciMmio64Base);
ASSERT_RETURN_ERROR (PcdStatus);
- PcdStatus = PcdSet64S (PcdPciMmio64Size, Pci64Size);
+ PcdStatus = PcdSet64S (PcdPciMmio64Size, PlatformInfoHob->PcdPciMmio64Size);
ASSERT_RETURN_ERROR (PcdStatus);
DEBUG ((
DEBUG_INFO,
"%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",
__FUNCTION__,
- Pci64Base,
- Pci64Size
+ PlatformInfoHob->PcdPciMmio64Base,
+ PlatformInfoHob->PcdPciMmio64Size
));
}
//
// The useful address space ends with the 64-bit PCI host aperture.
//
- FirstNonAddress = Pci64Base + Pci64Size;
+ FirstNonAddress = PlatformInfoHob->PcdPciMmio64Base + PlatformInfoHob->PcdPciMmio64Size;
return FirstNonAddress;
}
@@ -620,10 +608,11 @@ GetFirstNonAddress (
**/
VOID
AddressWidthInitialization (
- VOID
+ IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
)
{
UINT64 FirstNonAddress;
+ UINT8 PhysMemAddressWidth;
//
// As guest-physical memory size grows, the permanent PEI RAM requirements
@@ -631,15 +620,15 @@ AddressWidthInitialization (
// The DXL IPL keys off of the physical address bits advertized in the CPU
// HOB. To conserve memory, we calculate the minimum address width here.
//
- FirstNonAddress = GetFirstNonAddress ();
- mPhysMemAddressWidth = (UINT8)HighBitSet64 (FirstNonAddress);
+ FirstNonAddress = GetFirstNonAddress (PlatformInfoHob);
+ PhysMemAddressWidth = (UINT8)HighBitSet64 (FirstNonAddress);
//
// If FirstNonAddress is not an integral power of two, then we need an
// additional bit.
//
if ((FirstNonAddress & (FirstNonAddress - 1)) != 0) {
- ++mPhysMemAddressWidth;
+ ++PhysMemAddressWidth;
}
//
@@ -648,11 +637,14 @@ AddressWidthInitialization (
// X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits. We
// can simply assert that here, since 48 bits are good enough for 256 TB.
//
- if (mPhysMemAddressWidth <= 36) {
- mPhysMemAddressWidth = 36;
+ if (PhysMemAddressWidth <= 36) {
+ PhysMemAddressWidth = 36;
}
- ASSERT (mPhysMemAddressWidth <= 48);
+ ASSERT (PhysMemAddressWidth <= 48);
+
+ PlatformInfoHob->FirstNonAddress = FirstNonAddress;
+ PlatformInfoHob->PhysMemAddressWidth = PhysMemAddressWidth;
}
/**
@@ -698,12 +690,12 @@ GetPeiMemoryCap (
}
}
- if (mPhysMemAddressWidth <= 39) {
+ if (mPlatformInfoHob.PhysMemAddressWidth <= 39) {
Pml4Entries = 1;
- PdpEntries = 1 << (mPhysMemAddressWidth - 30);
+ PdpEntries = 1 << (mPlatformInfoHob.PhysMemAddressWidth - 30);
ASSERT (PdpEntries <= 0x200);
} else {
- Pml4Entries = 1 << (mPhysMemAddressWidth - 39);
+ Pml4Entries = 1 << (mPlatformInfoHob.PhysMemAddressWidth - 39);
ASSERT (Pml4Entries <= 0x200);
PdpEntries = 512;
}
@@ -736,38 +728,46 @@ PublishPeiMemory (
UINT64 MemorySize;
UINT32 LowerMemorySize;
UINT32 PeiMemoryCap;
+ UINT32 S3AcpiReservedMemoryBase;
+ UINT32 S3AcpiReservedMemorySize;
- LowerMemorySize = GetSystemMemorySizeBelow4gb ();
- if (FeaturePcdGet (PcdSmmSmramRequire)) {
+ LowerMemorySize = GetSystemMemorySizeBelow4gb (&mPlatformInfoHob);
+ if (mPlatformInfoHob.SmmSmramRequire) {
//
// TSEG is chipped from the end of low RAM
//
- LowerMemorySize -= mQ35TsegMbytes * SIZE_1MB;
+ LowerMemorySize -= mPlatformInfoHob.Q35TsegMbytes * SIZE_1MB;
}
+ S3AcpiReservedMemoryBase = 0;
+ S3AcpiReservedMemorySize = 0;
+
//
// If S3 is supported, then the S3 permanent PEI memory is placed next,
// downwards. Its size is primarily dictated by CpuMpPei. The formula below
// is an approximation.
//
- if (mS3Supported) {
- mS3AcpiReservedMemorySize = SIZE_512KB +
- mMaxCpuCount *
- PcdGet32 (PcdCpuApStackSize);
- mS3AcpiReservedMemoryBase = LowerMemorySize - mS3AcpiReservedMemorySize;
- LowerMemorySize = mS3AcpiReservedMemoryBase;
+ if (mPlatformInfoHob.S3Supported) {
+ S3AcpiReservedMemorySize = SIZE_512KB +
+ mPlatformInfoHob.PcdCpuMaxLogicalProcessorNumber *
+ PcdGet32 (PcdCpuApStackSize);
+ S3AcpiReservedMemoryBase = LowerMemorySize - S3AcpiReservedMemorySize;
+ LowerMemorySize = S3AcpiReservedMemoryBase;
}
- if (mBootMode == BOOT_ON_S3_RESUME) {
- MemoryBase = mS3AcpiReservedMemoryBase;
- MemorySize = mS3AcpiReservedMemorySize;
+ mPlatformInfoHob.S3AcpiReservedMemoryBase = S3AcpiReservedMemoryBase;
+ mPlatformInfoHob.S3AcpiReservedMemorySize = S3AcpiReservedMemorySize;
+
+ if (mPlatformInfoHob.BootMode == BOOT_ON_S3_RESUME) {
+ MemoryBase = S3AcpiReservedMemoryBase;
+ MemorySize = S3AcpiReservedMemorySize;
} else {
PeiMemoryCap = GetPeiMemoryCap ();
DEBUG ((
DEBUG_INFO,
"%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",
__FUNCTION__,
- mPhysMemAddressWidth,
+ mPlatformInfoHob.PhysMemAddressWidth,
PeiMemoryCap >> 10
));
@@ -781,7 +781,7 @@ PublishPeiMemory (
// allocation HOB, and other allocations served from the permanent PEI RAM
// shouldn't overlap with that HOB.
//
- MemoryBase = mS3Supported && FeaturePcdGet (PcdSmmSmramRequire) ?
+ MemoryBase = mPlatformInfoHob.S3Supported && mPlatformInfoHob.SmmSmramRequire ?
PcdGet32 (PcdOvmfDecompressionScratchEnd) :
PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);
MemorySize = LowerMemorySize - MemoryBase;
@@ -796,7 +796,7 @@ PublishPeiMemory (
// normal boot permanent PEI RAM. Regarding the S3 boot path, the S3
// permanent PEI RAM is located even higher.
//
- if (FeaturePcdGet (PcdSmmSmramRequire) && mQ35SmramAtDefaultSmbase) {
+ if (mPlatformInfoHob.SmmSmramRequire && mPlatformInfoHob.Q35SmramAtDefaultSmbase) {
ASSERT (SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE <= MemoryBase);
}
@@ -812,10 +812,10 @@ PublishPeiMemory (
STATIC
VOID
QemuInitializeRamBelow1gb (
- VOID
+ IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob
)
{
- if (FeaturePcdGet (PcdSmmSmramRequire) && mQ35SmramAtDefaultSmbase) {
+ if (PlatformInfoHob->SmmSmramRequire && PlatformInfoHob->Q35SmramAtDefaultSmbase) {
PlatformAddMemoryRangeHob (0, SMM_DEFAULT_SMBASE);
PlatformAddReservedMemoryBaseSizeHob (
SMM_DEFAULT_SMBASE,
@@ -842,7 +842,7 @@ QemuInitializeRamBelow1gb (
STATIC
VOID
QemuInitializeRam (
- VOID
+ IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob
)
{
UINT64 LowerMemorySize;
@@ -855,9 +855,9 @@ QemuInitializeRam (
//
// Determine total memory size available
//
- LowerMemorySize = GetSystemMemorySizeBelow4gb ();
+ LowerMemorySize = GetSystemMemorySizeBelow4gb (PlatformInfoHob);
- if (mBootMode == BOOT_ON_S3_RESUME) {
+ if (PlatformInfoHob->BootMode == BOOT_ON_S3_RESUME) {
//
// Create the following memory HOB as an exception on the S3 boot path.
//
@@ -878,17 +878,17 @@ QemuInitializeRam (
// allocation HOBs, and to honor preexistent memory allocation HOBs when
// looking for an area to borrow.
//
- QemuInitializeRamBelow1gb ();
+ QemuInitializeRamBelow1gb (PlatformInfoHob);
} else {
//
// Create memory HOBs
//
- QemuInitializeRamBelow1gb ();
+ QemuInitializeRamBelow1gb (PlatformInfoHob);
- if (FeaturePcdGet (PcdSmmSmramRequire)) {
+ if (PlatformInfoHob->SmmSmramRequire) {
UINT32 TsegSize;
- TsegSize = mQ35TsegMbytes * SIZE_1MB;
+ TsegSize = PlatformInfoHob->Q35TsegMbytes * SIZE_1MB;
PlatformAddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize);
PlatformAddReservedMemoryBaseSizeHob (
LowerMemorySize - TsegSize,
@@ -924,7 +924,7 @@ QemuInitializeRam (
// practically any alignment, and we may not have enough variable MTRRs to
// cover it exactly.
//
- if (IsMtrrSupported () && (mHostBridgeDevId != CLOUDHV_DEVICE_ID)) {
+ if (IsMtrrSupported () && (PlatformInfoHob->HostBridgeDevId != CLOUDHV_DEVICE_ID)) {
MtrrGetAllMtrrs (&MtrrSettings);
//
@@ -957,8 +957,8 @@ QemuInitializeRam (
// MMIO aperture on i440fx, PCIEXBAR on q35) to 4GB as uncacheable.
//
Status = MtrrSetMemoryAttribute (
- mQemuUc32Base,
- SIZE_4GB - mQemuUc32Base,
+ PlatformInfoHob->Uc32Base,
+ SIZE_4GB - PlatformInfoHob->Uc32Base,
CacheUncacheable
);
ASSERT_EFI_ERROR (Status);
@@ -971,20 +971,20 @@ QemuInitializeRam (
**/
VOID
InitializeRamRegions (
- VOID
+ IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob
)
{
- QemuInitializeRam ();
+ QemuInitializeRam (PlatformInfoHob);
SevInitializeRam ();
- if (mS3Supported && (mBootMode != BOOT_ON_S3_RESUME)) {
+ if (PlatformInfoHob->S3Supported && (PlatformInfoHob->BootMode != BOOT_ON_S3_RESUME)) {
//
// This is the memory range that will be used for PEI on S3 resume
//
BuildMemoryAllocationHob (
- mS3AcpiReservedMemoryBase,
- mS3AcpiReservedMemorySize,
+ PlatformInfoHob->S3AcpiReservedMemoryBase,
+ PlatformInfoHob->S3AcpiReservedMemorySize,
EfiACPIMemoryNVS
);
@@ -1021,7 +1021,7 @@ InitializeRamRegions (
EfiACPIMemoryNVS
);
- if (MemEncryptSevEsIsEnabled ()) {
+ if (PlatformInfoHob->SevEsIsEnabled) {
//
// If SEV-ES is enabled, reserve the GHCB-related memory area. This
// includes the extra page table used to break down the 2MB page
@@ -1051,8 +1051,8 @@ InitializeRamRegions (
#endif
}
- if (mBootMode != BOOT_ON_S3_RESUME) {
- if (!FeaturePcdGet (PcdSmmSmramRequire)) {
+ if (PlatformInfoHob->BootMode != BOOT_ON_S3_RESUME) {
+ if (!PlatformInfoHob->SmmSmramRequire) {
//
// Reserve the lock box storage area
//
@@ -1070,20 +1070,20 @@ InitializeRamRegions (
BuildMemoryAllocationHob (
(EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase),
(UINT64)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize),
- mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData
+ PlatformInfoHob->S3Supported ? EfiACPIMemoryNVS : EfiBootServicesData
);
}
- if (FeaturePcdGet (PcdSmmSmramRequire)) {
+ if (PlatformInfoHob->SmmSmramRequire) {
UINT32 TsegSize;
//
// Make sure the TSEG area that we reported as a reserved memory resource
// cannot be used for reserved memory allocations.
//
- TsegSize = mQ35TsegMbytes * SIZE_1MB;
+ TsegSize = PlatformInfoHob->Q35TsegMbytes * SIZE_1MB;
BuildMemoryAllocationHob (
- GetSystemMemorySizeBelow4gb () - TsegSize,
+ GetSystemMemorySizeBelow4gb (PlatformInfoHob) - TsegSize,
TsegSize,
EfiReservedMemoryType
);
@@ -1091,7 +1091,7 @@ InitializeRamRegions (
// Similarly, allocate away the (already reserved) SMRAM at the default
// SMBASE, if it exists.
//
- if (mQ35SmramAtDefaultSmbase) {
+ if (PlatformInfoHob->Q35SmramAtDefaultSmbase) {
BuildMemoryAllocationHob (
SMM_DEFAULT_SMBASE,
MCH_DEFAULT_SMBASE_SIZE,
@@ -1115,7 +1115,7 @@ InitializeRamRegions (
BuildMemoryAllocationHob (
(EFI_PHYSICAL_ADDRESS)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaBase),
(UINT64)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaSize),
- mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData
+ PlatformInfoHob->S3Supported ? EfiACPIMemoryNVS : EfiBootServicesData
);
}
diff --git a/OvmfPkg/PlatformPei/MemTypeInfo.c b/OvmfPkg/PlatformPei/MemTypeInfo.c
index fc5ccfaf113d..6ee36ad1cc5c 100644
--- a/OvmfPkg/PlatformPei/MemTypeInfo.c
+++ b/OvmfPkg/PlatformPei/MemTypeInfo.c
@@ -17,6 +17,8 @@
#include "Platform.h"
+extern EFI_HOB_PLATFORM_INFO mPlatformInfoHob;
+
#define MEMORY_TYPE_INFO_DEFAULT(Type) \
{ Type, FixedPcdGet32 (PcdMemoryType ## Type) }
@@ -208,7 +210,7 @@ MemTypeInfoInitialization (
{
EFI_STATUS Status;
- if (!FeaturePcdGet (PcdSmmSmramRequire)) {
+ if (!mPlatformInfoHob.SmmSmramRequire) {
//
// EFI_PEI_READ_ONLY_VARIABLE2_PPI will never be available; install
// the default memory type information HOB right away.
diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 62480c3c40e5..80eb4cc9adcd 100644
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -36,11 +36,13 @@
#include <IndustryStandard/Pci22.h>
#include <IndustryStandard/Q35MchIch9.h>
#include <IndustryStandard/QemuCpuHotplug.h>
-#include <Library/PlatformInitLib.h>
+#include <Library/MemEncryptSevLib.h>
#include <OvmfPlatforms.h>
#include "Platform.h"
+EFI_HOB_PLATFORM_INFO mPlatformInfoHob = { 0 };
+
EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {
{
EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
@@ -49,17 +51,9 @@ EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {
}
};
-UINT16 mHostBridgeDevId;
-
-EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
-
-BOOLEAN mS3Supported = FALSE;
-
-UINT32 mMaxCpuCount;
-
VOID
MemMapInitialization (
- VOID
+ IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
)
{
UINT64 PciIoBase;
@@ -78,16 +72,16 @@ MemMapInitialization (
//
PlatformAddIoMemoryRangeHob (0x0A0000, BASE_1MB);
- if (mHostBridgeDevId == 0xffff /* microvm */) {
+ if (PlatformInfoHob->HostBridgeDevId == 0xffff /* microvm */) {
PlatformAddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB);
PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */
PlatformAddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */
return;
}
- TopOfLowRam = GetSystemMemorySizeBelow4gb ();
+ TopOfLowRam = GetSystemMemorySizeBelow4gb (PlatformInfoHob);
PciExBarBase = 0;
- if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
+ if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
//
// The MMCONFIG area is expected to fall between the top of low RAM and
// the base of the 32-bit PCI host aperture.
@@ -97,8 +91,8 @@ MemMapInitialization (
ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);
PciBase = (UINT32)(PciExBarBase + SIZE_256MB);
} else {
- ASSERT (TopOfLowRam <= mQemuUc32Base);
- PciBase = mQemuUc32Base;
+ ASSERT (TopOfLowRam <= PlatformInfoHob->Uc32Base);
+ PciBase = PlatformInfoHob->Uc32Base;
}
//
@@ -121,9 +115,12 @@ MemMapInitialization (
PcdStatus = PcdSet64S (PcdPciMmio32Size, PciSize);
ASSERT_RETURN_ERROR (PcdStatus);
+ PlatformInfoHob->PcdPciMmio32Base = PciBase;
+ PlatformInfoHob->PcdPciMmio32Size = PciSize;
+
PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
PlatformAddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
- if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
+ if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
PlatformAddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);
//
// Note: there should be an
@@ -160,7 +157,7 @@ MemMapInitialization (
// On Q35, the IO Port space is available for PCI resource allocations from
// 0x6000 up.
//
- if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
+ if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
PciIoBase = 0x6000;
PciIoSize = 0xA000;
ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);
@@ -180,6 +177,9 @@ MemMapInitialization (
ASSERT_RETURN_ERROR (PcdStatus);
PcdStatus = PcdSet64S (PcdPciIoSize, PciIoSize);
ASSERT_RETURN_ERROR (PcdStatus);
+
+ PlatformInfoHob->PcdPciIoBase = PciIoBase;
+ PlatformInfoHob->PcdPciIoSize = PciIoSize;
}
#define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \
@@ -306,7 +306,7 @@ MicrovmInitialization (
VOID
MiscInitialization (
- VOID
+ IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob
)
{
UINTN PmCmd;
@@ -327,12 +327,12 @@ MiscInitialization (
// of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
// S3 resume as well, so we build it unconditionally.)
//
- BuildCpuHob (mPhysMemAddressWidth, 16);
+ BuildCpuHob (PlatformInfoHob->PhysMemAddressWidth, 16);
//
// Determine platform type and save Host Bridge DID to PCD
//
- switch (mHostBridgeDevId) {
+ switch (PlatformInfoHob->HostBridgeDevId) {
case INTEL_82441_DEVICE_ID:
PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
@@ -371,13 +371,13 @@ MiscInitialization (
DEBUG_ERROR,
"%a: Unknown Host Bridge Device ID: 0x%04x\n",
__FUNCTION__,
- mHostBridgeDevId
+ PlatformInfoHob->HostBridgeDevId
));
ASSERT (FALSE);
return;
}
- PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);
+ PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, PlatformInfoHob->HostBridgeDevId);
ASSERT_RETURN_ERROR (PcdStatus);
//
@@ -403,7 +403,7 @@ MiscInitialization (
PciOr8 (AcpiCtlReg, AcpiEnBit);
}
- if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
+ if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
//
// Set Root Complex Register Block BAR
//
@@ -421,18 +421,18 @@ MiscInitialization (
VOID
BootModeInitialization (
- VOID
+ IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
)
{
EFI_STATUS Status;
if (PlatformCmosRead8 (0xF) == 0xFE) {
- mBootMode = BOOT_ON_S3_RESUME;
+ PlatformInfoHob->BootMode = BOOT_ON_S3_RESUME;
}
PlatformCmosWrite8 (0xF, 0x00);
- Status = PeiServicesSetBootMode (mBootMode);
+ Status = PeiServicesSetBootMode (PlatformInfoHob->BootMode);
ASSERT_EFI_ERROR (Status);
Status = PeiServicesInstallPpi (mPpiBootMode);
@@ -473,7 +473,7 @@ S3Verification (
)
{
#if defined (MDE_CPU_X64)
- if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {
+ if (mPlatformInfoHob.SmmSmramRequire && mPlatformInfoHob.S3Supported) {
DEBUG ((
DEBUG_ERROR,
"%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n",
@@ -501,7 +501,7 @@ Q35BoardVerification (
VOID
)
{
- if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
+ if (mPlatformInfoHob.HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
return;
}
@@ -510,7 +510,7 @@ Q35BoardVerification (
"%a: no TSEG (SMRAM) on host bridge DID=0x%04x; "
"only DID=0x%04x (Q35) is supported\n",
__FUNCTION__,
- mHostBridgeDevId,
+ mPlatformInfoHob.HostBridgeDevId,
INTEL_Q35_MCH_DEVICE_ID
));
ASSERT (FALSE);
@@ -523,10 +523,11 @@ Q35BoardVerification (
**/
VOID
MaxCpuCountInitialization (
- VOID
+ IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
)
{
UINT16 BootCpuCount;
+ UINT32 MaxCpuCount;
RETURN_STATUS PcdStatus;
//
@@ -542,7 +543,7 @@ MaxCpuCountInitialization (
// first).
//
DEBUG ((DEBUG_WARN, "%a: boot CPU count unavailable\n", __FUNCTION__));
- mMaxCpuCount = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
+ MaxCpuCount = PlatformInfoHob->DefaultMaxCpuNumber;
} else {
//
// We will expose BootCpuCount to MpInitLib. MpInitLib will count APs up to
@@ -553,7 +554,7 @@ MaxCpuCountInitialization (
UINTN CpuHpBase;
UINT32 CmdData2;
- CpuHpBase = ((mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) ?
+ CpuHpBase = ((PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) ?
ICH9_CPU_HOTPLUG_BASE : PIIX4_CPU_HOTPLUG_BASE);
//
@@ -605,7 +606,7 @@ MaxCpuCountInitialization (
"%a: modern CPU hotplug interface unavailable\n",
__FUNCTION__
));
- mMaxCpuCount = BootCpuCount;
+ MaxCpuCount = BootCpuCount;
} else {
//
// Grab the possible CPU count from the modern CPU hotplug interface.
@@ -671,23 +672,26 @@ MaxCpuCountInitialization (
BootCpuCount = (UINT16)Present;
}
- mMaxCpuCount = Possible;
+ MaxCpuCount = Possible;
}
}
DEBUG ((
DEBUG_INFO,
- "%a: BootCpuCount=%d mMaxCpuCount=%u\n",
+ "%a: BootCpuCount=%d MaxCpuCount=%u\n",
__FUNCTION__,
BootCpuCount,
- mMaxCpuCount
+ MaxCpuCount
));
- ASSERT (BootCpuCount <= mMaxCpuCount);
+ ASSERT (BootCpuCount <= MaxCpuCount);
PcdStatus = PcdSet32S (PcdCpuBootLogicalProcessorNumber, BootCpuCount);
ASSERT_RETURN_ERROR (PcdStatus);
- PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, mMaxCpuCount);
+ PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, MaxCpuCount);
ASSERT_RETURN_ERROR (PcdStatus);
+
+ PlatformInfoHob->PcdCpuMaxLogicalProcessorNumber = MaxCpuCount;
+ PlatformInfoHob->PcdCpuBootLogicalProcessorNumber = BootCpuCount;
}
/**
@@ -710,27 +714,30 @@ InitializePlatform (
DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));
+ mPlatformInfoHob.SmmSmramRequire = FeaturePcdGet (PcdSmmSmramRequire);
+ mPlatformInfoHob.SevEsIsEnabled = MemEncryptSevEsIsEnabled ();
+
PlatformDebugDumpCmos ();
if (QemuFwCfgS3Enabled ()) {
DEBUG ((DEBUG_INFO, "S3 support was detected on QEMU\n"));
- mS3Supported = TRUE;
- Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);
+ mPlatformInfoHob.S3Supported = TRUE;
+ Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);
ASSERT_EFI_ERROR (Status);
}
S3Verification ();
- BootModeInitialization ();
- AddressWidthInitialization ();
+ BootModeInitialization (&mPlatformInfoHob);
+ AddressWidthInitialization (&mPlatformInfoHob);
//
// Query Host Bridge DID
//
- mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
+ mPlatformInfoHob.HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
- MaxCpuCountInitialization ();
+ MaxCpuCountInitialization (&mPlatformInfoHob);
- if (FeaturePcdGet (PcdSmmSmramRequire)) {
+ if (mPlatformInfoHob.SmmSmramRequire) {
Q35BoardVerification ();
Q35TsegMbytesInitialization ();
Q35SmramAtDefaultSmbaseInitialization ();
@@ -738,24 +745,24 @@ InitializePlatform (
PublishPeiMemory ();
- QemuUc32BaseInitialization ();
+ QemuUc32BaseInitialization (&mPlatformInfoHob);
- InitializeRamRegions ();
+ InitializeRamRegions (&mPlatformInfoHob);
- if (mBootMode != BOOT_ON_S3_RESUME) {
- if (!FeaturePcdGet (PcdSmmSmramRequire)) {
+ if (mPlatformInfoHob.BootMode != BOOT_ON_S3_RESUME) {
+ if (!mPlatformInfoHob.SmmSmramRequire) {
ReserveEmuVariableNvStore ();
}
PeiFvInitialization ();
MemTypeInfoInitialization ();
- MemMapInitialization ();
+ MemMapInitialization (&mPlatformInfoHob);
NoexecDxeInitialization ();
}
InstallClearCacheCallback ();
AmdSevInitialize ();
- MiscInitialization ();
+ MiscInitialization (&mPlatformInfoHob);
InstallFeatureControlCallback ();
return EFI_SUCCESS;
diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platform.h
index f193ff736549..a5fa27c3794f 100644
--- a/OvmfPkg/PlatformPei/Platform.h
+++ b/OvmfPkg/PlatformPei/Platform.h
@@ -10,10 +10,11 @@
#define _PLATFORM_PEI_H_INCLUDED_
#include <IndustryStandard/E820.h>
+#include <Library/PlatformInitLib.h>
VOID
AddressWidthInitialization (
- VOID
+ IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
);
VOID
@@ -33,17 +34,37 @@ PublishPeiMemory (
UINT32
GetSystemMemorySizeBelow4gb (
- VOID
+ IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob
);
VOID
QemuUc32BaseInitialization (
- VOID
+ IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
);
VOID
InitializeRamRegions (
- VOID
+ IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob
+ );
+
+VOID
+MemMapInitialization (
+ IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
+ );
+
+VOID
+MiscInitialization (
+ IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob
+ );
+
+VOID
+BootModeInitialization (
+ IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
+ );
+
+VOID
+MaxCpuCountInitialization (
+ IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
);
EFI_STATUS
@@ -71,23 +92,9 @@ AmdSevInitialize (
VOID
);
-extern EFI_BOOT_MODE mBootMode;
-
VOID
SevInitializeRam (
VOID
);
-extern BOOLEAN mS3Supported;
-
-extern UINT8 mPhysMemAddressWidth;
-
-extern UINT32 mMaxCpuCount;
-
-extern UINT16 mHostBridgeDevId;
-
-extern BOOLEAN mQ35SmramAtDefaultSmbase;
-
-extern UINT32 mQemuUc32Base;
-
#endif // _PLATFORM_PEI_H_INCLUDED_
--
2.29.2.windows.2
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