[edk2-devel] [PATCH 3/6] [RFC] UefiCpuPkg/BaseUefiCpuLib: Add RISC-V RISCV64 instace
Abner Chang
abner.chang at hpe.com
Fri Mar 18 05:43:19 UTC 2022
https://bugzilla.tianocore.org/show_bug.cgi?id=3860
Add BaseUefiCpuLib instance for RISC-V RISCV64 arch.
Signed-off-by: Abner Chang <abner.chang at hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer at hpe.com>
Cc: Eric Dong <eric.dong at intel.com>
Cc: Ray Ni <ray.ni at intel.com>
Cc: Rahul Kumar <rahul1.kumar at intel.com>
Cc: Sunil V L <sunilvl at ventanamicro.com>
Cc: Andrew Fish <afish at apple.com>
Cc: Leif Lindholm <quic_llindhol at quicinc.com>
Cc: Michael D Kinney <michael.d.kinney at intel.com>
Cc: Chao Li <lichao at loongson.cn>
---
UefiCpuPkg/UefiCpuPkg.dsc | 7 +-
.../Library/BaseUefiCpuLib/BaseUefiCpuLib.inf | 8 +-
.../Include/Library/RISC-V/RiscVCpuLib.h | 118 +++++++++++++++
.../Library/BaseUefiCpuLib/BaseUefiCpuLib.uni | 5 +-
.../Library/BaseUefiCpuLib/RISCV64/Cpu.S | 143 ++++++++++++++++++
5 files changed, 274 insertions(+), 7 deletions(-)
create mode 100644 UefiCpuPkg/Include/Library/RISC-V/RiscVCpuLib.h
create mode 100644 UefiCpuPkg/Library/BaseUefiCpuLib/RISCV64/Cpu.S
diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc
index 6b43ff6822..50c9fc294c 100644
--- a/UefiCpuPkg/UefiCpuPkg.dsc
+++ b/UefiCpuPkg/UefiCpuPkg.dsc
@@ -14,7 +14,7 @@
PLATFORM_VERSION = 0.90
DSC_SPECIFICATION = 0x00010005
OUTPUT_DIRECTORY = Build/UefiCpu
- SUPPORTED_ARCHITECTURES = IA32|X64
+ SUPPORTED_ARCHITECTURES = IA32|X64|RISCV64
BUILD_TARGETS = DEBUG|RELEASE|NOOPT
SKUID_IDENTIFIER = DEFAULT
@@ -55,9 +55,9 @@
PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+ UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
[LibraryClasses.IA32, LibraryClasses.X64]
- UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf
LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
SmmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.inf
@@ -120,6 +120,8 @@
#
# Drivers/Libraries within this package
#
+[Components.common]
+ UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
[Components.IA32, Components.X64]
UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
@@ -144,7 +146,6 @@
UefiCpuPkg/CpuIo2Smm/CpuIo2StandaloneMm.inf
UefiCpuPkg/CpuMpPei/CpuMpPei.inf
UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf
- UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf
UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf
diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
index 34d3a7bb43..f43498e9b4 100644
--- a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
+++ b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
@@ -5,6 +5,7 @@
#
# Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2020, AMD Inc. All rights reserved.<BR>
+# Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -21,7 +22,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64
+# VALID_ARCHITECTURES = IA32 X64 RISCV64
#
[Sources.IA32]
@@ -30,9 +31,12 @@
[Sources.X64]
X64/InitializeFpu.nasm
-[Sources]
+[Sources.IA32, Sources.X64]
BaseUefiCpuLib.c
+[Sources.RISCV64]
+ RISCV64/Cpu.S
+
[Packages]
MdePkg/MdePkg.dec
UefiCpuPkg/UefiCpuPkg.dec
diff --git a/UefiCpuPkg/Include/Library/RISC-V/RiscVCpuLib.h b/UefiCpuPkg/Include/Library/RISC-V/RiscVCpuLib.h
new file mode 100644
index 0000000000..610456d0be
--- /dev/null
+++ b/UefiCpuPkg/Include/Library/RISC-V/RiscVCpuLib.h
@@ -0,0 +1,118 @@
+/** @file
+ RISC-V CPU library definitions.
+
+ Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef RISCV_CPU_LIB_H_
+#define RISCV_CPU_LIB_H_
+
+#include "RiscVImpl.h"
+
+/**
+ RISCV_TRAP_HANDLER
+**/
+typedef
+VOID
+(EFIAPI *RISCV_TRAP_HANDLER)(
+ VOID
+ );
+
+VOID
+RiscVSetMachineScratch (
+ RISCV_MACHINE_MODE_CONTEXT *RiscvContext
+ );
+
+UINT32
+RiscVGetMachineScratch (
+ VOID
+ );
+
+UINT32
+RiscVGetMachineTrapCause (
+ VOID
+ );
+
+UINT64
+RiscVReadMachineTimer (
+ VOID
+ );
+
+UINT64
+RiscVReadMachineTimerInterface (
+ VOID
+ );
+
+VOID
+ RiscVSetMachineTimerCmp (UINT64);
+
+UINT64
+RiscVReadMachineTimerCmp (
+ VOID
+ );
+
+UINT64
+RiscVReadMachineInterruptEnable (
+ VOID
+ );
+
+UINT64
+RiscVReadMachineInterruptPending (
+ VOID
+ );
+
+UINT64
+RiscVReadMachineStatus (
+ VOID
+ );
+
+VOID
+ RiscVWriteMachineStatus (UINT64);
+
+UINT64
+RiscVReadMachineTrapVector (
+ VOID
+ );
+
+UINT64
+RiscVReadMachineIsa (
+ VOID
+ );
+
+UINT64
+RiscVReadMachineVendorId (
+ VOID
+ );
+
+UINT64
+RiscVReadMachineArchitectureId (
+ VOID
+ );
+
+UINT64
+RiscVReadMachineImplementId (
+ VOID
+ );
+
+VOID
+ RiscVSetSupervisorAddressTranslationRegister (UINT64);
+
+VOID
+ RiscVSetSupervisorScratch (UINT64);
+
+UINT64
+RiscVGetSupervisorScratch (
+ VOID
+ );
+
+VOID
+ RiscVSetSupervisorStvec (UINT64);
+
+UINT64
+RiscVGetSupervisorStvec (
+ VOID
+ );
+
+#endif
diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.uni b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.uni
index 83c96cea67..a94bbef53e 100644
--- a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.uni
+++ b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.uni
@@ -4,13 +4,14 @@
// The library routines are UEFI specification compliant.
//
// Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+// Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
// **/
-#string STR_MODULE_ABSTRACT #language en-US "Defines generic routines for IA32 family CPUs."
+#string STR_MODULE_ABSTRACT #language en-US "Base CPU library."
-#string STR_MODULE_DESCRIPTION #language en-US "The library routines comply with the UEFI Specification."
+#string STR_MODULE_DESCRIPTION #language en-US "Base CPU library provides generic routines for specific CPU architecture."
diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/RISCV64/Cpu.S b/UefiCpuPkg/Library/BaseUefiCpuLib/RISCV64/Cpu.S
new file mode 100644
index 0000000000..5bc31744db
--- /dev/null
+++ b/UefiCpuPkg/Library/BaseUefiCpuLib/RISCV64/Cpu.S
@@ -0,0 +1,143 @@
+//------------------------------------------------------------------------------
+//
+// RISC-V CPU functions.
+//
+// Copyright (c) 2022 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+#include <Base.h>
+#include <RISC-V/RiscVImpl.h>
+
+.data
+
+.text
+.align 3
+
+//
+// Set machine mode scratch.
+// @param a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT.
+//
+ASM_FUNC (RiscVSetMachineScratch)
+ csrrw a1, RISCV_CSR_MACHINE_MSCRATCH, a0
+ ret
+
+//
+// Get machine mode scratch.
+// @retval a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT.
+//
+ASM_FUNC (RiscVGetMachineScratch)
+ csrrs a0, RISCV_CSR_MACHINE_MSCRATCH, 0
+ ret
+
+//
+// Get machine trap cause CSR.
+//
+ASM_FUNC (RiscVGetMachineTrapCause)
+ csrrs a0, RISCV_CSR_MACHINE_MCAUSE, 0
+ ret
+
+//
+// Get machine interrupt enable
+//
+ASM_FUNC (RiscVReadMachineInterruptEnable)
+ csrr a0, RISCV_CSR_MACHINE_MIE
+ ret
+
+//
+// Get machine interrupt pending
+//
+ASM_FUNC (RiscVReadMachineInterruptPending)
+ csrr a0, RISCV_CSR_MACHINE_MIP
+ ret
+
+//
+// Get machine status
+//
+ASM_FUNC (RiscVReadMachineStatus)
+ csrr a0, RISCV_CSR_MACHINE_MSTATUS
+ ret
+
+//
+// Set machine status
+//
+ASM_FUNC (RiscVWriteMachineStatus)
+ csrw RISCV_CSR_MACHINE_MSTATUS, a0
+ ret
+
+//
+// Get machine trap vector
+//
+ASM_FUNC (RiscVReadMachineTrapVector)
+ csrr a0, RISCV_CSR_MACHINE_MTVEC
+ ret
+
+//
+// Read machine ISA
+//
+ASM_FUNC (RiscVReadMachineIsa)
+ csrr a0, RISCV_CSR_MACHINE_MISA
+ ret
+
+//
+// Read machine vendor ID
+//
+ASM_FUNC (RiscVReadMachineVendorId)
+ csrr a0, RISCV_CSR_MACHINE_MVENDORID
+ ret
+
+//
+// Read machine architecture ID
+//
+ASM_FUNC (RiscVReadMachineArchitectureId)
+ csrr a0, RISCV_CSR_MACHINE_MARCHID
+ ret
+
+//
+// Read machine implementation ID
+//
+ASM_FUNC (RiscVReadMachineImplementId)
+ csrr a0, RISCV_CSR_MACHINE_MIMPID
+ ret
+
+//
+// Set Supervisor mode scratch.
+// @param a0 : Value set to Supervisor mode scratch
+//
+ASM_FUNC (RiscVSetSupervisorScratch)
+ csrrw a1, RISCV_CSR_SUPERVISOR_SSCRATCH, a0
+ ret
+
+//
+// Get Supervisor mode scratch.
+// @retval a0 : Value in Supervisor mode scratch
+//
+ASM_FUNC (RiscVGetSupervisorScratch)
+ csrr a0, RISCV_CSR_SUPERVISOR_SSCRATCH
+ ret
+
+//
+// Set Supervisor mode trap vector.
+// @param a0 : Value set to Supervisor mode trap vector
+//
+ASM_FUNC (RiscVSetSupervisorStvec)
+ csrrw a1, RISCV_CSR_SUPERVISOR_STVEC, a0
+ ret
+
+//
+// Get Supervisor mode scratch.
+// @retval a0 : Value in Supervisor mode trap vector
+//
+ASM_FUNC (RiscVGetSupervisorStvec)
+ csrr a0, RISCV_CSR_SUPERVISOR_STVEC
+ ret
+
+//
+// Set Supervisor Address Translation and
+// Protection Register.
+//
+ASM_FUNC (RiscVSetSupervisorAddressTranslationRegister)
+ csrw RISCV_CSR_SUPERVISOR_SATP, a0
+ ret
+
--
2.31.1
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