[edk2-devel] [PATCH 5/6] [RFC] UefiCpuPkg/Library: Add RiscVOpensbiLib
Abner Chang
abner.chang at hpe.com
Fri Mar 18 05:43:21 UTC 2022
https://bugzilla.tianocore.org/show_bug.cgi?id=3860
(This is migrated from edk2-platforms:Silicon/RISC-V)
EDK2 RISC-V OpenSBI library which pull in external source files under
UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/opensbi to the build process.
Signed-off-by: Abner Chang <abner.chang at hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer at hpe.com>
Cc: Eric Dong <eric.dong at intel.com>
Cc: Ray Ni <ray.ni at intel.com>
Cc: Rahul Kumar <rahul1.kumar at intel.com>
Cc: Sunil V L <sunilvl at ventanamicro.com>
Cc: Andrew Fish <afish at apple.com>
Cc: Leif Lindholm <quic_llindhol at quicinc.com>
Cc: Michael D Kinney <michael.d.kinney at intel.com>
Cc: Chao Li <lichao at loongson.cn>
---
UefiCpuPkg/UefiCpuPkg.dec | 12 ++-
UefiCpuPkg/UefiCpuPkg.dsc | 6 ++
.../RiscVOpensbiLib/RiscVOpensbiLib.inf | 89 +++++++++++++++++++
.../IndustryStandard/RISC-V/RiscVOpensbi.h | 62 +++++++++++++
UefiCpuPkg/Include/RISC-V/OpensbiTypes.h | 82 +++++++++++++++++
BaseTools/Conf/tools_def.template | 2 +-
6 files changed, 250 insertions(+), 3 deletions(-)
create mode 100644 UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiLib.inf
create mode 100644 UefiCpuPkg/Include/IndustryStandard/RISC-V/RiscVOpensbi.h
create mode 100644 UefiCpuPkg/Include/RISC-V/OpensbiTypes.h
diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index 525cde4634..8e85d242a3 100644
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -1,7 +1,8 @@
## @file UefiCpuPkg.dec
# This Package provides UEFI compatible CPU modules and libraries.
#
-# Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -14,9 +15,16 @@
PACKAGE_GUID = 2171df9b-0d39-45aa-ac37-2de190010d23
PACKAGE_VERSION = 0.90
-[Includes]
+[Includes.common]
Include
+[Includes.RISCV64]
+ Include/Library
+ Library/RISC-V/RiscVOpensbiLib/opensbi # OpenSBI header file reference ("include/sbi/...")
+ Library/RISC-V/RiscVOpensbiLib/opensbi/include # Header file reference from opensbi files, ("sbi/...")
+ Library/RISC-V/RiscVOpensbiLib/opensbi/platform/generic/include # Header file reference from opensbi files, ("sbi/...")
+
+
[LibraryClasses]
## @libraryclass Defines some routines that are generic for IA32 family CPU
## to be UEFI specification compliant.
diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc
index 50c9fc294c..374e951f29 100644
--- a/UefiCpuPkg/UefiCpuPkg.dsc
+++ b/UefiCpuPkg/UefiCpuPkg.dsc
@@ -66,6 +66,9 @@
MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf
SmmCpuRendezvousLib|UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezvousLib.inf
+[LibraryClasses.RISCV64]
+ RiscVOpensbiLib|UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiLib.inf
+
[LibraryClasses.common.SEC]
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
@@ -185,5 +188,8 @@
UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf
UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezvousLib.inf
+[Components.RISCV64]
+ UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiLib.inf
+
[BuildOptions]
*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
diff --git a/UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiLib.inf b/UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiLib.inf
new file mode 100644
index 0000000000..54eed050d4
--- /dev/null
+++ b/UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiLib.inf
@@ -0,0 +1,89 @@
+## @file
+# RISC-V Opensbi Library Instance.
+#
+# Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVOpensbiLib
+ FILE_GUID = 6EF0C812-66F6-11E9-93CE-3F5D5F0DF0A7
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVOpensbiLib
+
+[Sources]
+ opensbi/lib/sbi/riscv_asm.c
+ opensbi/lib/sbi/riscv_atomic.c
+ opensbi/lib/sbi/riscv_hardfp.S
+ opensbi/lib/sbi/riscv_locks.c
+ opensbi/lib/sbi/sbi_bitmap.c
+ opensbi/lib/sbi/sbi_bitops.c
+ opensbi/lib/sbi/sbi_console.c
+ opensbi/lib/sbi/sbi_domain.c
+ opensbi/lib/sbi/sbi_ecall.c
+ opensbi/lib/sbi/sbi_ecall_base.c
+ opensbi/lib/sbi/sbi_ecall_hsm.c
+ opensbi/lib/sbi/sbi_ecall_legacy.c
+ opensbi/lib/sbi/sbi_ecall_replace.c
+ opensbi/lib/sbi/sbi_ecall_vendor.c
+ opensbi/lib/sbi/sbi_emulate_csr.c
+ opensbi/lib/sbi/sbi_fifo.c
+ opensbi/lib/sbi/sbi_hart.c
+ opensbi/lib/sbi/sbi_math.c
+ opensbi/lib/sbi/sbi_hfence.S
+ opensbi/lib/sbi/sbi_hsm.c
+ opensbi/lib/sbi/sbi_illegal_insn.c
+ opensbi/lib/sbi/sbi_init.c
+ opensbi/lib/sbi/sbi_ipi.c
+ opensbi/lib/sbi/sbi_misaligned_ldst.c
+ opensbi/lib/sbi/sbi_platform.c
+ opensbi/lib/sbi/sbi_scratch.c
+ opensbi/lib/sbi/sbi_string.c
+ opensbi/lib/sbi/sbi_system.c
+ opensbi/lib/sbi/sbi_timer.c
+ opensbi/lib/sbi/sbi_tlb.c
+ opensbi/lib/sbi/sbi_trap.c
+ opensbi/lib/sbi/sbi_unpriv.c
+ opensbi/lib/sbi/sbi_expected_trap.S
+
+ opensbi/lib/utils/fdt/fdt_helper.c
+ opensbi/lib/utils/fdt/fdt_fixup.c
+ opensbi/lib/utils/fdt/fdt_domain.c
+ opensbi/lib/utils/ipi/fdt_ipi.c
+ opensbi/lib/utils/ipi/aclint_mswi.c
+ opensbi/lib/utils/ipi/fdt_ipi_mswi.c
+ opensbi/lib/utils/irqchip/fdt_irqchip.c
+ opensbi/lib/utils/irqchip/fdt_irqchip_plic.c
+ opensbi/lib/utils/irqchip/plic.c
+ opensbi/lib/utils/reset/fdt_reset.c
+ opensbi/lib/utils/reset/fdt_reset_htif.c
+ opensbi/lib/utils/reset/fdt_reset_sifive.c
+ opensbi/lib/utils/reset/fdt_reset_thead.c
+ opensbi/lib/utils/reset/fdt_reset_thead_asm.S
+ opensbi/lib/utils/serial/fdt_serial.c
+ opensbi/lib/utils/serial/fdt_serial_htif.c
+ opensbi/lib/utils/serial/fdt_serial_shakti.c
+ opensbi/lib/utils/serial/fdt_serial_sifive.c
+ opensbi/lib/utils/serial/fdt_serial_uart8250.c
+ opensbi/lib/utils/serial/fdt_serial_gaisler.c
+ opensbi/lib/utils/serial/gaisler-uart.c
+ opensbi/lib/utils/serial/shakti-uart.c
+ opensbi/lib/utils/serial/sifive-uart.c
+ opensbi/lib/utils/serial/uart8250.c
+ opensbi/lib/utils/sys/htif.c
+ opensbi/lib/utils/sys/sifive_test.c
+ opensbi/lib/utils/timer/fdt_timer.c
+ opensbi/lib/utils/timer/aclint_mtimer.c
+ opensbi/lib/utils/timer/fdt_timer_mtimer.c
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec # For libfdt.
+ MdePkg/MdePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[BuildOptions]
+ GCC:*_*_*_PP_FLAGS = -D__ASSEMBLY__
diff --git a/UefiCpuPkg/Include/IndustryStandard/RISC-V/RiscVOpensbi.h b/UefiCpuPkg/Include/IndustryStandard/RISC-V/RiscVOpensbi.h
new file mode 100644
index 0000000000..db57aeeb37
--- /dev/null
+++ b/UefiCpuPkg/Include/IndustryStandard/RISC-V/RiscVOpensbi.h
@@ -0,0 +1,62 @@
+/** @file
+ SBI inline function calls.
+
+ Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef EDK2_SBI_H_
+#define EDK2_SBI_H_
+
+#include <RiscVImpl.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_atomic.h>
+#include <sbi/sbi_ecall_interface.h>
+#include <sbi/sbi_error.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_types.h>
+#include <sbi/sbi_hartmask.h>
+
+#define RISC_V_MAX_HART_SUPPORTED SBI_HARTMASK_MAX_BITS
+
+typedef
+VOID
+(EFIAPI *RISCV_HART_SWITCH_MODE)(
+ IN UINTN FuncArg0,
+ IN UINTN FuncArg1,
+ IN UINTN NextAddr,
+ IN UINTN NextMode,
+ IN BOOLEAN NextVirt
+ );
+
+//
+// Keep the structure member in 64-bit alignment.
+//
+typedef struct {
+ UINT64 IsaExtensionSupported; // The ISA extension this core supported.
+ RISCV_UINT128 MachineVendorId; // Machine vendor ID
+ RISCV_UINT128 MachineArchId; // Machine Architecture ID
+ RISCV_UINT128 MachineImplId; // Machine Implementation ID
+ RISCV_HART_SWITCH_MODE HartSwitchMode; // OpenSBI's function to switch the mode of a hart
+} EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC;
+#define FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE (64 * 8) // This is the size of EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC
+ // structure. Referred by both C code and assembly code.
+
+typedef struct {
+ UINT64 BootHartId;
+ VOID *PeiServiceTable; // PEI Service table
+ UINT64 FlattenedDeviceTree; // Pointer to Flattened Device tree
+ UINT64 SecPeiHandOffData; // This is EFI_SEC_PEI_HAND_OFF passed to PEI Core.
+ EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX_HART_SUPPORTED];
+} EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT;
+
+//
+// Typedefs of OpenSBI type to make them conform to EDK2 coding guidelines
+//
+typedef struct sbi_scratch SBI_SCRATCH;
+typedef struct sbi_platform SBI_PLATFORM;
+
+#endif
diff --git a/UefiCpuPkg/Include/RISC-V/OpensbiTypes.h b/UefiCpuPkg/Include/RISC-V/OpensbiTypes.h
new file mode 100644
index 0000000000..918cf686fc
--- /dev/null
+++ b/UefiCpuPkg/Include/RISC-V/OpensbiTypes.h
@@ -0,0 +1,82 @@
+/** @file
+ RISC-V OpenSBI header file reference.
+
+ Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef EDK2_SBI_TYPES_H_
+#define EDK2_SBI_TYPES_H_
+
+#include <Base.h>
+
+typedef INT8 s8;
+typedef UINT8 u8;
+typedef UINT8 uint8_t;
+
+typedef INT16 s16;
+typedef UINT16 u16;
+typedef INT16 int16_t;
+typedef UINT16 uint16_t;
+
+typedef INT32 s32;
+typedef UINT32 u32;
+typedef INT32 int32_t;
+typedef UINT32 uint32_t;
+
+typedef INT64 s64;
+typedef UINT64 u64;
+typedef INT64 int64_t;
+typedef UINT64 uint64_t;
+
+// PRILX is not used in EDK2 but we need to define it here because when
+// defining our own types, this constant is not defined but used by OpenSBI.
+#define PRILX "016lx"
+
+typedef BOOLEAN bool;
+typedef unsigned long ulong;
+typedef UINT64 uintptr_t;
+typedef UINT64 size_t;
+typedef INT64 ssize_t;
+typedef UINT64 virtual_addr_t;
+typedef UINT64 virtual_size_t;
+typedef UINT64 physical_addr_t;
+typedef UINT64 physical_size_t;
+
+#define true TRUE
+#define false FALSE
+
+#define __packed __attribute__((packed))
+#define __noreturn __attribute__((noreturn))
+#define __aligned(x) __attribute__((aligned(x)))
+
+#if defined (__GNUC__) || defined (__clang__)
+#define likely(x) __builtin_expect((x), 1)
+#define unlikely(x) __builtin_expect((x), 0)
+#else
+#define likely(x) (x)
+#define unlikely(x) (x)
+#endif
+
+#undef offsetof
+#ifdef __compiler_offsetof
+#define offsetof(TYPE, MEMBER) __compiler_offsetof(TYPE,MEMBER)
+#else
+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+#endif
+
+#define container_of(ptr, type, member) ({ \
+ const typeof(((type *)0)->member) * __mptr = (ptr); \
+ (type *)((char *)__mptr - offsetof(type, member)); })
+
+#define array_size(x) (sizeof(x) / sizeof((x)[0]))
+
+#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
+#define ROUNDUP(a, b) ((((a)-1) / (b) + 1) * (b))
+#define ROUNDDOWN(a, b) ((a) / (b) * (b))
+
+/* clang-format on */
+
+#endif
diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.template
index 9c310cf23d..32af0bd15e 100755
--- a/BaseTools/Conf/tools_def.template
+++ b/BaseTools/Conf/tools_def.template
@@ -1978,7 +1978,7 @@ DEFINE GCC5_RISCV_ALL_DLINK2_FLAGS = -Wl,--defsym=PECOFF_HEADER_S
DEFINE GCC5_RISCV_ALL_ASM_FLAGS = -c -x assembler -imacros $(DEST_DIR_DEBUG)/AutoGen.h
DEFINE GCC5_RISCV_ALL_CC_FLAGS_WARNING_DISABLE = -Wno-tautological-compare -Wno-pointer-compare
-DEFINE GCC5_RISCV_OPENSBI_TYPES = -DOPENSBI_EXTERNAL_SBI_TYPES=OpensbiTypes.h
+DEFINE GCC5_RISCV_OPENSBI_TYPES = -DOPENSBI_EXTERNAL_SBI_TYPES=RISC-V/OpensbiTypes.h
DEFINE GCC5_RISCV64_ARCH = rv64imafdc
DEFINE GCC5_RISCV32_RISCV64_ASLDLINK_FLAGS = DEF(GCC5_RISCV_ALL_DLINK_COMMON) -Wl,--entry,ReferenceAcpiTable -u ReferenceAcpiTable
--
2.31.1
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