[edk2-devel] [PATCH 2/5] UefiPayloadPkg/Include/Coreboot: Add headers for SMMSTOREv2 table

[Sean Rhodes]

From: Patrick Rudolph <patrick.rudolph at 9elements.com>

Since commit bc744f5893fc4d53275ed26dd8d968011c6a09c1 coreboot supports
the SMMSTORE v2 feature. It implements a SMI handler that is able to
write, read and erase pages in the boot media (SPI flash).
The existence of this optional feature is advertised by a coreboot table.

Add the tag and headers to parse the table.

Cc: Guo Dong <guo.dong at intel.com>
Cc: Ray Ni <ray.ni at intel.com>
Cc: Maurice Ma <maurice.ma at intel.com>
Cc: Benjamin You <benjamin.you at intel.com>
Cc: Sean Rhodes <sean at starlabs.systems>
Signed-off-by: Patrick Rudolph <patrick.rudolph at 9elements.com>
---
 UefiPayloadPkg/Include/Coreboot.h | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/UefiPayloadPkg/Include/Coreboot.h b/UefiPayloadPkg/Include/Coreboot.h
index a3e1109fe8..617e5e9bc0 100644
--- a/UefiPayloadPkg/Include/Coreboot.h
+++ b/UefiPayloadPkg/Include/Coreboot.h
@@ -236,6 +236,19 @@ struct cb_cbmem_tab {
   UINT64    cbmem_tab;
 };
 
+#define CB_TAG_SMMSTOREV2  0x0039
+struct cb_smmstorev2 {
+  UINT32    tag;
+  UINT32    size;
+  UINT32    num_blocks;      /* Number of writeable blocks in Smm */
+  UINT32    block_size;      /* Size of a block in byte. Default: 64 KiB */
+  UINT32    mmap_addr;       /* MMIO address of the store for read only access */
+  UINT32    com_buffer;      /* Physical address of the communication buffer */
+  UINT32    com_buffer_size; /* Size of the communication buffer in byte */
+  UINT8     apm_cmd;         /* The command byte to write to the APM I/O port */
+  UINT8     unused[3];       /* Set to zero */
+};
+
 /* Helpful macros */
 
 #define MEM_RANGE_COUNT(_rec) \
-- 
2.32.0



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