[edk2-devel] [RFC PATCH 16/17] UefiCpuPkg/CpuDxe: Add RISC-V support in CpuDxe module
Sunil V L
sunilvl at ventanamicro.com
Thu Sep 8 10:53:22 UTC 2022
On Wed, Sep 07, 2022 at 12:46:59PM +0000, Chang, Abner wrote:
> [AMD Official Use Only - General]
>
>
>
> > -----Original Message-----
> > From: Sunil V L <sunilvl at ventanamicro.com>
> > Sent: Wednesday, September 7, 2022 7:22 PM
> > To: Chang, Abner <Abner.Chang at amd.com>
> > Cc: devel at edk2.groups.io; Jian J Wang <jian.j.wang at intel.com>; Liming Gao
> > <gaoliming at byosoft.com.cn>; Eric Dong <eric.dong at intel.com>; Ray Ni
> > <ray.ni at intel.com>; Rahul Kumar <rahul1.kumar at intel.com>; Debkumar De
> > <debkumar.de at intel.com>; Catharine West <catharine.west at intel.com>;
> > Daniel Schaefer <git at danielschaefer.me>; Leif Lindholm
> > <quic_llindhol at quicinc.com>; Ard Biesheuvel <ardb at kernel.org>; Heinrich
> > Schuchardt <heinrich.schuchardt at canonical.com>; Anup Patel
> > <apatel at ventanamicro.com>
> > Subject: Re: [RFC PATCH 16/17] UefiCpuPkg/CpuDxe: Add RISC-V support in
> > CpuDxe module
> >
> > [CAUTION: External Email]
> >
> > On Wed, Sep 07, 2022 at 09:32:12AM +0000, Chang, Abner wrote:
> > > [AMD Official Use Only - General]
> > >
> > > Hi Sunil and UefiCpuPkg maintainers,
> > > For CpuDxe case, I think we should abstract CpuDxe to accommodate all
> > processor architectures instead of having copy for each archs.
> > CpuDxeCommon.c can have the generic protocol structure and the
> > installation functions, and CpuDxeCommon.h has the general definitions. So
> > does CpuMp related files. Move processor architecture dependent files to
> > under arch folders. AMD may have some differences with Intel so we will
> > have CpuDxeAmd.inf under CpuDxe\. AMD is revising SmmFeatureCpuLib
> > base on the similar concept. I think this makes the module looks simple and
> > architectural. Furthermore, the similar concept should apply to all modules (if
> > necessary) under UefiCpuPkg.
> > > I think we should revise CpuDxe before adding new arch such as RISC-V
> > and Loongson64 to this module.
> > Thanks Abner!. I have sent V2 in the current form itself since I had to move
> > DSC to OvmfPkg instead of edk2-platforms.
> >
> > I am not sure whether we really need this level of restructuring since I didn't
> > find much to share between architectures. Thats why, I just made current
> > sources as x86 speicifc and added RISC-V sources.
> > Anyway, let me wait for maintainers feedback.
> I was also struggled with UefiCpuPkg when I tried to move RISC-V stuff over here. Some modules are easy to be abstracted but some are not. Some as you mentioned have not much to share among processor archs. For these cases we can use folder or a separate module for the abstraction. Having X86 source code on the module root and other processor archs in the folder look weird though.
>
> >Do you have a patch already
> > for this restructuring? If so, I can rebase RISC-V changes on top of it if
> > maintainers accept the approach.
> No, I don't have that yet. But I am willing to help on restructuring this module and others if maintainers agree with this.
That's great!. Could you please take care of refactoring
DxeCpuExceptionHandlerLib also in UefiCpuPkg along with CpuDxe as soon
as maintainers agree? That would be very helful.
Thanks
Sunil
> Thanks
> Abner
> >
> > Thanks
> > Sunil
> > >
> > > Here is a BZ for UefiCpuPkg rearchitecture,
> > >
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugz
> > >
> > illa.tianocore.org%2Fshow_bug.cgi%3Fid%3D3860&data=05%7C01%7CA
> > bner
> > > .Chang%40amd.com%7Cc9bca42bd85c489c38ff08da90c33618%7C3dd8961fe
> > 4884e60
> > >
> > 8e11a82d994e183d%7C0%7C0%7C637981465382450232%7CUnknown%7CTW
> > FpbGZsb3d8
> > >
> > eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3
> > D%7C3
> > >
> > 000%7C%7C%7C&sdata=iDjOPZCMAH6BSBhR2kx567ibVHza2ZfhjzLHC77
> > cfI8%3D&
> > > amp;reserved=0
> > >
> > > Abner
> > >
> > > Something looks like below,
> > > CpuDxe\X86\Ia32\
> > > \IA32\CpuAsm.asm
> > > \IA32\PageAttribute.c
> > > \X86\X64\
> > > \X64\CpuAsm.asm
> > > \X64\PageAttribute.c
> > > \X86\CpuGdt.c
> > > \CpuGdt.h
> > > \CpuPageTable.C
> > > \CpuPageTableh.h
> > > \CpuDxe.c
> > > \RISCV\RISCV64\
> > > \RISCV64\CpuDxe.h
> > > \CpuDxe.c
> > > \ARM\ARM\
> > > \AARCH64\
> > > \CpuDxe.c
> > > \CpuDxeCommon.c
> > > \CpuMpCommon.c
> > > \CpuDxeCommon.h
> > > \CpuMpCommon.h
> > > \CpuDxe.inf
> > >
> > >
> > > > -----Original Message-----
> > > > From: Sunil V L <sunilvl at ventanamicro.com>
> > > > Sent: Wednesday, September 7, 2022 1:09 AM
> > > > To: devel at edk2.groups.io
> > > > Cc: Jian J Wang <jian.j.wang at intel.com>; Liming Gao
> > > > <gaoliming at byosoft.com.cn>; Eric Dong <eric.dong at intel.com>; Ray Ni
> > > > <ray.ni at intel.com>; Rahul Kumar <rahul1.kumar at intel.com>; Debkumar
> > > > De <debkumar.de at intel.com>; Catharine West
> > > > <catharine.west at intel.com>; Daniel Schaefer <git at danielschaefer.me>;
> > > > Chang, Abner <Abner.Chang at amd.com>; Leif Lindholm
> > > > <quic_llindhol at quicinc.com>; Ard Biesheuvel <ardb at kernel.org>;
> > > > Heinrich Schuchardt <heinrich.schuchardt at canonical.com>; Anup Patel
> > > > <apatel at ventanamicro.com>; Sunil V L <sunilvl at ventanamicro.com>
> > > > Subject: [RFC PATCH 16/17] UefiCpuPkg/CpuDxe: Add RISC-V support in
> > > > CpuDxe module
> > > >
> > > > [CAUTION: External Email]
> > > >
> > > > This DXE module initializes the RISC-V CPU by installing the CPU
> > > > specific ARCH protocol handlers. This also initializes the
> > > > RISCV_EFI_BOOT_PROTOCOL which is required on RISC-V platforms.
> > > >
> > > > Signed-off-by: Sunil V L <sunilvl at ventanamicro.com>
> > > > ---
> > > > UefiCpuPkg/CpuDxe/CpuDxe.inf | 16 +-
> > > > UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c | 337
> > > > +++++++++++++++++++++++++++++
> > > > UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h | 200 +++++++++++++++++
> > > > 3 files changed, 552 insertions(+), 1 deletion(-) create mode
> > > > 100644 UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
> > > > create mode 100644 UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h
> > > >
> > > > diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf
> > > > b/UefiCpuPkg/CpuDxe/CpuDxe.inf index 4f2ea42f16..17cf2b1ecd 100644
> > > > --- a/UefiCpuPkg/CpuDxe/CpuDxe.inf
> > > > +++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf
> > > > @@ -1,8 +1,12 @@
> > > > ## @file
> > > >
> > > > -# CPU driver installs CPU Architecture Protocol and CPU MP protocol.
> > > >
> > > > +# On X86, CPU driver installs CPU Architecture Protocol and CPU MP
> > > > protocol.
> > > >
> > > > +#
> > > >
> > > > +# On RISC-V, CPU driver installs CPU Architecture Protocol and
> > > > +RISC-V boot
> > > >
> > > > +# protocol
> > > >
> > > > #
> > > >
> > > > # Copyright (c) 2008 - 2019, Intel Corporation. All rights
> > > > reserved.<BR>
> > > >
> > > > # Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
> > > >
> > > > +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights
> > > > +reserved.<BR>
> > > >
> > > > #
> > > >
> > > > # SPDX-License-Identifier: BSD-2-Clause-Patent
> > > >
> > > > #
> > > >
> > > > @@ -44,6 +48,9 @@
> > > > MtrrLib
> > > >
> > > > UefiCpuLib
> > > >
> > > >
> > > >
> > > > +[LibraryClasses.RISCV64]
> > > >
> > > > + RiscVSbiLib
> > > >
> > > > +
> > > >
> > > > [Sources.IA32, Sources.X64]
> > > >
> > > > CpuDxe.c
> > > >
> > > > CpuDxe.h
> > > >
> > > > @@ -62,11 +69,18 @@
> > > > X64/CpuAsm.nasm
> > > >
> > > > X64/PagingAttribute.c
> > > >
> > > >
> > > >
> > > > +[Sources.RISCV64]
> > > >
> > > > + RiscV64/CpuDxe.c
> > > >
> > > > + RiscV64/CpuDxe.h
> > > >
> > > > +
> > > >
> > > > [Protocols]
> > > >
> > > > gEfiCpuArchProtocolGuid ## PRODUCES
> > > >
> > > > gEfiMpServiceProtocolGuid ## PRODUCES
> > > >
> > > > gEfiSmmBase2ProtocolGuid ## SOMETIMES_CONSUMES
> > > >
> > > >
> > > >
> > > > +[Protocols.RISCV64]
> > > >
> > > > + gRiscVEfiBootProtocolGuid ## PRODUCES
> > > >
> > > > +
> > > >
> > > > [Guids]
> > > >
> > > > gIdleLoopEventGuid ## CONSUMES ## Event
> > > >
> > > > gEfiVectorHandoffTableGuid ## SOMETIMES_CONSUMES ##
> > > > SystemTable
> > > >
> > > > diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
> > > > b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
> > > > new file mode 100644
> > > > index 0000000000..4112b6b8c6
> > > > --- /dev/null
> > > > +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
> > > > @@ -0,0 +1,337 @@
> > > > +/** @file
> > > >
> > > > + RISC-V CPU DXE driver.
> > > >
> > > > +
> > > >
> > > > + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP.
> > > > + All rights reserved.<BR>
> > > >
> > > > + Copyright (c) 2022, Ventana Micro Systems Inc. All rights
> > > > + reserved.<BR>
> > > >
> > > > +
> > > >
> > > > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +
> > > >
> > > > +#include <Library/PcdLib.h>
> > > >
> > > > +#include <Register/RiscV64/RiscVAsm.h>
> > > >
> > > > +#include "CpuDxe.h"
> > > >
> > > > +
> > > >
> > > > +//
> > > >
> > > > +// Global Variables
> > > >
> > > > +//
> > > >
> > > > +STATIC BOOLEAN mInterruptState = FALSE;
> > > >
> > > > +STATIC EFI_HANDLE mCpuHandle = NULL;
> > > >
> > > > +STATIC UINTN mBootHartId;
> > > >
> > > > +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol;
> > > >
> > > > +
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +RiscvGetBootHartId (
> > > >
> > > > + IN RISCV_EFI_BOOT_PROTOCOL *This,
> > > >
> > > > + OUT UINTN *BootHartId
> > > >
> > > > + )
> > > >
> > > > +{
> > > >
> > > > + if((This != &gRiscvBootProtocol) || (BootHartId == NULL)) {
> > > >
> > > > + return EFI_INVALID_PARAMETER;
> > > >
> > > > + }
> > > >
> > > > +
> > > >
> > > > + *BootHartId = mBootHartId;
> > > >
> > > > + return EFI_SUCCESS;
> > > >
> > > > +}
> > > >
> > > > +
> > > >
> > > > +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol = {
> > > >
> > > > + RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION,
> > > >
> > > > + RiscvGetBootHartId
> > > >
> > > > +};
> > > >
> > > > +
> > > >
> > > > +EFI_CPU_ARCH_PROTOCOL gCpu = {
> > > >
> > > > + CpuFlushCpuDataCache,
> > > >
> > > > + CpuEnableInterrupt,
> > > >
> > > > + CpuDisableInterrupt,
> > > >
> > > > + CpuGetInterruptState,
> > > >
> > > > + CpuInit,
> > > >
> > > > + CpuRegisterInterruptHandler,
> > > >
> > > > + CpuGetTimerValue,
> > > >
> > > > + CpuSetMemoryAttributes,
> > > >
> > > > + 1, // NumberOfTimers
> > > >
> > > > + 4 // DmaBufferAlignment
> > > >
> > > > +};
> > > >
> > > > +
> > > >
> > > > +//
> > > >
> > > > +// CPU Arch Protocol Functions
> > > >
> > > > +//
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Flush CPU data cache. If the instruction cache is fully coherent
> > > >
> > > > + with all DMA operations then function can just return EFI_SUCCESS.
> > > >
> > > > +
> > > >
> > > > + @param This Protocol instance structure
> > > >
> > > > + @param Start Physical address to start flushing from.
> > > >
> > > > + @param Length Number of bytes to flush. Round up to chipset
> > > >
> > > > + granularity.
> > > >
> > > > + @param FlushType Specifies the type of flush operation to
> > perform.
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS If cache was flushed
> > > >
> > > > + @retval EFI_UNSUPPORTED If flush type is not supported.
> > > >
> > > > + @retval EFI_DEVICE_ERROR If requested range could not be flushed.
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuFlushCpuDataCache (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > >
> > > > + IN EFI_PHYSICAL_ADDRESS Start,
> > > >
> > > > + IN UINT64 Length,
> > > >
> > > > + IN EFI_CPU_FLUSH_TYPE FlushType
> > > >
> > > > + )
> > > >
> > > > +{
> > > >
> > > > + return EFI_SUCCESS;
> > > >
> > > > +}
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Enables CPU interrupts.
> > > >
> > > > +
> > > >
> > > > + @param This Protocol instance structure
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS If interrupts were enabled in the CPU
> > > >
> > > > + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the
> > CPU.
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuEnableInterrupt (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This
> > > >
> > > > + )
> > > >
> > > > +{
> > > >
> > > > + EnableInterrupts ();
> > > >
> > > > + mInterruptState = TRUE;
> > > >
> > > > + return EFI_SUCCESS;
> > > >
> > > > +}
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Disables CPU interrupts.
> > > >
> > > > +
> > > >
> > > > + @param This Protocol instance structure
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS If interrupts were disabled in the CPU.
> > > >
> > > > + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the
> > CPU.
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuDisableInterrupt (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This
> > > >
> > > > + )
> > > >
> > > > +{
> > > >
> > > > + DisableInterrupts ();
> > > >
> > > > + mInterruptState = FALSE;
> > > >
> > > > + return EFI_SUCCESS;
> > > >
> > > > +}
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Return the state of interrupts.
> > > >
> > > > +
> > > >
> > > > + @param This Protocol instance structure
> > > >
> > > > + @param State Pointer to the CPU's current interrupt state
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS If interrupts were disabled in the CPU.
> > > >
> > > > + @retval EFI_INVALID_PARAMETER State is NULL.
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuGetInterruptState (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > >
> > > > + OUT BOOLEAN *State
> > > >
> > > > + )
> > > >
> > > > +{
> > > >
> > > > + if (State == NULL) {
> > > >
> > > > + return EFI_INVALID_PARAMETER;
> > > >
> > > > + }
> > > >
> > > > +
> > > >
> > > > + *State = mInterruptState;
> > > >
> > > > + return EFI_SUCCESS;
> > > >
> > > > +}
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Generates an INIT to the CPU.
> > > >
> > > > +
> > > >
> > > > + @param This Protocol instance structure
> > > >
> > > > + @param InitType Type of CPU INIT to perform
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS If CPU INIT occurred. This value should never
> > be
> > > >
> > > > + seen.
> > > >
> > > > + @retval EFI_DEVICE_ERROR If CPU INIT failed.
> > > >
> > > > + @retval EFI_UNSUPPORTED Requested type of CPU INIT not
> > supported.
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuInit (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > >
> > > > + IN EFI_CPU_INIT_TYPE InitType
> > > >
> > > > + )
> > > >
> > > > +{
> > > >
> > > > + return EFI_UNSUPPORTED;
> > > >
> > > > +}
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Registers a function to be called from the CPU interrupt handler.
> > > >
> > > > +
> > > >
> > > > + @param This Protocol instance structure
> > > >
> > > > + @param InterruptType Defines which interrupt to hook. IA-32
> > > >
> > > > + valid range is 0x00 through 0xFF
> > > >
> > > > + @param InterruptHandler A pointer to a function of type
> > > >
> > > > + EFI_CPU_INTERRUPT_HANDLER that is
> > > > + called
> > > >
> > > > + when a processor interrupt occurs.
> > > > + A null
> > > >
> > > > + pointer is an error condition.
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS If handler installed or uninstalled.
> > > >
> > > > + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a
> > > > handler
> > > >
> > > > + for InterruptType was previously installed.
> > > >
> > > > + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a
> > > > + handler for
> > > >
> > > > + InterruptType was not previously installed.
> > > >
> > > > + @retval EFI_UNSUPPORTED The interrupt specified by
> > InterruptType
> > > >
> > > > + is not supported.
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuRegisterInterruptHandler (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > >
> > > > + IN EFI_EXCEPTION_TYPE InterruptType,
> > > >
> > > > + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
> > > >
> > > > + )
> > > >
> > > > +{
> > > >
> > > > + return RegisterCpuInterruptHandler (InterruptType,
> > > > + InterruptHandler);
> > > >
> > > > +}
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Returns a timer value from one of the CPU's internal timers.
> > > > + There is no
> > > >
> > > > + inherent time interval between ticks but is a function of the CPU
> > > > frequency.
> > > >
> > > > +
> > > >
> > > > + @param This - Protocol instance structure.
> > > >
> > > > + @param TimerIndex - Specifies which CPU timer is requested.
> > > >
> > > > + @param TimerValue - Pointer to the returned timer value.
> > > >
> > > > + @param TimerPeriod - A pointer to the amount of time that
> > passes
> > > >
> > > > + in femtoseconds (10-15) for each
> > > > + increment
> > > >
> > > > + of TimerValue. If TimerValue does
> > > > + not
> > > >
> > > > + increment at a predictable rate,
> > > > + then 0 is
> > > >
> > > > + returned. The amount of time that
> > > > + has
> > > >
> > > > + passed between two calls to
> > > > + GetTimerValue()
> > > >
> > > > + can be calculated with the formula
> > > >
> > > > + (TimerValue2 - TimerValue1) * TimerPeriod.
> > > >
> > > > + This parameter is optional and may be NULL.
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS - If the CPU timer count was returned.
> > > >
> > > > + @retval EFI_UNSUPPORTED - If the CPU does not have any readable
> > > > timers.
> > > >
> > > > + @retval EFI_DEVICE_ERROR - If an error occurred while reading the
> > > > timer.
> > > >
> > > > + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or
> > > > + TimerValue
> > > > is NULL.
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuGetTimerValue (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > >
> > > > + IN UINT32 TimerIndex,
> > > >
> > > > + OUT UINT64 *TimerValue,
> > > >
> > > > + OUT UINT64 *TimerPeriod OPTIONAL
> > > >
> > > > + )
> > > >
> > > > +{
> > > >
> > > > + return EFI_UNSUPPORTED;
> > > >
> > > > +}
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Implementation of SetMemoryAttributes() service of CPU
> > > > + Architecture
> > > > Protocol.
> > > >
> > > > +
> > > >
> > > > + This function modifies the attributes for the memory region
> > > > + specified by BaseAddress and
> > > >
> > > > + Length from their current attributes to the attributes specified
> > > > + by
> > > > Attributes.
> > > >
> > > > +
> > > >
> > > > + @param This The EFI_CPU_ARCH_PROTOCOL instance.
> > > >
> > > > + @param BaseAddress The physical address that is the start address
> > of a
> > > > memory region.
> > > >
> > > > + @param Length The size in bytes of the memory region.
> > > >
> > > > + @param Attributes The bit mask of attributes to set for the
> > memory
> > > > region.
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS The attributes were set for the memory
> > region.
> > > >
> > > > + @retval EFI_ACCESS_DENIED The attributes for the memory
> > resource
> > > > range specified by
> > > >
> > > > + BaseAddress and Length cannot be modified.
> > > >
> > > > + @retval EFI_INVALID_PARAMETER Length is zero.
> > > >
> > > > + Attributes specified an illegal
> > > > + combination of attributes that
> > > >
> > > > + cannot be set together.
> > > >
> > > > + @retval EFI_OUT_OF_RESOURCES There are not enough system
> > > > resources
> > > > + to modify the attributes of
> > > >
> > > > + the memory resource range.
> > > >
> > > > + @retval EFI_UNSUPPORTED The processor does not support one or
> > > > more bytes of the memory
> > > >
> > > > + resource range specified by BaseAddress and Length.
> > > >
> > > > + The bit mask of attributes is not
> > > > + support for the memory resource
> > > >
> > > > + range specified by BaseAddress and Length.
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuSetMemoryAttributes (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > >
> > > > + IN EFI_PHYSICAL_ADDRESS BaseAddress,
> > > >
> > > > + IN UINT64 Length,
> > > >
> > > > + IN UINT64 Attributes
> > > >
> > > > + )
> > > >
> > > > +{
> > > >
> > > > + DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported
> > > > + yet\n", __FUNCTION__));
> > > >
> > > > + return EFI_SUCCESS;
> > > >
> > > > +}
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Initialize the state information for the CPU Architectural Protocol.
> > > >
> > > > +
> > > >
> > > > + @param ImageHandle Image handle this driver.
> > > >
> > > > + @param SystemTable Pointer to the System Table.
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS Thread can be successfully created
> > > >
> > > > + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data
> > > > + structure
> > > >
> > > > + @retval EFI_DEVICE_ERROR Cannot create the thread
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +InitializeCpu (
> > > >
> > > > + IN EFI_HANDLE ImageHandle,
> > > >
> > > > + IN EFI_SYSTEM_TABLE *SystemTable
> > > >
> > > > + )
> > > >
> > > > +{
> > > >
> > > > + EFI_STATUS Status;
> > > >
> > > > + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext;
> > > >
> > > > +
> > > >
> > > > + GetFirmwareContextPointer (&FirmwareContext);
> > > >
> > > > + ASSERT (FirmwareContext != NULL);
> > > >
> > > > + if (FirmwareContext == NULL) {
> > > >
> > > > + DEBUG ((DEBUG_ERROR, "Failed to get the pointer of
> > > > + EFI_RISCV_FIRMWARE_CONTEXT\n"));
> > > >
> > > > + return EFI_NOT_FOUND;
> > > >
> > > > + }
> > > >
> > > > + DEBUG ((DEBUG_INFO, " %a: Firmware Context is at 0x%x.\n",
> > > > + __FUNCTION__, FirmwareContext));
> > > >
> > > > +
> > > >
> > > > + mBootHartId = FirmwareContext->BootHartId;
> > > >
> > > > + DEBUG ((DEBUG_INFO, " %a: mBootHartId = 0x%x.\n",
> > __FUNCTION__,
> > > > + mBootHartId));
> > > >
> > > > +
> > > >
> > > > +
> > > >
> > > > + InitializeCpuExceptionHandlers(NULL);
> > > >
> > > > +
> > > >
> > > > + //
> > > >
> > > > + // Make sure interrupts are disabled
> > > >
> > > > + //
> > > >
> > > > + DisableInterrupts ();
> > > >
> > > > +
> > > >
> > > > + Status = gBS->InstallProtocolInterface (&ImageHandle,
> > > >
> > > > +
> > > > + &gRiscVEfiBootProtocolGuid,
> > > >
> > > > + EFI_NATIVE_INTERFACE,
> > > >
> > > > + &gRiscvBootProtocol
> > > >
> > > > + );
> > > >
> > > > +
> > > >
> > > > + ASSERT_EFI_ERROR (Status);
> > > >
> > > > +
> > > >
> > > > + //
> > > >
> > > > + // Install CPU Architectural Protocol
> > > >
> > > > + //
> > > >
> > > > + Status = gBS->InstallMultipleProtocolInterfaces (
> > > >
> > > > + &mCpuHandle,
> > > >
> > > > + &gEfiCpuArchProtocolGuid,
> > > >
> > > > + &gCpu,
> > > >
> > > > + NULL
> > > >
> > > > + );
> > > >
> > > > + ASSERT_EFI_ERROR (Status);
> > > >
> > > > + return Status;
> > > >
> > > > +}
> > > >
> > > > diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h
> > > > b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h
> > > > new file mode 100644
> > > > index 0000000000..f039759dbd
> > > > --- /dev/null
> > > > +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h
> > > > @@ -0,0 +1,200 @@
> > > > +/** @file
> > > >
> > > > + RISC-V CPU DXE module header file.
> > > >
> > > > +
> > > >
> > > > + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP.
> > > > + All rights reserved.<BR>
> > > >
> > > > + Copyright (c) 2022, Ventana Micro Systems Inc. All rights
> > > > + reserved.<BR>
> > > >
> > > > +
> > > >
> > > > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +
> > > >
> > > > +#ifndef CPU_DXE_H_
> > > >
> > > > +#define CPU_DXE_H_
> > > >
> > > > +
> > > >
> > > > +#include <PiDxe.h>
> > > >
> > > > +
> > > >
> > > > +#include <Protocol/Cpu.h>
> > > >
> > > > +#include <Protocol/RiscVBootProtocol.h>
> > > >
> > > > +#include <Library/RiscVSbiLib.h>
> > > >
> > > > +#include <Library/BaseLib.h>
> > > >
> > > > +#include <Library/CpuExceptionHandlerLib.h>
> > > >
> > > > +#include <Library/DebugLib.h>
> > > >
> > > > +#include <Library/UefiBootServicesTableLib.h>
> > > >
> > > > +#include <Library/UefiDriverEntryPoint.h>
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Flush CPU data cache. If the instruction cache is fully coherent
> > > >
> > > > + with all DMA operations then function can just return EFI_SUCCESS.
> > > >
> > > > +
> > > >
> > > > + @param This Protocol instance structure
> > > >
> > > > + @param Start Physical address to start flushing from.
> > > >
> > > > + @param Length Number of bytes to flush. Round up to chipset
> > > >
> > > > + granularity.
> > > >
> > > > + @param FlushType Specifies the type of flush operation to
> > perform.
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS If cache was flushed
> > > >
> > > > + @retval EFI_UNSUPPORTED If flush type is not supported.
> > > >
> > > > + @retval EFI_DEVICE_ERROR If requested range could not be flushed.
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuFlushCpuDataCache (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > >
> > > > + IN EFI_PHYSICAL_ADDRESS Start,
> > > >
> > > > + IN UINT64 Length,
> > > >
> > > > + IN EFI_CPU_FLUSH_TYPE FlushType
> > > >
> > > > + );
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Enables CPU interrupts.
> > > >
> > > > +
> > > >
> > > > + @param This Protocol instance structure
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS If interrupts were enabled in the CPU
> > > >
> > > > + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the
> > CPU.
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuEnableInterrupt (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This
> > > >
> > > > + );
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Disables CPU interrupts.
> > > >
> > > > +
> > > >
> > > > + @param This Protocol instance structure
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS If interrupts were disabled in the CPU.
> > > >
> > > > + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the
> > CPU.
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuDisableInterrupt (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This
> > > >
> > > > + );
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Return the state of interrupts.
> > > >
> > > > +
> > > >
> > > > + @param This Protocol instance structure
> > > >
> > > > + @param State Pointer to the CPU's current interrupt state
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS If interrupts were disabled in the CPU.
> > > >
> > > > + @retval EFI_INVALID_PARAMETER State is NULL.
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuGetInterruptState (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > >
> > > > + OUT BOOLEAN *State
> > > >
> > > > + );
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Generates an INIT to the CPU.
> > > >
> > > > +
> > > >
> > > > + @param This Protocol instance structure
> > > >
> > > > + @param InitType Type of CPU INIT to perform
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS If CPU INIT occurred. This value should never
> > be
> > > >
> > > > + seen.
> > > >
> > > > + @retval EFI_DEVICE_ERROR If CPU INIT failed.
> > > >
> > > > + @retval EFI_UNSUPPORTED Requested type of CPU INIT not
> > supported.
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuInit (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > >
> > > > + IN EFI_CPU_INIT_TYPE InitType
> > > >
> > > > + );
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Registers a function to be called from the CPU interrupt handler.
> > > >
> > > > +
> > > >
> > > > + @param This Protocol instance structure
> > > >
> > > > + @param InterruptType Defines which interrupt to hook. IA-32
> > > >
> > > > + valid range is 0x00 through 0xFF
> > > >
> > > > + @param InterruptHandler A pointer to a function of type
> > > >
> > > > + EFI_CPU_INTERRUPT_HANDLER that is
> > > > + called
> > > >
> > > > + when a processor interrupt occurs.
> > > > + A null
> > > >
> > > > + pointer is an error condition.
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS If handler installed or uninstalled.
> > > >
> > > > + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a
> > > > handler
> > > >
> > > > + for InterruptType was previously installed.
> > > >
> > > > + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a
> > > > + handler for
> > > >
> > > > + InterruptType was not previously installed.
> > > >
> > > > + @retval EFI_UNSUPPORTED The interrupt specified by
> > InterruptType
> > > >
> > > > + is not supported.
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuRegisterInterruptHandler (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > >
> > > > + IN EFI_EXCEPTION_TYPE InterruptType,
> > > >
> > > > + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
> > > >
> > > > + );
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Returns a timer value from one of the CPU's internal timers.
> > > > + There is no
> > > >
> > > > + inherent time interval between ticks but is a function of the CPU
> > > > frequency.
> > > >
> > > > +
> > > >
> > > > + @param This - Protocol instance structure.
> > > >
> > > > + @param TimerIndex - Specifies which CPU timer is requested.
> > > >
> > > > + @param TimerValue - Pointer to the returned timer value.
> > > >
> > > > + @param TimerPeriod - A pointer to the amount of time that
> > passes
> > > >
> > > > + in femtoseconds (10-15) for each
> > > > + increment
> > > >
> > > > + of TimerValue. If TimerValue does
> > > > + not
> > > >
> > > > + increment at a predictable rate,
> > > > + then 0 is
> > > >
> > > > + returned. The amount of time that
> > > > + has
> > > >
> > > > + passed between two calls to
> > > > + GetTimerValue()
> > > >
> > > > + can be calculated with the formula
> > > >
> > > > + (TimerValue2 - TimerValue1) * TimerPeriod.
> > > >
> > > > + This parameter is optional and may be NULL.
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS - If the CPU timer count was returned.
> > > >
> > > > + @retval EFI_UNSUPPORTED - If the CPU does not have any readable
> > > > timers.
> > > >
> > > > + @retval EFI_DEVICE_ERROR - If an error occurred while reading the
> > > > timer.
> > > >
> > > > + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or
> > > > + TimerValue
> > > > is NULL.
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuGetTimerValue (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > >
> > > > + IN UINT32 TimerIndex,
> > > >
> > > > + OUT UINT64 *TimerValue,
> > > >
> > > > + OUT UINT64 *TimerPeriod OPTIONAL
> > > >
> > > > + );
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Set memory cacheability attributes for given range of memeory.
> > > >
> > > > +
> > > >
> > > > + @param This Protocol instance structure
> > > >
> > > > + @param BaseAddress Specifies the start address of the
> > > >
> > > > + memory range
> > > >
> > > > + @param Length Specifies the length of the memory range
> > > >
> > > > + @param Attributes The memory cacheability for the memory
> > range
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS If the cacheability of that memory range is
> > > >
> > > > + set successfully
> > > >
> > > > + @retval EFI_UNSUPPORTED If the desired operation cannot be
> > done
> > > >
> > > > + @retval EFI_INVALID_PARAMETER The input parameter is not
> > > > + correct,
> > > >
> > > > + such as Length = 0
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuSetMemoryAttributes (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > >
> > > > + IN EFI_PHYSICAL_ADDRESS BaseAddress,
> > > >
> > > > + IN UINT64 Length,
> > > >
> > > > + IN UINT64 Attributes
> > > >
> > > > + );
> > > >
> > > > +
> > > >
> > > > +#endif
> > > >
> > > > --
> > > > 2.25.1
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