[edk2-devel] [PATCH v3 09/16] ArmPlatformPkg/PrePeiCore: permit entry with the MMU enabled

[Leif Lindholm]

On 2022-09-26 01:25, Ard Biesheuvel wrote:
> Some platforms may set up a preliminary ID map in flash and enter EFI
> with the MMU and caches enabled, as this removes a lot of the complexity
> around cache coherency. Let's take this into account, and avoid touching
> the MMU controls or perform cache invalidation when the MMU is enabled
> at entry.
> 
> Signed-off-by: Ard Biesheuvel <ardb at kernel.org>

Reviewed-by: Leif Lindholm <quic_llindhol at quicinc.com>

/
     Leif

> ---
>   ArmPlatformPkg/PrePeiCore/PrePeiCore.c | 22 +++++++++++---------
>   1 file changed, 12 insertions(+), 10 deletions(-)
> 
> diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
> index 9c4b25df953d..8b86c6e69abd 100644
> --- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
> +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
> @@ -58,17 +58,19 @@ CEntryPoint (
>     IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint
> 
>     )
> 
>   {
> 
> -  // Data Cache enabled on Primary core when MMU is enabled.
> 
> -  ArmDisableDataCache ();
> 
> -  // Invalidate instruction cache
> 
> -  ArmInvalidateInstructionCache ();
> 
> -  // Enable Instruction Caches on all cores.
> 
> -  ArmEnableInstructionCache ();
> 
> +  if (!ArmMmuEnabled ()) {
> 
> +    // Data Cache enabled on Primary core when MMU is enabled.
> 
> +    ArmDisableDataCache ();
> 
> +    // Invalidate instruction cache
> 
> +    ArmInvalidateInstructionCache ();
> 
> +    // Enable Instruction Caches on all cores.
> 
> +    ArmEnableInstructionCache ();
> 
>   
> 
> -  InvalidateDataCacheRange (
> 
> -    (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),
> 
> -    PcdGet32 (PcdCPUCorePrimaryStackSize)
> 
> -    );
> 
> +    InvalidateDataCacheRange (
> 
> +      (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),
> 
> +      PcdGet32 (PcdCPUCorePrimaryStackSize)
> 
> +      );
> 
> +  }
> 
>   
> 
>     //
> 
>     // Note: Doesn't have to Enable CPU interface in non-secure world,
> 



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