[edk2-devel] [PATCH v2 2/2] UefiCpuPkg: Support 5 level page table in ResetVector

[Zhiguang Liu]

Add a macro USE_5_LEVEL_PAGE_TABLE to determine whether to create
5 level page table.
If macro USE_5_LEVEL_PAGE_TABLE is defined, PML5Table is created
at (4G-12K), while PML4Table is at (4G-16K). In runtime check, if
5level paging is supported, use PML5Table, otherwise, use PML4Table.
If macro USE_5_LEVEL_PAGE_TABLE is not defined, to save space, 5level
paging is not created, and 4level paging is at (4G-12K) and be used.

Cc: Eric Dong <eric.dong at intel.com>
Cc: Ray Ni <ray.ni at intel.com>
Cc: Rahul Kumar <rahul1.kumar at intel.com>
Cc: Gerd Hoffmann <kraxel at redhat.com>
Cc: Debkumar De <debkumar.de at intel.com>
Cc: Catharine West <catharine.west at intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu at intel.com>
---
 .../ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm  | 24 ++++++++++++++++--
 .../ResetVector/Vtf0/Ia32/PageTables64.asm    | 25 -------------------
 UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb        |  4 ++-
 .../ResetVector/Vtf0/X64/PageTables5L.asm     | 20 +++++++++++++++
 4 files changed, 45 insertions(+), 28 deletions(-)
 delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
 create mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/PageTables5L.asm

diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm
index 6891397c2a..0b4a21061b 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm
+++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm
@@ -2,7 +2,7 @@
 ; @file
 ; Transition from 32 bit flat protected mode into 64 bit flat protected mode
 ;
-; Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR>
 ; SPDX-License-Identifier: BSD-2-Clause-Patent
 ;
 ;------------------------------------------------------------------------------
@@ -13,8 +13,28 @@ BITS    32
 ; Modified:  EAX
 ;
 Transition32FlatTo64Flat:
+%ifdef USE_5_LEVEL_PAGE_TABLE
+    mov     eax, 0
+    cpuid
+    cmp     eax, 07h                    ; check if basic CPUID leaf contains leaf 07
+    jb      NotSupport5LevelPaging      ; 5level paging not support, downgrade to 4level paging
+    mov     eax, 07h                    ; check cpuid leaf 7, subleaf 0
+    mov     ecx, 0
+    cpuid
+    bt      ecx, 16                     ; [Bits 16] Supports 5-level paging if 1.
+    jnc     NotSupport5LevelPaging      ; 5level paging not support, downgrade to 4level paging
+    mov     eax, ADDR_OF(PML5Table)
+    mov     cr3, eax
+    mov     eax, cr4
+    bts     eax, 12                     ; Set LA57=1.
+    mov     cr4, eax
+    jmp     CR3ProgramDone
+NotSupport5LevelPaging:
+%endif
 
-    OneTimeCall SetCr3ForPageTables64
+    mov     eax, ADDR_OF(PML4Table)
+    mov     cr3, eax
+CR3ProgramDone:
 
     mov     eax, cr4
     bts     eax, 5                      ; enable PAE
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
deleted file mode 100644
index 717e380892..0000000000
--- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
+++ /dev/null
@@ -1,25 +0,0 @@
-;------------------------------------------------------------------------------
-; @file
-; Sets the CR3 register for 64-bit paging
-;
-; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
-; SPDX-License-Identifier: BSD-2-Clause-Patent
-;
-;------------------------------------------------------------------------------
-
-BITS    32
-
-;
-; Modified:  EAX
-;
-SetCr3ForPageTables64:
-
-    ;
-    ; These pages are built into the ROM image in X64/PageTables.asm
-    ; Highest level PageTable is at the highest address
-    ;
-    mov     eax, ADDR_OF(PML4Table)
-    mov     cr3, eax
-
-    OneTimeCallRet SetCr3ForPageTables64
-
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
index 4b972a90a5..ececa244e3 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
+++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
@@ -43,6 +43,9 @@
   %else
     %include "X64/PageTables2M.asm"
   %endif
+%ifdef USE_5_LEVEL_PAGE_TABLE
+  %include "X64/PageTables5L.asm"
+%endif
 %endif
 EndOfPageTables:
 
@@ -59,7 +62,6 @@ EndOfPageTables:
 
 %ifdef ARCH_X64
 %include "Ia32/Flat32ToFlat64.asm"
-%include "Ia32/PageTables64.asm"
 %endif
 
 %include "Ia16/Real16ToFlat32.asm"
diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables5L.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables5L.asm
new file mode 100644
index 0000000000..62c9be047a
--- /dev/null
+++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables5L.asm
@@ -0,0 +1,20 @@
+;------------------------------------------------------------------------------
+; @file
+; PML5 page table creation.
+;
+; Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+PML5Table:
+    ;
+    ; PML5 table Pointers
+    ; Assume page table is create from bottom to top, and only one PML4 table there.
+    ;
+    DQ      (ADDR_OF($) - 0x1000 + PAGE_PDP_ATTR)
+
+    ;
+    ; Only first PML5 entry(first 8 bytes) pointting to a PML4 table. Others are zero
+    ;
+    TIMES   (0x1000 - 0x8) DB 0
-- 
2.31.1.windows.1



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