[edk2-devel] [PATCH v2 2/6] AlderlakeOpenBoardPkg: Add modules
Chaganty, Rangasai V
rangasai.v.chaganty at intel.com
Wed Aug 2 17:46:49 UTC 2023
Reviewed-by: Sai Chaganty <rangasai.v.chaganty at intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar at intel.com>
Sent: Tuesday, August 01, 2023 3:18 PM
To: devel at edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar at intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty at intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone at intel.com>; Oram, Isaac W <isaac.w.oram at intel.com>; Chuang, Rosen <rosen.chuang at intel.com>
Subject: [PATCH v2 2/6] AlderlakeOpenBoardPkg: Add modules
Adds the following modules:
-BiosInfo
-OpenBoardPlatformInit
-SBCVpdStructurePcd
Cc: Sai Chaganty <rangasai.v.chaganty at intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone at intel.com>
Cc: Isaac Oram <isaac.w.oram at intel.com>
Cc: Rosen Chuang <rosen.chuang at intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar at intel.com>
---
.../AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c | 196 +++++++++++++++
.../BiosInfo/BiosInfo.inf | 84 +++++++
.../OpenBoardPlatformInitPostMem.c | 233 ++++++++++++++++++
.../OpenBoardPlatformInitPostMem.inf | 75 ++++++
.../SBCVpdStructurePcd/AllStructPCD.dsc | 19 ++
.../GpioTableAdlPPostMem.dsc | 40 +++
.../GpioTableAdlPPreMem.dsc | 29 +++
.../MrcDqDqsSPD/AdlPSpdMap.dsc | 138 +++++++++++
.../PcieClocks/AdlPPcieClocks.dsc | 31 +++
9 files changed, 845 insertions(+)
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStructPCD.dsc
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.dsc
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c
new file mode 100644
index 0000000000..64462900de
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c
@@ -0,0 +1,196 @@
+/** @file
+ PEIM to provide BiosInfo structure listing up all firmware volume's
+base addresses, sizes,
+ attributes, and information associated to the firmware volume.
+ Primarily the structure is used on FIT table creation and Bpm.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Guid/BiosInfo.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/FirmwareInterfaceTable.h>
+#include <Ppi/FirmwareVolumeInfoMeasurementExcluded.h>
+#include <Library/MemoryAllocationLib.h>
+
+#define BASE_FV_SIZE 10
+
+#define FSP_WRAPPER_FV_SIZE 3
+
+#define TSN_MAC_ADDRESS_FV_SIZE 0
+
+#define BIOS_INFO_STRUCT_SIZE (BASE_FV_SIZE + FSP_WRAPPER_FV_SIZE +
+TSN_MAC_ADDRESS_FV_SIZE)
+
+
+/*
+ BIOS_INFO structure is the base of the firmware volume layout for
+Intel platform BIOS implementation
+ so security checker module can run based on the structure and throw
+warnings, error or deadloop
+ when any unexpected firmware volumes are detected.
+
+ BIOS_INFO is recommended to support full entries of firmware volumes
+present in a flash
+ with right type, attribute, version, flash map base address and size,
+ all associated information which is defined by BIOS_INFO_STRUCT structure.
+ - IBB firmware volumes, which are expected to be measured or/and verified
+ by hardware base security solution to meet SecureBoot chain of trust
+ (Intel BootGuard for example), have attribute 0x0.
+ - Post IBB firmware volumes, which are expected to be measured or/and verified
+ by BIOS (TCG code for measurement, RSA2048SHA256Sign algorithm for verification for example),
+ have attribute BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB.
+ - Else, follows Firmware Interface Table specification.
+*/
+#pragma pack (1)
+typedef struct {
+ BIOS_INFO_HEADER Header;
+ BIOS_INFO_STRUCT Entry[BIOS_INFO_STRUCT_SIZE]; } BIOS_INFO; #pragma
+pack ()
+
+GLOBAL_REMOVE_IF_UNREFERENCED BIOS_INFO mBiosInfo = {
+ {
+ BIOS_INFO_SIGNATURE,
+ BIOS_INFO_STRUCT_SIZE,
+ 0,
+ },
+ {
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_GENERAL_EXCLUDE_FROM_FIT,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashNvStorageVariableSize) + FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) + FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize),
+ FixedPcdGet32 (PcdFlashNvStorageVariableBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvAdvancedSize),
+ FixedPcdGet32 (PcdFlashFvAdvancedBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvOptionalSize),
+ FixedPcdGet32 (PcdFlashFvOptionalBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvSecuritySize),
+ FixedPcdGet32 (PcdFlashFvSecurityBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvOsBootSize),
+ FixedPcdGet32 (PcdFlashFvOsBootBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvUefiBootSize),
+ FixedPcdGet32 (PcdFlashFvUefiBootBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvPostMemorySize),
+ FixedPcdGet32 (PcdFlashFvPostMemoryBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_GENERAL_EXCLUDE_FROM_FIT,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvFirmwareBinariesSize),
+ FixedPcdGet32 (PcdFlashFvFirmwareBinariesBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvFspSSize),
+ FixedPcdGet32 (PcdFlashFvFspSBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ 0x00, // IBB FV
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvFspMSize),
+ FixedPcdGet32 (PcdFlashFvFspMBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ 0x00, // IBB FV
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvFspTSize),
+ FixedPcdGet32 (PcdFlashFvFspTBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ 0x00, // IBB FV
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvPreMemorySize),
+ FixedPcdGet32 (PcdFlashFvPreMemoryBase)
+ },
+ {
+ FIT_TYPE_01_MICROCODE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_MICROCODE_WHOLE_REGION,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashMicrocodeFvSize),
+ FixedPcdGet32 (PcdFlashMicrocodeFvBase)
+ },
+ }
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mBiosInfoPpiList
+= {
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gBiosInfoGuid,
+ &mBiosInfo
+};
+
+/**
+ Installs BiosInfo Ppi.
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @retval EFI_SUCCESS Install the BiosInfo Ppi successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+BiosInfoEntryPoint (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ VOID *HobData;
+
+ //
+ // Install PPI, so that other PEI module can add dependency.
+ //
+ Status = PeiServicesInstallPpi (&mBiosInfoPpiList);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Build hob, so that DXE module can also get the data.
+ //
+ HobData = BuildGuidHob (&gBiosInfoGuid, sizeof (mBiosInfo));
+ ASSERT (HobData != NULL);
+ if (HobData == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ CopyMem (HobData, &mBiosInfo, sizeof (mBiosInfo));
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf
new file mode 100644
index 0000000000..b11451807a
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf
@@ -0,0 +1,84 @@
+### @file
+# Module Information description file for BIOS Info PEIM.
+# The module provides BiosInfo structure listing up all firmware
+volume's base addresses, # sizes, attributes, those information associated to each firmware volume.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = BiosInfo
+ FILE_GUID = 4A4CA1C6-871C-45BB-8801-6910A7AA5807
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ ENTRY_POINT = BiosInfoEntryPoint
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES IA32 X64
+#
+
+[LibraryClasses]
+ PeimEntryPoint
+ PeiServicesLib
+ PeiServicesTablePointerLib
+ HobLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ DebugLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ SecurityPkg/SecurityPkg.dec
+ BoardModulePkg/BoardModulePkg.dec
+
+[Pcd]
+ gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress ## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase ##
+CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalBase ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize ## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize ## CONSUMES
+
+[Sources]
+ BiosInfo.c
+
+[Guids]
+ gBiosInfoGuid ## PRODUCES
+
+[Depex]
+ gEfiPeiMasterBootModePpiGuid
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c
new file mode 100644
index 0000000000..4fab4ad8e6
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoa
+++ rdPlatformInitPei/OpenBoardPlatformInitPostMem.c
@@ -0,0 +1,233 @@
+/** @file
+ Source code file for OpenBoard Platform Init PEI module
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Register/Msr.h>
+#include <CpuRegs.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Ppi/EndOfPeiPhase.h>
+#include <Library/MtrrLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Guid/SmramMemoryReserve.h>
+#include <Library/ConfigBlockLib.h>
+#include <Ppi/SiPolicy.h>
+#include <PchPolicyCommon.h>
+#include <Library/SiPolicyLib.h>
+#include <Guid/FirmwareFileSystem2.h>
+#include <Protocol/FirmwareVolumeBlock.h> #include
+<Library/PostCodeLib.h> #include <PlatformPostCode.h> #include
+<Ppi/Spi.h> #include <Library/MtrrLib.h> #include
+<Library/PciSegmentLib.h> #include <Register/PchRegs.h> #include
+<PlatformBoardId.h> #include <Core/Pei/PeiMain.h> #include
+<Library/PchPciBdfLib.h> #include <Ppi/GraphicsPlatformPolicyPpi.h>
+#include <Library/PeiGetFvInfoLib.h>
+
+
+EFI_STATUS
+EFIAPI
+OpenBoardPlatformInitEndOfPei (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+static EFI_PEI_NOTIFY_DESCRIPTOR mEndOfPeiNotifyList = {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK |
+EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiEndOfPeiSignalPpiGuid,
+ (EFI_PEIM_NOTIFY_ENTRY_POINT) OpenBoardPlatformInitEndOfPei };
+
+EFI_STATUS
+EFIAPI
+GetPeiPlatformLidStatus (
+ OUT LID_STATUS *CurrentLidStatus
+ );
+
+EFI_STATUS
+EFIAPI
+GetVbtData (
+ OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
+ OUT UINT32 *VbtSize
+ );
+
+PEI_GRAPHICS_PLATFORM_POLICY_PPI PeiGraphicsPlatform = {
+ PEI_GRAPHICS_PLATFORM_POLICY_REVISION,
+ GetPeiPlatformLidStatus,
+ GetVbtData
+};
+
+EFI_PEI_PPI_DESCRIPTOR mPeiGraphicsPlatformPpi = {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gPeiGraphicsPlatformPpiGuid,
+ &PeiGraphicsPlatform
+};
+
+EFI_STATUS
+EFIAPI
+GetVbtData (
+ OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
+ OUT UINT32 *VbtSize
+ )
+{
+ EFI_GUID FileGuid;
+ EFI_GUID BmpImageGuid;
+ VOID *Buffer;
+ UINT32 Size;
+
+ Size = 0;
+ Buffer = NULL;
+
+
+ DEBUG((DEBUG_INFO, "GetVbtData Entry\n"));
+
+ CopyMem (&BmpImageGuid, PcdGetPtr(PcdIntelGraphicsVbtFileGuid),
+ sizeof(BmpImageGuid));
+
+ CopyMem(&FileGuid, &BmpImageGuid, sizeof(FileGuid));
+ PeiGetSectionFromFv(FileGuid, &Buffer, &Size); if (Buffer == NULL) {
+ DEBUG((DEBUG_ERROR, "Could not locate VBT\n")); } else {
+ DEBUG ((DEBUG_INFO, "GetVbtData Buffer is 0x%x\n", Buffer));
+ DEBUG ((DEBUG_INFO, "GetVbtData Size is 0x%x\n", Size));
+ *VbtAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)Buffer;
+ *VbtSize = Size;
+ }
+ DEBUG((DEBUG_INFO, "GetVbtData exit\n"));
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function will return Lid Status in PEI phase.
+
+ @param[out] CurrentLidStatus
+
+ @retval EFI_SUCCESS
+ @retval EFI_UNSUPPORTED
+**/
+
+EFI_STATUS
+EFIAPI
+GetPeiPlatformLidStatus (
+ OUT LID_STATUS *CurrentLidStatus
+ )
+{
+ DEBUG ((DEBUG_INFO, "LidStatus Unsupported\n"));
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Configure PciHostBridge related PCDs
+**/
+VOID
+ConfigurePciHostBridgePcds (
+ VOID
+ )
+{
+ //
+ // Provide 256GB available above 4GB MMIO resource
+ // limited to use single variable MTRR to cover this above 4GB MMIO region.
+ //
+ PcdSet64S (PcdPciReservedMemAbove4GBBase, BASE_256GB);
+ PcdSet64S (PcdPciReservedMemAbove4GBLimit, BASE_256GB + SIZE_256GB -
+1);
+ if (PcdGet64 (PcdPciReservedMemAbove4GBBase) < PcdGet64 (PcdPciReservedMemAbove4GBLimit)) {
+ DEBUG ((DEBUG_INFO, " PCI space that above 4GB MMIO is from 0x%lX", PcdGet64 (PcdPciReservedMemAbove4GBBase)));
+ DEBUG ((DEBUG_INFO, " to 0x%lX\n", PcdGet64
+(PcdPciReservedMemAbove4GBLimit)));
+ }
+}
+
+/**
+ This function handles PlatformInit task at the end of PEI
+
+ @param[in] PeiServices Pointer to PEI Services Table.
+ @param[in] NotifyDesc Pointer to the descriptor for the Notification event that
+ caused this function to execute.
+ @param[in] Ppi Pointer to the PPI data associated with this function.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval others
+**/
+EFI_STATUS
+EFIAPI
+OpenBoardPlatformInitEndOfPei (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ //
+ // Configure PciHostBridge related PCDs before DXE phase
+ //
+ ConfigurePciHostBridgePcds ();
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Platform Init PEI module entry point
+
+ @param[in] FileHandle Not used.
+ @param[in] PeiServices General purpose services available to every PEIM.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database
+**/
+EFI_STATUS
+EFIAPI
+OpenBoardPlatformInitPostMemEntryPoint (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ PEI_CORE_INSTANCE *PrivateData;
+ UINTN CurrentFv;
+ PEI_CORE_FV_HANDLE *CoreFvHandle;
+ VOID *HobData;
+
+ PostCode (PLATFORM_INIT_POSTMEM_ENTRY);
+
+ //
+ // Build a HOB to show current FV location for SA policy update code to consume.
+ //
+ PrivateData = PEI_CORE_INSTANCE_FROM_PS_THIS(PeiServices);
+ CurrentFv = PrivateData->CurrentPeimFvCount; CoreFvHandle =
+ &(PrivateData->Fv[CurrentFv]);
+
+ HobData = BuildGuidHob (
+ &gPlatformInitFvLocationGuid,
+ sizeof (VOID *)
+ );
+ ASSERT (HobData != NULL);
+ CopyMem (HobData, (VOID *) &CoreFvHandle, sizeof (VOID *));
+
+ //
+ // Install mPeiGraphicsPlatformPpi
+ //
+ DEBUG ((DEBUG_INFO, "Install mPeiGraphicsPlatformPpi \n")); Status =
+ PeiServicesInstallPpi (&mPeiGraphicsPlatformPpi);
+
+ //
+ // Performing PlatformInitEndOfPei after EndOfPei PPI produced //
+ Status = PeiServicesNotifyPpi (&mEndOfPeiNotifyList); PostCode
+ (PLATFORM_INIT_POSTMEM_EXIT);
+
+ return Status;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf
new file mode 100644
index 0000000000..b2bfd97f8a
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoa
+++ rdPlatformInitPei/OpenBoardPlatformInitPostMem.inf
@@ -0,0 +1,75 @@
+### @file
+# Component information file for the OpenBoard Platform Init PEI module.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = OpenBoardPlatformInitPostMem
+ FILE_GUID = 314EE04C-1106-4DC6-ACBC-CF19C0DBC5CC
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ ENTRY_POINT = OpenBoardPlatformInitPostMemEntryPoint
+
+[LibraryClasses]
+ PeimEntryPoint
+ DebugLib
+ IoLib
+ MemoryAllocationLib
+ BaseMemoryLib
+ HobLib
+ PeiServicesLib
+ PciSegmentLib
+ MtrrLib
+ PchInfoLib
+ PostCodeLib
+ SiPolicyLib
+ FspCommonLib
+ PcdLib
+ PchPciBdfLib
+ GpioLib
+ PeiGetFvInfoLib
+
+[Packages]
+ AlderlakeSiliconPkg/SiPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ IntelFsp2Pkg/IntelFsp2Pkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ AlderLakeFspBinPkg/Client/AlderLakeP/AlderLakeFspBinPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Sources]
+ OpenBoardPlatformInitPostMem.c
+
+[Ppis]
+ gEfiEndOfPeiSignalPpiGuid ## CONSUMES
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
+ gPeiGraphicsPlatformPpiGuid ## PRODUCES
+ gFspSiliconInitDonePpiGuid ## CONSUMES
+
+[Protocols]
+
+[Guids]
+ gEfiSmmSmramMemoryGuid ## CONSUMES
+ gPlatformInitFvLocationGuid ## PRODUCES
+
+[Depex]
+ gEfiPeiMemoryDiscoveredPpiGuid
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIobase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIoLimit ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciSegmentCount ## CONSUMES
+
+ gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid ## CONSUMES
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStructPCD.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStructPCD.dsc
new file mode 100644
index 0000000000..9215a026ae
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStructP
+++ CD.dsc
@@ -0,0 +1,19 @@
+## @file
+# Include All Board Gpio configuration file.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+!include
+$(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc
+!include
+$(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc
+
+
+# PCIe clock mapping
+!include
+$(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.
+dsc
+
+# MRC DQS DQ and SPD mapping
+!include
+$(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc
+
+
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc
new file mode 100644
index 0000000000..3eb8c276b5
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableA
+++ dlPPostMem.dsc
@@ -0,0 +1,40 @@
+## @file
+# GPIO definition table for Alderlake P #
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+###
+### !!! GPIOs designated to Native Functions shall not be configured by Platform Code.
+### Native Pins shall be configured by Silicon Code (based on BIOS policies setting) or soft straps(set by CSME in FITc).
+###
+###
+
+
+#mGpioTableAdlPDdr5Rvp
+[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp]
+gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTable|*|{CODE({
+ // CPU M.2 SSD1
+ {GPIO_VER2_LP_GPP_F20, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD1 RESET
+
+ // CPU M.2 SSD2
+ {GPIO_VER2_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD2 PWREN
+ {GPIO_VER2_LP_GPP_H1, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, // CPU SSD2 RESET
+
+ // X4 Pcie Slot for Gen3 and Gen 4
+ {GPIO_VER2_LP_GPP_F10, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}},//ONBOARD_X4_PCIE_SLOT1_RESET_N
+
+ // PCH M.2 SSD
+ {GPIO_VER2_LP_GPP_D16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //M2_PCH_SSD_PWREN
+ {GPIO_VER2_LP_GPP_H0, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //M2_SSD_RST_N
+
+ // EC
+ {GPIO_VER2_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault,GpioIntLevel|GpioIntSmi,GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock }}, //EC_SMI_N
+ {GPIO_VER2_LP_GPP_F9, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //EC_SLP_S0_CS_N
+
+ {0x0} // terminator
+})}
+
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc
new file mode 100644
index 0000000000..7bf8571c27
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableA
+++ dlPPreMem.dsc
@@ -0,0 +1,29 @@
+## @file
+# Alderlake P RVP GPIO definition table for Pre-Memory Initialization
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+###
+### !!! GPIOs designated to Native Functions shall not be configured by Platform Code.
+### Native Pins shall be configured by Silicon Code (based on BIOS policies setting) or soft straps(set by CSME in FITc).
+###
+###
+
+# mGpioTablePreMemAdlPDdr5Rvp
+[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp]
+gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem|*|{CODE({
+ // CPU M.2 SSD
+ { GPIO_VER2_LP_GPP_F20, { GpioPadModeGpio, GpioHostOwnAcpi,
+GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }
+}, //CPU SSD RESET
+
+ // CPU M.2 SSD2
+ {GPIO_VER2_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD2 PWREN
+ {GPIO_VER2_LP_GPP_H1, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD2 RESET
+
+ // X4 Pcie Slot for Gen3 and Gen 4
+ {GPIO_VER2_LP_GPP_F10, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}},//ONBOARD_X4_PCIE_SLOT1_RESET_N
+
+ {0x0} // terminator
+})}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc
new file mode 100644
index 0000000000..096cc380cd
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/MrcDqDqsSP
+++ D/AdlPSpdMap.dsc
@@ -0,0 +1,138 @@
+## @file
+# ADL P SPD DATA configuration file.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp]
+gBoardModuleTokenSpaceGuid.VpdPcdMrcSpdData|*|{CODE(
+{
+// DDR5 1Rx16 - 4800 MHz
+ 1,
+ {0x30, ///< 0 1024 SPD bytes total
+ 0x08, ///< 1 SPD Revision 0.8
+ 0x12, ///< 2 DRAM Type: DDR5 SDRAM
+ 0x03, ///< 3 Module Type: Not Hybrid (DRAM only) / SO-DIMM Solution
+ 0x04, ///< 4 Monolithic SDRAM, 16 Gb SDRAM density
+ 0x00, ///< 5 16 Rows, 10 Columns
+ 0x40, ///< 6 x16 SDRAM I/O Width
+ 0x42, ///< 7 4 Bank Groups, 4 Banks per Bank Group
+ 0x00, ///< 8 Secondary SDRAM Density and Package
+ 0x00, ///< 9 Secondary SDRAM Addressing
+ 0x00, ///< 10 Secondary SDRAM I/O Width
+ 0x00, ///< 11 Secondary BankGroups and Banks per Bank Group
+ 0x60, ///< 12 PPR Supported, One row per bank group, Soft PPR Supported
+ 0x00, ///< 13 Commercial Temperature Grade, 0 to 85 C
+ 0x00, ///< 14 Reserved
+ 0x00, ///< 15 Reserved
+ 0x00, ///< 16 SDRAM Nominal Voltage VDD: 1.1V
+ 0x00, ///< 17 SDRAM Nominal Voltage VDDQ: 1.1V
+ 0x00, ///< 18 SDRAM Nominal Voltage VPP: 1.8V
+ 0x00, ///< 19 Reserved
+ 0xA1, ///< 20 tCKAVGmin LSB
+ 0x01, ///< 21 tCKAVGmin MSB
+ 0xE8, ///< 22 tCKAVGmax LSB
+ 0x03, ///< 23 tCKAVGmax MSB
+ 0x72, ///< 24 CAS Latencies supported (First Byte) : 32, 30, 28, 22
+ 0x15, ///< 25 CAS Latencies supported (Second Byte): 44, 40, 36
+ 0x00, ///< 26 CAS Latencies supported (Third Byte) :
+ 0x00, ///< 27 CAS Latencies supported (Fourth Byte):
+ 0x00, ///< 28 CAS Latencies supported (Fifth Byte) :
+ 0x00, ///< 29 Reserved
+ 0x1E, ///< 30 Minimum CAS Latency (tAAmin) LSB
+ 0x41, ///< 31 Minimum CAS Latency (tAAmin) MSB
+ 0x1E, ///< 32 Minimum RAS-to-CAS delay (tRCDmin) LSB
+ 0x41, ///< 33 Minimum RAS-to-CAS delay (tRCDmin) MSB
+ 0x1E, ///< 34 Minimum Row Precharge delay (tRPmin) LSB
+ 0x41, ///< 35 Minimum Row Precharge delay (tRPmin) MSB
+ 0x00, ///< 36 Minimum Active to Precharge delay (tRASmin) LSB
+ 0x7D, ///< 37 Minimum Active to Precharge delay (tRASmin) MSB
+ 0x1E, ///< 38 Minimum Active to Active/Refresh delay (tRCmin) LSB
+ 0xBE, ///< 39 Minimum Active to Active/Refresh delay (tRCmin) MSB
+ 0x30, ///< 40 Minimum Write Recovery time (tWRmin) LSB
+ 0x75, ///< 41 Minimum Write Recovery time (tWRmin) MSB
+ 0x27, ///< 42 Refresh Recovery Delay (tRFC1min) LSB
+ 0x01, ///< 43 Refresh Recovery Delay (tRFC1min) MSB
+ 0xA0, ///< 44 Refresh Recovery Delay (tRFC2min) MSB
+ 0x00, ///< 45 Refresh Recovery Delay (tRFC2min) MSB
+ 0x82, ///< 46 Refresh Recovery Delay (tRFCsbmin) MSB
+ 0x00, ///< 47 Refresh Recovery Delay (tRFCsbmin) MSB
+ 0, 0, ///< 48 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
+ 0, 0, 0, 0, 0, 0, ///< 120 - 125
+ 0x47, ///< 126 CRC Bytes 0 - 127 LSB
+ 0xAE, ///< 127 CRC Bytes 0 - 127 MSB
+ 0, 0, ///< 128 - 129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
+ 0, 0, ///< 190 - 191
+ 0x08, ///< 192 SPD Revision for Module Information: 0.8
+ 0x00, ///< 193 Reserved
+ 0xC2, ///< 194 SPD Manufacturer ID First Byte
+ 0xC4, ///< 195 SPD Manufacturer ID Second Byte
+ 0x80, ///< 196 SPD Device Type
+ 0x00, ///< 197 SPD Device Revision
+ 0x80, ///< 198 PMIC0 Manufacturer ID First Byte
+ 0xB3, ///< 199 PMIC0 Manufacturer ID Second Byte
+ 0x80, ///< 200 PMIC0 Device Type
+ 0x11, ///< 201 PMIC0 Device Revision
+ 0, 0, 0, 0, ///< 202 - 205 PMIC1
+ 0, 0, 0, 0, ///< 206 - 209 PMIC2
+ 0x80, ///< 210 Thermal Sensors Manufacturer ID First Byte
+ 0xB3, ///< 211 Thermal Sensors Manufacturer ID First Byte
+ 0x80, ///< 212 Thermal Sensors Device Type
+ 0x11, ///< 213 Thermal Sensors Device Revision
+ 0, 0, 0, 0, 0, 0, ///< 214 - 219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
+ 0x0F, ///< 230 Module Nominal Height
+ 0x10, ///< 231 Module Nominal Thickness
+ 0x00, ///< 232 Reference Raw Card Used
+ 0x01, ///< 233 1 Row of DRAM on Module
+ 0x01, ///< 234 1 Rank, 8 bits SDRAM data width per channel
+ 0x22, ///< 235 2 Channels per DIMM, 32 bits per Channel
+ 0, 0, 0, 0, ///< 236 - 239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 320 - 329
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 330 - 339
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 340 - 349
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 350 - 359
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ///< 440 - 445
+ 0x9C, ///< 446 CRC for Bytes 128 - 253 LSB
+ 0xAD, ///< 447 CRC for Bytes 128 - 253 MSB
+ 0, 0, ///< 448 - 449
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509
+ 0, 0 ///< 510 - 511
+ ///< Ignore bytes 512-1023, @todo_adl: support 1024 bytes SPD
+array }})}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.dsc
new file mode 100644
index 0000000000..57106e92c4
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/PcieClocks
+++ /AdlPPcieClocks.dsc
@@ -0,0 +1,31 @@
+## @file
+# Alderlake P Pcie Clock configuration file.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+
+[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp]
+gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap|*|{CODE(
+{{
+ PCIE_PEG, // CPU M.2 SSD 1
+ PCIE_PCH + 8, // PCH M.2 SSD
+ PCIE_PCH + 4,
+ PCIE_PEG + 1, // X8 DG/DG2
+ PCIE_PEG + 2, // CPU M.2 SSD 2
+ PCIE_PCH + 5, // M.2 KEY B WWAN - PCIe P6
+ LAN_CLOCK,
+ // Default Case:
+ // - PCIe P7 mapped to GBELAN
+ // - PCIe P8 mapped to x4 PCIe DT Slot (Pair 1)
+ PCIE_PCH + 7, // x4 PCIe DT Slot (x1)
+ // Reworked Case: with rework and soft strap changes
+ // - PCIe P7 mapped to x4 PCIe DT Slot (Pair 2)
+ // - PCIe P8 mapped to x4 PCIe DT Slot (Pair 1)
+ // PCIE_PCH + 6, // x4 PCIe DT Slot (x2)
+ NOT_USED,
+ NOT_USED
+}}
+)}
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#107467): https://edk2.groups.io/g/devel/message/107467
Mute This Topic: https://groups.io/mt/100494310/1813853
Group Owner: devel+owner at edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [edk2-devel-archive at redhat.com]
-=-=-=-=-=-=-=-=-=-=-=-
More information about the edk2-devel-archive
mailing list